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Searched
refs:Intf
(Results
1 - 5
of
5
) sorted by null
/external/swiftshader/third_party/LLVM/lib/CodeGen/
RegAllocGreedy.cpp
190
InterferenceCache::Cursor
Intf
;
199
Intf
.setPhysReg(Cache, Reg);
543
LiveInterval *
Intf
= Q.interferingVRegs()[i - 1];
544
if (TargetRegisterInfo::isPhysicalRegister(
Intf
->reg))
547
if (getStage(*
Intf
) == RS_Done)
552
bool Urgent = !VirtReg.isSpillable() &&
Intf
->isSpillable();
554
unsigned IntfCascade = ExtraRegInfo[
Intf
->reg].Cascade;
563
bool BreaksHint = VRM->hasPreferredPhys(
Intf
->reg);
566
Cost.MaxWeight = std::max(Cost.MaxWeight,
Intf
->weight);
571
if (!Urgent && !shouldEvict(VirtReg, IsHint, *
Intf
, BreaksHint)
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
RegAllocGreedy.cpp
364
InterferenceCache::Cursor
Intf
;
373
Intf
.setPhysReg(Cache, Reg);
[
all
...]
RegAllocBasic.cpp
216
LiveInterval *
Intf
= Q.interferingVRegs()[i - 1];
217
if (!
Intf
->isSpillable() ||
Intf
->weight > VirtReg.weight)
219
Intfs.push_back(
Intf
);
/external/llvm/lib/CodeGen/
RegAllocGreedy.cpp
269
InterferenceCache::Cursor
Intf
;
278
Intf
.setPhysReg(Cache, Reg);
753
LiveInterval *
Intf
= Q.interferingVRegs()[i - 1];
754
assert(TargetRegisterInfo::isVirtualRegister(
Intf
->reg) &&
757
if (getStage(*
Intf
) == RS_Done)
766
(
Intf
->isSpillable() ||
768
RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(
Intf
->reg)));
770
unsigned IntfCascade = ExtraRegInfo[
Intf
->reg].Cascade;
779
bool BreaksHint = VRM->hasPreferredPhys(
Intf
->reg);
782
Cost.MaxWeight = std::max(Cost.MaxWeight,
Intf
->weight)
[
all
...]
RegAllocBasic.cpp
179
LiveInterval *
Intf
= Q.interferingVRegs()[i - 1];
180
if (!
Intf
->isSpillable() ||
Intf
->weight > VirtReg.weight)
182
Intfs.push_back(
Intf
);
Completed in 88 milliseconds