| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.h | 53 void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const;
|
| AVRRegisterInfo.cpp | 267 unsigned &LoReg,
271 LoReg = getSubReg(Reg, AVR::sub_lo);
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 89 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
97 BuildMI(MBB, I, dl, Mtc1Tdd, *SubReg).addReg(LoReg);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCopyToCombine.cpp | 734 unsigned LoReg = LoOperand.getReg();
745 .addReg(LoReg, LoRegKillFlag);
753 .addReg(LoReg, LoRegKillFlag);
760 .addReg(LoReg, LoRegKillFlag);
768 .addReg(LoReg, LoRegKillFlag);
772 // DoubleRegDest = combine #HiImm, LoReg
775 .addReg(LoReg, LoRegKillFlag);
833 unsigned LoReg = LoOperand.getReg();
840 // DoubleRegDest = combine HiReg, LoReg
843 .addReg(LoReg, LoRegKillFlag)
[all...] |
| HexagonFrameLowering.cpp | 827 unsigned LoReg = HRI.getSubReg(Reg, Hexagon::subreg_loreg);
829 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonCopyToCombine.cpp | 763 unsigned LoReg = LoOperand.getReg();
774 .addReg(LoReg, LoRegKillFlag);
782 .addReg(LoReg, LoRegKillFlag);
789 .addReg(LoReg, LoRegKillFlag);
797 .addReg(LoReg, LoRegKillFlag);
801 // DoubleRegDest = combine #HiImm, LoReg
804 .addReg(LoReg, LoRegKillFlag);
862 unsigned LoReg = LoOperand.getReg();
869 // DoubleRegDest = combine HiReg, LoReg
881 .addReg(LoReg, LoRegKillFlag)
[all...] |
| HexagonFrameLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstructionSelector.cpp | 362 unsigned LoReg = MRI.createVirtualRegister(RC);
366 BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg)
374 .addReg(LoReg)
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 284 unsigned LoReg = I->getOperand(1).getReg();
301 std::swap(LoReg, HiReg);
302 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
[all...] |
| MipsSEInstrInfo.cpp | 651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
680 .addReg(LoReg);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 309 unsigned LoReg = I->getOperand(1).getReg();
326 std::swap(LoReg, HiReg);
327 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
[all...] |
| MipsSEInstrInfo.cpp | 813 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
842 .addReg(LoReg);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 496 unsigned LoReg = MI.getOperand(0).getReg();
507 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg)
529 unsigned LoReg = MI.getOperand(1).getReg();
538 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill()))
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
