1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer (at) pengutronix.de> 4 */ 5 6 #ifndef __ASM_ARCH_MX31_IMX_REGS_H 7 #define __ASM_ARCH_MX31_IMX_REGS_H 8 9 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 10 #include <asm/types.h> 11 12 /* Clock control module registers */ 13 struct clock_control_regs { 14 u32 ccmr; 15 u32 pdr0; 16 u32 pdr1; 17 u32 rcsr; 18 u32 mpctl; 19 u32 upctl; 20 u32 spctl; 21 u32 cosr; 22 u32 cgr0; 23 u32 cgr1; 24 u32 cgr2; 25 u32 wimr0; 26 u32 ldc; 27 u32 dcvr0; 28 u32 dcvr1; 29 u32 dcvr2; 30 u32 dcvr3; 31 u32 ltr0; 32 u32 ltr1; 33 u32 ltr2; 34 u32 ltr3; 35 u32 ltbr0; 36 u32 ltbr1; 37 u32 pmcr0; 38 u32 pmcr1; 39 u32 pdr2; 40 }; 41 42 struct cspi_regs { 43 u32 rxdata; 44 u32 txdata; 45 u32 ctrl; 46 u32 intr; 47 u32 dma; 48 u32 stat; 49 u32 period; 50 u32 test; 51 }; 52 53 /* IIM control registers */ 54 struct iim_regs { 55 u32 iim_stat; 56 u32 iim_statm; 57 u32 iim_err; 58 u32 iim_emask; 59 u32 iim_fctl; 60 u32 iim_ua; 61 u32 iim_la; 62 u32 iim_sdat; 63 u32 iim_prev; 64 u32 iim_srev; 65 u32 iim_prg_p; 66 u32 iim_scs0; 67 u32 iim_scs1; 68 u32 iim_scs2; 69 u32 iim_scs3; 70 u32 res[0x1f1]; 71 struct fuse_bank { 72 u32 fuse_regs[0x20]; 73 u32 fuse_rsvd[0xe0]; 74 } bank[3]; 75 }; 76 77 struct fuse_bank0_regs { 78 u32 fuse0_5[6]; 79 u32 usr; 80 u32 fuse7_15[9]; 81 }; 82 83 struct fuse_bank2_regs { 84 u32 fuse0; 85 u32 uid[8]; 86 u32 fuse9_15[7]; 87 }; 88 89 struct iomuxc_regs { 90 u32 unused1; 91 u32 unused2; 92 u32 gpr; 93 }; 94 95 struct mx3_cpu_type { 96 u8 srev; 97 u32 v; 98 }; 99 100 #define IOMUX_PADNUM_MASK 0x1ff 101 #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) 102 103 /* 104 * various IOMUX pad functions 105 */ 106 enum iomux_pad_config { 107 PAD_CTL_NOLOOPBACK = 0x0 << 9, 108 PAD_CTL_LOOPBACK = 0x1 << 9, 109 PAD_CTL_PKE_NONE = 0x0 << 8, 110 PAD_CTL_PKE_ENABLE = 0x1 << 8, 111 PAD_CTL_PUE_KEEPER = 0x0 << 7, 112 PAD_CTL_PUE_PUD = 0x1 << 7, 113 PAD_CTL_100K_PD = 0x0 << 5, 114 PAD_CTL_100K_PU = 0x1 << 5, 115 PAD_CTL_47K_PU = 0x2 << 5, 116 PAD_CTL_22K_PU = 0x3 << 5, 117 PAD_CTL_HYS_CMOS = 0x0 << 4, 118 PAD_CTL_HYS_SCHMITZ = 0x1 << 4, 119 PAD_CTL_ODE_CMOS = 0x0 << 3, 120 PAD_CTL_ODE_OpenDrain = 0x1 << 3, 121 PAD_CTL_DRV_NORMAL = 0x0 << 1, 122 PAD_CTL_DRV_HIGH = 0x1 << 1, 123 PAD_CTL_DRV_MAX = 0x2 << 1, 124 PAD_CTL_SRE_SLOW = 0x0 << 0, 125 PAD_CTL_SRE_FAST = 0x1 << 0 126 }; 127 128 /* 129 * This enumeration is constructed based on the Section 130 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated 131 * value is constructed based on the rules described above. 132 */ 133 134 enum iomux_pins { 135 MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), 136 MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), 137 MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), 138 MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), 139 MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), 140 MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), 141 MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), 142 MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), 143 MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), 144 MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), 145 MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), 146 MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), 147 MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), 148 MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), 149 MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), 150 MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), 151 MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), 152 MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), 153 MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), 154 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), 155 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), 156 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), 157 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), 158 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), 159 MX31_PIN_READ = IOMUX_PIN(0xff, 24), 160 MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), 161 MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), 162 MX31_PIN_SER_RS = IOMUX_PIN(89, 27), 163 MX31_PIN_LCS1 = IOMUX_PIN(88, 28), 164 MX31_PIN_LCS0 = IOMUX_PIN(87, 29), 165 MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), 166 MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), 167 MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), 168 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), 169 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), 170 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), 171 MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), 172 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), 173 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), 174 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), 175 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), 176 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), 177 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), 178 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), 179 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), 180 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), 181 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), 182 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), 183 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), 184 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), 185 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), 186 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), 187 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), 188 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), 189 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), 190 MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), 191 MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), 192 MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), 193 MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), 194 MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), 195 MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), 196 MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), 197 MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), 198 MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), 199 MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), 200 MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), 201 MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), 202 MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), 203 MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), 204 MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), 205 MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), 206 MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), 207 MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), 208 MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), 209 MX31_PIN_USB_OC = IOMUX_PIN(30, 74), 210 MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), 211 MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), 212 MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), 213 MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), 214 MX31_PIN_TDO = IOMUX_PIN(0xff, 79), 215 MX31_PIN_TDI = IOMUX_PIN(0xff, 80), 216 MX31_PIN_TMS = IOMUX_PIN(0xff, 81), 217 MX31_PIN_TCK = IOMUX_PIN(0xff, 82), 218 MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), 219 MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), 220 MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), 221 MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), 222 MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), 223 MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), 224 MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), 225 MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), 226 MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), 227 MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), 228 MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), 229 MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), 230 MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), 231 MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), 232 MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), 233 MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), 234 MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), 235 MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), 236 MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), 237 MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), 238 MX31_PIN_TXD2 = IOMUX_PIN(28, 103), 239 MX31_PIN_RXD2 = IOMUX_PIN(27, 104), 240 MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), 241 MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), 242 MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), 243 MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), 244 MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), 245 MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), 246 MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), 247 MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), 248 MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), 249 MX31_PIN_CTS1 = IOMUX_PIN(39, 114), 250 MX31_PIN_RTS1 = IOMUX_PIN(38, 115), 251 MX31_PIN_TXD1 = IOMUX_PIN(37, 116), 252 MX31_PIN_RXD1 = IOMUX_PIN(36, 117), 253 MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), 254 MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), 255 MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), 256 MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), 257 MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), 258 MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), 259 MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), 260 MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), 261 MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), 262 MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), 263 MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), 264 MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), 265 MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), 266 MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), 267 MX31_PIN_SFS6 = IOMUX_PIN(26, 132), 268 MX31_PIN_SCK6 = IOMUX_PIN(25, 133), 269 MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), 270 MX31_PIN_STXD6 = IOMUX_PIN(23, 135), 271 MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), 272 MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), 273 MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), 274 MX31_PIN_STXD5 = IOMUX_PIN(21, 139), 275 MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), 276 MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), 277 MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), 278 MX31_PIN_STXD4 = IOMUX_PIN(19, 143), 279 MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), 280 MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), 281 MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), 282 MX31_PIN_STXD3 = IOMUX_PIN(17, 147), 283 MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), 284 MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), 285 MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), 286 MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), 287 MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), 288 MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), 289 MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), 290 MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), 291 MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), 292 MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), 293 MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), 294 MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), 295 MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), 296 MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), 297 MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), 298 MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), 299 MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), 300 MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), 301 MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), 302 MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), 303 MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), 304 MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), 305 MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), 306 MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), 307 MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), 308 MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), 309 MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), 310 MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), 311 MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), 312 MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), 313 MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), 314 MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), 315 MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), 316 MX31_PIN_D0 = IOMUX_PIN(0xff, 181), 317 MX31_PIN_D1 = IOMUX_PIN(0xff, 182), 318 MX31_PIN_D2 = IOMUX_PIN(0xff, 183), 319 MX31_PIN_D3 = IOMUX_PIN(0xff, 184), 320 MX31_PIN_D4 = IOMUX_PIN(0xff, 185), 321 MX31_PIN_D5 = IOMUX_PIN(0xff, 186), 322 MX31_PIN_D6 = IOMUX_PIN(0xff, 187), 323 MX31_PIN_D7 = IOMUX_PIN(0xff, 188), 324 MX31_PIN_D8 = IOMUX_PIN(0xff, 189), 325 MX31_PIN_D9 = IOMUX_PIN(0xff, 190), 326 MX31_PIN_D10 = IOMUX_PIN(0xff, 191), 327 MX31_PIN_D11 = IOMUX_PIN(0xff, 192), 328 MX31_PIN_D12 = IOMUX_PIN(0xff, 193), 329 MX31_PIN_D13 = IOMUX_PIN(0xff, 194), 330 MX31_PIN_D14 = IOMUX_PIN(0xff, 195), 331 MX31_PIN_D15 = IOMUX_PIN(0xff, 196), 332 MX31_PIN_NFRB = IOMUX_PIN(16, 197), 333 MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), 334 MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), 335 MX31_PIN_NFCLE = IOMUX_PIN(13, 200), 336 MX31_PIN_NFALE = IOMUX_PIN(12, 201), 337 MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), 338 MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), 339 MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), 340 MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), 341 MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), 342 MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), 343 MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), 344 MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), 345 MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), 346 MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), 347 MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), 348 MX31_PIN_CAS = IOMUX_PIN(0xff, 213), 349 MX31_PIN_RAS = IOMUX_PIN(0xff, 214), 350 MX31_PIN_RW = IOMUX_PIN(0xff, 215), 351 MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), 352 MX31_PIN_LBA = IOMUX_PIN(0xff, 217), 353 MX31_PIN_ECB = IOMUX_PIN(0xff, 218), 354 MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), 355 MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), 356 MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), 357 MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), 358 MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), 359 MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), 360 MX31_PIN_OE = IOMUX_PIN(0xff, 225), 361 MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), 362 MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), 363 MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), 364 MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), 365 MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), 366 MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), 367 MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), 368 MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), 369 MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), 370 MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), 371 MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), 372 MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), 373 MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), 374 MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), 375 MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), 376 MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), 377 MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), 378 MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), 379 MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), 380 MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), 381 MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), 382 MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), 383 MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), 384 MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), 385 MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), 386 MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), 387 MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), 388 MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), 389 MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), 390 MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), 391 MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), 392 MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), 393 MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), 394 MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), 395 MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), 396 MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), 397 MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), 398 MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), 399 MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), 400 MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), 401 MX31_PIN_A25 = IOMUX_PIN(0xff, 266), 402 MX31_PIN_A24 = IOMUX_PIN(0xff, 267), 403 MX31_PIN_A23 = IOMUX_PIN(0xff, 268), 404 MX31_PIN_A22 = IOMUX_PIN(0xff, 269), 405 MX31_PIN_A21 = IOMUX_PIN(0xff, 270), 406 MX31_PIN_A20 = IOMUX_PIN(0xff, 271), 407 MX31_PIN_A19 = IOMUX_PIN(0xff, 272), 408 MX31_PIN_A18 = IOMUX_PIN(0xff, 273), 409 MX31_PIN_A17 = IOMUX_PIN(0xff, 274), 410 MX31_PIN_A16 = IOMUX_PIN(0xff, 275), 411 MX31_PIN_A14 = IOMUX_PIN(0xff, 276), 412 MX31_PIN_A15 = IOMUX_PIN(0xff, 277), 413 MX31_PIN_A13 = IOMUX_PIN(0xff, 278), 414 MX31_PIN_A12 = IOMUX_PIN(0xff, 279), 415 MX31_PIN_A11 = IOMUX_PIN(0xff, 280), 416 MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), 417 MX31_PIN_A10 = IOMUX_PIN(0xff, 282), 418 MX31_PIN_A9 = IOMUX_PIN(0xff, 283), 419 MX31_PIN_A8 = IOMUX_PIN(0xff, 284), 420 MX31_PIN_A7 = IOMUX_PIN(0xff, 285), 421 MX31_PIN_A6 = IOMUX_PIN(0xff, 286), 422 MX31_PIN_A5 = IOMUX_PIN(0xff, 287), 423 MX31_PIN_A4 = IOMUX_PIN(0xff, 288), 424 MX31_PIN_A3 = IOMUX_PIN(0xff, 289), 425 MX31_PIN_A2 = IOMUX_PIN(0xff, 290), 426 MX31_PIN_A1 = IOMUX_PIN(0xff, 291), 427 MX31_PIN_A0 = IOMUX_PIN(0xff, 292), 428 MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), 429 MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), 430 MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), 431 MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), 432 MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), 433 MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), 434 MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), 435 MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), 436 MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), 437 MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), 438 MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), 439 MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), 440 MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), 441 MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), 442 MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), 443 MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), 444 MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), 445 MX31_PIN_SRX0 = IOMUX_PIN(34, 310), 446 MX31_PIN_STX0 = IOMUX_PIN(33, 311), 447 MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), 448 MX31_PIN_SRST0 = IOMUX_PIN(67, 313), 449 MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), 450 MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), 451 MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), 452 MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317), 453 MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318), 454 MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319), 455 MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320), 456 MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321), 457 MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322), 458 MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323), 459 MX31_PIN_PWMO = IOMUX_PIN(9, 324), 460 MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), 461 MX31_PIN_COMPARE = IOMUX_PIN(8, 326), 462 MX31_PIN_CAPTURE = IOMUX_PIN(7, 327), 463 }; 464 465 /* 466 * various IOMUX general purpose functions 467 */ 468 enum iomux_gp_func { 469 MUX_PGP_FIRI = 1 << 0, 470 MUX_DDR_MODE = 1 << 1, 471 MUX_PGP_CSPI_BB = 1 << 2, 472 MUX_PGP_ATA_1 = 1 << 3, 473 MUX_PGP_ATA_2 = 1 << 4, 474 MUX_PGP_ATA_3 = 1 << 5, 475 MUX_PGP_ATA_4 = 1 << 6, 476 MUX_PGP_ATA_5 = 1 << 7, 477 MUX_PGP_ATA_6 = 1 << 8, 478 MUX_PGP_ATA_7 = 1 << 9, 479 MUX_PGP_ATA_8 = 1 << 10, 480 MUX_PGP_UH2 = 1 << 11, 481 MUX_SDCTL_CSD0_SEL = 1 << 12, 482 MUX_SDCTL_CSD1_SEL = 1 << 13, 483 MUX_CSPI1_UART3 = 1 << 14, 484 MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, 485 MUX_TAMPER_DETECT_EN = 1 << 16, 486 MUX_PGP_USB_4WIRE = 1 << 17, 487 MUX_PGP_USB_COMMON = 1 << 18, 488 MUX_SDHC_MEMSTICK1 = 1 << 19, 489 MUX_SDHC_MEMSTICK2 = 1 << 20, 490 MUX_PGP_SPLL_BYP = 1 << 21, 491 MUX_PGP_UPLL_BYP = 1 << 22, 492 MUX_PGP_MSHC1_CLK_SEL = 1 << 23, 493 MUX_PGP_MSHC2_CLK_SEL = 1 << 24, 494 MUX_CSPI3_UART5_SEL = 1 << 25, 495 MUX_PGP_ATA_9 = 1 << 26, 496 MUX_PGP_USB_SUSPEND = 1 << 27, 497 MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, 498 MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, 499 MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, 500 MUX_CLKO_DDR_MODE = 1 << 31, 501 }; 502 503 /* Bit definitions for RCSR register in CCM */ 504 #define CCM_RCSR_NF16B (1 << 31) 505 #define CCM_RCSR_NFMS (1 << 30) 506 507 /* WEIM CS control registers */ 508 struct mx31_weim_cscr { 509 u32 upper; 510 u32 lower; 511 u32 additional; 512 u32 reserved; 513 }; 514 515 struct mx31_weim { 516 struct mx31_weim_cscr cscr[6]; 517 }; 518 519 /* ESD control registers */ 520 struct esdc_regs { 521 u32 ctl0; 522 u32 cfg0; 523 u32 ctl1; 524 u32 cfg1; 525 u32 misc; 526 u32 dly[5]; 527 u32 dlyl; 528 }; 529 530 #endif 531 532 #define ARCH_MXC 533 534 #define __REG(x) (*((volatile u32 *)(x))) 535 #define __REG16(x) (*((volatile u16 *)(x))) 536 #define __REG8(x) (*((volatile u8 *)(x))) 537 538 #define CCM_BASE 0x53f80000 539 #define CCM_CCMR (CCM_BASE + 0x00) 540 #define CCM_PDR0 (CCM_BASE + 0x04) 541 #define CCM_PDR1 (CCM_BASE + 0x08) 542 #define CCM_RCSR (CCM_BASE + 0x0c) 543 #define CCM_MPCTL (CCM_BASE + 0x10) 544 #define CCM_UPCTL (CCM_BASE + 0x14) 545 #define CCM_SPCTL (CCM_BASE + 0x18) 546 #define CCM_COSR (CCM_BASE + 0x1C) 547 #define CCM_CGR0 (CCM_BASE + 0x20) 548 #define CCM_CGR1 (CCM_BASE + 0x24) 549 #define CCM_CGR2 (CCM_BASE + 0x28) 550 551 #define CCMR_MDS (1 << 7) 552 #define CCMR_SBYCS (1 << 4) 553 #define CCMR_MPE (1 << 3) 554 #define CCMR_PRCS_MASK (3 << 1) 555 #define CCMR_FPM (1 << 1) 556 #define CCMR_CKIH (2 << 1) 557 558 #define MX31_IIM_BASE_ADDR 0x5001C000 559 #define IIM_BASE_ADDR MX31_IIM_BASE_ADDR 560 561 #define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26) 562 #define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23) 563 #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) 564 #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) 565 #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) 566 #define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) 567 #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) 568 #define PDR0_MCU_PODF(x) ((x) & 0x7) 569 570 #define PDR1_USB_PRDF(x) (((x) & 0x3) << 30) 571 #define PDR1_USB_PODF(x) (((x) & 0x7) << 27) 572 #define PDR1_FIRI_PRDF(x) (((x) & 0x7) << 24) 573 #define PDR1_FIRI_PODF(x) (((x) & 0x3f) << 18) 574 #define PDR1_SSI2_PRDF(x) (((x) & 0x7) << 15) 575 #define PDR1_SSI2_PODF(x) (((x) & 0x3f) << 9) 576 #define PDR1_SSI1_PRDF(x) (((x) & 0x7) << 6) 577 #define PDR1_SSI1_PODF(x) ((x) & 0x3f) 578 579 #define PLL_BRMO(x) (((x) & 0x1) << 31) 580 #define PLL_PD(x) (((x) & 0xf) << 26) 581 #define PLL_MFD(x) (((x) & 0x3ff) << 16) 582 #define PLL_MFI(x) (((x) & 0xf) << 10) 583 #define PLL_MFN(x) (((x) & 0x3ff) << 0) 584 585 #define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f) 586 #define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7) 587 #define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f) 588 #define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7) 589 #define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7) 590 #define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3) 591 #define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7) 592 #define GET_PDR0_MCU_PODF(x) ((x) & 0x7) 593 594 #define GET_PLL_PD(x) (((x) >> 26) & 0xf) 595 #define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff) 596 #define GET_PLL_MFI(x) (((x) >> 10) & 0xf) 597 #define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff) 598 599 600 #define WEIM_ESDCTL0 0xB8001000 601 #define WEIM_ESDCFG0 0xB8001004 602 #define WEIM_ESDCTL1 0xB8001008 603 #define WEIM_ESDCFG1 0xB800100C 604 #define WEIM_ESDMISC 0xB8001010 605 606 #define UART1_BASE 0x43F90000 607 #define UART2_BASE 0x43F94000 608 #define UART3_BASE 0x5000C000 609 #define UART4_BASE 0x43FB0000 610 #define UART5_BASE 0x43FB4000 611 612 #define I2C1_BASE_ADDR 0x43f80000 613 #define I2C1_CLK_OFFSET 26 614 #define I2C2_BASE_ADDR 0x43F98000 615 #define I2C2_CLK_OFFSET 28 616 #define I2C3_BASE_ADDR 0x43f84000 617 #define I2C3_CLK_OFFSET 30 618 619 #define ESDCTL_SDE (1 << 31) 620 #define ESDCTL_CMD_RW (0 << 28) 621 #define ESDCTL_CMD_PRECHARGE (1 << 28) 622 #define ESDCTL_CMD_AUTOREFRESH (2 << 28) 623 #define ESDCTL_CMD_LOADMODEREG (3 << 28) 624 #define ESDCTL_CMD_MANUALREFRESH (4 << 28) 625 #define ESDCTL_ROW_13 (2 << 24) 626 #define ESDCTL_ROW(x) ((x) << 24) 627 #define ESDCTL_COL_9 (1 << 20) 628 #define ESDCTL_COL(x) ((x) << 20) 629 #define ESDCTL_DSIZ(x) ((x) << 16) 630 #define ESDCTL_SREFR(x) ((x) << 13) 631 #define ESDCTL_PWDT(x) ((x) << 10) 632 #define ESDCTL_FP(x) ((x) << 8) 633 #define ESDCTL_BL(x) ((x) << 7) 634 #define ESDCTL_PRCT(x) ((x) << 0) 635 636 #define ESDCTL_BASE_ADDR 0xB8001000 637 638 /* 13 fields of the upper CS control register */ 639 #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ 640 cnc, wsc, ew, wws, edc) \ 641 ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ 642 (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ 643 (wws) << 4 | (edc) << 0) 644 /* 12 fields of the lower CS control register */ 645 #define CSCR_L(oea, oen, ebwa, ebwn, \ 646 csa, ebc, dsz, csn, psr, cre, wrap, csen) \ 647 ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ 648 (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ 649 (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) 650 /* 14 fields of the additional CS control register */ 651 #define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ 652 wwu, age, cnc2, fce) \ 653 ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ 654 (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ 655 (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ 656 (age) << 2 | (cnc2) << 1 | (fce) << 0) 657 658 #define WEIM_BASE 0xb8002000 659 660 #define IOMUXC_BASE 0x43FAC000 661 #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) 662 #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) 663 664 #define IPU_BASE 0x53fc0000 665 #define IPU_CONF IPU_BASE 666 667 #define IPU_CONF_PXL_ENDIAN (1<<8) 668 #define IPU_CONF_DU_EN (1<<7) 669 #define IPU_CONF_DI_EN (1<<6) 670 #define IPU_CONF_ADC_EN (1<<5) 671 #define IPU_CONF_SDC_EN (1<<4) 672 #define IPU_CONF_PF_EN (1<<3) 673 #define IPU_CONF_ROT_EN (1<<2) 674 #define IPU_CONF_IC_EN (1<<1) 675 #define IPU_CONF_CSI_EN (1<<0) 676 677 #define ARM_PPMRR 0x40000015 678 679 #define WDOG1_BASE_ADDR 0x53FDC000 680 681 /* 682 * GPIO 683 */ 684 #define GPIO1_BASE_ADDR 0x53FCC000 685 #define GPIO2_BASE_ADDR 0x53FD0000 686 #define GPIO3_BASE_ADDR 0x53FA4000 687 #define GPIO_DR 0x00000000 /* data register */ 688 #define GPIO_GDIR 0x00000004 /* direction register */ 689 #define GPIO_PSR 0x00000008 /* pad status register */ 690 691 /* 692 * Signal Multiplexing (IOMUX) 693 */ 694 695 /* bits in the SW_MUX_CTL registers */ 696 #define MUX_CTL_OUT_GPIO_DR (0 << 4) 697 #define MUX_CTL_OUT_FUNC (1 << 4) 698 #define MUX_CTL_OUT_ALT1 (2 << 4) 699 #define MUX_CTL_OUT_ALT2 (3 << 4) 700 #define MUX_CTL_OUT_ALT3 (4 << 4) 701 #define MUX_CTL_OUT_ALT4 (5 << 4) 702 #define MUX_CTL_OUT_ALT5 (6 << 4) 703 #define MUX_CTL_OUT_ALT6 (7 << 4) 704 #define MUX_CTL_IN_NONE (0 << 0) 705 #define MUX_CTL_IN_GPIO (1 << 0) 706 #define MUX_CTL_IN_FUNC (2 << 0) 707 #define MUX_CTL_IN_ALT1 (4 << 0) 708 #define MUX_CTL_IN_ALT2 (8 << 0) 709 710 #define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) 711 #define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) 712 #define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) 713 #define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) 714 715 /* Register offsets based on IOMUXC_BASE */ 716 /* 0x00 .. 0x7b */ 717 #define MUX_CTL_CSPI3_MISO 0x0c 718 #define MUX_CTL_CSPI3_SCLK 0x0d 719 #define MUX_CTL_CSPI3_SPI_RDY 0x0e 720 #define MUX_CTL_CSPI3_MOSI 0x13 721 722 #define MUX_CTL_SD1_DATA1 0x18 723 #define MUX_CTL_SD1_DATA2 0x19 724 #define MUX_CTL_SD1_DATA3 0x1a 725 #define MUX_CTL_SD1_CMD 0x1d 726 #define MUX_CTL_SD1_CLK 0x1e 727 #define MUX_CTL_SD1_DATA0 0x1f 728 729 #define MUX_CTL_USBH2_DATA1 0x40 730 #define MUX_CTL_USBH2_DIR 0x44 731 #define MUX_CTL_USBH2_STP 0x45 732 #define MUX_CTL_USBH2_NXT 0x46 733 #define MUX_CTL_USBH2_DATA0 0x47 734 #define MUX_CTL_USBH2_CLK 0x4B 735 736 #define MUX_CTL_TXD2 0x70 737 #define MUX_CTL_RTS2 0x71 738 #define MUX_CTL_CTS2 0x72 739 #define MUX_CTL_RXD2 0x77 740 741 #define MUX_CTL_RTS1 0x7c 742 #define MUX_CTL_CTS1 0x7d 743 #define MUX_CTL_DTR_DCE1 0x7e 744 #define MUX_CTL_DSR_DCE1 0x7f 745 #define MUX_CTL_CSPI2_SCLK 0x80 746 #define MUX_CTL_CSPI2_SPI_RDY 0x81 747 #define MUX_CTL_RXD1 0x82 748 #define MUX_CTL_TXD1 0x83 749 #define MUX_CTL_CSPI2_MISO 0x84 750 #define MUX_CTL_CSPI2_SS0 0x85 751 #define MUX_CTL_CSPI2_SS1 0x86 752 #define MUX_CTL_CSPI2_SS2 0x87 753 #define MUX_CTL_CSPI1_SS2 0x88 754 #define MUX_CTL_CSPI1_SCLK 0x89 755 #define MUX_CTL_CSPI1_SPI_RDY 0x8a 756 #define MUX_CTL_CSPI2_MOSI 0x8b 757 #define MUX_CTL_CSPI1_MOSI 0x8c 758 #define MUX_CTL_CSPI1_MISO 0x8d 759 #define MUX_CTL_CSPI1_SS0 0x8e 760 #define MUX_CTL_CSPI1_SS1 0x8f 761 #define MUX_CTL_STXD6 0x90 762 #define MUX_CTL_SRXD6 0x91 763 #define MUX_CTL_SCK6 0x92 764 #define MUX_CTL_SFS6 0x93 765 766 #define MUX_CTL_STXD3 0x9C 767 #define MUX_CTL_SRXD3 0x9D 768 #define MUX_CTL_SCK3 0x9E 769 #define MUX_CTL_SFS3 0x9F 770 771 #define MUX_CTL_NFC_WP 0xD0 772 #define MUX_CTL_NFC_CE 0xD1 773 #define MUX_CTL_NFC_RB 0xD2 774 #define MUX_CTL_NFC_WE 0xD4 775 #define MUX_CTL_NFC_RE 0xD5 776 #define MUX_CTL_NFC_ALE 0xD6 777 #define MUX_CTL_NFC_CLE 0xD7 778 779 780 #define MUX_CTL_CAPTURE 0x150 781 #define MUX_CTL_COMPARE 0x151 782 783 /* 784 * Helper macros for the MUX_[contact name]__[pin function] macros 785 */ 786 #define IOMUX_MODE_POS 9 787 #define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact)) 788 789 /* 790 * These macros can be used in mx31_gpio_mux() and have the form 791 * MUX_[contact name]__[pin function] 792 */ 793 #define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC) 794 #define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC) 795 #define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) 796 #define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) 797 798 #define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC) 799 #define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC) 800 #define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC) 801 #define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC) 802 803 #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) 804 #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) 805 #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) 806 #define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC) 807 #define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC) 808 #define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \ 809 IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC) 810 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC) 811 812 #define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC) 813 #define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC) 814 #define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC) 815 #define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC) 816 #define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC) 817 #define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \ 818 IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC) 819 #define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC) 820 821 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) 822 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1) 823 824 /* PAD control registers for SDR/DDR */ 825 #define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C) 826 #define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270) 827 #define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274) 828 #define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278) 829 #define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C) 830 #define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280) 831 #define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284) 832 #define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288) 833 #define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C) 834 #define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290) 835 #define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294) 836 #define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298) 837 #define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C) 838 #define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0) 839 #define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4) 840 #define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8) 841 #define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC) 842 #define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0) 843 #define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4) 844 #define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8) 845 #define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC) 846 #define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0) 847 #define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4) 848 #define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8) 849 #define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC) 850 #define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0) 851 #define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4) 852 #define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8) 853 #define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC) 854 855 /* 856 * Memory regions and CS 857 */ 858 #define IPU_MEM_BASE 0x70000000 859 #define CSD0_BASE 0x80000000 860 #define CSD1_BASE 0x90000000 861 #define CS0_BASE 0xA0000000 862 #define CS1_BASE 0xA8000000 863 #define CS2_BASE 0xB0000000 864 #define CS3_BASE 0xB2000000 865 #define CS4_BASE 0xB4000000 866 #define CS4_PSRAM_BASE 0xB5000000 867 #define CS5_BASE 0xB6000000 868 #define PCMCIA_MEM_BASE 0xC0000000 869 870 /* 871 * NAND controller 872 */ 873 #define NFC_BASE_ADDR 0xB8000000 874 875 /* SD card controller */ 876 #define SDHC1_BASE_ADDR 0x50004000 877 #define SDHC2_BASE_ADDR 0x50008000 878 879 /* 880 * Internal RAM (16KB) 881 */ 882 #define IRAM_BASE_ADDR 0x1FFFC000 883 #define IRAM_SIZE (16 * 1024) 884 885 #define MX31_AIPS1_BASE_ADDR 0x43f00000 886 #define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) 887 #define IMX_USB_PORT_OFFSET 0x200 888 889 /* 890 * CSPI register definitions 891 */ 892 #define MXC_CSPI 893 #define MXC_CSPICTRL_EN (1 << 0) 894 #define MXC_CSPICTRL_MODE (1 << 1) 895 #define MXC_CSPICTRL_XCH (1 << 2) 896 #define MXC_CSPICTRL_SMC (1 << 3) 897 #define MXC_CSPICTRL_POL (1 << 4) 898 #define MXC_CSPICTRL_PHA (1 << 5) 899 #define MXC_CSPICTRL_SSCTL (1 << 6) 900 #define MXC_CSPICTRL_SSPOL (1 << 7) 901 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) 902 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) 903 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) 904 #define MXC_CSPICTRL_TC (1 << 8) 905 #define MXC_CSPICTRL_RXOVF (1 << 6) 906 #define MXC_CSPICTRL_MAXBITS 0x1f 907 908 #define MXC_CSPIPERIOD_32KHZ (1 << 15) 909 #define MAX_SPI_BYTES 4 910 911 912 #define MXC_SPI_BASE_ADDRESSES \ 913 0x43fa4000, \ 914 0x50010000, \ 915 0x53f84000, 916 917 /* 918 * Generic timer support 919 */ 920 #ifdef CONFIG_MX31_CLK32 921 #define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32 922 #else 923 #define CONFIG_SYS_TIMER_RATE 32768 924 #endif 925 926 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */ 927
