1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ 7 #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ 8 9 #define MXC_CCM_BASE CCM_BASE_ADDR 10 11 /* DPLL register mapping structure */ 12 struct mxc_pll_reg { 13 u32 ctrl; 14 u32 config; 15 u32 op; 16 u32 mfd; 17 u32 mfn; 18 u32 mfn_minus; 19 u32 mfn_plus; 20 u32 hfs_op; 21 u32 hfs_mfd; 22 u32 hfs_mfn; 23 u32 mfn_togc; 24 u32 destat; 25 }; 26 27 /* Register maping of CCM*/ 28 struct mxc_ccm_reg { 29 u32 ccr; /* 0x0000 */ 30 u32 ccdr; 31 u32 csr; 32 u32 ccsr; 33 u32 cacrr; /* 0x0010*/ 34 u32 cbcdr; 35 u32 cbcmr; 36 u32 cscmr1; 37 u32 cscmr2; /* 0x0020 */ 38 u32 cscdr1; 39 u32 cs1cdr; 40 u32 cs2cdr; 41 u32 cdcdr; /* 0x0030 */ 42 u32 chsccdr; 43 u32 cscdr2; 44 u32 cscdr3; 45 u32 cscdr4; /* 0x0040 */ 46 u32 cwdr; 47 u32 cdhipr; 48 u32 cdcr; 49 u32 ctor; /* 0x0050 */ 50 u32 clpcr; 51 u32 cisr; 52 u32 cimr; 53 u32 ccosr; /* 0x0060 */ 54 u32 cgpr; 55 u32 CCGR0; 56 u32 CCGR1; 57 u32 CCGR2; /* 0x0070 */ 58 u32 CCGR3; 59 u32 CCGR4; 60 u32 CCGR5; 61 u32 CCGR6; /* 0x0080 */ 62 #ifdef CONFIG_MX53 63 u32 CCGR7; /* 0x0084 */ 64 #endif 65 u32 cmeor; 66 }; 67 68 /* Define the bits in register CCR */ 69 #define MXC_CCM_CCR_COSC_EN (0x1 << 12) 70 #if defined(CONFIG_MX51) 71 #define MXC_CCM_CCR_FPM_MULT (0x1 << 11) 72 #endif 73 #define MXC_CCM_CCR_CAMP2_EN (0x1 << 10) 74 #define MXC_CCM_CCR_CAMP1_EN (0x1 << 9) 75 #if defined(CONFIG_MX51) 76 #define MXC_CCM_CCR_FPM_EN (0x1 << 8) 77 #endif 78 #define MXC_CCM_CCR_OSCNT_OFFSET 0 79 #define MXC_CCM_CCR_OSCNT_MASK 0xFF 80 #define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF) 81 #define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF) 82 83 /* Define the bits in register CCSR */ 84 #if defined(CONFIG_MX51) 85 #define MXC_CCM_CCSR_LP_APM (0x1 << 9) 86 #elif defined(CONFIG_MX53) 87 #define MXC_CCM_CCSR_LP_APM (0x1 << 10) 88 #define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9) 89 #endif 90 #define MXC_CCM_CCSR_STEP_SEL_OFFSET 7 91 #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) 92 #define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7) 93 #define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3) 94 #define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5 95 #define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5) 96 #define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5) 97 #define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3) 98 #define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3 99 #define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3) 100 #define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3) 101 #define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3) 102 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2) 103 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1) 104 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1 105 106 /* Define the bits in register CACRR */ 107 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 108 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 109 #define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7) 110 #define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7) 111 112 /* Define the bits in register CBCDR */ 113 #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) 114 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 115 #define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) 116 #define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27) 117 #define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7) 118 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) 119 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) 120 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 121 #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) 122 #define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22) 123 #define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7) 124 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 125 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) 126 #define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19) 127 #define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7) 128 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 129 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) 130 #define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16) 131 #define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7) 132 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 133 #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) 134 #define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13) 135 #define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7) 136 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 137 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 138 #define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10) 139 #define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7) 140 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 141 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 142 #define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8) 143 #define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3) 144 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 145 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) 146 #define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6) 147 #define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3) 148 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 149 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) 150 #define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3) 151 #define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7) 152 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 153 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 154 #define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7) 155 #define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7) 156 157 /* Define the bits in register CSCMR1 */ 158 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 159 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) 160 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30) 161 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3) 162 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 163 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) 164 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28) 165 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3) 166 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) 167 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 168 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) 169 #define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24) 170 #define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3) 171 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 172 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) 173 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22) 174 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3) 175 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 176 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) 177 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20) 178 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3) 179 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) 180 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) 181 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 182 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) 183 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16) 184 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3) 185 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 186 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) 187 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14) 188 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3) 189 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 190 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 191 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12) 192 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3) 193 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) 194 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) 195 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 196 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) 197 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8) 198 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3) 199 #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) 200 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) 201 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 202 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) 203 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4) 204 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3) 205 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 206 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) 207 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2) 208 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3) 209 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) 210 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 211 212 /* Define the bits in register CSCMR2 */ 213 #define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET 26 214 #define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK (0x7 << 26) 215 #define MXC_CCM_CSCMR2_DI0_CLK_SEL(v) (((v) & 0x7) << 26) 216 #define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r) (((r) >> 26) & 0x7) 217 218 #define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5 219 220 /* Define the bits in register CSCDR2 */ 221 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 222 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) 223 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25) 224 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7) 225 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 226 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) 227 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19) 228 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F) 229 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 230 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) 231 #define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16) 232 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7) 233 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 234 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) 235 #define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9) 236 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F) 237 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 238 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6) 239 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6) 240 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7) 241 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0 242 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F 243 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F) 244 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F) 245 246 /* Define the bits in register CBCMR */ 247 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 248 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 249 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14) 250 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3) 251 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 252 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) 253 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12) 254 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3) 255 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 256 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) 257 #define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10) 258 #define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3) 259 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 260 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) 261 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8) 262 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3) 263 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 264 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) 265 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6) 266 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3) 267 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 268 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) 269 #define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4) 270 #define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3) 271 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) 272 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) 273 274 /* Define the bits in register CSCDR1 */ 275 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 276 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) 277 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22) 278 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7) 279 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 280 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) 281 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19) 282 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7) 283 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 284 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) 285 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16) 286 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7) 287 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 288 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) 289 #define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14) 290 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3) 291 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 292 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) 293 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11) 294 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7) 295 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 296 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 297 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8) 298 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7) 299 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 300 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 301 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6) 302 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3) 303 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 304 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) 305 #define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3) 306 #define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7) 307 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 308 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 309 #define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7) 310 #define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7) 311 312 /* Define the bits in register CCDR */ 313 #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) 314 315 /* Define the bits in register CGPR */ 316 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) 317 318 /* Define the bits in register CCGRx */ 319 #define MXC_CCM_CCGR_CG_MASK 0x3 320 #define MXC_CCM_CCGR_CG_OFF 0x0 321 #define MXC_CCM_CCGR_CG_RUN_ON 0x1 322 #define MXC_CCM_CCGR_CG_ON 0x3 323 324 #define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0 325 #define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0) 326 #define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2 327 #define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2) 328 #define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4 329 #define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4) 330 #define MXC_CCM_CCGR0_TZIC_OFFSET 6 331 #define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6) 332 #define MXC_CCM_CCGR0_DAP_OFFSET 8 333 #define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8) 334 #define MXC_CCM_CCGR0_TPIU_OFFSET 10 335 #define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10) 336 #define MXC_CCM_CCGR0_CTI2_OFFSET 12 337 #define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12) 338 #define MXC_CCM_CCGR0_CTI3_OFFSET 14 339 #define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14) 340 #define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16 341 #define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16) 342 #define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18 343 #define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18) 344 #define MXC_CCM_CCGR0_ROMCP_OFFSET 20 345 #define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20) 346 #define MXC_CCM_CCGR0_ROM_OFFSET 22 347 #define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22) 348 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24 349 #define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24) 350 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26 351 #define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26) 352 #define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28 353 #define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28) 354 #define MXC_CCM_CCGR0_IIM_OFFSET 30 355 #define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30) 356 357 #define MXC_CCM_CCGR1_TMAX1_OFFSET 0 358 #define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0) 359 #define MXC_CCM_CCGR1_TMAX2_OFFSET 2 360 #define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2) 361 #define MXC_CCM_CCGR1_TMAX3_OFFSET 4 362 #define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4) 363 #define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6 364 #define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6) 365 #define MXC_CCM_CCGR1_UART1_PER_OFFSET 8 366 #define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8) 367 #define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10 368 #define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10) 369 #define MXC_CCM_CCGR1_UART2_PER_OFFSET 12 370 #define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12) 371 #define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14 372 #define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14) 373 #define MXC_CCM_CCGR1_UART3_PER_OFFSET 16 374 #define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16) 375 #define MXC_CCM_CCGR1_I2C1_OFFSET 18 376 #define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18) 377 #define MXC_CCM_CCGR1_I2C2_OFFSET 20 378 #define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20) 379 #if defined(CONFIG_MX51) 380 #define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22 381 #define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22) 382 #define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24 383 #define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24) 384 #elif defined(CONFIG_MX53) 385 #define MXC_CCM_CCGR1_I2C3_OFFSET 22 386 #define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22) 387 #endif 388 #define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26 389 #define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26) 390 #define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28 391 #define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28) 392 #define MXC_CCM_CCGR1_SCC_OFFSET 30 393 #define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30) 394 395 #if defined(CONFIG_MX51) 396 #define MXC_CCM_CCGR2_USB_PHY_OFFSET 0 397 #define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0) 398 #endif 399 #define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2 400 #define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2) 401 #define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4 402 #define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4) 403 #define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6 404 #define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6) 405 #define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8 406 #define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8) 407 #define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10 408 #define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10) 409 #define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12 410 #define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12) 411 #define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14 412 #define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14) 413 #define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16 414 #define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16) 415 #define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18 416 #define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18) 417 #define MXC_CCM_CCGR2_GPT_HF_OFFSET 20 418 #define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20) 419 #define MXC_CCM_CCGR2_OWIRE_OFFSET 22 420 #define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22) 421 #define MXC_CCM_CCGR2_FEC_OFFSET 24 422 #define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24) 423 #define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26 424 #define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26) 425 #define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28 426 #define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28) 427 #define MXC_CCM_CCGR2_TVE_OFFSET 30 428 #define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30) 429 430 #define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0 431 #define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0) 432 #define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2 433 #define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2) 434 #define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4 435 #define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4) 436 #define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6 437 #define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6) 438 #define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8 439 #define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8) 440 #define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10 441 #define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10) 442 #define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12 443 #define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12) 444 #define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14 445 #define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14) 446 #define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16 447 #define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16) 448 #define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18 449 #define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18) 450 #define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20 451 #define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20) 452 #define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22 453 #define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22) 454 #define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24 455 #define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24) 456 #define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26 457 #define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26) 458 #define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28 459 #define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28) 460 #define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30 461 #define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30) 462 463 #define MXC_CCM_CCGR4_PATA_OFFSET 0 464 #define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0) 465 #if defined(CONFIG_MX51) 466 #define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2 467 #define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2) 468 #define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4 469 #define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4) 470 #elif defined(CONFIG_MX53) 471 #define MXC_CCM_CCGR4_SATA_OFFSET 2 472 #define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2) 473 #define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6 474 #define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6) 475 #define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8 476 #define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8) 477 #define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10 478 #define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10) 479 #define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12 480 #define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12) 481 #endif 482 #define MXC_CCM_CCGR4_SAHARA_OFFSET 14 483 #define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14) 484 #define MXC_CCM_CCGR4_RTIC_OFFSET 16 485 #define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16) 486 #define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18 487 #define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18) 488 #define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20 489 #define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20) 490 #define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22 491 #define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22) 492 #define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24 493 #define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24) 494 #define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26 495 #define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26) 496 #define MXC_CCM_CCGR4_SRTC_OFFSET 28 497 #define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28) 498 #define MXC_CCM_CCGR4_SDMA_OFFSET 30 499 #define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30) 500 501 #define MXC_CCM_CCGR5_SPBA_OFFSET 0 502 #define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0) 503 #define MXC_CCM_CCGR5_GPU_OFFSET 2 504 #define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2) 505 #define MXC_CCM_CCGR5_GARB_OFFSET 4 506 #define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4) 507 #define MXC_CCM_CCGR5_VPU_OFFSET 6 508 #define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6) 509 #define MXC_CCM_CCGR5_VPU_REF_OFFSET 8 510 #define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8) 511 #define MXC_CCM_CCGR5_IPU_OFFSET 10 512 #define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10) 513 #if defined(CONFIG_MX51) 514 #define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12 515 #define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12) 516 #elif defined(CONFIG_MX53) 517 #define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12 518 #define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12) 519 #endif 520 #define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14 521 #define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14) 522 #define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16 523 #define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16) 524 #define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18 525 #define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18) 526 #define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20 527 #define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20) 528 #define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22 529 #define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22) 530 #define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24 531 #define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24) 532 #define MXC_CCM_CCGR5_SPDIF0_OFFSET 26 533 #define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26) 534 #if defined(CONFIG_MX51) 535 #define MXC_CCM_CCGR5_SPDIF1_OFFSET 28 536 #define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28) 537 #endif 538 #define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30 539 #define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30) 540 541 #if defined(CONFIG_MX53) 542 #define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0 543 #define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0) 544 #define MXC_CCM_CCGR6_OCRAM_OFFSET 2 545 #define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2) 546 #endif 547 #define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4 548 #define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4) 549 #if defined(CONFIG_MX51) 550 #define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6 551 #define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6) 552 #define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8 553 #define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8) 554 #elif defined(CONFIG_MX53) 555 #define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8 556 #define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8) 557 #endif 558 #define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10 559 #define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10) 560 #define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12 561 #define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12) 562 #define MXC_CCM_CCGR6_GPU2D_OFFSET 14 563 #define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14) 564 #if defined(CONFIG_MX53) 565 #define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16 566 #define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16) 567 #define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18 568 #define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18) 569 #define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20 570 #define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20) 571 #define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22 572 #define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22) 573 #define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24 574 #define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24) 575 #define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26 576 #define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26) 577 #define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28 578 #define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28) 579 #define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30 580 #define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30) 581 582 #define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0 583 #define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0) 584 #define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2 585 #define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2) 586 #define MXC_CCM_CCGR7_MLB_OFFSET 4 587 #define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4) 588 #define MXC_CCM_CCGR7_IEEE1588_OFFSET 6 589 #define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6) 590 #define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8 591 #define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8) 592 #define MXC_CCM_CCGR7_UART4_PER_OFFSET 10 593 #define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10) 594 #define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12 595 #define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12) 596 #define MXC_CCM_CCGR7_UART5_PER_OFFSET 14 597 #define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14) 598 #endif 599 600 /* Define the bits in register CLPCR */ 601 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) 602 603 #define MXC_DPLLC_CTL_HFSM (1 << 7) 604 #define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) 605 606 #define MXC_DPLLC_OP_PDF_MASK 0xf 607 #define MXC_DPLLC_OP_MFI_OFFSET 4 608 #define MXC_DPLLC_OP_MFI_MASK (0xf << 4) 609 #define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4) 610 #define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf) 611 612 #define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff 613 614 #define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff 615 616 #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ 617
