| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64CondBrTuning.cpp | 11 /// into a conditional branch (B.cond), when the NZCV flags can be set for
90 // just make sure the implicit-def of NZCV isn't marked dead.
95 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
145 // We don't want NZCV bits live across blocks.
197 // reads NZCV.
200 if (I->modifiesRegister(AArch64::NZCV, TRI) ||
201 I->readsRegister(AArch64::NZCV, TRI))
256 // reads NZCV.
259 if (I->modifiesRegister(AArch64::NZCV, TRI) ||
260 I->readsRegister(AArch64::NZCV, TRI)
[all...] |
| AArch64ConditionalCompares.cpp | 64 STATISTIC(NumMultNZCVUses, "Number of ccmps rejected (NZCV used)");
65 STATISTIC(NumUnknNZCVDefs, "Number of ccmps rejected (NZCV def unknown)");
100 // operand that specifies the NZCV flag values when the condition is false and
123 // ccmp w1, #17, 4, ne ; 4 = nZcv
304 if (!I->readsRegister(AArch64::NZCV)) {
356 MIOperands(*I).analyzePhysReg(AArch64::NZCV, TRI);
385 // Reject any live-in physregs. It's probably NZCV/EFLAGS, and very hard to
428 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {
686 // The NZCV immediate operand should provide flags for the case where Head
689 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(CmpBBTailCC)
[all...] |
| AArch64ConditionOptimizer.cpp | 155 // Since we may modify cmp of this MBB, make sure NZCV does not live out.
157 if (SuccBB->isLiveIn(AArch64::NZCV))
164 // Check if there is any use of NZCV between CMP and Bcc.
165 if (I->readsRegister(AArch64::NZCV))
|
| AArch64InstrInfo.cpp | 433 // if NZCV is used, do not fold.
434 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
461 // if NZCV is used, do not fold.
462 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
[all...] |
| AArch64RedundantCopyElimination.cpp | 117 /// in \p MBB for some cases. Otherwise, we find and inspect the NZCV setting
120 /// \p MMB for some cases. In addition, if the NZCV setting instruction is
167 // Find compare instruction that sets NZCV used by CondBr.
197 // We've found the instruction that sets NZCV.
213 // The destination register must not be modified between the NZCV setting
223 // Look for NZCV setting instructions that define something other than
257 // The destination register of the NZCV setting instruction must not be
262 // We've found the instruction that sets NZCV whose DstReg == 0.
269 // Bail if we see an instruction that defines NZCV that we don't handle.
270 if (PredI.definesRegister(AArch64::NZCV))
[all...] |
| AArch64ExpandPseudoInsts.cpp | 631 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ConditionalCompares.cpp | 63 STATISTIC(NumMultNZCVUses, "Number of ccmps rejected (NZCV used)");
64 STATISTIC(NumUnknNZCVDefs, "Number of ccmps rejected (NZCV def unknown)");
99 // operand that specifies the NZCV flag values when the condition is false and
122 // ccmp w1, #17, 4, ne ; 4 = nZcv
300 if (!I->readsRegister(AArch64::NZCV)) {
351 MIOperands(*I).analyzePhysReg(AArch64::NZCV, TRI);
379 // Reject any live-in physregs. It's probably NZCV/EFLAGS, and very hard to
422 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {
643 // The NZCV immediate operand should provide flags for the case where Head
646 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(CmpBBTailCC)
[all...] |
| AArch64ConditionOptimizer.cpp | 146 // Since we may modify cmp of this MBB, make sure NZCV does not live out.
148 if (SuccBB->isLiveIn(AArch64::NZCV))
155 // Check if there is any use of NZCV between CMP and Bcc.
156 if (I->readsRegister(AArch64::NZCV))
|
| AArch64InstrInfo.cpp | 315 // if NZCV is used, do not fold.
316 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
342 // if NZCV is used, do not fold.
343 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
710 // Replace SUBSWrr with SUBWrr if NZCV is not used.
866 if ( ((AccessToCheck & AK_Write) && Instr.modifiesRegister(AArch64::NZCV, TRI)) ||
867 ((AccessToCheck & AK_Read) && Instr.readsRegister(AArch64::NZCV, TRI)))
874 /// instruction which produces AArch64::NZCV. It can be truly compare instruction
888 // Replace SUBSWrr with SUBWrr if NZCV is not used.
889 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true)
[all...] |
| AArch64ExpandPseudoInsts.cpp | 641 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
727 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
[all...] |
| /external/vixl/tools/test_generator/ |
| data_types.py | 408 class NZCV(U32):
410 Description of NZCV flags as inputs to an instruction.
413 and record the NZCV flags before and after emitting the instruction under
418 # When setting the `NZCV` flags, we need to make sure we do not override the
428 // Set the `NZCV` and `Q` flags together.
441 // Only record the NZCV bits.
458 # When clearing or setting the `Q` bit, we need to make sure the `NZCV`
465 // Save the `NZCV` flags.
468 // Set the `NZCV` and `Q` flags together.
|
| parser.py | 170 NZCV flags.
202 "type": "NZCV"
|
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | [all...] |
| test-utils-aarch64.cc | 526 __ Mrs(tmp, NZCV);
|
| test-simulator-aarch64.cc | 746 __ Mrs(flags, NZCV);
793 // Each NZCV result only requires 4 bits.
882 __ Mrs(flags, NZCV);
925 // Each NZCV result only requires 4 bits.
[all...] |
| /external/vixl/src/aarch64/ |
| simulator-aarch64.cc | 56 case NZCV:
119 nzcv_ = SimSystemRegister::DefaultValueFor(NZCV);
365 LogSystemRegister(NZCV);
480 LogSystemRegister(NZCV);
633 PrintSystemRegister(NZCV);
914 case NZCV:
[all...] |
| constants-aarch64.h | 101 V_(Nzcv, 3, 0, ExtractBits) \
179 /* NZCV */ \
185 M_(NZCV, Flags_mask) \
364 NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value,
[all...] |
| macro-assembler-aarch64.cc | [all...] |
| /external/v8/src/arm64/ |
| simulator-arm64.cc | 91 case NZCV:
349 nzcv_ = SimSystemRegister::DefaultValueFor(NZCV);
789 nzcv().SetN(CalcNFlag(result));
790 nzcv().SetZ(CalcZFlag(result));
794 nzcv().SetC((left > max_uint_2op) || ((max_uint_2op - left) < right));
802 nzcv().SetV((left_sign == right_sign) && (left_sign != result_sign));
804 LogSystemRegister(NZCV);
825 nzcv().C());
912 nzcv().SetRawValue(FPUnorderedFlag);
914 nzcv().SetRawValue(FPLessThanFlag)
[all...] |
| constants-arm64.h | 202 V_(Nzcv, 3, 0, Bits) \
271 /* NZCV */ \
277 M_(NZCV, Flags_mask) \
413 NZCV = ((0x1 << SysO0_offset) |
[all...] |
| disasm-arm64.cc | 3640 int nzcv = (instr->Nzcv() << Flags_offset); local
[all...] |
| macro-assembler-arm64.cc | 580 StatusFlags nzcv, Condition cond,
587 ConditionalCompareMacro(rn, temp, nzcv, cond, op);
594 ConditionalCompare(rn, operand, nzcv, cond, op);
602 ConditionalCompare(rn, temp, nzcv, cond, op);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| AArch64GenDAGISel.inc | [all...] |
| /external/llvm/test/MC/AArch64/ |
| basic-a64-instructions.s | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| basic-a64-instructions.s | [all...] |
