| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| PredicateExpander.h | 57 void expandCheckImmOperand(formatted_raw_ostream &OS, int OpIndex,
59 void expandCheckImmOperand(formatted_raw_ostream &OS, int OpIndex,
61 void expandCheckRegOperand(formatted_raw_ostream &OS, int OpIndex,
74 void expandCheckIsRegOperand(formatted_raw_ostream &OS, int OpIndex);
75 void expandCheckIsImmOperand(formatted_raw_ostream &OS, int OpIndex);
76 void expandCheckInvalidRegOperand(formatted_raw_ostream &OS, int OpIndex);
|
| PredicateExpander.cpp | 24 int OpIndex, int ImmVal) {
25 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
30 int OpIndex, StringRef ImmVal) {
31 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
36 int OpIndex, const Record *Reg) {
39 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
48 int OpIndex) {
49 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
153 int OpIndex) {
155 << "getOperand(" << OpIndex << ").isReg() "
[all...] |
| AsmWriterEmitter.cpp | 693 int OpIndex, PrintIndex;
694 std::tie(OpIndex, PrintIndex) = getOpData(Name);
697 OS << format("\\x%02X", (unsigned char)OpIndex + 1);
701 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1);
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsELFStreamer.cpp | 25 for (unsigned OpIndex = 0; OpIndex < Inst.getNumOperands(); ++OpIndex) {
26 const MCOperand &Op = Inst.getOperand(OpIndex);
|
| /external/swiftshader/third_party/LLVM/lib/MC/MCDisassembler/ |
| EDOperand.h | 39 unsigned int OpIndex;
47 /// @arg opIndex - The index of the operand in inst
51 unsigned int opIndex,
|
| EDOperand.cpp | 25 unsigned int opIndex,
29 OpIndex(opIndex),
35 uint8_t operandType = inst.ThisInstInfo->operandTypes[opIndex];
59 uint8_t operandType = inst.ThisInstInfo->operandTypes[opIndex];
127 uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex];
246 return(Inst.ThisInstInfo->operandFlags[OpIndex] == kOperandTypeRegister);
254 return(Inst.ThisInstInfo->operandFlags[OpIndex] == kOperandTypeImmediate);
262 uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex];
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsELFStreamer.cpp | 44 for (unsigned OpIndex = 0; OpIndex < Inst.getNumOperands(); ++OpIndex) {
45 const MCOperand &Op = Inst.getOperand(OpIndex);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/ |
| MCInstrDescView.cpp | 23 unsigned OpIndex = 0;
24 for (; OpIndex < MCInstrDesc.getNumOperands(); ++OpIndex) {
25 const auto &OpInfo = MCInstrDesc.opInfo_begin()[OpIndex];
27 Operand.Index = OpIndex;
28 Operand.IsDef = (OpIndex < MCInstrDesc.getNumDefs());
34 MCInstrDesc.getOperandConstraint(OpIndex, llvm::MCOI::TIED_TO);
39 MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) {
41 Operand.Index = OpIndex;
49 MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) {
[all...] |
| Assembler.cpp | 93 for (unsigned OpIndex = 0, E = Inst.getNumOperands(); OpIndex < E;
94 ++OpIndex) {
95 const llvm::MCOperand &Op = Inst.getOperand(OpIndex);
97 const bool IsDef = OpIndex < MCID.getNumDefs();
99 const llvm::MCOperandInfo &OpInfo = MCID.operands().begin()[OpIndex];
|
| Uops.cpp | 107 for (const unsigned OpIndex : Var.TiedOperands) {
108 const Operand &Op = Instr.Operands[OpIndex];
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/ |
| PTXInstPrinter.cpp | 61 int OpIndex;
65 OpIndex = 1;
68 OpIndex = MI->getNumOperands()-1;
71 int PredOp = MI->getOperand(OpIndex).getImm();
|
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| InstrBuilder.cpp | 196 Write.OpIndex = i;
211 dbgs() << "\t\t[Def] OpIdx=" << Write.OpIndex
226 Write.OpIndex = ~CurrentDef;
244 dbgs() << "\t\t[Def] OpIdx=" << Write.OpIndex
262 Write.OpIndex = MCI.getNumOperands() - 1;
300 Read.OpIndex = i + CurrentUse;
303 LLVM_DEBUG(dbgs() << "\t\t[Use] OpIdx=" << Read.OpIndex
309 Read.OpIndex = ~CurrentUse;
313 LLVM_DEBUG(dbgs() << "\t\t[Use] OpIdx=" << Read.OpIndex << ", RegisterID="
415 const MCOperand &Op = MCI.getOperand(RD.OpIndex);
[all...] |
| Instruction.h | 37 // a bitwise not of the OpIndex.
38 int OpIndex;
58 bool isImplicitWrite() const { return OpIndex < 0; };
65 // implicit read is the bitwise not of field OpIndex.
66 int OpIndex;
76 bool isImplicitRead() const { return OpIndex < 0; };
|
| Instruction.cpp | 96 dbgs() << "{ OpIdx=" << WD.OpIndex << ", Lat=" << getLatency() << ", RegID "
|
| /external/llvm/utils/TableGen/ |
| AsmWriterEmitter.cpp | 683 int OpIndex, PrintIndex;
684 std::tie(OpIndex, PrintIndex) = getOpData(Name);
687 OS << format("\\x%02X", (unsigned char)OpIndex + 1);
691 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| TypeBasedAliasAnalysis.cpp | 297 unsigned OpIndex = FirstFieldOpNo + FieldIndex * NumOpsPerField;
298 auto *TypeNode = cast<MDNode>(getNode()->getOperand(OpIndex));
|
| ScalarEvolution.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 511 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
512 MCOperand &MCO = MI.getOperand(OpIndex);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 345 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
346 MCOperand &MCO = MI.getOperand(OpIndex);
[all...] |
| /external/llvm/lib/Analysis/ |
| ScalarEvolution.cpp | [all...] |
