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    Searched refs:OpRC (Results 1 - 9 of 9) sorted by null

  /external/swiftshader/third_party/LLVM/lib/CodeGen/
MachineRegisterInfo.cpp 82 const TargetRegisterClass *OpRC =
84 if (OpRC)
85 NewRC = TRI->getCommonSubClass(NewRC, OpRC);
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
BreakFalseDeps.cpp 126 const TargetRegisterClass *OpRC =
133 !OpRC->contains(CurrMO.getReg()))
145 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
MachineInstr.cpp 721 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
727 if (OpRC)
728 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
731 } else if (OpRC)
732 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 333 const TargetRegisterClass *OpRC = nullptr;
335 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
337 if (OpRC) {
339 = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
341 OpRC = TRI->getAllocatableClass(OpRC);
342 assert(OpRC && "Constraints cannot be fulfilled for allocation");
343 unsigned NewVReg = MRI->createVirtualRegister(OpRC);
399 const TargetRegisterClass *OpRC =
405 if (OpRC && IIRC && OpRC != IIRC &
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
X86SpeculativeLoadHardening.cpp     [all...]
  /external/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp     [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp     [all...]
  /external/llvm/lib/CodeGen/
MachineInstr.cpp     [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
HexagonBitSimplify.cpp     [all...]

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