| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 50 /// The OpSize field from the record
51 uint8_t OpSize;
117 /// @param OpSize Indicates the operand size of the instruction.
118 /// If register size does not match OpSize, then
122 bool hasREX_WPrefix, uint8_t OpSize);
129 /// @param OpSize - Indicates whether this is an OpSize16 instruction.
133 uint8_t OpSize);
138 uint8_t OpSize);
143 uint8_t OpSize);
145 uint8_t OpSize);
[all...] |
| X86RecognizableInstr.cpp | 211 OpSize = byteFromRec(Rec, "OpSizeBits");
419 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
423 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
425 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
427 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
429 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
446 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
448 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
450 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
452 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 172 /// The OpSize field from the record
173 uint8_t OpSize;
237 /// @param OpSize Indicates the operand size of the instruction.
238 /// If register size does not match OpSize, then
242 bool hasREX_WPrefix, uint8_t OpSize);
249 /// @param OpSize - Indicates whether this is an OpSize16 instruction.
253 uint8_t OpSize);
258 uint8_t OpSize);
263 uint8_t OpSize);
265 uint8_t OpSize);
[all...] |
| X86RecognizableInstr.cpp | 83 OpSize = byteFromRec(Rec, "OpSizeBits");
304 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
308 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
310 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
314 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
316 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
333 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
335 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
343 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
345 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD
[all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 44 uint32_t getLitEncoding(const MCOperand &MO, unsigned OpSize) const;
164 unsigned OpSize) const {
183 if (OpSize == 4)
186 assert(OpSize == 8);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsInstructionSelector.cpp | 133 const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
135 if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMLegalizerInfo.cpp | 349 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
354 auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
366 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
367 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
|
| ARMInstructionSelector.cpp | 354 unsigned OpSize)
356 OperandRegBankID(OpRegBank), OperandSize(OpSize) {}
[all...] |
| /external/llvm/lib/IR/ |
| Metadata.cpp | 445 size_t OpSize = NumOps * sizeof(MDOperand);
448 OpSize = alignTo(OpSize, llvm::alignOf<uint64_t>());
449 void *Ptr = reinterpret_cast<char *>(::operator new(OpSize + Size)) + OpSize;
458 size_t OpSize = N->NumOperands * sizeof(MDOperand);
459 OpSize = alignTo(OpSize, llvm::alignOf<uint64_t>());
464 ::operator delete(reinterpret_cast<char *>(Mem) - OpSize);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| LegalizerHelper.cpp | 343 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
347 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
362 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
365 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
396 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
400 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
418 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
423 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
427 if (ExtractOffset != 0 || SegSize != OpSize) {
[all...] |
| MachineIRBuilder.cpp | 442 unsigned OpSize = OpTy.getSizeInBits();
445 if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
451 if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
|
| /external/llvm/include/llvm/Analysis/ |
| TargetTransformInfoImpl.h | 76 unsigned OpSize = OpTy->getScalarSizeInBits();
77 if (DL.isLegalInteger(OpSize) &&
78 OpSize <= DL.getPointerTypeSizeInBits(Ty))
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64RegisterBankInfo.cpp | 540 SmallVector<unsigned, 4> OpSize(NumOperands);
548 OpSize[Idx] = Ty.getSizeInBits();
581 OpSize[0]);
641 auto Mapping = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
|
| AArch64InstructionSelector.cpp | 220 /// and of size \p OpSize.
223 unsigned OpSize) {
226 if (OpSize == 32) {
237 } else if (OpSize == 64) {
253 switch (OpSize) {
290 /// size \p OpSize. This returns the variant with the base+unsigned-immediate
294 unsigned OpSize) {
298 switch (OpSize) {
310 switch (OpSize) {
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIFoldOperands.cpp | 317 unsigned OpSize = TII->getOpSize(MI, 1);
329 if (FoldingImm && !TII->isInlineConstant(OpToFold, OpSize) &&
|
| SIInstrInfo.h | 376 bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
377 bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
389 unsigned OpSize) const;
|
| SIInstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/ |
| Metadata.cpp | 482 size_t OpSize = NumOps * sizeof(MDOperand);
485 OpSize = alignTo(OpSize, alignof(uint64_t));
486 void *Ptr = reinterpret_cast<char *>(::operator new(OpSize + Size)) + OpSize;
495 size_t OpSize = N->NumOperands * sizeof(MDOperand);
496 OpSize = alignTo(OpSize, alignof(uint64_t));
501 ::operator delete(reinterpret_cast<char *>(Mem) - OpSize);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 256 // OpSize - Set if this instruction requires an operand size prefix (0x66),
259 OpSize = 1 << 6,
|
| X86MCCodeEmitter.cpp | 452 if (TSFlags & X86II::OpSize)
771 if (TSFlags & X86II::OpSize)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Analysis/ |
| TargetTransformInfoImpl.h | 77 unsigned OpSize = OpTy->getScalarSizeInBits();
78 if (DL.isLegalInteger(OpSize) &&
79 OpSize <= DL.getPointerTypeSizeInBits(Ty))
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 558 int64_t OpSize = MFI.getObjectSize(FI);
563 OpSize = SubRegSize / 8;
566 MemSize = std::max(MemSize, OpSize);
[all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | 676 unsigned OpSize = DL.getTypeSizeInBits(Op0->getType());
681 return ConstantInt::get(Op0->getType(), Offs1.zextOrTrunc(OpSize) -
682 Offs2.zextOrTrunc(OpSize));
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| ConstantFolding.cpp | 720 unsigned OpSize = DL.getTypeSizeInBits(Op0->getType());
725 return ConstantInt::get(Op0->getType(), Offs1.zextOrTrunc(OpSize) -
726 Offs2.zextOrTrunc(OpSize));
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86CodeEmitter.cpp | 651 if (Desc->TSFlags & X86II::OpSize)
[all...] |
