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  /external/protobuf/python/google/protobuf/
text_encoding.py 74 # PY3 hack: make Ord work for str and bytes:
76 Ord = ord if isinstance(text, six.string_types) else lambda x: x
78 return ''.join(_cescape_utf8_to_str[Ord(c)] for c in text)
79 return ''.join(_cescape_byte_to_str[Ord(c)] for c in text)
103 result = ''.join(_cescape_highbit_to_str[ord(c)] for c in result)
  /external/antlr/runtime/Delphi/Sources/Antlr3.Runtime.Tests/
Antlr.Runtime.Tests.pas 117 CheckEquals(Ord('e'), Stream.LA(1));
121 CheckEquals(Ord('O'), Stream.LA(1));
127 CheckEquals(Ord('n'), Stream.LA(1));
133 CheckEquals(Ord('e'), Stream.LA(1));
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
RISCVISelLowering.h 76 AtomicOrdering Ord) const override;
78 AtomicOrdering Ord) const override;
RISCVISelLowering.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMISelLowering.h 441 AtomicOrdering Ord) const override;
443 Value *Addr, AtomicOrdering Ord) const override;
447 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
449 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
  /external/llvm/lib/Target/Hexagon/
HexagonISelLowering.h 255 AtomicOrdering Ord) const override;
257 Value *Addr, AtomicOrdering Ord) const override;
HexagonGenInsert.cpp 213 // - ref1 < ref2, if ord(ref1.Reg) < ord(ref2.Reg),
214 // or ord(ref1.Reg) == ord(ref2.Reg), and ref1.Pos < ref2.Pos.
361 OrderedRegisterList(const RegisterOrdering &RO) : Ord(RO) {}
383 const RegisterOrdering &Ord;
411 iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord);
420 iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord);
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
LocalStackSlotAllocation.cpp 62 FrameRef(MachineInstr *I, int64_t Offset, int Idx, unsigned Ord) :
63 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {}
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAGHVX.cpp 107 Coloring(ArrayRef<Node> Ord) : Order(Ord) {
332 PermNetwork(ArrayRef<ElemType> Ord, unsigned Mult = 1) {
333 Order.assign(Ord.data(), Ord.data()+Ord.size());
380 ForwardDeltaNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord) {}
394 ReverseDeltaNetwork(ArrayRef<ElemType> Ord) : PermNetwork(Ord) {}
    [all...]
HexagonISelLowering.h 303 AtomicOrdering Ord) const override;
305 Value *Addr, AtomicOrdering Ord) const override;
HexagonGenInsert.cpp 229 // - ref1 < ref2, if ord(ref1.Reg) < ord(ref2.Reg),
230 // or ord(ref1.Reg) == ord(ref2.Reg), and ref1.Pos < ref2.Pos.
384 : MaxSize(MaxORLSize), Ord(RO) {}
411 const RegisterOrdering &Ord;
440 iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord);
453 iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord);
    [all...]
  /external/llvm/include/llvm/Target/
TargetLowering.h     [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
ARMISelLowering.h 512 AtomicOrdering Ord) const override;
514 Value *Addr, AtomicOrdering Ord) const override;
519 AtomicOrdering Ord) const override;
521 AtomicOrdering Ord) const override;
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp 534 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
535 for (auto Reg : Ord) {
AArch64ISelLowering.h 347 AtomicOrdering Ord) const override;
349 Value *Addr, AtomicOrdering Ord) const override;
  /external/spirv-llvm/lib/SPIRV/
SPIRVToOCL20.cpp 362 [](unsigned Ord) { return mapSPIRVMemOrderToOCL(Ord); });
OCL20ToSPIRV.cpp 797 [](unsigned Ord) {
798 return mapOCLMemSemanticToSPIRV(0, static_cast<OCLMemOrderKind>(Ord));
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
TargetLowering.h     [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp 521 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
522 for (auto Reg : Ord) {
AArch64ISelLowering.h 379 AtomicOrdering Ord) const override;
381 Value *Addr, AtomicOrdering Ord) const override;
  /external/antlr/runtime/Delphi/Sources/Antlr3.Runtime/
Antlr.Runtime.Tree.pas     [all...]
  /external/llvm/lib/Target/PowerPC/
PPCISelLowering.h 577 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
579 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/ObjectYAML/
CodeViewYAMLSymbols.cpp 168 ThunkOrdinal &Ord) {
171 io.enumCase(Ord, E.Name.str().c_str(), static_cast<ThunkOrdinal>(E.Value));
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
PPCISelLowering.h 686 AtomicOrdering Ord) const override;
688 AtomicOrdering Ord) const override;
    [all...]
  /external/llvm/lib/DebugInfo/CodeView/
SymbolDumper.cpp 112 W.printEnum("Ordinal", Thunk.Header.Ord, getThunkOrdinalNames());

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