1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2006-2008 4 * Texas Instruments, <www.ti.com> 5 * Richard Woodruff <r-woodruff2 (at) ti.com> 6 */ 7 #ifndef _CLOCKS_OMAP3_H_ 8 #define _CLOCKS_OMAP3_H_ 9 10 #define PLL_STOP 1 /* PER & IVA */ 11 #define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ 12 #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ 13 #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ 14 15 /* 16 * The following configurations are OPP and SysClk value independant 17 * and hence are defined here. All the other DPLL related values are 18 * tabulated in lowlevel_init.S. 19 */ 20 21 /* CORE DPLL */ 22 #define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ 23 #define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ 24 #define CORE_FUSB_DIV 2 /* 41.5MHz: */ 25 #define CORE_L4_DIV 2 /* 83MHz : L4 */ 26 #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ 27 #define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ 28 #define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */ 29 #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ 30 31 /* PER DPLL */ 32 #define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ 33 #define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ 34 #define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ 35 #define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ 36 37 #define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) 38 39 /* MPU DPLL */ 40 41 #define MPU_M_12_ES1 0x0FE 42 #define MPU_N_12_ES1 0x07 43 #define MPU_FSEL_12_ES1 0x05 44 #define MPU_M2_12_ES1 0x01 45 46 #define MPU_M_12_ES2 0x0FA 47 #define MPU_N_12_ES2 0x05 48 #define MPU_FSEL_12_ES2 0x07 49 #define MPU_M2_ES2 0x01 50 51 #define MPU_M_12 0x085 52 #define MPU_N_12 0x05 53 #define MPU_FSEL_12 0x07 54 #define MPU_M2_12 0x01 55 56 #define MPU_M_13_ES1 0x17D 57 #define MPU_N_13_ES1 0x0C 58 #define MPU_FSEL_13_ES1 0x03 59 #define MPU_M2_13_ES1 0x01 60 61 #define MPU_M_13_ES2 0x258 62 #define MPU_N_13_ES2 0x0C 63 #define MPU_FSEL_13_ES2 0x03 64 #define MPU_M2_13_ES2 0x01 65 66 #define MPU_M_13 0x10A 67 #define MPU_N_13 0x0C 68 #define MPU_FSEL_13 0x03 69 #define MPU_M2_13 0x01 70 71 #define MPU_M_19P2_ES1 0x179 72 #define MPU_N_19P2_ES1 0x12 73 #define MPU_FSEL_19P2_ES1 0x04 74 #define MPU_M2_19P2_ES1 0x01 75 76 #define MPU_M_19P2_ES2 0x271 77 #define MPU_N_19P2_ES2 0x17 78 #define MPU_FSEL_19P2_ES2 0x03 79 #define MPU_M2_19P2_ES2 0x01 80 81 #define MPU_M_19P2 0x14C 82 #define MPU_N_19P2 0x17 83 #define MPU_FSEL_19P2 0x03 84 #define MPU_M2_19P2 0x01 85 86 #define MPU_M_26_ES1 0x17D 87 #define MPU_N_26_ES1 0x19 88 #define MPU_FSEL_26_ES1 0x03 89 #define MPU_M2_26_ES1 0x01 90 91 #define MPU_M_26_ES2 0x0FA 92 #define MPU_N_26_ES2 0x0C 93 #define MPU_FSEL_26_ES2 0x07 94 #define MPU_M2_26_ES2 0x01 95 96 #define MPU_M_26 0x085 97 #define MPU_N_26 0x0C 98 #define MPU_FSEL_26 0x07 99 #define MPU_M2_26 0x01 100 101 #define MPU_M_38P4_ES1 0x1FA 102 #define MPU_N_38P4_ES1 0x32 103 #define MPU_FSEL_38P4_ES1 0x03 104 #define MPU_M2_38P4_ES1 0x01 105 106 #define MPU_M_38P4_ES2 0x271 107 #define MPU_N_38P4_ES2 0x2F 108 #define MPU_FSEL_38P4_ES2 0x03 109 #define MPU_M2_38P4_ES2 0x01 110 111 #define MPU_M_38P4 0x14C 112 #define MPU_N_38P4 0x2F 113 #define MPU_FSEL_38P4 0x03 114 #define MPU_M2_38P4 0x01 115 116 /* IVA DPLL */ 117 118 #define IVA_M_12_ES1 0x07D 119 #define IVA_N_12_ES1 0x05 120 #define IVA_FSEL_12_ES1 0x07 121 #define IVA_M2_12_ES1 0x01 122 123 #define IVA_M_12_ES2 0x0B4 124 #define IVA_N_12_ES2 0x05 125 #define IVA_FSEL_12_ES2 0x07 126 #define IVA_M2_12_ES2 0x01 127 128 #define IVA_M_12 0x085 129 #define IVA_N_12 0x05 130 #define IVA_FSEL_12 0x07 131 #define IVA_M2_12 0x01 132 133 #define IVA_M_13_ES1 0x0FA 134 #define IVA_N_13_ES1 0x0C 135 #define IVA_FSEL_13_ES1 0x03 136 #define IVA_M2_13_ES1 0x01 137 138 #define IVA_M_13_ES2 0x168 139 #define IVA_N_13_ES2 0x0C 140 #define IVA_FSEL_13_ES2 0x03 141 #define IVA_M2_13_ES2 0x01 142 143 #define IVA_M_13 0x10A 144 #define IVA_N_13 0x0C 145 #define IVA_FSEL_13 0x03 146 #define IVA_M2_13 0x01 147 148 #define IVA_M_19P2_ES1 0x082 149 #define IVA_N_19P2_ES1 0x09 150 #define IVA_FSEL_19P2_ES1 0x07 151 #define IVA_M2_19P2_ES1 0x01 152 153 #define IVA_M_19P2_ES2 0x0E1 154 #define IVA_N_19P2_ES2 0x0B 155 #define IVA_FSEL_19P2_ES2 0x06 156 #define IVA_M2_19P2_ES2 0x01 157 158 #define IVA_M_19P2 0x14C 159 #define IVA_N_19P2 0x17 160 #define IVA_FSEL_19P2 0x03 161 #define IVA_M2_19P2 0x01 162 163 #define IVA_M_26_ES1 0x07D 164 #define IVA_N_26_ES1 0x0C 165 #define IVA_FSEL_26_ES1 0x07 166 #define IVA_M2_26_ES1 0x01 167 168 #define IVA_M_26_ES2 0x0B4 169 #define IVA_N_26_ES2 0x0C 170 #define IVA_FSEL_26_ES2 0x07 171 #define IVA_M2_26_ES2 0x01 172 173 #define IVA_M_26 0x085 174 #define IVA_N_26 0x0C 175 #define IVA_FSEL_26 0x07 176 #define IVA_M2_26 0x01 177 178 #define IVA_M_38P4_ES1 0x13F 179 #define IVA_N_38P4_ES1 0x30 180 #define IVA_FSEL_38P4_ES1 0x03 181 #define IVA_M2_38P4_ES1 0x01 182 183 #define IVA_M_38P4_ES2 0x0E1 184 #define IVA_N_38P4_ES2 0x17 185 #define IVA_FSEL_38P4_ES2 0x06 186 #define IVA_M2_38P4_ES2 0x01 187 188 #define IVA_M_38P4 0x14C 189 #define IVA_N_38P4 0x2F 190 #define IVA_FSEL_38P4 0x03 191 #define IVA_M2_38P4 0x01 192 193 /* CORE DPLL */ 194 195 #define CORE_M_12 0xA6 196 #define CORE_N_12 0x05 197 #define CORE_FSEL_12 0x07 198 #define CORE_M2_12 0x01 /* M3 of 2 */ 199 200 #define CORE_M_12_ES1 0x19F 201 #define CORE_N_12_ES1 0x0E 202 #define CORE_FSL_12_ES1 0x03 203 #define CORE_M2_12_ES1 0x1 /* M3 of 2 */ 204 205 #define CORE_M_13 0x14C 206 #define CORE_N_13 0x0C 207 #define CORE_FSEL_13 0x03 208 #define CORE_M2_13 0x01 /* M3 of 2 */ 209 210 #define CORE_M_13_ES1 0x1B2 211 #define CORE_N_13_ES1 0x10 212 #define CORE_FSL_13_ES1 0x03 213 #define CORE_M2_13_ES1 0x01 /* M3 of 2 */ 214 215 #define CORE_M_19P2 0x19F 216 #define CORE_N_19P2 0x17 217 #define CORE_FSEL_19P2 0x03 218 #define CORE_M2_19P2 0x01 /* M3 of 2 */ 219 220 #define CORE_M_19P2_ES1 0x19F 221 #define CORE_N_19P2_ES1 0x17 222 #define CORE_FSL_19P2_ES1 0x03 223 #define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ 224 225 #define CORE_M_26 0xA6 226 #define CORE_N_26 0x0C 227 #define CORE_FSEL_26 0x07 228 #define CORE_M2_26 0x01 /* M3 of 2 */ 229 230 #define CORE_M_26_ES1 0x1B2 231 #define CORE_N_26_ES1 0x21 232 #define CORE_FSL_26_ES1 0x03 233 #define CORE_M2_26_ES1 0x01 /* M3 of 2 */ 234 235 #define CORE_M_38P4 0x19F 236 #define CORE_N_38P4 0x2F 237 #define CORE_FSEL_38P4 0x03 238 #define CORE_M2_38P4 0x01 /* M3 of 2 */ 239 240 #define CORE_M_38P4_ES1 0x19F 241 #define CORE_N_38P4_ES1 0x2F 242 #define CORE_FSL_38P4_ES1 0x03 243 #define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ 244 245 /* PER DPLL */ 246 247 #define PER_M_12 0xD8 248 #define PER_N_12 0x05 249 #define PER_FSEL_12 0x07 250 #define PER_M2_12 0x09 251 252 #define PER_M_13 0x1B0 253 #define PER_N_13 0x0C 254 #define PER_FSEL_13 0x03 255 #define PER_M2_13 0x09 256 257 #define PER_M_19P2 0xE1 258 #define PER_N_19P2 0x09 259 #define PER_FSEL_19P2 0x07 260 #define PER_M2_19P2 0x09 261 262 #define PER_M_26 0xD8 263 #define PER_N_26 0x0C 264 #define PER_FSEL_26 0x07 265 #define PER_M2_26 0x09 266 267 #define PER_M_38P4 0xE1 268 #define PER_N_38P4 0x13 269 #define PER_FSEL_38P4 0x07 270 #define PER_M2_38P4 0x09 271 272 /* PER2 DPLL */ 273 #define PER2_M_12 0x78 274 #define PER2_N_12 0x0B 275 #define PER2_FSEL_12 0x03 276 #define PER2_M2_12 0x01 277 278 #define PER2_M_13 0x78 279 #define PER2_N_13 0x0C 280 #define PER2_FSEL_13 0x03 281 #define PER2_M2_13 0x01 282 283 #define PER2_M_19P2 0x2EE 284 #define PER2_N_19P2 0x0B 285 #define PER2_FSEL_19P2 0x06 286 #define PER2_M2_19P2 0x0A 287 288 #define PER2_M_26 0x78 289 #define PER2_N_26 0x0C 290 #define PER2_FSEL_26 0x03 291 #define PER2_M2_26 0x01 292 293 #define PER2_M_38P4 0x2EE 294 #define PER2_N_38P4 0x0B 295 #define PER2_FSEL_38P4 0x06 296 #define PER2_M2_38P4 0x0A 297 298 /* 36XX PER DPLL */ 299 300 #define PER_36XX_M_12 0x1B0 301 #define PER_36XX_N_12 0x05 302 #define PER_36XX_FSEL_12 0x07 303 #define PER_36XX_M2_12 0x09 304 305 #define PER_36XX_M_13 0x360 306 #define PER_36XX_N_13 0x0C 307 #define PER_36XX_FSEL_13 0x03 308 #define PER_36XX_M2_13 0x09 309 310 #define PER_36XX_M_19P2 0x1C2 311 #define PER_36XX_N_19P2 0x09 312 #define PER_36XX_FSEL_19P2 0x07 313 #define PER_36XX_M2_19P2 0x09 314 315 #define PER_36XX_M_26 0x1B0 316 #define PER_36XX_N_26 0x0C 317 #define PER_36XX_FSEL_26 0x07 318 #define PER_36XX_M2_26 0x09 319 320 #define PER_36XX_M_38P4 0x1C2 321 #define PER_36XX_N_38P4 0x13 322 #define PER_36XX_FSEL_38P4 0x07 323 #define PER_36XX_M2_38P4 0x09 324 325 /* 36XX PER2 DPLL */ 326 327 #define PER2_36XX_M_12 0x50 328 #define PER2_36XX_N_12 0x00 329 #define PER2_36XX_M2_12 0x08 330 331 #define PER2_36XX_M_13 0x1BB 332 #define PER2_36XX_N_13 0x05 333 #define PER2_36XX_M2_13 0x08 334 335 #define PER2_36XX_M_19P2 0x32 336 #define PER2_36XX_N_19P2 0x00 337 #define PER2_36XX_M2_19P2 0x08 338 339 #define PER2_36XX_M_26 0x1BB 340 #define PER2_36XX_N_26 0x0B 341 #define PER2_36XX_M2_26 0x08 342 343 #define PER2_36XX_M_38P4 0x19 344 #define PER2_36XX_N_38P4 0x00 345 #define PER2_36XX_M2_38P4 0x08 346 347 #endif /* endif _CLOCKS_OMAP3_H_ */ 348
