1 /** @file 2 * 3 * Copyright (c) 2011, ARM Limited. All rights reserved. 4 * 5 * This program and the accompanying materials 6 * are licensed and made available under the terms and conditions of the BSD License 7 * which accompanies this distribution. The full text of the license may be found at 8 * http://opensource.org/licenses/bsd-license.php 9 * 10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 **/ 14 15 #include <Library/IoLib.h> 16 #include <Library/DebugLib.h> 17 18 #define PL301_QOS_TIDEMARK_MI_0 0x400 19 #define PL301_QOS_ACCESSCONTROL_MI_0 0x404 20 21 #define PL301_QOS_TIDEMARK_MI_1 0x420 22 #define PL301_QOS_ACCESSCONTROL_MI_1 0x424 23 24 #define PL301_QOS_TIDEMARK_MI_2 0x440 25 #define PL301_QOS_ACCESSCONTROL_MI_2 0x444 26 27 #define PL301_AR_ARB_MI_0 0x408 28 #define PL301_AW_ARB_MI_0 0x40C 29 30 #define PL301_AR_ARB_MI_1 0x428 31 #define PL301_AW_ARB_MI_1 0x42C 32 33 #define PL301_AR_ARB_MI_2 0x448 34 #define PL301_AW_ARB_MI_2 0x44C 35 36 #define PL301_MI_1_OFFSET 0x20 37 #define PL301_MI_2_OFFSET 0x40 38 #define PL301_MI_3_OFFSET 0x60 39 #define PL301_MI_4_OFFSET 0x80 40 #define PL301_MI_5_OFFSET 0xa0 41 42 #define V2P_CA9_FAXI_MI0_TIDEMARK_VAL 0x6 43 #define V2P_CA9_FAXI_MI0_ACCESSCNTRL_VAL 0x1 44 45 #define V2P_CA9_FAXI_MI1_TIDEMARK_VAL 0x6 46 #define V2P_CA9_FAXI_MI1_ACCESSCNTRL_VAL 0x1 47 48 #define V2P_CA9_FAXI_MI2_TIDEMARK_VAL 0x6 49 #define V2P_CA9_FAXI_MI2_ACCESSCNTRL_VAL 0x1 50 51 52 #define FAxiWriteReg(reg,val) MmioWrite32(FAxiBase + reg, val) 53 #define FAxiReadReg(reg) MmioRead32(FAxiBase + reg) 54 55 // IN FAxiBase 56 // Initialize PL301 Dynamic Memory Controller 57 VOID PL301AxiInit(UINTN FAxiBase) { 58 // Configure Tidemark Register for Master Port 0 (MI 0) 59 FAxiWriteReg(PL301_QOS_TIDEMARK_MI_0, V2P_CA9_FAXI_MI0_TIDEMARK_VAL); 60 61 // Configure the Access Control Register (MI 0) 62 FAxiWriteReg(PL301_QOS_ACCESSCONTROL_MI_0, V2P_CA9_FAXI_MI0_ACCESSCNTRL_VAL); 63 64 // MP0 65 // Set priority for Read 66 FAxiWriteReg(PL301_AR_ARB_MI_0, 0x00000100); 67 FAxiWriteReg(PL301_AR_ARB_MI_0, 0x01000200); 68 FAxiWriteReg(PL301_AR_ARB_MI_0, 0x02000200); 69 FAxiWriteReg(PL301_AR_ARB_MI_0, 0x03000200); 70 FAxiWriteReg(PL301_AR_ARB_MI_0, 0x04000200); 71 72 // Set priority for Write 73 FAxiWriteReg(PL301_AW_ARB_MI_0, 0x00000100); 74 FAxiWriteReg(PL301_AW_ARB_MI_0, 0x01000200); 75 FAxiWriteReg(PL301_AW_ARB_MI_0, 0x02000200); 76 FAxiWriteReg(PL301_AW_ARB_MI_0, 0x03000200); 77 FAxiWriteReg(PL301_AW_ARB_MI_0, 0x04000200); 78 79 // MP1 80 // Set priority for Read 81 FAxiWriteReg(PL301_AR_ARB_MI_1, 0x00000100); 82 FAxiWriteReg(PL301_AR_ARB_MI_1, 0x01000200); 83 FAxiWriteReg(PL301_AR_ARB_MI_1, 0x02000200); 84 FAxiWriteReg(PL301_AR_ARB_MI_1, 0x03000200); 85 FAxiWriteReg(PL301_AR_ARB_MI_1, 0x04000200); 86 87 // Set priority for Write 88 FAxiWriteReg(PL301_AW_ARB_MI_1, 0x00000100); 89 FAxiWriteReg(PL301_AW_ARB_MI_1, 0x01000200); 90 FAxiWriteReg(PL301_AW_ARB_MI_1, 0x02000200); 91 FAxiWriteReg(PL301_AW_ARB_MI_1, 0x03000200); 92 FAxiWriteReg(PL301_AW_ARB_MI_1, 0x04000200); 93 94 // MP2 95 // Set priority for Read 96 FAxiWriteReg(PL301_AR_ARB_MI_2, 0x00000100); 97 FAxiWriteReg(PL301_AR_ARB_MI_2, 0x01000100); 98 FAxiWriteReg(PL301_AR_ARB_MI_2, 0x02000100); 99 FAxiWriteReg(PL301_AR_ARB_MI_2, 0x03000100); 100 FAxiWriteReg(PL301_AR_ARB_MI_2, 0x04000100); 101 102 // Set priority for Write 103 FAxiWriteReg(PL301_AW_ARB_MI_2, 0x00000100); 104 FAxiWriteReg(PL301_AW_ARB_MI_2, 0x01000200); 105 FAxiWriteReg(PL301_AW_ARB_MI_2, 0x02000200); 106 FAxiWriteReg(PL301_AW_ARB_MI_2, 0x03000200); 107 FAxiWriteReg(PL301_AW_ARB_MI_2, 0x04000200); 108 } 109
