Home | History | Annotate | Download | only in arch-mxs
      1 /* SPDX-License-Identifier: GPL-2.0+ */
      2 /*
      3  * Freescale i.MX28 Power Controller Register Definitions
      4  *
      5  * Copyright (C) 2011 Marek Vasut <marek.vasut (at) gmail.com>
      6  */
      7 
      8 #ifndef __MX28_REGS_POWER_H__
      9 #define __MX28_REGS_POWER_H__
     10 
     11 #include <asm/mach-imx/regs-common.h>
     12 
     13 #ifndef	__ASSEMBLY__
     14 struct mxs_power_regs {
     15 	mxs_reg_32(hw_power_ctrl)
     16 	mxs_reg_32(hw_power_5vctrl)
     17 	mxs_reg_32(hw_power_minpwr)
     18 	mxs_reg_32(hw_power_charge)
     19 	uint32_t	hw_power_vdddctrl;
     20 	uint32_t	reserved_vddd[3];
     21 	uint32_t	hw_power_vddactrl;
     22 	uint32_t	reserved_vdda[3];
     23 	uint32_t	hw_power_vddioctrl;
     24 	uint32_t	reserved_vddio[3];
     25 	uint32_t	hw_power_vddmemctrl;
     26 	uint32_t	reserved_vddmem[3];
     27 	uint32_t	hw_power_dcdc4p2;
     28 	uint32_t	reserved_dcdc4p2[3];
     29 	uint32_t	hw_power_misc;
     30 	uint32_t	reserved_misc[3];
     31 	uint32_t	hw_power_dclimits;
     32 	uint32_t	reserved_dclimits[3];
     33 	mxs_reg_32(hw_power_loopctrl)
     34 	uint32_t	hw_power_sts;
     35 	uint32_t	reserved_sts[3];
     36 	mxs_reg_32(hw_power_speed)
     37 	uint32_t	hw_power_battmonitor;
     38 	uint32_t	reserved_battmonitor[3];
     39 
     40 	uint32_t	reserved[4];
     41 
     42 	mxs_reg_32(hw_power_reset)
     43 	mxs_reg_32(hw_power_debug)
     44 	mxs_reg_32(hw_power_thermal)
     45 	mxs_reg_32(hw_power_usb1ctrl)
     46 	mxs_reg_32(hw_power_special)
     47 	mxs_reg_32(hw_power_version)
     48 	mxs_reg_32(hw_power_anaclkctrl)
     49 	mxs_reg_32(hw_power_refctrl)
     50 };
     51 #endif
     52 
     53 #define	POWER_CTRL_PSWITCH_MID_TRAN			(1 << 27)
     54 #define	POWER_CTRL_DCDC4P2_BO_IRQ			(1 << 24)
     55 #define	POWER_CTRL_ENIRQ_DCDC4P2_BO			(1 << 23)
     56 #define	POWER_CTRL_VDD5V_DROOP_IRQ			(1 << 22)
     57 #define	POWER_CTRL_ENIRQ_VDD5V_DROOP			(1 << 21)
     58 #define	POWER_CTRL_PSWITCH_IRQ				(1 << 20)
     59 #define	POWER_CTRL_PSWITCH_IRQ_SRC			(1 << 19)
     60 #define	POWER_CTRL_POLARITY_PSWITCH			(1 << 18)
     61 #define	POWER_CTRL_ENIRQ_PSWITCH			(1 << 17)
     62 #define	POWER_CTRL_POLARITY_DC_OK			(1 << 16)
     63 #define	POWER_CTRL_DC_OK_IRQ				(1 << 15)
     64 #define	POWER_CTRL_ENIRQ_DC_OK				(1 << 14)
     65 #define	POWER_CTRL_BATT_BO_IRQ				(1 << 13)
     66 #define	POWER_CTRL_ENIRQ_BATT_BO			(1 << 12)
     67 #define	POWER_CTRL_VDDIO_BO_IRQ				(1 << 11)
     68 #define	POWER_CTRL_ENIRQ_VDDIO_BO			(1 << 10)
     69 #define	POWER_CTRL_VDDA_BO_IRQ				(1 << 9)
     70 #define	POWER_CTRL_ENIRQ_VDDA_BO			(1 << 8)
     71 #define	POWER_CTRL_VDDD_BO_IRQ				(1 << 7)
     72 #define	POWER_CTRL_ENIRQ_VDDD_BO			(1 << 6)
     73 #define	POWER_CTRL_POLARITY_VBUSVALID			(1 << 5)
     74 #define	POWER_CTRL_VBUS_VALID_IRQ			(1 << 4)
     75 #define	POWER_CTRL_ENIRQ_VBUS_VALID			(1 << 3)
     76 #define	POWER_CTRL_POLARITY_VDD5V_GT_VDDIO		(1 << 2)
     77 #define	POWER_CTRL_VDD5V_GT_VDDIO_IRQ			(1 << 1)
     78 #define	POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO			(1 << 0)
     79 
     80 #define	POWER_5VCTRL_VBUSDROOP_TRSH_MASK		(0x3 << 30)
     81 #define	POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET		30
     82 #define	POWER_5VCTRL_VBUSDROOP_TRSH_4V3			(0x0 << 30)
     83 #define	POWER_5VCTRL_VBUSDROOP_TRSH_4V4			(0x1 << 30)
     84 #define	POWER_5VCTRL_VBUSDROOP_TRSH_4V5			(0x2 << 30)
     85 #define	POWER_5VCTRL_VBUSDROOP_TRSH_4V7			(0x3 << 30)
     86 #define	POWER_5VCTRL_HEADROOM_ADJ_MASK			(0x7 << 24)
     87 #define	POWER_5VCTRL_HEADROOM_ADJ_OFFSET		24
     88 #define	POWER_5VCTRL_PWD_CHARGE_4P2_MASK		(0x3 << 20)
     89 #define	POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET		20
     90 #define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK		(0x3f << 12)
     91 #define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET		12
     92 #define	POWER_5VCTRL_VBUSVALID_TRSH_MASK		(0x7 << 8)
     93 #define	POWER_5VCTRL_VBUSVALID_TRSH_OFFSET		8
     94 #define	POWER_5VCTRL_VBUSVALID_TRSH_2V9			(0x0 << 8)
     95 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V0			(0x1 << 8)
     96 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V1			(0x2 << 8)
     97 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V2			(0x3 << 8)
     98 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V3			(0x4 << 8)
     99 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V4			(0x5 << 8)
    100 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V5			(0x6 << 8)
    101 #define	POWER_5VCTRL_VBUSVALID_TRSH_4V6			(0x7 << 8)
    102 #define	POWER_5VCTRL_PWDN_5VBRNOUT			(1 << 7)
    103 #define	POWER_5VCTRL_ENABLE_LINREG_ILIMIT		(1 << 6)
    104 #define	POWER_5VCTRL_DCDC_XFER				(1 << 5)
    105 #define	POWER_5VCTRL_VBUSVALID_5VDETECT			(1 << 4)
    106 #define	POWER_5VCTRL_VBUSVALID_TO_B			(1 << 3)
    107 #define	POWER_5VCTRL_ILIMIT_EQ_ZERO			(1 << 2)
    108 #define	POWER_5VCTRL_PWRUP_VBUS_CMPS			(1 << 1)
    109 #define	POWER_5VCTRL_ENABLE_DCDC			(1 << 0)
    110 
    111 #define	POWER_MINPWR_LOWPWR_4P2				(1 << 14)
    112 #define	POWER_MINPWR_PWD_BO				(1 << 12)
    113 #define	POWER_MINPWR_USE_VDDXTAL_VBG			(1 << 11)
    114 #define	POWER_MINPWR_PWD_ANA_CMPS			(1 << 10)
    115 #define	POWER_MINPWR_ENABLE_OSC				(1 << 9)
    116 #define	POWER_MINPWR_SELECT_OSC				(1 << 8)
    117 #define	POWER_MINPWR_VBG_OFF				(1 << 7)
    118 #define	POWER_MINPWR_DOUBLE_FETS			(1 << 6)
    119 #define	POWER_MINPWR_HALFFETS				(1 << 5)
    120 #define	POWER_MINPWR_LESSANA_I				(1 << 4)
    121 #define	POWER_MINPWR_PWD_XTAL24				(1 << 3)
    122 #define	POWER_MINPWR_DC_STOPCLK				(1 << 2)
    123 #define	POWER_MINPWR_EN_DC_PFM				(1 << 1)
    124 #define	POWER_MINPWR_DC_HALFCLK				(1 << 0)
    125 
    126 #define	POWER_CHARGE_ADJ_VOLT_MASK			(0x7 << 24)
    127 #define	POWER_CHARGE_ADJ_VOLT_OFFSET			24
    128 #define	POWER_CHARGE_ADJ_VOLT_M025P			(0x1 << 24)
    129 #define	POWER_CHARGE_ADJ_VOLT_P050P			(0x2 << 24)
    130 #define	POWER_CHARGE_ADJ_VOLT_M075P			(0x3 << 24)
    131 #define	POWER_CHARGE_ADJ_VOLT_P025P			(0x4 << 24)
    132 #define	POWER_CHARGE_ADJ_VOLT_M050P			(0x5 << 24)
    133 #define	POWER_CHARGE_ADJ_VOLT_P075P			(0x6 << 24)
    134 #define	POWER_CHARGE_ADJ_VOLT_M100P			(0x7 << 24)
    135 #define	POWER_CHARGE_ENABLE_LOAD			(1 << 22)
    136 #define	POWER_CHARGE_ENABLE_FAULT_DETECT		(1 << 20)
    137 #define	POWER_CHARGE_CHRG_STS_OFF			(1 << 19)
    138 #define	POWER_CHARGE_LIION_4P1				(1 << 18)
    139 #define	POWER_CHARGE_PWD_BATTCHRG			(1 << 16)
    140 #define	POWER_CHARGE_ENABLE_CHARGER_USB1		(1 << 13)
    141 #define	POWER_CHARGE_ENABLE_CHARGER_USB0		(1 << 12)
    142 #define	POWER_CHARGE_STOP_ILIMIT_MASK			(0xf << 8)
    143 #define	POWER_CHARGE_STOP_ILIMIT_OFFSET			8
    144 #define	POWER_CHARGE_STOP_ILIMIT_10MA			(0x1 << 8)
    145 #define	POWER_CHARGE_STOP_ILIMIT_20MA			(0x2 << 8)
    146 #define	POWER_CHARGE_STOP_ILIMIT_50MA			(0x4 << 8)
    147 #define	POWER_CHARGE_STOP_ILIMIT_100MA			(0x8 << 8)
    148 #define	POWER_CHARGE_BATTCHRG_I_MASK			0x3f
    149 #define	POWER_CHARGE_BATTCHRG_I_OFFSET			0
    150 #define	POWER_CHARGE_BATTCHRG_I_10MA			0x01
    151 #define	POWER_CHARGE_BATTCHRG_I_20MA			0x02
    152 #define	POWER_CHARGE_BATTCHRG_I_50MA			0x04
    153 #define	POWER_CHARGE_BATTCHRG_I_100MA			0x08
    154 #define	POWER_CHARGE_BATTCHRG_I_200MA			0x10
    155 #define	POWER_CHARGE_BATTCHRG_I_400MA			0x20
    156 
    157 #define	POWER_VDDDCTRL_ADJTN_MASK			(0xf << 28)
    158 #define	POWER_VDDDCTRL_ADJTN_OFFSET			28
    159 #define	POWER_VDDDCTRL_PWDN_BRNOUT			(1 << 23)
    160 #define	POWER_VDDDCTRL_DISABLE_STEPPING			(1 << 22)
    161 #define	POWER_VDDDCTRL_ENABLE_LINREG			(1 << 21)
    162 #define	POWER_VDDDCTRL_DISABLE_FET			(1 << 20)
    163 #define	POWER_VDDDCTRL_LINREG_OFFSET_MASK		(0x3 << 16)
    164 #define	POWER_VDDDCTRL_LINREG_OFFSET_OFFSET		16
    165 #define	POWER_VDDDCTRL_LINREG_OFFSET_0STEPS		(0x0 << 16)
    166 #define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 16)
    167 #define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 16)
    168 #define	POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 16)
    169 #define	POWER_VDDDCTRL_BO_OFFSET_MASK			(0x7 << 8)
    170 #define	POWER_VDDDCTRL_BO_OFFSET_OFFSET			8
    171 #define	POWER_VDDDCTRL_TRG_MASK				0x1f
    172 #define	POWER_VDDDCTRL_TRG_OFFSET			0
    173 
    174 #define	POWER_VDDACTRL_PWDN_BRNOUT			(1 << 19)
    175 #define	POWER_VDDACTRL_DISABLE_STEPPING			(1 << 18)
    176 #define	POWER_VDDACTRL_ENABLE_LINREG			(1 << 17)
    177 #define	POWER_VDDACTRL_DISABLE_FET			(1 << 16)
    178 #define	POWER_VDDACTRL_LINREG_OFFSET_MASK		(0x3 << 12)
    179 #define	POWER_VDDACTRL_LINREG_OFFSET_OFFSET		12
    180 #define	POWER_VDDACTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
    181 #define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
    182 #define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
    183 #define	POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
    184 #define	POWER_VDDACTRL_BO_OFFSET_MASK			(0x7 << 8)
    185 #define	POWER_VDDACTRL_BO_OFFSET_OFFSET			8
    186 #define	POWER_VDDACTRL_TRG_MASK				0x1f
    187 #define	POWER_VDDACTRL_TRG_OFFSET			0
    188 
    189 #define	POWER_VDDIOCTRL_ADJTN_MASK			(0xf << 20)
    190 #define	POWER_VDDIOCTRL_ADJTN_OFFSET			20
    191 #define	POWER_VDDIOCTRL_PWDN_BRNOUT			(1 << 18)
    192 #define	POWER_VDDIOCTRL_DISABLE_STEPPING		(1 << 17)
    193 #define	POWER_VDDIOCTRL_DISABLE_FET			(1 << 16)
    194 #define	POWER_VDDIOCTRL_LINREG_OFFSET_MASK		(0x3 << 12)
    195 #define	POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET		12
    196 #define	POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
    197 #define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
    198 #define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
    199 #define	POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
    200 #define	POWER_VDDIOCTRL_BO_OFFSET_MASK			(0x7 << 8)
    201 #define	POWER_VDDIOCTRL_BO_OFFSET_OFFSET		8
    202 #define	POWER_VDDIOCTRL_TRG_MASK			0x1f
    203 #define	POWER_VDDIOCTRL_TRG_OFFSET			0
    204 
    205 #define	POWER_VDDMEMCTRL_PULLDOWN_ACTIVE		(1 << 10)
    206 #define	POWER_VDDMEMCTRL_ENABLE_ILIMIT			(1 << 9)
    207 #define	POWER_VDDMEMCTRL_ENABLE_LINREG			(1 << 8)
    208 #define	POWER_VDDMEMCTRL_BO_OFFSET_MASK			(0x7 << 5)
    209 #define	POWER_VDDMEMCTRL_BO_OFFSET_OFFSET		5
    210 #define	POWER_VDDMEMCTRL_TRG_MASK			0x1f
    211 #define	POWER_VDDMEMCTRL_TRG_OFFSET			0
    212 
    213 #define	POWER_DCDC4P2_DROPOUT_CTRL_MASK			(0xf << 28)
    214 #define	POWER_DCDC4P2_DROPOUT_CTRL_OFFSET		28
    215 #define	POWER_DCDC4P2_DROPOUT_CTRL_200MV		(0x3 << 30)
    216 #define	POWER_DCDC4P2_DROPOUT_CTRL_100MV		(0x2 << 30)
    217 #define	POWER_DCDC4P2_DROPOUT_CTRL_50MV			(0x1 << 30)
    218 #define	POWER_DCDC4P2_DROPOUT_CTRL_25MV			(0x0 << 30)
    219 #define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2		(0x0 << 28)
    220 #define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT	(0x1 << 28)
    221 #define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL		(0x2 << 28)
    222 #define	POWER_DCDC4P2_ISTEAL_THRESH_MASK		(0x3 << 24)
    223 #define	POWER_DCDC4P2_ISTEAL_THRESH_OFFSET		24
    224 #define	POWER_DCDC4P2_ENABLE_4P2			(1 << 23)
    225 #define	POWER_DCDC4P2_ENABLE_DCDC			(1 << 22)
    226 #define	POWER_DCDC4P2_HYST_DIR				(1 << 21)
    227 #define	POWER_DCDC4P2_HYST_THRESH			(1 << 20)
    228 #define	POWER_DCDC4P2_TRG_MASK				(0x7 << 16)
    229 #define	POWER_DCDC4P2_TRG_OFFSET			16
    230 #define	POWER_DCDC4P2_TRG_4V2				(0x0 << 16)
    231 #define	POWER_DCDC4P2_TRG_4V1				(0x1 << 16)
    232 #define	POWER_DCDC4P2_TRG_4V0				(0x2 << 16)
    233 #define	POWER_DCDC4P2_TRG_3V9				(0x3 << 16)
    234 #define	POWER_DCDC4P2_TRG_BATT				(0x4 << 16)
    235 #define	POWER_DCDC4P2_BO_MASK				(0x1f << 8)
    236 #define	POWER_DCDC4P2_BO_OFFSET				8
    237 #define	POWER_DCDC4P2_CMPTRIP_MASK			0x1f
    238 #define	POWER_DCDC4P2_CMPTRIP_OFFSET			0
    239 
    240 #define	POWER_MISC_FREQSEL_MASK				(0x7 << 4)
    241 #define	POWER_MISC_FREQSEL_OFFSET			4
    242 #define	POWER_MISC_FREQSEL_20MHZ			(0x1 << 4)
    243 #define	POWER_MISC_FREQSEL_24MHZ			(0x2 << 4)
    244 #define	POWER_MISC_FREQSEL_19MHZ			(0x3 << 4)
    245 #define	POWER_MISC_FREQSEL_14MHZ			(0x4 << 4)
    246 #define	POWER_MISC_FREQSEL_18MHZ			(0x5 << 4)
    247 #define	POWER_MISC_FREQSEL_21MHZ			(0x6 << 4)
    248 #define	POWER_MISC_FREQSEL_17MHZ			(0x7 << 4)
    249 #define	POWER_MISC_DISABLE_FET_BO_LOGIC			(1 << 3)
    250 #define	POWER_MISC_DELAY_TIMING				(1 << 2)
    251 #define	POWER_MISC_TEST					(1 << 1)
    252 #define	POWER_MISC_SEL_PLLCLK				(1 << 0)
    253 
    254 #define	POWER_DCLIMITS_POSLIMIT_BUCK_MASK		(0x7f << 8)
    255 #define	POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET		8
    256 #define	POWER_DCLIMITS_NEGLIMIT_MASK			0x7f
    257 #define	POWER_DCLIMITS_NEGLIMIT_OFFSET			0
    258 
    259 #define	POWER_LOOPCTRL_TOGGLE_DIF			(1 << 20)
    260 #define	POWER_LOOPCTRL_HYST_SIGN			(1 << 19)
    261 #define	POWER_LOOPCTRL_EN_CM_HYST			(1 << 18)
    262 #define	POWER_LOOPCTRL_EN_DF_HYST			(1 << 17)
    263 #define	POWER_LOOPCTRL_CM_HYST_THRESH			(1 << 16)
    264 #define	POWER_LOOPCTRL_DF_HYST_THRESH			(1 << 15)
    265 #define	POWER_LOOPCTRL_RCSCALE_THRESH			(1 << 14)
    266 #define	POWER_LOOPCTRL_EN_RCSCALE_MASK			(0x3 << 12)
    267 #define	POWER_LOOPCTRL_EN_RCSCALE_OFFSET		12
    268 #define	POWER_LOOPCTRL_EN_RCSCALE_DIS			(0x0 << 12)
    269 #define	POWER_LOOPCTRL_EN_RCSCALE_2X			(0x1 << 12)
    270 #define	POWER_LOOPCTRL_EN_RCSCALE_4X			(0x2 << 12)
    271 #define	POWER_LOOPCTRL_EN_RCSCALE_8X			(0x3 << 12)
    272 #define	POWER_LOOPCTRL_DC_FF_MASK			(0x7 << 8)
    273 #define	POWER_LOOPCTRL_DC_FF_OFFSET			8
    274 #define	POWER_LOOPCTRL_DC_R_MASK			(0xf << 4)
    275 #define	POWER_LOOPCTRL_DC_R_OFFSET			4
    276 #define	POWER_LOOPCTRL_DC_C_MASK			0x3
    277 #define	POWER_LOOPCTRL_DC_C_OFFSET			0
    278 #define	POWER_LOOPCTRL_DC_C_MAX				0x0
    279 #define	POWER_LOOPCTRL_DC_C_2X				0x1
    280 #define	POWER_LOOPCTRL_DC_C_4X				0x2
    281 #define	POWER_LOOPCTRL_DC_C_MIN				0x3
    282 
    283 #define	POWER_STS_PWRUP_SOURCE_MASK			(0x3f << 24)
    284 #define	POWER_STS_PWRUP_SOURCE_OFFSET			24
    285 #define	POWER_STS_PWRUP_SOURCE_5V			(0x20 << 24)
    286 #define	POWER_STS_PWRUP_SOURCE_RTC			(0x10 << 24)
    287 #define	POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH		(0x02 << 24)
    288 #define	POWER_STS_PWRUP_SOURCE_PSWITCH_MID		(0x01 << 24)
    289 #define	POWER_STS_PSWITCH_MASK				(0x3 << 20)
    290 #define	POWER_STS_PSWITCH_OFFSET			20
    291 #define	POWER_STS_THERMAL_WARNING			(1 << 19)
    292 #define	POWER_STS_VDDMEM_BO				(1 << 18)
    293 #define	POWER_STS_AVALID0_STATUS			(1 << 17)
    294 #define	POWER_STS_BVALID0_STATUS			(1 << 16)
    295 #define	POWER_STS_VBUSVALID0_STATUS			(1 << 15)
    296 #define	POWER_STS_SESSEND0_STATUS			(1 << 14)
    297 #define	POWER_STS_BATT_BO				(1 << 13)
    298 #define	POWER_STS_VDD5V_FAULT				(1 << 12)
    299 #define	POWER_STS_CHRGSTS				(1 << 11)
    300 #define	POWER_STS_DCDC_4P2_BO				(1 << 10)
    301 #define	POWER_STS_DC_OK					(1 << 9)
    302 #define	POWER_STS_VDDIO_BO				(1 << 8)
    303 #define	POWER_STS_VDDA_BO				(1 << 7)
    304 #define	POWER_STS_VDDD_BO				(1 << 6)
    305 #define	POWER_STS_VDD5V_GT_VDDIO			(1 << 5)
    306 #define	POWER_STS_VDD5V_DROOP				(1 << 4)
    307 #define	POWER_STS_AVALID0				(1 << 3)
    308 #define	POWER_STS_BVALID0				(1 << 2)
    309 #define	POWER_STS_VBUSVALID0				(1 << 1)
    310 #define	POWER_STS_SESSEND0				(1 << 0)
    311 
    312 #define	POWER_SPEED_STATUS_MASK				(0xffff << 8)
    313 #define	POWER_SPEED_STATUS_OFFSET			8
    314 #define	POWER_SPEED_STATUS_SEL_MASK			(0x3 << 6)
    315 #define	POWER_SPEED_STATUS_SEL_OFFSET			6
    316 #define	POWER_SPEED_STATUS_SEL_DCDC_STAT		(0x0 << 6)
    317 #define	POWER_SPEED_STATUS_SEL_CORE_STAT		(0x1 << 6)
    318 #define	POWER_SPEED_STATUS_SEL_ARM_STAT			(0x2 << 6)
    319 #define	POWER_SPEED_CTRL_MASK				0x3
    320 #define	POWER_SPEED_CTRL_OFFSET				0
    321 #define	POWER_SPEED_CTRL_SS_OFF				0x0
    322 #define	POWER_SPEED_CTRL_SS_ON				0x1
    323 #define	POWER_SPEED_CTRL_SS_ENABLE			0x3
    324 
    325 #define	POWER_BATTMONITOR_BATT_VAL_MASK			(0x3ff << 16)
    326 #define	POWER_BATTMONITOR_BATT_VAL_OFFSET		16
    327 #define	POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN	(1 << 11)
    328 #define	POWER_BATTMONITOR_EN_BATADJ			(1 << 10)
    329 #define	POWER_BATTMONITOR_PWDN_BATTBRNOUT		(1 << 9)
    330 #define	POWER_BATTMONITOR_BRWNOUT_PWD			(1 << 8)
    331 #define	POWER_BATTMONITOR_BRWNOUT_LVL_MASK		0x1f
    332 #define	POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET		0
    333 
    334 #define	POWER_RESET_UNLOCK_MASK				(0xffff << 16)
    335 #define	POWER_RESET_UNLOCK_OFFSET			16
    336 #define	POWER_RESET_UNLOCK_KEY				(0x3e77 << 16)
    337 #define	POWER_RESET_FASTFALL_PSWITCH_OFF		(1 << 2)
    338 #define	POWER_RESET_PWD_OFF				(1 << 1)
    339 #define	POWER_RESET_PWD					(1 << 0)
    340 
    341 #define	POWER_DEBUG_VBUSVALIDPIOLOCK			(1 << 3)
    342 #define	POWER_DEBUG_AVALIDPIOLOCK			(1 << 2)
    343 #define	POWER_DEBUG_BVALIDPIOLOCK			(1 << 1)
    344 #define	POWER_DEBUG_SESSENDPIOLOCK			(1 << 0)
    345 
    346 #define	POWER_THERMAL_TEST				(1 << 8)
    347 #define	POWER_THERMAL_PWD				(1 << 7)
    348 #define	POWER_THERMAL_LOW_POWER				(1 << 6)
    349 #define	POWER_THERMAL_OFFSET_ADJ_MASK			(0x3 << 4)
    350 #define	POWER_THERMAL_OFFSET_ADJ_OFFSET			4
    351 #define	POWER_THERMAL_OFFSET_ADJ_ENABLE			(1 << 3)
    352 #define	POWER_THERMAL_TEMP_THRESHOLD_MASK		0x7
    353 #define	POWER_THERMAL_TEMP_THRESHOLD_OFFSET		0
    354 
    355 #define	POWER_USB1CTRL_AVALID1				(1 << 3)
    356 #define	POWER_USB1CTRL_BVALID1				(1 << 2)
    357 #define	POWER_USB1CTRL_VBUSVALID1			(1 << 1)
    358 #define	POWER_USB1CTRL_SESSEND1				(1 << 0)
    359 
    360 #define	POWER_SPECIAL_TEST_MASK				0xffffffff
    361 #define	POWER_SPECIAL_TEST_OFFSET			0
    362 
    363 #define	POWER_VERSION_MAJOR_MASK			(0xff << 24)
    364 #define	POWER_VERSION_MAJOR_OFFSET			24
    365 #define	POWER_VERSION_MINOR_MASK			(0xff << 16)
    366 #define	POWER_VERSION_MINOR_OFFSET			16
    367 #define	POWER_VERSION_STEP_MASK				0xffff
    368 #define	POWER_VERSION_STEP_OFFSET			0
    369 
    370 #define	POWER_ANACLKCTRL_CLKGATE_0			(1 << 31)
    371 #define	POWER_ANACLKCTRL_OUTDIV_MASK			(0x7 << 28)
    372 #define	POWER_ANACLKCTRL_OUTDIV_OFFSET			28
    373 #define	POWER_ANACLKCTRL_INVERT_OUTCLK			(1 << 27)
    374 #define	POWER_ANACLKCTRL_CLKGATE_I			(1 << 26)
    375 #define	POWER_ANACLKCTRL_DITHER_OFF			(1 << 10)
    376 #define	POWER_ANACLKCTRL_SLOW_DITHER			(1 << 9)
    377 #define	POWER_ANACLKCTRL_INVERT_INCLK			(1 << 8)
    378 #define	POWER_ANACLKCTRL_INCLK_SHIFT_MASK		(0x3 << 4)
    379 #define	POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET		4
    380 #define	POWER_ANACLKCTRL_INDIV_MASK			0x7
    381 #define	POWER_ANACLKCTRL_INDIV_OFFSET			0
    382 
    383 #define	POWER_REFCTRL_FASTSETTLING			(1 << 26)
    384 #define	POWER_REFCTRL_RAISE_REF				(1 << 25)
    385 #define	POWER_REFCTRL_XTAL_BGR_BIAS			(1 << 24)
    386 #define	POWER_REFCTRL_VBG_ADJ_MASK			(0x7 << 20)
    387 #define	POWER_REFCTRL_VBG_ADJ_OFFSET			20
    388 #define	POWER_REFCTRL_LOW_PWR				(1 << 19)
    389 #define	POWER_REFCTRL_BIAS_CTRL_MASK			(0x3 << 16)
    390 #define	POWER_REFCTRL_BIAS_CTRL_OFFSET			16
    391 #define	POWER_REFCTRL_VDDXTAL_TO_VDDD			(1 << 14)
    392 #define	POWER_REFCTRL_ADJ_ANA				(1 << 13)
    393 #define	POWER_REFCTRL_ADJ_VAG				(1 << 12)
    394 #define	POWER_REFCTRL_ANA_REFVAL_MASK			(0xf << 8)
    395 #define	POWER_REFCTRL_ANA_REFVAL_OFFSET			8
    396 #define	POWER_REFCTRL_VAG_VAL_MASK			(0xf << 4)
    397 #define	POWER_REFCTRL_VAG_VAL_OFFSET			4
    398 
    399 #endif	/* __MX28_REGS_POWER_H__ */
    400