| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ISDOpcodes.h | 653 /// PRE_INC Similar to the unindexed mode where the effective address is
673 PRE_INC,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGAddressAnalysis.cpp | 89 if (N->getAddressingMode() == ISD::PRE_INC) {
|
| SelectionDAGDumper.cpp | 409 case ISD::PRE_INC: return "<pre-inc>";
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | [all...] |
| BasicTTIImpl.h | 119 return ISD::PRE_INC;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 730 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
766 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
786 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
859 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 97 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
99 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
100 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
101 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
102 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
103 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
104 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
105 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
106 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal)
[all...] |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 92 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
95 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
96 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal)
[all...] |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 165 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
166 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
167 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
168 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
169 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
170 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
171 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
172 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
173 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
174 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal)
[all...] |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 751 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
787 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
807 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 365 case ISD::PRE_INC: return "<pre-inc>";
|
| DAGCombiner.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 588 for (unsigned IM = (unsigned)ISD::PRE_INC;
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 558 for (unsigned IM = (unsigned)ISD::PRE_INC;
[all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | [all...] |
| AArch64ISelLowering.cpp | 440 for (unsigned im = (unsigned)ISD::PRE_INC;
709 for (unsigned im = (unsigned)ISD::PRE_INC;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | [all...] |
| AArch64ISelLowering.cpp | 525 for (unsigned im = (unsigned)ISD::PRE_INC;
[all...] |
