HomeSort by relevance Sort by last modified time
    Searched refs:PredOp (Results 1 - 7 of 7) sorted by null

  /external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/
PTXInstPrinter.cpp 71 int PredOp = MI->getOperand(OpIndex).getImm();
72 if (PredOp == PTXPredicate::None)
75 if (PredOp == PTXPredicate::Negate)
  /external/swiftshader/third_party/LLVM/lib/Target/PTX/
PTXISelDAGToDAG.cpp 95 SDValue PredOp = CurDAG->getTargetConstant(PTXPredicate::Normal, MVT::i32);
102 SDValue Ops[] = { Target, Pred, PredOp, Chain };
134 SDValue PredOp = CurDAG->getTargetConstant(PTXPredicate::None, MVT::i32);
137 SDValue Ops[] = { Index, Pred, PredOp, Chain };
172 SDValue PredOp = CurDAG->getTargetConstant(PTXPredicate::None, MVT::i32);
175 SDValue Ops[] = { Value, Pred, PredOp, Chain };
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
HexagonExpandCondsets.cpp 215 unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
226 const MachineOperand &PredOp, bool Cond,
621 /// PredOp. The Cond argument specifies whether the predicate is to be
622 /// if(PredOp), or if(!PredOp).
625 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp,
639 unsigned PredState = getRegState(PredOp) & ~RegState::Kill;
648 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
653 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()
    [all...]
HexagonGenMux.cpp 246 MachineOperand &PredOp = MI->getOperand(1);
247 if (PredOp.isUndef())
250 unsigned PR = PredOp.getReg();
HexagonISelLowering.cpp     [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonExpandCondsets.cpp 251 unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
263 const MachineOperand &PredOp, bool Cond,
609 /// PredOp. The Cond argument specifies whether the predicate is to be
610 /// if(PredOp), or if(!PredOp).
613 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp,
629 .addOperand(PredOp)
857 const MachineOperand &PredOp, bool Cond,
    [all...]
HexagonISelLowering.cpp     [all...]

Completed in 231 milliseconds