1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SH7751 PCI Controller (PCIC) for U-Boot. 4 * (C) Dustin McIntire (dustin (at) sensoria.com) 5 * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu (at) nigauri.org> 6 */ 7 8 #include <common.h> 9 #include <pci.h> 10 #include <asm/processor.h> 11 #include <asm/io.h> 12 #include <asm/pci.h> 13 14 /* Register addresses and such */ 15 #define SH7751_BCR1 (vu_long *)0xFF800000 16 #define SH7751_BCR2 (vu_short *)0xFF800004 17 #define SH7751_WCR1 (vu_long *)0xFF800008 18 #define SH7751_WCR2 (vu_long *)0xFF80000C 19 #define SH7751_WCR3 (vu_long *)0xFF800010 20 #define SH7751_MCR (vu_long *)0xFF800014 21 #define SH7751_BCR3 (vu_short *)0xFF800050 22 #define SH7751_PCICONF0 (vu_long *)0xFE200000 23 #define SH7751_PCICONF1 (vu_long *)0xFE200004 24 #define SH7751_PCICONF2 (vu_long *)0xFE200008 25 #define SH7751_PCICONF3 (vu_long *)0xFE20000C 26 #define SH7751_PCICONF4 (vu_long *)0xFE200010 27 #define SH7751_PCICONF5 (vu_long *)0xFE200014 28 #define SH7751_PCICONF6 (vu_long *)0xFE200018 29 #define SH7751_PCICR (vu_long *)0xFE200100 30 #define SH7751_PCILSR0 (vu_long *)0xFE200104 31 #define SH7751_PCILSR1 (vu_long *)0xFE200108 32 #define SH7751_PCILAR0 (vu_long *)0xFE20010C 33 #define SH7751_PCILAR1 (vu_long *)0xFE200110 34 #define SH7751_PCIMBR (vu_long *)0xFE2001C4 35 #define SH7751_PCIIOBR (vu_long *)0xFE2001C8 36 #define SH7751_PCIPINT (vu_long *)0xFE2001CC 37 #define SH7751_PCIPINTM (vu_long *)0xFE2001D0 38 #define SH7751_PCICLKR (vu_long *)0xFE2001D4 39 #define SH7751_PCIBCR1 (vu_long *)0xFE2001E0 40 #define SH7751_PCIBCR2 (vu_long *)0xFE2001E4 41 #define SH7751_PCIWCR1 (vu_long *)0xFE2001E8 42 #define SH7751_PCIWCR2 (vu_long *)0xFE2001EC 43 #define SH7751_PCIWCR3 (vu_long *)0xFE2001F0 44 #define SH7751_PCIMCR (vu_long *)0xFE2001F4 45 #define SH7751_PCIBCR3 (vu_long *)0xFE2001F8 46 47 #define BCR1_BREQEN 0x00080000 48 #define PCI_SH7751_ID 0x35051054 49 #define PCI_SH7751R_ID 0x350E1054 50 #define SH7751_PCICONF1_WCC 0x00000080 51 #define SH7751_PCICONF1_PER 0x00000040 52 #define SH7751_PCICONF1_BUM 0x00000004 53 #define SH7751_PCICONF1_MES 0x00000002 54 #define SH7751_PCICONF1_CMDS 0x000000C6 55 #define SH7751_PCI_HOST_BRIDGE 0x6 56 #define SH7751_PCICR_PREFIX 0xa5000000 57 #define SH7751_PCICR_PRST 0x00000002 58 #define SH7751_PCICR_CFIN 0x00000001 59 #define SH7751_PCIPINT_D3 0x00000002 60 #define SH7751_PCIPINT_D0 0x00000001 61 #define SH7751_PCICLKR_PREFIX 0xa5000000 62 63 #define SH7751_PCI_MEM_BASE 0xFD000000 64 #define SH7751_PCI_MEM_SIZE 0x01000000 65 #define SH7751_PCI_IO_BASE 0xFE240000 66 #define SH7751_PCI_IO_SIZE 0x00040000 67 68 #define SH7751_PCIPAR (vu_long *)0xFE2001C0 69 #define SH7751_PCIPDR (vu_long *)0xFE200220 70 71 #define p4_in(addr) (*addr) 72 #define p4_out(data, addr) (*addr) = (data) 73 74 /* Double word */ 75 int pci_sh4_read_config_dword(struct pci_controller *hose, 76 pci_dev_t dev, int offset, u32 *value) 77 { 78 u32 par_data = 0x80000000 | dev; 79 80 p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR); 81 *value = p4_in(SH7751_PCIPDR); 82 83 return 0; 84 } 85 86 int pci_sh4_write_config_dword(struct pci_controller *hose, 87 pci_dev_t dev, int offset, u32 value) 88 { 89 u32 par_data = 0x80000000 | dev; 90 91 p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR); 92 p4_out(value, SH7751_PCIPDR); 93 94 return 0; 95 } 96 97 int pci_sh7751_init(struct pci_controller *hose) 98 { 99 /* Double-check that we're a 7751 or 7751R chip */ 100 if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID 101 && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) { 102 printf("PCI: Unknown PCI host bridge.\n"); 103 return 1; 104 } 105 printf("PCI: SH7751 PCI host bridge found.\n"); 106 107 /* Double-check some BSC config settings */ 108 /* (Area 3 non-MPX 32-bit, PCI bus pins) */ 109 if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) { 110 printf("SH7751_BCR1 value is wrong(0x%08X)\n", 111 (unsigned int)p4_in(SH7751_BCR1)); 112 return 2; 113 } 114 if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) { 115 printf("SH7751_BCR2 value is wrong(0x%08X)\n", 116 (unsigned int)p4_in(SH7751_BCR2)); 117 return 3; 118 } 119 if (p4_in(SH7751_BCR2) & 0x01) { 120 printf("SH7751_BCR2 value is wrong(0x%08X)\n", 121 (unsigned int)p4_in(SH7751_BCR2)); 122 return 4; 123 } 124 125 /* Force BREQEN in BCR1 to allow PCIC access */ 126 p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1); 127 128 /* Toggle PCI reset pin */ 129 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR); 130 udelay(32); 131 p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR); 132 133 /* Set cmd bits: WCC, PER, BUM, MES */ 134 /* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */ 135 p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */ 136 137 /* Define this host as the host bridge */ 138 p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2); 139 140 /* Force PCI clock(s) on */ 141 p4_out(0, SH7751_PCICLKR); 142 p4_out(0x03, SH7751_PCICLKR); 143 144 /* Clear powerdown IRQs, also mask them (unused) */ 145 p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT); 146 p4_out(0, SH7751_PCIPINTM); 147 148 p4_out(0xab000001, SH7751_PCICONF4); 149 150 /* Set up target memory mappings (for external DMA access) */ 151 /* Map both P0 and P2 range to Area 3 RAM for ease of use */ 152 p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0); 153 p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0); 154 p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5); 155 156 p4_out(0, SH7751_PCILSR1); 157 p4_out(0, SH7751_PCILAR1); 158 p4_out(0xd0000000, SH7751_PCICONF6); 159 160 /* Map memory window to same address on PCI bus */ 161 p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR); 162 163 /* Map IO window to same address on PCI bus */ 164 p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR); 165 166 /* set BREQEN */ 167 p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1); 168 169 /* Copy BSC registers into PCI BSC */ 170 p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1); 171 p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2); 172 p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3); 173 p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1); 174 p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2); 175 p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3); 176 p4_out(inl(SH7751_MCR), SH7751_PCIMCR); 177 178 /* Finally, set central function init complete */ 179 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR); 180 181 pci_sh4_init(hose); 182 183 return 0; 184 } 185
