/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
ISDOpcodes.h | 375 // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 380 SIGN_EXTEND_INREG, [all...] |
/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 408 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 413 SIGN_EXTEND_INREG, 431 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to [all...] |
/external/llvm/lib/Target/AMDGPU/ |
R600ISelLowering.cpp | 143 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); 146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); 149 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); 151 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); 154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 155 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); 156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); 158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal) [all...] |
SIISelLowering.cpp | 118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom); 119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom); 120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); 121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom); 122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); 123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom); 124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom); [all...] |
AMDGPUISelLowering.cpp | 706 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); 735 case ISD::SIGN_EXTEND_INREG: 737 // sign_extend_inreg is the one to check for custom lowering. The extended [all...] |
/external/llvm/lib/Target/BPF/ |
BPFISelLowering.cpp | 107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 453 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 458 SIGN_EXTEND_INREG, 476 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
R600ISelLowering.cpp | 182 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 184 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); 185 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); 188 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 189 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); 190 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); 193 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 194 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); 195 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); 197 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
BPFISelLowering.cpp | 117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 189 case ISD::SIGN_EXTEND_INREG:
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LegalizeIntegerTypes.cpp | 71 case ISD::SIGN_EXTEND_INREG: 397 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 462 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 535 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 667 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), [all...] |
DAGCombiner.cpp | 724 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 736 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
PTXISelLowering.cpp | 67 // sign_extend_inreg => sign_extend 69 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
ARCISelLowering.cpp | 139 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom); 183 "Unhandled target sign_extend_inreg."); 758 case ISD::SIGN_EXTEND_INREG:
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/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeIntegerTypes.cpp | 84 case ISD::SIGN_EXTEND_INREG: 461 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 556 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 640 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), [all...] |
LegalizeVectorOps.cpp | 75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA. 327 case ISD::SIGN_EXTEND_INREG: 679 case ISD::SIGN_EXTEND_INREG: [all...] |
/external/llvm/lib/Target/Lanai/ |
LanaiISelLowering.cpp | 116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
SparcISelLowering.cpp | 710 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 711 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 712 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
LanaiISelLowering.cpp | 131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 133 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
HexagonISelLoweringHVX.cpp | 138 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Custom); [all...] |
HexagonISelDAGToDAG.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
WebAssemblyISelLowering.cpp | 119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 122 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeIntegerTypes.cpp | 86 case ISD::SIGN_EXTEND_INREG: 455 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 555 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 631 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | 159 // Some SIGN_EXTEND_INREG can be done using cvt instruction. 161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal); 162 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); 164 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | 391 // Some SIGN_EXTEND_INREG can be done using cvt instruction. 393 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal); 394 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 395 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); 396 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 397 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); [all...] |