| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 129 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
132 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
134 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
136 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
138 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
140 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
142 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
144 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
146 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
148 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 190 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
193 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
195 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
197 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
199 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
201 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
203 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
205 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
207 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
209 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 215 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
216 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
217 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
223 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
224 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
225 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
231 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
237 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 },
238 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 318 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
319 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
320 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
326 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
327 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
328 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
334 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
335 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
340 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 },
341 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 575 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
576 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
577 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 },
578 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 },
579 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
580 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
581 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
582 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
673 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
674 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }
[all...] |
| X86IntrinsicsInfo.h | 501 ISD::SINT_TO_FP, 0),
503 ISD::SINT_TO_FP, 0), // no rm
505 ISD::SINT_TO_FP, 0),
507 ISD::SINT_TO_FP, 0),
509 ISD::SINT_TO_FP, ISD::SINT_TO_FP), //er
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 195 case ISD::SINT_TO_FP:
303 // Make sure that the SINT_TO_FP and SRL instructions are available.
304 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, VT) ||
330 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
332 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
|
| LegalizeFloatTypes.cpp | 96 case ISD::SINT_TO_FP:
540 bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeVectorTypes.cpp | 90 case ISD::SINT_TO_FP:
467 case ISD::SINT_TO_FP:
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | [all...] |
| X86IntrinsicsInfo.h | 469 ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND), //er
523 ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND),
527 ISD::SINT_TO_FP, 0),
529 ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND),
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ISDOpcodes.h | 372 SINT_TO_FP,
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 405 SINT_TO_FP,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 450 SINT_TO_FP,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 340 case ISD::SINT_TO_FP:
387 case ISD::SINT_TO_FP:
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeFloatTypes.cpp | 109 case ISD::SINT_TO_FP:
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 403 case ISD::SINT_TO_FP:
459 case ISD::SINT_TO_FP:
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeFloatTypes.cpp | 109 case ISD::SINT_TO_FP:
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 342 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
343 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
344 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
348 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
384 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 116 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
117 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
123 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
263 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
372 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
390 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
396 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
517 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
644 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 195 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
196 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
202 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
373 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
503 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
510 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
524 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
530 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
655 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
