| /external/llvm/lib/Target/Lanai/ |
| LanaiAluCode.h | 38 SRA = 0x37,
97 case SRA:
115 .Case("sha", SRA)
139 case ISD::SRA:
140 return AluCode::SRA;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| LanaiAluCode.h | 38 SRA = 0x37,
97 case SRA:
115 .Case("sha", SRA)
139 case ISD::SRA:
140 return AluCode::SRA;
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr;
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 29 case ISD::SRA: return ARM_AM::asr;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 29 case ISD::SRA: return ARM_AM::asr;
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 102 // normally expanded to the sequence SRA + SRL + ADD + SRA.
119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
137 { ISD::SRA, MVT::v16i32, 1 },
140 { ISD::SRA, MVT::v8i64, 1 },
153 { ISD::SRA, MVT::v4i32, 1 },
156 { ISD::SRA, MVT::v8i32, 1 },
180 { ISD::SRA, MVT::v16i8, 2 },
183 { ISD::SRA, MVT::v8i16, 2 },
186 { ISD::SRA, MVT::v4i32, 2 }
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 254 // normally expanded to the sequence SRA + SRL + ADD + SRA.
292 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb.
308 { ISD::SRA, MVT::v2i64, 1 },
309 { ISD::SRA, MVT::v4i64, 1 },
310 { ISD::SRA, MVT::v8i64, 1 },
328 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb.
330 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
352 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
356 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split
[all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeSPARC_32.c | 60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst));
71 return push_inst(compiler, (op == SLJIT_MOV_S16 ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst));
111 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(dst) | IMM(31), DR(TMP_REG1)));
133 FAIL_IF(push_inst(compiler, SRA | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
|
| sljitNativeMIPS_32.c | 93 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(24), DR(dst));
112 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(16), DR(dst));
381 FAIL_IF(push_inst(compiler, SRA | T(dst) | DA(OTHER_FLAG) | SH_IMM(31), OTHER_FLAG));
405 EMIT_SHIFT(SRA, SRAV);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| MSP430ISelLowering.cpp | 91 setOperationAction(ISD::SRA, MVT::i8, Custom);
94 setOperationAction(ISD::SRA, MVT::i16, Custom);
184 case ISD::SRA: return LowerShifts(Op, DAG);
728 case ISD::SRA:
729 return DAG.getNode(MSP430ISD::SRA, dl,
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ISDOpcodes.h | 317 SHL, SRA, SRL, ROTL, ROTR,
375 // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| MSP430ISelLowering.cpp | 98 setOperationAction(ISD::SRA, MVT::i8, Custom);
101 setOperationAction(ISD::SRA, MVT::i16, Custom);
184 case ISD::SRA: return LowerShifts(Op, DAG);
607 case ISD::SRA:
608 return DAG.getNode(MSP430ISD::SRA, dl,
827 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 86 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
678 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
[all...] |
| LegalizeVectorOps.cpp | 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
280 case ISD::SRA:
615 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
770 // Make sure that the SRA and SHL instructions are available.
771 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
784 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
828 return DAG.getNode(ISD::SRA, DL, VT,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 73 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
552 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
[all...] |
| /device/linaro/bootloader/edk2/Omap35xxPkg/MmcHostDxe/ |
| MmcHostDxe.c | 435 MmioWrite32 (MMCHS_SYSCTL, SRA);
437 while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0);
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530MMCHS.h | 106 #define SRA BIT24
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 339 SHL, SRA, SRL, ROTL, ROTR,
408 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUTargetTransformInfo.cpp | 135 case ISD::SRA: {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 382 SHL, SRA, SRL, ROTL, ROTR,
453 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips1/ |
| valid.s | 131 sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
132 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
134 sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
135 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
137 sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
138 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
140 sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
141 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/ |
| valid.s | 170 sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
171 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
173 sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
174 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
176 sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
177 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
179 sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
180 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
[all...] |
