1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 7 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 8 9 /* core clocks */ 10 #define PLL_APLL 1 11 #define PLL_DPLL 2 12 #define PLL_CPLL 3 13 #define PLL_GPLL 4 14 #define ARMCLK 5 15 16 /* sclk gates (special clocks) */ 17 #define SCLK_SPI0 65 18 #define SCLK_NANDC 67 19 #define SCLK_SDMMC 68 20 #define SCLK_SDIO 69 21 #define SCLK_EMMC 71 22 #define SCLK_TSADC 72 23 #define SCLK_UART0 77 24 #define SCLK_UART1 78 25 #define SCLK_UART2 79 26 #define SCLK_I2S0 80 27 #define SCLK_I2S1 81 28 #define SCLK_I2S2 82 29 #define SCLK_SPDIF 83 30 #define SCLK_TIMER0 85 31 #define SCLK_TIMER1 86 32 #define SCLK_TIMER2 87 33 #define SCLK_TIMER3 88 34 #define SCLK_TIMER4 89 35 #define SCLK_TIMER5 90 36 #define SCLK_I2S_OUT 113 37 #define SCLK_SDMMC_DRV 114 38 #define SCLK_SDIO_DRV 115 39 #define SCLK_EMMC_DRV 117 40 #define SCLK_SDMMC_SAMPLE 118 41 #define SCLK_SDIO_SAMPLE 119 42 #define SCLK_EMMC_SAMPLE 121 43 #define SCLK_VOP 122 44 #define SCLK_HDMI_HDCP 123 45 #define SCLK_MAC_SRC 124 46 #define SCLK_MAC_EXTCLK 125 47 #define SCLK_MAC 126 48 #define SCLK_MAC_REFOUT 127 49 #define SCLK_MAC_REF 128 50 #define SCLK_MAC_RX 129 51 #define SCLK_MAC_TX 130 52 #define SCLK_MAC_PHY 131 53 #define SCLK_MAC_OUT 132 54 55 /* dclk gates */ 56 #define DCLK_VOP 190 57 #define DCLK_HDMI_PHY 191 58 59 /* aclk gates */ 60 #define ACLK_DMAC 194 61 #define ACLK_PERI 210 62 #define ACLK_VOP 211 63 #define ACLK_GMAC 212 64 65 /* pclk gates */ 66 #define PCLK_GPIO0 320 67 #define PCLK_GPIO1 321 68 #define PCLK_GPIO2 322 69 #define PCLK_GPIO3 323 70 #define PCLK_GRF 329 71 #define PCLK_I2C0 332 72 #define PCLK_I2C1 333 73 #define PCLK_I2C2 334 74 #define PCLK_I2C3 335 75 #define PCLK_SPI0 338 76 #define PCLK_UART0 341 77 #define PCLK_UART1 342 78 #define PCLK_UART2 343 79 #define PCLK_TSADC 344 80 #define PCLK_PWM 350 81 #define PCLK_TIMER 353 82 #define PCLK_PERI 363 83 #define PCLK_HDMI_CTRL 364 84 #define PCLK_HDMI_PHY 365 85 #define PCLK_GMAC 367 86 87 /* hclk gates */ 88 #define HCLK_I2S0_8CH 442 89 #define HCLK_I2S1_8CH 443 90 #define HCLK_I2S2_2CH 444 91 #define HCLK_SPDIF_8CH 445 92 #define HCLK_VOP 452 93 #define HCLK_NANDC 453 94 #define HCLK_SDMMC 456 95 #define HCLK_SDIO 457 96 #define HCLK_EMMC 459 97 #define HCLK_PERI 478 98 99 #define CLK_NR_CLKS (HCLK_PERI + 1) 100 101 /* soft-reset indices */ 102 #define SRST_CORE0_PO 0 103 #define SRST_CORE1_PO 1 104 #define SRST_CORE2_PO 2 105 #define SRST_CORE3_PO 3 106 #define SRST_CORE0 4 107 #define SRST_CORE1 5 108 #define SRST_CORE2 6 109 #define SRST_CORE3 7 110 #define SRST_CORE0_DBG 8 111 #define SRST_CORE1_DBG 9 112 #define SRST_CORE2_DBG 10 113 #define SRST_CORE3_DBG 11 114 #define SRST_TOPDBG 12 115 #define SRST_ACLK_CORE 13 116 #define SRST_NOC 14 117 #define SRST_L2C 15 118 119 #define SRST_CPUSYS_H 18 120 #define SRST_BUSSYS_H 19 121 #define SRST_SPDIF 20 122 #define SRST_INTMEM 21 123 #define SRST_ROM 22 124 #define SRST_OTG_ADP 23 125 #define SRST_I2S0 24 126 #define SRST_I2S1 25 127 #define SRST_I2S2 26 128 #define SRST_ACODEC_P 27 129 #define SRST_DFIMON 28 130 #define SRST_MSCH 29 131 #define SRST_EFUSE1024 30 132 #define SRST_EFUSE256 31 133 134 #define SRST_GPIO0 32 135 #define SRST_GPIO1 33 136 #define SRST_GPIO2 34 137 #define SRST_GPIO3 35 138 #define SRST_PERIPH_NOC_A 36 139 #define SRST_PERIPH_NOC_BUS_H 37 140 #define SRST_PERIPH_NOC_P 38 141 #define SRST_UART0 39 142 #define SRST_UART1 40 143 #define SRST_UART2 41 144 #define SRST_PHYNOC 42 145 #define SRST_I2C0 43 146 #define SRST_I2C1 44 147 #define SRST_I2C2 45 148 #define SRST_I2C3 46 149 150 #define SRST_PWM 48 151 #define SRST_A53_GIC 49 152 #define SRST_DAP 51 153 #define SRST_DAP_NOC 52 154 #define SRST_CRYPTO 53 155 #define SRST_SGRF 54 156 #define SRST_GRF 55 157 #define SRST_GMAC 56 158 #define SRST_PERIPH_NOC_H 58 159 #define SRST_MACPHY 63 160 161 #define SRST_DMA 64 162 #define SRST_NANDC 68 163 #define SRST_USBOTG 69 164 #define SRST_OTGC 70 165 #define SRST_USBHOST0 71 166 #define SRST_HOST_CTRL0 72 167 #define SRST_USBHOST1 73 168 #define SRST_HOST_CTRL1 74 169 #define SRST_USBHOST2 75 170 #define SRST_HOST_CTRL2 76 171 #define SRST_USBPOR0 77 172 #define SRST_USBPOR1 78 173 #define SRST_DDRMSCH 79 174 175 #define SRST_SMART_CARD 80 176 #define SRST_SDMMC 81 177 #define SRST_SDIO 82 178 #define SRST_EMMC 83 179 #define SRST_SPI 84 180 #define SRST_TSP_H 85 181 #define SRST_TSP 86 182 #define SRST_TSADC 87 183 #define SRST_DDRPHY 88 184 #define SRST_DDRPHY_P 89 185 #define SRST_DDRCTRL 90 186 #define SRST_DDRCTRL_P 91 187 #define SRST_HOST0_ECHI 92 188 #define SRST_HOST1_ECHI 93 189 #define SRST_HOST2_ECHI 94 190 #define SRST_VOP_NOC_A 95 191 192 #define SRST_HDMI_P 96 193 #define SRST_VIO_ARBI_H 97 194 #define SRST_IEP_NOC_A 98 195 #define SRST_VIO_NOC_H 99 196 #define SRST_VOP_A 100 197 #define SRST_VOP_H 101 198 #define SRST_VOP_D 102 199 #define SRST_UTMI0 103 200 #define SRST_UTMI1 104 201 #define SRST_UTMI2 105 202 #define SRST_UTMI3 106 203 #define SRST_RGA 107 204 #define SRST_RGA_NOC_A 108 205 #define SRST_RGA_A 109 206 #define SRST_RGA_H 110 207 #define SRST_HDCP_A 111 208 209 #define SRST_VPU_A 112 210 #define SRST_VPU_H 113 211 #define SRST_VPU_NOC_A 116 212 #define SRST_VPU_NOC_H 117 213 #define SRST_RKVDEC_A 118 214 #define SRST_RKVDEC_NOC_A 119 215 #define SRST_RKVDEC_H 120 216 #define SRST_RKVDEC_NOC_H 121 217 #define SRST_RKVDEC_CORE 122 218 #define SRST_RKVDEC_CABAC 123 219 #define SRST_IEP_A 124 220 #define SRST_IEP_H 125 221 #define SRST_GPU_A 126 222 #define SRST_GPU_NOC_A 127 223 224 #define SRST_CORE_DBG 128 225 #define SRST_DBG_P 129 226 #define SRST_TIMER0 130 227 #define SRST_TIMER1 131 228 #define SRST_TIMER2 132 229 #define SRST_TIMER3 133 230 #define SRST_TIMER4 134 231 #define SRST_TIMER5 135 232 #define SRST_VIO_H2P 136 233 #define SRST_HDMIPHY 139 234 #define SRST_VDAC 140 235 #define SRST_TIMER_6CH_P 141 236 237 #endif 238
