| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| MachineCopyPropagation.cpp | 287 const TargetRegisterClass *SuperRC = UseDstRC;
289 SuperRC; SuperRC = *SuperRCI++)
290 if (SuperRC->contains(CopySrcReg))
|
| AggressiveAntiDepBreaker.cpp | 630 const TargetRegisterClass *SuperRC =
633 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
641 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
643 unsigned OrigR = RenameOrder[SuperRC];
737 RenameOrder.erase(SuperRC);
738 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
[all...] |
| RegAllocGreedy.cpp | [all...] |
| TargetLoweringBase.cpp | [all...] |
| MachineVerifier.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SILoadStoreOptimizer.cpp | 510 const TargetRegisterClass *SuperRC
512 unsigned DestReg = MRI->createVirtualRegister(SuperRC);
646 const TargetRegisterClass *SuperRC =
648 unsigned DestReg = MRI->createVirtualRegister(SuperRC);
698 const TargetRegisterClass *SuperRC =
700 unsigned DestReg = MRI->createVirtualRegister(SuperRC);
792 const TargetRegisterClass *SuperRC =
794 unsigned SrcReg = MRI->createVirtualRegister(SuperRC);
[all...] |
| SIInstrInfo.h | 70 const TargetRegisterClass *SuperRC,
76 const TargetRegisterClass *SuperRC,
[all...] |
| AMDGPUISelDAGToDAG.cpp | 341 const TargetRegisterClass *SuperRC =
346 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
[all...] |
| SIInstrInfo.cpp | [all...] |
| SIISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| AggressiveAntiDepBreaker.cpp | 620 const TargetRegisterClass *SuperRC =
623 ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC);
631 if (RenameOrder.count(SuperRC) == 0)
632 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
634 unsigned OrigR = RenameOrder[SuperRC];
701 RenameOrder.erase(SuperRC);
702 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
[all...] |
| MachineVerifier.cpp | 770 const TargetRegisterClass *SuperRC =
772 if (!SuperRC) {
776 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
[all...] |
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.cpp | 611 const TargetRegisterClass *SuperRC =
614 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
622 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
624 unsigned OrigR = RenameOrder[SuperRC];
717 RenameOrder.erase(SuperRC);
718 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
[all...] |
| RegAllocGreedy.cpp | [all...] |
| TargetLoweringBase.cpp | [all...] |
| MachineVerifier.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SILoadStoreOptimizer.cpp | 229 const TargetRegisterClass *SuperRC
231 unsigned DestReg = MRI->createVirtualRegister(SuperRC);
|
| SIInstrInfo.h | 47 const TargetRegisterClass *SuperRC,
53 const TargetRegisterClass *SuperRC,
|
| SILowerControlFlow.cpp | 604 const TargetRegisterClass *SuperRC = TRI->getPhysRegClass(VecReg);
606 int NumElts = SuperRC->getSize() / RC->getSize();
|
| AMDGPUISelDAGToDAG.cpp | 208 const TargetRegisterClass *SuperRC =
213 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
[all...] |
| SIInstrInfo.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 288 // classes SuperRC such that:
290 // R:SubRegIndex in this RC for all R in SuperRC.
365 CodeGenRegisterClass *SuperRC) {
366 SuperRegClasses[SubIdx].insert(SuperRC);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 335 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
336 return getHexagonSubRegIndex(*SuperRC, GenIdx);
|
| HexagonCopyToCombine.cpp | 590 const TargetRegisterClass *SuperRC = nullptr;
592 SuperRC = &Hexagon::DoubleRegsRegClass;
596 SuperRC = &Hexagon::HvxWRRegClass;
602 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 314 // classes SuperRC such that:
316 // R:SubRegIndex in this RC for all R in SuperRC.
404 CodeGenRegisterClass *SuperRC) {
405 SuperRegClasses[SubIdx].insert(SuperRC);
|
