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/external/u-boot/include/ | |
fsl_ddr_sdram.h | 134 #define TIMING_CFG_2_CPO_MASK 0x0F800000 |
/external/u-boot/drivers/ddr/fsl/ | |
mpc85xx_ddr_gen3.c | 459 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); |