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      1 /* SPDX-License-Identifier: GPL-2.0+ */
      2 /*
      3  * Freescale i.MX28 TIMROT Register Definitions
      4  *
      5  * Copyright (C) 2011 Marek Vasut <marek.vasut (at) gmail.com>
      6  *
      7  * Based on code from LTIB:
      8  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
      9  */
     10 
     11 #ifndef __MX28_REGS_TIMROT_H__
     12 #define __MX28_REGS_TIMROT_H__
     13 
     14 #include <asm/mach-imx/regs-common.h>
     15 
     16 #ifndef	__ASSEMBLY__
     17 struct mxs_timrot_regs {
     18 	mxs_reg_32(hw_timrot_rotctrl)
     19 	mxs_reg_32(hw_timrot_rotcount)
     20 #if defined(CONFIG_MX23)
     21 	mxs_reg_32(hw_timrot_timctrl0)
     22 	mxs_reg_32(hw_timrot_timcount0)
     23 	mxs_reg_32(hw_timrot_timctrl1)
     24 	mxs_reg_32(hw_timrot_timcount1)
     25 	mxs_reg_32(hw_timrot_timctrl2)
     26 	mxs_reg_32(hw_timrot_timcount2)
     27 	mxs_reg_32(hw_timrot_timctrl3)
     28 	mxs_reg_32(hw_timrot_timcount3)
     29 #elif defined(CONFIG_MX28)
     30 	mxs_reg_32(hw_timrot_timctrl0)
     31 	mxs_reg_32(hw_timrot_running_count0)
     32 	mxs_reg_32(hw_timrot_fixed_count0)
     33 	mxs_reg_32(hw_timrot_match_count0)
     34 	mxs_reg_32(hw_timrot_timctrl1)
     35 	mxs_reg_32(hw_timrot_running_count1)
     36 	mxs_reg_32(hw_timrot_fixed_count1)
     37 	mxs_reg_32(hw_timrot_match_count1)
     38 	mxs_reg_32(hw_timrot_timctrl2)
     39 	mxs_reg_32(hw_timrot_running_count2)
     40 	mxs_reg_32(hw_timrot_fixed_count2)
     41 	mxs_reg_32(hw_timrot_match_count2)
     42 	mxs_reg_32(hw_timrot_timctrl3)
     43 	mxs_reg_32(hw_timrot_running_count3)
     44 	mxs_reg_32(hw_timrot_fixed_count3)
     45 	mxs_reg_32(hw_timrot_match_count3)
     46 #endif
     47 	mxs_reg_32(hw_timrot_version)
     48 };
     49 #endif
     50 
     51 #define	TIMROT_ROTCTRL_SFTRST				(1 << 31)
     52 #define	TIMROT_ROTCTRL_CLKGATE				(1 << 30)
     53 #define	TIMROT_ROTCTRL_ROTARY_PRESENT			(1 << 29)
     54 #define	TIMROT_ROTCTRL_TIM3_PRESENT			(1 << 28)
     55 #define	TIMROT_ROTCTRL_TIM2_PRESENT			(1 << 27)
     56 #define	TIMROT_ROTCTRL_TIM1_PRESENT			(1 << 26)
     57 #define	TIMROT_ROTCTRL_TIM0_PRESENT			(1 << 25)
     58 #define	TIMROT_ROTCTRL_STATE_MASK			(0x7 << 22)
     59 #define	TIMROT_ROTCTRL_STATE_OFFSET			22
     60 #define	TIMROT_ROTCTRL_DIVIDER_MASK			(0x3f << 16)
     61 #define	TIMROT_ROTCTRL_DIVIDER_OFFSET			16
     62 #define	TIMROT_ROTCTRL_RELATIVE				(1 << 12)
     63 #define	TIMROT_ROTCTRL_OVERSAMPLE_MASK			(0x3 << 10)
     64 #define	TIMROT_ROTCTRL_OVERSAMPLE_OFFSET		10
     65 #define	TIMROT_ROTCTRL_OVERSAMPLE_8X			(0x0 << 10)
     66 #define	TIMROT_ROTCTRL_OVERSAMPLE_4X			(0x1 << 10)
     67 #define	TIMROT_ROTCTRL_OVERSAMPLE_2X			(0x2 << 10)
     68 #define	TIMROT_ROTCTRL_OVERSAMPLE_1X			(0x3 << 10)
     69 #define	TIMROT_ROTCTRL_POLARITY_B			(1 << 9)
     70 #define	TIMROT_ROTCTRL_POLARITY_A			(1 << 8)
     71 #if defined(CONFIG_MX23)
     72 #define	TIMROT_ROTCTRL_SELECT_B_MASK			(0x7 << 4)
     73 #elif defined(CONFIG_MX28)
     74 #define	TIMROT_ROTCTRL_SELECT_B_MASK			(0xf << 4)
     75 #endif
     76 #define	TIMROT_ROTCTRL_SELECT_B_OFFSET			4
     77 #define	TIMROT_ROTCTRL_SELECT_B_NEVER_TICK		(0x0 << 4)
     78 #define	TIMROT_ROTCTRL_SELECT_B_PWM0			(0x1 << 4)
     79 #define	TIMROT_ROTCTRL_SELECT_B_PWM1			(0x2 << 4)
     80 #define	TIMROT_ROTCTRL_SELECT_B_PWM2			(0x3 << 4)
     81 #define	TIMROT_ROTCTRL_SELECT_B_PWM3			(0x4 << 4)
     82 #define	TIMROT_ROTCTRL_SELECT_B_PWM4			(0x5 << 4)
     83 #if defined(CONFIG_MX23)
     84 #define	TIMROT_ROTCTRL_SELECT_B_ROTARYA		(0x6 << 4)
     85 #define	TIMROT_ROTCTRL_SELECT_B_ROTARYB		(0x7 << 4)
     86 #elif defined(CONFIG_MX28)
     87 #define	TIMROT_ROTCTRL_SELECT_B_PWM5			(0x6 << 4)
     88 #define	TIMROT_ROTCTRL_SELECT_B_PWM6			(0x7 << 4)
     89 #define	TIMROT_ROTCTRL_SELECT_B_PWM7			(0x8 << 4)
     90 #define	TIMROT_ROTCTRL_SELECT_B_ROTARYA			(0x9 << 4)
     91 #define	TIMROT_ROTCTRL_SELECT_B_ROTARYB			(0xa << 4)
     92 #endif
     93 #if defined(CONFIG_MX23)
     94 #define	TIMROT_ROTCTRL_SELECT_A_MASK			0x7
     95 #elif defined(CONFIG_MX28)
     96 #define	TIMROT_ROTCTRL_SELECT_A_MASK			0xf
     97 #endif
     98 #define	TIMROT_ROTCTRL_SELECT_A_OFFSET			0
     99 #define	TIMROT_ROTCTRL_SELECT_A_NEVER_TICK		0x0
    100 #define	TIMROT_ROTCTRL_SELECT_A_PWM0			0x1
    101 #define	TIMROT_ROTCTRL_SELECT_A_PWM1			0x2
    102 #define	TIMROT_ROTCTRL_SELECT_A_PWM2			0x3
    103 #define	TIMROT_ROTCTRL_SELECT_A_PWM3			0x4
    104 #define	TIMROT_ROTCTRL_SELECT_A_PWM4			0x5
    105 #if defined(CONFIG_MX23)
    106 #define	TIMROT_ROTCTRL_SELECT_A_ROTARYA		0x6
    107 #define	TIMROT_ROTCTRL_SELECT_A_ROTARYB		0x7
    108 #elif defined(CONFIG_MX28)
    109 #define	TIMROT_ROTCTRL_SELECT_A_PWM5			0x6
    110 #define	TIMROT_ROTCTRL_SELECT_A_PWM6			0x7
    111 #define	TIMROT_ROTCTRL_SELECT_A_PWM7			0x8
    112 #define	TIMROT_ROTCTRL_SELECT_A_ROTARYA			0x9
    113 #define	TIMROT_ROTCTRL_SELECT_A_ROTARYB			0xa
    114 #endif
    115 
    116 #define	TIMROT_ROTCOUNT_UPDOWN_MASK			0xffff
    117 #define	TIMROT_ROTCOUNT_UPDOWN_OFFSET			0
    118 
    119 #define	TIMROT_TIMCTRLn_IRQ				(1 << 15)
    120 #define	TIMROT_TIMCTRLn_IRQ_EN				(1 << 14)
    121 #if defined(CONFIG_MX28)
    122 #define	TIMROT_TIMCTRLn_MATCH_MODE			(1 << 11)
    123 #endif
    124 #define	TIMROT_TIMCTRLn_POLARITY			(1 << 8)
    125 #define	TIMROT_TIMCTRLn_UPDATE				(1 << 7)
    126 #define	TIMROT_TIMCTRLn_RELOAD				(1 << 6)
    127 #define	TIMROT_TIMCTRLn_PRESCALE_MASK			(0x3 << 4)
    128 #define	TIMROT_TIMCTRLn_PRESCALE_OFFSET			4
    129 #define	TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1		(0x0 << 4)
    130 #define	TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2		(0x1 << 4)
    131 #define	TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4		(0x2 << 4)
    132 #define	TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8		(0x3 << 4)
    133 #define	TIMROT_TIMCTRLn_SELECT_MASK			0xf
    134 #define	TIMROT_TIMCTRLn_SELECT_OFFSET			0
    135 #define	TIMROT_TIMCTRLn_SELECT_NEVER_TICK		0x0
    136 #define	TIMROT_TIMCTRLn_SELECT_PWM0			0x1
    137 #define	TIMROT_TIMCTRLn_SELECT_PWM1			0x2
    138 #define	TIMROT_TIMCTRLn_SELECT_PWM2			0x3
    139 #define	TIMROT_TIMCTRLn_SELECT_PWM3			0x4
    140 #define	TIMROT_TIMCTRLn_SELECT_PWM4			0x5
    141 #if defined(CONFIG_MX23)
    142 #define	TIMROT_TIMCTRLn_SELECT_ROTARYA		0x6
    143 #define	TIMROT_TIMCTRLn_SELECT_ROTARYB		0x7
    144 #define	TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL		0x8
    145 #define	TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL		0x9
    146 #define	TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL		0xa
    147 #define	TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL		0xb
    148 #define	TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS		0xc
    149 #elif defined(CONFIG_MX28)
    150 #define	TIMROT_TIMCTRLn_SELECT_PWM5			0x6
    151 #define	TIMROT_TIMCTRLn_SELECT_PWM6			0x7
    152 #define	TIMROT_TIMCTRLn_SELECT_PWM7			0x8
    153 #define	TIMROT_TIMCTRLn_SELECT_ROTARYA			0x9
    154 #define	TIMROT_TIMCTRLn_SELECT_ROTARYB			0xa
    155 #define	TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL		0xb
    156 #define	TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL		0xc
    157 #define	TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL		0xd
    158 #define	TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL		0xe
    159 #define	TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS		0xf
    160 #endif
    161 
    162 #if defined(CONFIG_MX23)
    163 #define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK	(0xffff << 16)
    164 #define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET	16
    165 #elif defined(CONFIG_MX28)
    166 #define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK	0xffffffff
    167 #define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET	0
    168 #endif
    169 
    170 #if defined(CONFIG_MX23)
    171 #define	TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK		0xffff
    172 #define	TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET		0
    173 #elif defined(CONFIG_MX28)
    174 #define	TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK		0xffffffff
    175 #define	TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET		0
    176 #endif
    177 
    178 #if defined(CONFIG_MX28)
    179 #define	TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK		0xffffffff
    180 #define	TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET		0
    181 #endif
    182 
    183 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_MASK		(0xf << 16)
    184 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET		16
    185 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK		(0x0 << 16)
    186 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0		(0x1 << 16)
    187 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1		(0x2 << 16)
    188 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2		(0x3 << 16)
    189 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3		(0x4 << 16)
    190 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4		(0x5 << 16)
    191 #if defined(CONFIG_MX23)
    192 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA		(0x6 << 16)
    193 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB		(0x7 << 16)
    194 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL		(0x8 << 16)
    195 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL		(0x9 << 16)
    196 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL		(0xa << 16)
    197 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL		(0xb << 16)
    198 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS		(0xc << 16)
    199 #elif defined(CONFIG_MX28)
    200 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5		(0x6 << 16)
    201 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6		(0x7 << 16)
    202 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7		(0x8 << 16)
    203 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA		(0x9 << 16)
    204 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB		(0xa << 16)
    205 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL		(0xb << 16)
    206 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL		(0xc << 16)
    207 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL		(0xd << 16)
    208 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL		(0xe << 16)
    209 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS		(0xf << 16)
    210 #endif
    211 #if defined(CONFIG_MX23)
    212 #define	TIMROT_TIMCTRL3_IRQ				(1 << 15)
    213 #define	TIMROT_TIMCTRL3_IRQ_EN				(1 << 14)
    214 #define	TIMROT_TIMCTRL3_DUTU_VALID			(1 << 10)
    215 #endif
    216 #define	TIMROT_TIMCTRL3_DUTY_CYCLE			(1 << 9)
    217 #if defined(CONFIG_MX23)
    218 #define	TIMROT_TIMCTRL3_POLARITY_MASK			(0x1 << 8)
    219 #define	TIMROT_TIMCTRL3_POLARITY_OFFSET		8
    220 #define	TIMROT_TIMCTRL3_POLARITY_POSITIVE		(0x0 << 8)
    221 #define	TIMROT_TIMCTRL3_POLARITY_NEGATIVE		(0x1 << 8)
    222 #define	TIMROT_TIMCTRL3_UPDATE				(1 << 7)
    223 #define	TIMROT_TIMCTRL3_RELOAD				(1 << 6)
    224 #define	TIMROT_TIMCTRL3_PRESCALE_MASK			(0x3 << 4)
    225 #define	TIMROT_TIMCTRL3_PRESCALE_OFFSET		4
    226 #define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1		(0x0 << 4)
    227 #define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2		(0x1 << 4)
    228 #define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4		(0x2 << 4)
    229 #define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8		(0x3 << 4)
    230 #define	TIMROT_TIMCTRL3_SELECT_MASK			0xf
    231 #define	TIMROT_TIMCTRL3_SELECT_OFFSET			0
    232 #define	TIMROT_TIMCTRL3_SELECT_NEVER_TICK		0x0
    233 #define	TIMROT_TIMCTRL3_SELECT_PWM0			0x1
    234 #define	TIMROT_TIMCTRL3_SELECT_PWM1			0x2
    235 #define	TIMROT_TIMCTRL3_SELECT_PWM2			0x3
    236 #define	TIMROT_TIMCTRL3_SELECT_PWM3			0x4
    237 #define	TIMROT_TIMCTRL3_SELECT_PWM4			0x5
    238 #define	TIMROT_TIMCTRL3_SELECT_ROTARYA		0x6
    239 #define	TIMROT_TIMCTRL3_SELECT_ROTARYB		0x7
    240 #define	TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL		0x8
    241 #define	TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL		0x9
    242 #define	TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL		0xa
    243 #define	TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL		0xb
    244 #define	TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS		0xc
    245 #define	TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK	(0xffff << 16)
    246 #define	TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET	16
    247 #define	TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK	0xffff
    248 #define	TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET	0
    249 #endif
    250 
    251 #define	TIMROT_VERSION_MAJOR_MASK			(0xff << 24)
    252 #define	TIMROT_VERSION_MAJOR_OFFSET			24
    253 #define	TIMROT_VERSION_MINOR_MASK			(0xff << 16)
    254 #define	TIMROT_VERSION_MINOR_OFFSET			16
    255 #define	TIMROT_VERSION_STEP_MASK			0xffff
    256 #define	TIMROT_VERSION_STEP_OFFSET			0
    257 
    258 #endif /* __MX28_REGS_TIMROT_H__ */
    259