| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| SubtargetFeatureInfo.h | 31 Record *TheDef;
36 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
40 return "Feature_" + TheDef->getName().str();
46 return "Feature_" + TheDef->getName().str() + "Bit";
50 return TheDef->getValueAsBit("RecomputePerFunction");
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| X86EVEX2VEXTablesEmitter.cpp | 64 OS << " { X86::" << Pair.first->TheDef->getName()
65 << ", X86::" << Pair.second->TheDef->getName() << " },\n";
110 Record *RecE = EVEXInst->TheDef;
111 Record *RecV = VEXInst->TheDef;
196 if (!Inst->TheDef->isSubClassOf("X86Inst"))
201 if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncVEX") {
202 uint64_t Opcode = getValueFromBitsInit(Inst->TheDef->
207 else if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncEVEX" &&
208 !Inst->TheDef->getValueAsBit("hasEVEX_K") &&
209 !Inst->TheDef->getValueAsBit("hasEVEX_B") &
[all...] |
| AsmWriterInst.cpp | 98 CGI.TheDef->getName() + "'!");
136 + CGI.TheDef->getName() + "'");
143 + CGI.TheDef->getName() + "'");
151 PrintFatalError("Bad operand modifier name in '"+ CGI.TheDef->getName() + "'");
156 + CGI.TheDef->getName() + "'");
160 PrintFatalError("Stray '$' in '" + CGI.TheDef->getName() +
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| RegisterBankEmitter.cpp | 35 const Record &TheDef;
44 RegisterBank(const Record &TheDef)
45 : TheDef(TheDef), RCs(), RCWithLargestRegsSize(nullptr) {}
48 StringRef getName() const { return TheDef.getValueAsString("Name"); }
50 std::string getEnumeratorName() const { return (TheDef.getName() + "ID").str(); }
54 return (TheDef.getName() + "CoverageData").str();
58 StringRef getInstanceVarName() const { return TheDef.getName(); }
60 const Record &getDef() const { return TheDef; }
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| X86FoldTablesEmitter.cpp | 79 return Inst->TheDef->getName().find(InstStr) != StringRef::npos;
85 return Inst->TheDef->getName().find(InstStr) != StringRef::npos;
111 OS << "{ X86::" << E.RegInst->TheDef->getName()
112 << ", X86::" << E.MemInst->TheDef->getName() << ", ";
299 StringRef AltRegInstStr = I->TheDef->getValueAsString("FoldGenRegForm");
317 Record *MemRec = MemInst->TheDef;
318 Record *RegRec = RegInst->TheDef;
447 Record *RegRec = RegInstr->TheDef;
448 Record *MemRec = MemInstr->TheDef;
503 Record *RegRec = RegInstr->TheDef;
[all...] |
| InstrInfoEmitter.cpp | 227 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
240 Inst->TheDef->getName().str());
446 Record *Inst = II->TheDef;
474 InstrNames.add(Inst->TheDef->getName());
492 OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
564 << Inst.TheDef->getValueAsInt("Size") << ",\t"
609 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
617 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName());
624 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
630 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs")
[all...] |
| SubtargetFeatureInfo.cpp | 22 errs() << getEnumName() << " " << Index << "\n" << *TheDef;
114 OS << " if (" << SFI.TheDef->getValueAsString("CondString") << ")\n";
132 SFI.TheDef->getValueAsString("AssemblerCondString");
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| CodeGenSchedule.cpp | 122 StringRef InstName = Inst->TheDef->getName();
125 Elts.insert(Inst->TheDef);
135 return LHS->TheDef->getName() < RHS;
138 return LHS < RHS->TheDef->getName() &&
139 !RHS->TheDef->getName().startswith(LHS);
150 StringRef InstName = Inst->TheDef->getName();
152 Elts.insert(Inst->TheDef);
335 Record *SchedDef = Inst->TheDef;
411 findRWs(CGRW.TheDef->getValueAsListOfDefs("Writes"), CGRW.Sequence,
462 RWVec, [Def](const CodeGenSchedRW &RW) { return RW.TheDef == Def; })
[all...] |
| AsmWriterEmitter.cpp | 126 << FirstInst.CGI->TheDef->getName() << ":\n";
129 << AWI.CGI->TheDef->getName() << ":\n";
141 FirstInst.CGI->TheDef->getName().str(),
146 AWI.CGI->TheDef->getName().str(),
184 InstrsForCase[idx] += Inst.CGI->TheDef->getName();
188 InstrsForCase.push_back(Inst.CGI->TheDef->getName());
404 << NumberedInstructions[i]->TheDef->getName() << "\n";
511 AsmName = Reg.TheDef->getValueAsString("AsmName");
517 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
527 Reg.TheDef->getValueAsListOfStrings("AltNames")
[all...] |
| CodeGenSchedule.h | 38 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
39 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
47 Record *TheDef;
57 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
60 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
75 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
81 assert((!HasVariants || TheDef) && "Variant write needs record def");
86 return TheDef || !Sequence.empty();
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| /external/llvm/utils/TableGen/ |
| AsmWriterInst.cpp | 98 CGI.TheDef->getName() + "'!");
136 + CGI.TheDef->getName() + "'");
143 + CGI.TheDef->getName() + "'");
151 PrintFatalError("Bad operand modifier name in '"+ CGI.TheDef->getName() + "'");
156 + CGI.TheDef->getName() + "'");
160 PrintFatalError("Stray '$' in '" + CGI.TheDef->getName() +
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| InstrInfoEmitter.cpp | 208 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
220 OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName());
360 Record *Inst = II->TheDef;
388 InstrNames.add(Inst->TheDef->getName());
406 OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
474 << Inst.TheDef->getValueAsInt("Size") << ",\t"
512 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
520 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName());
527 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
533 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs")
[all...] |
| CodeGenSchedule.h | 40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
41 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
49 Record *TheDef;
59 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
77 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
83 assert((!HasVariants || TheDef) && "Variant write needs record def");
88 return TheDef || !Sequence.empty();
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| AsmMatcherEmitter.cpp | 470 /// TheDef - This is the definition of the instruction or InstAlias that this
472 Record *const TheDef;
514 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI),
519 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
522 TheDef->getValueAsBit("UseInstAsmMatchConverter")) {
530 TheDef(RHS.TheDef), DefRec(RHS.DefRec), ResOperands(RHS.ResOperands),
660 Record *TheDef;
[all...] |
| AsmWriterEmitter.cpp | 105 << FirstInst.CGI->TheDef->getName() << ":\n";
108 << AWI.CGI->TheDef->getName() << ":\n";
120 FirstInst.CGI->TheDef->getName(),
125 AWI.CGI->TheDef->getName(),
165 InstrsForCase[idx] += Inst.CGI->TheDef->getName();
169 InstrsForCase.push_back(Inst.CGI->TheDef->getName());
386 << NumberedInstructions[i]->TheDef->getName() << "\n";
504 AsmName = Reg.TheDef->getValueAsString("AsmName");
510 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
520 Reg.TheDef->getValueAsListOfStrings("AltNames")
[all...] |
| CodeGenIntrinsics.h | 27 Record *TheDef; // The actual record defining this intrinsic.
|
| CodeGenSchedule.cpp | 73 if (R.match(Inst->TheDef->getName()))
74 Elts.insert(Inst->TheDef);
214 Record *SchedDef = Inst->TheDef;
293 findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence,
346 if (I->TheDef == Def)
354 Record *ReadDef = SchedReads[i].TheDef;
409 SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1;
435 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
438 AliasDef = AliasRW.TheDef;
[all...] |
| SubtargetEmitter.cpp | 653 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
654 return SchedWrite.TheDef;
660 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
661 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
666 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
669 AliasDef = AliasRW.TheDef;
680 || SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
694 + SchedWrite.TheDef->getName());
704 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance"))
705 return SchedRead.TheDef;
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| AsmWriterInst.cpp | 127 CGI.TheDef->getName() + "'!";
166 + CGI.TheDef->getName() + "'";
173 + CGI.TheDef->getName() + "'";
181 throw "Bad operand modifier name in '"+ CGI.TheDef->getName() + "'";
186 + CGI.TheDef->getName() + "'";
190 throw "Stray '$' in '" + CGI.TheDef->getName() +
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| InstrEnumEmitter.cpp | 42 OS << " " << NumberedInstructions[i]->TheDef->getName()
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| CodeGenIntrinsics.h | 27 Record *TheDef; // The actual record defining this intrinsic.
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| InstrInfoEmitter.cpp | 186 Record *Inst = (*II)->TheDef;
266 << getItinClassNumber(Inst.TheDef) << ",\t"
267 << Inst.TheDef->getValueAsInt("Size") << ",\t\""
268 << Inst.TheDef->getName() << "\", 0";
300 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
307 throw "Invalid TSFlags bit in " + Inst.TheDef->getName();
314 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
320 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
333 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
361 OS << " " << NumberedInstructions[i]->TheDef->getName(
[all...] |
| CodeGenRegisters.cpp | 29 : TheDef(R),
36 return TheDef->getName();
55 std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
56 std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
58 throw TGError(TheDef->getLoc(), "Register " + getName() +
65 throw TGError(TheDef->getLoc(), "SubRegIndex " + Indices[i]->getName() +
95 ListInit *Comps = TheDef->getValueAsListInit("CompositeIndices");
99 throw TGError(TheDef->getLoc(), "Invalid dag '" +
104 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
113 throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in "
[all...] |
| AsmMatcherEmitter.cpp | 369 /// TheDef - This is the definition of the instruction or InstAlias that this
371 Record *const TheDef;
409 : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) {
413 : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) {
520 Record *TheDef;
525 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
529 return "Feature_" + TheDef->getName();
638 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n"
[all...] |
| CodeGenInstruction.cpp | 28 CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
137 throw "'" + TheDef->getName() + "' does not have an operand named '$" +
157 throw TheDef->getName() + ": Illegal operand name: '" + Op + "'";
167 throw TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'";
177 throw TheDef->getName() + ": Illegal to refer to"
187 throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
195 throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
290 CodeGenInstruction::CodeGenInstruction(Record *R) : TheDef(R), Operands(R) {
481 CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
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