1 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This tablegen backend is responsible for emitting a description of the target 11 // instruction set for the code generator. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "CodeGenDAGPatterns.h" 16 #include "CodeGenSchedule.h" 17 #include "CodeGenTarget.h" 18 #include "SequenceToOffsetTable.h" 19 #include "TableGenBackends.h" 20 #include "llvm/ADT/StringExtras.h" 21 #include "llvm/TableGen/Error.h" 22 #include "llvm/TableGen/Record.h" 23 #include "llvm/TableGen/TableGenBackend.h" 24 #include <algorithm> 25 #include <cstdio> 26 #include <map> 27 #include <vector> 28 29 using namespace llvm; 30 31 namespace { 32 class InstrInfoEmitter { 33 RecordKeeper &Records; 34 CodeGenDAGPatterns CDP; 35 const CodeGenSchedModels &SchedModels; 36 37 public: 38 InstrInfoEmitter(RecordKeeper &R): 39 Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {} 40 41 // run - Output the instruction set description. 42 void run(raw_ostream &OS); 43 44 private: 45 void emitEnums(raw_ostream &OS); 46 47 typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy; 48 49 /// The keys of this map are maps which have OpName enum values as their keys 50 /// and instruction operand indices as their values. The values of this map 51 /// are lists of instruction names. 52 typedef std::map<std::map<unsigned, unsigned>, 53 std::vector<std::string> > OpNameMapTy; 54 typedef std::map<std::string, unsigned>::iterator StrUintMapIter; 55 void emitRecord(const CodeGenInstruction &Inst, unsigned Num, 56 Record *InstrInfo, 57 std::map<std::vector<Record*>, unsigned> &EL, 58 const OperandInfoMapTy &OpInfo, 59 raw_ostream &OS); 60 void emitOperandTypesEnum(raw_ostream &OS, const CodeGenTarget &Target); 61 void initOperandMapData( 62 ArrayRef<const CodeGenInstruction *> NumberedInstructions, 63 const std::string &Namespace, 64 std::map<std::string, unsigned> &Operands, 65 OpNameMapTy &OperandMap); 66 void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target, 67 ArrayRef<const CodeGenInstruction*> NumberedInstructions); 68 69 // Operand information. 70 void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs); 71 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst); 72 }; 73 } // end anonymous namespace 74 75 static void PrintDefList(const std::vector<Record*> &Uses, 76 unsigned Num, raw_ostream &OS) { 77 OS << "static const MCPhysReg ImplicitList" << Num << "[] = { "; 78 for (Record *U : Uses) 79 OS << getQualifiedName(U) << ", "; 80 OS << "0 };\n"; 81 } 82 83 //===----------------------------------------------------------------------===// 84 // Operand Info Emission. 85 //===----------------------------------------------------------------------===// 86 87 std::vector<std::string> 88 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { 89 std::vector<std::string> Result; 90 91 for (auto &Op : Inst.Operands) { 92 // Handle aggregate operands and normal operands the same way by expanding 93 // either case into a list of operands for this op. 94 std::vector<CGIOperandList::OperandInfo> OperandList; 95 96 // This might be a multiple operand thing. Targets like X86 have 97 // registers in their multi-operand operands. It may also be an anonymous 98 // operand, which has a single operand, but no declared class for the 99 // operand. 100 DagInit *MIOI = Op.MIOperandInfo; 101 102 if (!MIOI || MIOI->getNumArgs() == 0) { 103 // Single, anonymous, operand. 104 OperandList.push_back(Op); 105 } else { 106 for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) { 107 OperandList.push_back(Op); 108 109 Record *OpR = cast<DefInit>(MIOI->getArg(j))->getDef(); 110 OperandList.back().Rec = OpR; 111 } 112 } 113 114 for (unsigned j = 0, e = OperandList.size(); j != e; ++j) { 115 Record *OpR = OperandList[j].Rec; 116 std::string Res; 117 118 if (OpR->isSubClassOf("RegisterOperand")) 119 OpR = OpR->getValueAsDef("RegClass"); 120 if (OpR->isSubClassOf("RegisterClass")) 121 Res += getQualifiedName(OpR) + "RegClassID, "; 122 else if (OpR->isSubClassOf("PointerLikeRegClass")) 123 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", "; 124 else 125 // -1 means the operand does not have a fixed register class. 126 Res += "-1, "; 127 128 // Fill in applicable flags. 129 Res += "0"; 130 131 // Ptr value whose register class is resolved via callback. 132 if (OpR->isSubClassOf("PointerLikeRegClass")) 133 Res += "|(1<<MCOI::LookupPtrRegClass)"; 134 135 // Predicate operands. Check to see if the original unexpanded operand 136 // was of type PredicateOp. 137 if (Op.Rec->isSubClassOf("PredicateOp")) 138 Res += "|(1<<MCOI::Predicate)"; 139 140 // Optional def operands. Check to see if the original unexpanded operand 141 // was of type OptionalDefOperand. 142 if (Op.Rec->isSubClassOf("OptionalDefOperand")) 143 Res += "|(1<<MCOI::OptionalDef)"; 144 145 // Fill in operand type. 146 Res += ", "; 147 assert(!Op.OperandType.empty() && "Invalid operand type."); 148 Res += Op.OperandType; 149 150 // Fill in constraint info. 151 Res += ", "; 152 153 const CGIOperandList::ConstraintInfo &Constraint = 154 Op.Constraints[j]; 155 if (Constraint.isNone()) 156 Res += "0"; 157 else if (Constraint.isEarlyClobber()) 158 Res += "(1 << MCOI::EARLY_CLOBBER)"; 159 else { 160 assert(Constraint.isTied()); 161 Res += "((" + utostr(Constraint.getTiedOperand()) + 162 " << 16) | (1 << MCOI::TIED_TO))"; 163 } 164 165 Result.push_back(Res); 166 } 167 } 168 169 return Result; 170 } 171 172 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS, 173 OperandInfoMapTy &OperandInfoIDs) { 174 // ID #0 is for no operand info. 175 unsigned OperandListNum = 0; 176 OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum; 177 178 OS << "\n"; 179 const CodeGenTarget &Target = CDP.getTargetInfo(); 180 for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) { 181 std::vector<std::string> OperandInfo = GetOperandInfo(*Inst); 182 unsigned &N = OperandInfoIDs[OperandInfo]; 183 if (N != 0) continue; 184 185 N = ++OperandListNum; 186 OS << "static const MCOperandInfo OperandInfo" << N << "[] = { "; 187 for (const std::string &Info : OperandInfo) 188 OS << "{ " << Info << " }, "; 189 OS << "};\n"; 190 } 191 } 192 193 /// Initialize data structures for generating operand name mappings. 194 /// 195 /// \param Operands [out] A map used to generate the OpName enum with operand 196 /// names as its keys and operand enum values as its values. 197 /// \param OperandMap [out] A map for representing the operand name mappings for 198 /// each instructions. This is used to generate the OperandMap table as 199 /// well as the getNamedOperandIdx() function. 200 void InstrInfoEmitter::initOperandMapData( 201 ArrayRef<const CodeGenInstruction *> NumberedInstructions, 202 const std::string &Namespace, 203 std::map<std::string, unsigned> &Operands, 204 OpNameMapTy &OperandMap) { 205 206 unsigned NumOperands = 0; 207 for (const CodeGenInstruction *Inst : NumberedInstructions) { 208 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) 209 continue; 210 std::map<unsigned, unsigned> OpList; 211 for (const auto &Info : Inst->Operands) { 212 StrUintMapIter I = Operands.find(Info.Name); 213 214 if (I == Operands.end()) { 215 I = Operands.insert(Operands.begin(), 216 std::pair<std::string, unsigned>(Info.Name, NumOperands++)); 217 } 218 OpList[I->second] = Info.MIOperandNo; 219 } 220 OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName()); 221 } 222 } 223 224 /// Generate a table and function for looking up the indices of operands by 225 /// name. 226 /// 227 /// This code generates: 228 /// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry 229 /// for each operand name. 230 /// - A 2-dimensional table called OperandMap for mapping OpName enum values to 231 /// operand indices. 232 /// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) 233 /// for looking up the operand index for an instruction, given a value from 234 /// OpName enum 235 void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS, 236 const CodeGenTarget &Target, 237 ArrayRef<const CodeGenInstruction*> NumberedInstructions) { 238 239 const std::string &Namespace = Target.getInstNamespace(); 240 std::string OpNameNS = "OpName"; 241 // Map of operand names to their enumeration value. This will be used to 242 // generate the OpName enum. 243 std::map<std::string, unsigned> Operands; 244 OpNameMapTy OperandMap; 245 246 initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap); 247 248 OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n"; 249 OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n"; 250 OS << "namespace llvm {\n"; 251 OS << "namespace " << Namespace << " {\n"; 252 OS << "namespace " << OpNameNS << " {\n"; 253 OS << "enum {\n"; 254 for (const auto &Op : Operands) 255 OS << " " << Op.first << " = " << Op.second << ",\n"; 256 257 OS << "OPERAND_LAST"; 258 OS << "\n};\n"; 259 OS << "} // end namespace OpName\n"; 260 OS << "} // end namespace " << Namespace << "\n"; 261 OS << "} // end namespace llvm\n"; 262 OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n\n"; 263 264 OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n"; 265 OS << "#undef GET_INSTRINFO_NAMED_OPS\n"; 266 OS << "namespace llvm {\n"; 267 OS << "namespace " << Namespace << " {\n"; 268 OS << "LLVM_READONLY\n"; 269 OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n"; 270 if (!Operands.empty()) { 271 OS << " static const int16_t OperandMap [][" << Operands.size() 272 << "] = {\n"; 273 for (const auto &Entry : OperandMap) { 274 const std::map<unsigned, unsigned> &OpList = Entry.first; 275 OS << "{"; 276 277 // Emit a row of the OperandMap table 278 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 279 OS << (OpList.count(i) == 0 ? -1 : (int)OpList.find(i)->second) << ", "; 280 281 OS << "},\n"; 282 } 283 OS << "};\n"; 284 285 OS << " switch(Opcode) {\n"; 286 unsigned TableIndex = 0; 287 for (const auto &Entry : OperandMap) { 288 for (const std::string &Name : Entry.second) 289 OS << " case " << Name << ":\n"; 290 291 OS << " return OperandMap[" << TableIndex++ << "][NamedIdx];\n"; 292 } 293 OS << " default: return -1;\n"; 294 OS << " }\n"; 295 } else { 296 // There are no operands, so no need to emit anything 297 OS << " return -1;\n"; 298 } 299 OS << "}\n"; 300 OS << "} // end namespace " << Namespace << "\n"; 301 OS << "} // end namespace llvm\n"; 302 OS << "#endif //GET_INSTRINFO_NAMED_OPS\n\n"; 303 304 } 305 306 /// Generate an enum for all the operand types for this target, under the 307 /// llvm::TargetNamespace::OpTypes namespace. 308 /// Operand types are all definitions derived of the Operand Target.td class. 309 void InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS, 310 const CodeGenTarget &Target) { 311 312 const std::string &Namespace = Target.getInstNamespace(); 313 std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand"); 314 315 OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n"; 316 OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n"; 317 OS << "namespace llvm {\n"; 318 OS << "namespace " << Namespace << " {\n"; 319 OS << "namespace OpTypes {\n"; 320 OS << "enum OperandType {\n"; 321 322 unsigned EnumVal = 0; 323 for (const Record *Op : Operands) { 324 if (!Op->isAnonymous()) 325 OS << " " << Op->getName() << " = " << EnumVal << ",\n"; 326 ++EnumVal; 327 } 328 329 OS << " OPERAND_TYPE_LIST_END" << "\n};\n"; 330 OS << "} // end namespace OpTypes\n"; 331 OS << "} // end namespace " << Namespace << "\n"; 332 OS << "} // end namespace llvm\n"; 333 OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n"; 334 } 335 336 //===----------------------------------------------------------------------===// 337 // Main Output. 338 //===----------------------------------------------------------------------===// 339 340 // run - Emit the main instruction description records for the target... 341 void InstrInfoEmitter::run(raw_ostream &OS) { 342 emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS); 343 emitEnums(OS); 344 345 OS << "#ifdef GET_INSTRINFO_MC_DESC\n"; 346 OS << "#undef GET_INSTRINFO_MC_DESC\n"; 347 348 OS << "namespace llvm {\n\n"; 349 350 CodeGenTarget &Target = CDP.getTargetInfo(); 351 const std::string &TargetName = Target.getName(); 352 Record *InstrInfo = Target.getInstructionSet(); 353 354 // Keep track of all of the def lists we have emitted already. 355 std::map<std::vector<Record*>, unsigned> EmittedLists; 356 unsigned ListNumber = 0; 357 358 // Emit all of the instruction's implicit uses and defs. 359 for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) { 360 Record *Inst = II->TheDef; 361 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses"); 362 if (!Uses.empty()) { 363 unsigned &IL = EmittedLists[Uses]; 364 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS); 365 } 366 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); 367 if (!Defs.empty()) { 368 unsigned &IL = EmittedLists[Defs]; 369 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); 370 } 371 } 372 373 OperandInfoMapTy OperandInfoIDs; 374 375 // Emit all of the operand info records. 376 EmitOperandInfo(OS, OperandInfoIDs); 377 378 // Emit all of the MCInstrDesc records in their ENUM ordering. 379 // 380 OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n"; 381 ArrayRef<const CodeGenInstruction*> NumberedInstructions = 382 Target.getInstructionsByEnumValue(); 383 384 SequenceToOffsetTable<std::string> InstrNames; 385 unsigned Num = 0; 386 for (const CodeGenInstruction *Inst : NumberedInstructions) { 387 // Keep a list of the instruction names. 388 InstrNames.add(Inst->TheDef->getName()); 389 // Emit the record into the table. 390 emitRecord(*Inst, Num++, InstrInfo, EmittedLists, OperandInfoIDs, OS); 391 } 392 OS << "};\n\n"; 393 394 // Emit the array of instruction names. 395 InstrNames.layout(); 396 OS << "extern const char " << TargetName << "InstrNameData[] = {\n"; 397 InstrNames.emit(OS, printChar); 398 OS << "};\n\n"; 399 400 OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {"; 401 Num = 0; 402 for (const CodeGenInstruction *Inst : NumberedInstructions) { 403 // Newline every eight entries. 404 if (Num % 8 == 0) 405 OS << "\n "; 406 OS << InstrNames.get(Inst->TheDef->getName()) << "U, "; 407 ++Num; 408 } 409 410 OS << "\n};\n\n"; 411 412 // MCInstrInfo initialization routine. 413 OS << "static inline void Init" << TargetName 414 << "MCInstrInfo(MCInstrInfo *II) {\n"; 415 OS << " II->InitMCInstrInfo(" << TargetName << "Insts, " 416 << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, " 417 << NumberedInstructions.size() << ");\n}\n\n"; 418 419 OS << "} // end llvm namespace\n"; 420 421 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n"; 422 423 // Create a TargetInstrInfo subclass to hide the MC layer initialization. 424 OS << "#ifdef GET_INSTRINFO_HEADER\n"; 425 OS << "#undef GET_INSTRINFO_HEADER\n"; 426 427 std::string ClassName = TargetName + "GenInstrInfo"; 428 OS << "namespace llvm {\n"; 429 OS << "struct " << ClassName << " : public TargetInstrInfo {\n" 430 << " explicit " << ClassName 431 << "(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);\n" 432 << " ~" << ClassName << "() override {}\n" 433 << "};\n"; 434 OS << "} // end llvm namespace\n"; 435 436 OS << "#endif // GET_INSTRINFO_HEADER\n\n"; 437 438 OS << "#ifdef GET_INSTRINFO_CTOR_DTOR\n"; 439 OS << "#undef GET_INSTRINFO_CTOR_DTOR\n"; 440 441 OS << "namespace llvm {\n"; 442 OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n"; 443 OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n"; 444 OS << "extern const char " << TargetName << "InstrNameData[];\n"; 445 OS << ClassName << "::" << ClassName 446 << "(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)\n" 447 << " : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {\n" 448 << " InitMCInstrInfo(" << TargetName << "Insts, " << TargetName 449 << "InstrNameIndices, " << TargetName << "InstrNameData, " 450 << NumberedInstructions.size() << ");\n}\n"; 451 OS << "} // end llvm namespace\n"; 452 453 OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n"; 454 455 emitOperandNameMappings(OS, Target, NumberedInstructions); 456 457 emitOperandTypesEnum(OS, Target); 458 } 459 460 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, 461 Record *InstrInfo, 462 std::map<std::vector<Record*>, unsigned> &EmittedLists, 463 const OperandInfoMapTy &OpInfo, 464 raw_ostream &OS) { 465 int MinOperands = 0; 466 if (!Inst.Operands.empty()) 467 // Each logical operand can be multiple MI operands. 468 MinOperands = Inst.Operands.back().MIOperandNo + 469 Inst.Operands.back().MINumOperands; 470 471 OS << " { "; 472 OS << Num << ",\t" << MinOperands << ",\t" 473 << Inst.Operands.NumDefs << ",\t" 474 << Inst.TheDef->getValueAsInt("Size") << ",\t" 475 << SchedModels.getSchedClassIdx(Inst) << ",\t0"; 476 477 // Emit all of the target independent flags... 478 if (Inst.isPseudo) OS << "|(1ULL<<MCID::Pseudo)"; 479 if (Inst.isReturn) OS << "|(1ULL<<MCID::Return)"; 480 if (Inst.isBranch) OS << "|(1ULL<<MCID::Branch)"; 481 if (Inst.isIndirectBranch) OS << "|(1ULL<<MCID::IndirectBranch)"; 482 if (Inst.isCompare) OS << "|(1ULL<<MCID::Compare)"; 483 if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)"; 484 if (Inst.isBitcast) OS << "|(1ULL<<MCID::Bitcast)"; 485 if (Inst.isSelect) OS << "|(1ULL<<MCID::Select)"; 486 if (Inst.isBarrier) OS << "|(1ULL<<MCID::Barrier)"; 487 if (Inst.hasDelaySlot) OS << "|(1ULL<<MCID::DelaySlot)"; 488 if (Inst.isCall) OS << "|(1ULL<<MCID::Call)"; 489 if (Inst.canFoldAsLoad) OS << "|(1ULL<<MCID::FoldableAsLoad)"; 490 if (Inst.mayLoad) OS << "|(1ULL<<MCID::MayLoad)"; 491 if (Inst.mayStore) OS << "|(1ULL<<MCID::MayStore)"; 492 if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)"; 493 if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)"; 494 if (Inst.isCommutable) OS << "|(1ULL<<MCID::Commutable)"; 495 if (Inst.isTerminator) OS << "|(1ULL<<MCID::Terminator)"; 496 if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)"; 497 if (Inst.isNotDuplicable) OS << "|(1ULL<<MCID::NotDuplicable)"; 498 if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)"; 499 if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)"; 500 if (Inst.hasPostISelHook) OS << "|(1ULL<<MCID::HasPostISelHook)"; 501 if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)"; 502 if (Inst.hasSideEffects) OS << "|(1ULL<<MCID::UnmodeledSideEffects)"; 503 if (Inst.isAsCheapAsAMove) OS << "|(1ULL<<MCID::CheapAsAMove)"; 504 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)"; 505 if (Inst.hasExtraDefRegAllocReq) OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)"; 506 if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)"; 507 if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)"; 508 if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)"; 509 if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)"; 510 511 // Emit all of the target-specific flags... 512 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags"); 513 if (!TSF) 514 PrintFatalError("no TSFlags?"); 515 uint64_t Value = 0; 516 for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) { 517 if (BitInit *Bit = dyn_cast<BitInit>(TSF->getBit(i))) 518 Value |= uint64_t(Bit->getValue()) << i; 519 else 520 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName()); 521 } 522 OS << ", 0x"; 523 OS.write_hex(Value); 524 OS << "ULL, "; 525 526 // Emit the implicit uses and defs lists... 527 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); 528 if (UseList.empty()) 529 OS << "nullptr, "; 530 else 531 OS << "ImplicitList" << EmittedLists[UseList] << ", "; 532 533 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); 534 if (DefList.empty()) 535 OS << "nullptr, "; 536 else 537 OS << "ImplicitList" << EmittedLists[DefList] << ", "; 538 539 // Emit the operand info. 540 std::vector<std::string> OperandInfo = GetOperandInfo(Inst); 541 if (OperandInfo.empty()) 542 OS << "nullptr"; 543 else 544 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; 545 546 CodeGenTarget &Target = CDP.getTargetInfo(); 547 if (Inst.HasComplexDeprecationPredicate) 548 // Emit a function pointer to the complex predicate method. 549 OS << ", -1 " 550 << ",&get" << Inst.DeprecatedReason << "DeprecationInfo"; 551 else if (!Inst.DeprecatedReason.empty()) 552 // Emit the Subtarget feature. 553 OS << ", " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason 554 << " ,nullptr"; 555 else 556 // Instruction isn't deprecated. 557 OS << ", -1 ,nullptr"; 558 559 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; 560 } 561 562 // emitEnums - Print out enum values for all of the instructions. 563 void InstrInfoEmitter::emitEnums(raw_ostream &OS) { 564 565 OS << "#ifdef GET_INSTRINFO_ENUM\n"; 566 OS << "#undef GET_INSTRINFO_ENUM\n"; 567 568 OS << "namespace llvm {\n\n"; 569 570 CodeGenTarget Target(Records); 571 572 // We must emit the PHI opcode first... 573 std::string Namespace = Target.getInstNamespace(); 574 575 if (Namespace.empty()) 576 PrintFatalError("No instructions defined!"); 577 578 OS << "namespace " << Namespace << " {\n"; 579 OS << " enum {\n"; 580 unsigned Num = 0; 581 for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) 582 OS << " " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n"; 583 OS << " INSTRUCTION_LIST_END = " << Num << "\n"; 584 OS << " };\n\n"; 585 OS << "namespace Sched {\n"; 586 OS << " enum {\n"; 587 Num = 0; 588 for (const auto &Class : SchedModels.explicit_classes()) 589 OS << " " << Class.Name << "\t= " << Num++ << ",\n"; 590 OS << " SCHED_LIST_END = " << Num << "\n"; 591 OS << " };\n"; 592 OS << "} // end Sched namespace\n"; 593 OS << "} // end " << Namespace << " namespace\n"; 594 OS << "} // end llvm namespace\n"; 595 596 OS << "#endif // GET_INSTRINFO_ENUM\n\n"; 597 } 598 599 namespace llvm { 600 601 void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) { 602 InstrInfoEmitter(RK).run(OS); 603 EmitMapTable(RK, OS); 604 } 605 606 } // end llvm namespace 607