| /external/vixl/test/aarch32/ |
| test-simulator-cond-rd-operand-rn-a32.cc | 127 M(Uxtb) \
486 #include "aarch32/traces/simulator-cond-rd-operand-rn-uxtb-a32.h"
|
| test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 119 M(Uxtb) \
549 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-uxtb-a32.h"
[all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 119 M(Uxtb) \
549 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-uxtb-t32.h"
[all...] |
| test-simulator-cond-rd-operand-rn-t32.cc | 127 M(Uxtb) \
486 #include "aarch32/traces/simulator-cond-rd-operand-rn-uxtb-t32.h"
|
| test-disasm-a32.cc | [all...] |
| /art/compiler/utils/arm64/ |
| jni_macro_assembler_arm64.cc | 520 ___ Uxtb(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister()));
|
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 1005 void TurboAssembler::Uxtb(const Register& rd, const Register& rn) {
1008 uxtb(rd, rn);
[all...] |
| macro-assembler-arm64.h | [all...] |
| /art/compiler/optimizing/ |
| intrinsics_arm64.cc | [all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.h | [all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.h | [all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | 491 __ Mvn(w10, Operand(w2, UXTB));
666 __ Mov(w23, Operand(w13, UXTB));
720 __ Mov(w19, Operand(w11, UXTB, 1));
801 __ Orr(w6, w0, Operand(w1, UXTB));
895 __ Orn(w6, w0, Operand(w1, UXTB));
[all...] |
