1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 28 // ----------------------------------------------------------------------------- 29 // This file is auto generated from the 30 // test/aarch32/config/template-simulator-aarch32.cc.in template file using 31 // tools/generate_tests.py. 32 // 33 // PLEASE DO NOT EDIT. 34 // ----------------------------------------------------------------------------- 35 36 37 #include "test-runner.h" 38 39 #include "test-utils.h" 40 #include "test-utils-aarch32.h" 41 42 #include "aarch32/assembler-aarch32.h" 43 #include "aarch32/disasm-aarch32.h" 44 #include "aarch32/macro-assembler-aarch32.h" 45 46 #define __ masm. 47 #define BUF_SIZE (4096) 48 49 #ifdef VIXL_INCLUDE_SIMULATOR_AARCH32 50 // Run tests with the simulator. 51 52 #define SETUP() MacroAssembler masm(BUF_SIZE) 53 54 #define START() masm.GetBuffer()->Reset() 55 56 #define END() \ 57 __ Hlt(0); \ 58 __ FinalizeCode(); 59 60 // TODO: Run the tests in the simulator. 61 #define RUN() 62 63 #else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32. 64 65 #define SETUP() \ 66 MacroAssembler masm(BUF_SIZE); \ 67 UseScratchRegisterScope harness_scratch; 68 69 #define START() \ 70 harness_scratch.Open(&masm); \ 71 harness_scratch.ExcludeAll(); \ 72 masm.GetBuffer()->Reset(); \ 73 __ Push(r4); \ 74 __ Push(r5); \ 75 __ Push(r6); \ 76 __ Push(r7); \ 77 __ Push(r8); \ 78 __ Push(r9); \ 79 __ Push(r10); \ 80 __ Push(r11); \ 81 __ Push(lr); \ 82 harness_scratch.Include(ip); 83 84 #define END() \ 85 harness_scratch.Exclude(ip); \ 86 __ Pop(lr); \ 87 __ Pop(r11); \ 88 __ Pop(r10); \ 89 __ Pop(r9); \ 90 __ Pop(r8); \ 91 __ Pop(r7); \ 92 __ Pop(r6); \ 93 __ Pop(r5); \ 94 __ Pop(r4); \ 95 __ Bx(lr); \ 96 __ FinalizeCode(); \ 97 harness_scratch.Close(); 98 99 #define RUN() \ 100 { \ 101 int pcs_offset = masm.IsUsingT32() ? 1 : 0; \ 102 masm.GetBuffer()->SetExecutable(); \ 103 ExecuteMemory(masm.GetBuffer()->GetStartAddress<byte*>(), \ 104 masm.GetSizeOfCodeGenerated(), \ 105 pcs_offset); \ 106 masm.GetBuffer()->SetWritable(); \ 107 } 108 109 #endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32 110 111 namespace vixl { 112 namespace aarch32 { 113 114 // List of instruction encodings: 115 #define FOREACH_INSTRUCTION(M) \ 116 M(Sxtb) \ 117 M(Sxtb16) \ 118 M(Sxth) \ 119 M(Uxtb) \ 120 M(Uxtb16) \ 121 M(Uxth) 122 123 124 // The following definitions are defined again in each generated test, therefore 125 // we need to place them in an anomymous namespace. It expresses that they are 126 // local to this file only, and the compiler is not allowed to share these types 127 // across test files during template instantiation. Specifically, `Operands` and 128 // `Inputs` have various layouts across generated tests so they absolutely 129 // cannot be shared. 130 131 #ifdef VIXL_INCLUDE_TARGET_T32 132 namespace { 133 134 // Values to be passed to the assembler to produce the instruction under test. 135 struct Operands { 136 Condition cond; 137 Register rd; 138 Register rn; 139 ShiftType ror; 140 uint32_t amount; 141 }; 142 143 // Input data to feed to the instruction. 144 struct Inputs { 145 uint32_t apsr; 146 uint32_t rd; 147 uint32_t rn; 148 }; 149 150 // This structure contains all input data needed to test one specific encoding. 151 // It used to generate a loop over an instruction. 152 struct TestLoopData { 153 // The `operands` fields represents the values to pass to the assembler to 154 // produce the instruction. 155 Operands operands; 156 // Description of the operands, used for error reporting. 157 const char* operands_description; 158 // Unique identifier, used for generating traces. 159 const char* identifier; 160 // Array of values to be fed to the instruction. 161 size_t input_size; 162 const Inputs* inputs; 163 }; 164 165 static const Inputs kCondition[] = {{NFlag, 0xabababab, 0xabababab}, 166 {ZFlag, 0xabababab, 0xabababab}, 167 {CFlag, 0xabababab, 0xabababab}, 168 {VFlag, 0xabababab, 0xabababab}, 169 {NZFlag, 0xabababab, 0xabababab}, 170 {NCFlag, 0xabababab, 0xabababab}, 171 {NVFlag, 0xabababab, 0xabababab}, 172 {ZCFlag, 0xabababab, 0xabababab}, 173 {ZVFlag, 0xabababab, 0xabababab}, 174 {CVFlag, 0xabababab, 0xabababab}, 175 {NZCFlag, 0xabababab, 0xabababab}, 176 {NZVFlag, 0xabababab, 0xabababab}, 177 {NCVFlag, 0xabababab, 0xabababab}, 178 {ZCVFlag, 0xabababab, 0xabababab}, 179 {NZCVFlag, 0xabababab, 0xabababab}}; 180 181 static const Inputs kRdIsRn[] = 182 {{NoFlag, 0x00000000, 0x00000000}, {NoFlag, 0x00000001, 0x00000001}, 183 {NoFlag, 0x00000002, 0x00000002}, {NoFlag, 0x00000020, 0x00000020}, 184 {NoFlag, 0x0000007d, 0x0000007d}, {NoFlag, 0x0000007e, 0x0000007e}, 185 {NoFlag, 0x0000007f, 0x0000007f}, {NoFlag, 0x00007ffd, 0x00007ffd}, 186 {NoFlag, 0x00007ffe, 0x00007ffe}, {NoFlag, 0x00007fff, 0x00007fff}, 187 {NoFlag, 0x33333333, 0x33333333}, {NoFlag, 0x55555555, 0x55555555}, 188 {NoFlag, 0x7ffffffd, 0x7ffffffd}, {NoFlag, 0x7ffffffe, 0x7ffffffe}, 189 {NoFlag, 0x7fffffff, 0x7fffffff}, {NoFlag, 0x80000000, 0x80000000}, 190 {NoFlag, 0x80000001, 0x80000001}, {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa}, 191 {NoFlag, 0xcccccccc, 0xcccccccc}, {NoFlag, 0xffff8000, 0xffff8000}, 192 {NoFlag, 0xffff8001, 0xffff8001}, {NoFlag, 0xffff8002, 0xffff8002}, 193 {NoFlag, 0xffff8003, 0xffff8003}, {NoFlag, 0xffffff80, 0xffffff80}, 194 {NoFlag, 0xffffff81, 0xffffff81}, {NoFlag, 0xffffff82, 0xffffff82}, 195 {NoFlag, 0xffffff83, 0xffffff83}, {NoFlag, 0xffffffe0, 0xffffffe0}, 196 {NoFlag, 0xfffffffd, 0xfffffffd}, {NoFlag, 0xfffffffe, 0xfffffffe}, 197 {NoFlag, 0xffffffff, 0xffffffff}}; 198 199 static const Inputs kRdIsNotRn[] = 200 {{NoFlag, 0x00000002, 0xcccccccc}, {NoFlag, 0x7ffffffd, 0x00007ffe}, 201 {NoFlag, 0xffffff80, 0x00000020}, {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa}, 202 {NoFlag, 0x33333333, 0xffffff82}, {NoFlag, 0xffff8001, 0x7ffffffe}, 203 {NoFlag, 0xfffffffd, 0x00007ffe}, {NoFlag, 0xffffff80, 0x80000000}, 204 {NoFlag, 0x00000001, 0x33333333}, {NoFlag, 0xcccccccc, 0x7ffffffe}, 205 {NoFlag, 0x00000000, 0xcccccccc}, {NoFlag, 0x00000000, 0x55555555}, 206 {NoFlag, 0xffffffff, 0xffffffff}, {NoFlag, 0x0000007e, 0xffff8002}, 207 {NoFlag, 0x80000000, 0x7ffffffd}, {NoFlag, 0xffffff81, 0x0000007e}, 208 {NoFlag, 0x0000007f, 0xffff8001}, {NoFlag, 0xffffffe0, 0x00007ffd}, 209 {NoFlag, 0xffff8003, 0x00000002}, {NoFlag, 0xffffff83, 0x55555555}, 210 {NoFlag, 0xffffff83, 0xffffff80}, {NoFlag, 0xffffff81, 0xffff8000}, 211 {NoFlag, 0x00000020, 0x7ffffffe}, {NoFlag, 0xffffffe0, 0x00000000}, 212 {NoFlag, 0x7fffffff, 0x0000007e}, {NoFlag, 0x80000001, 0xffffffff}, 213 {NoFlag, 0x00000001, 0x80000001}, {NoFlag, 0x00000002, 0x0000007f}, 214 {NoFlag, 0x7fffffff, 0xcccccccc}, {NoFlag, 0x80000001, 0x00007ffe}, 215 {NoFlag, 0xffff8002, 0x0000007e}, {NoFlag, 0x00007ffe, 0xcccccccc}, 216 {NoFlag, 0x80000000, 0xffff8002}, {NoFlag, 0xffffff83, 0x7ffffffe}, 217 {NoFlag, 0xffff8001, 0x00000001}, {NoFlag, 0xffffff81, 0x00000020}, 218 {NoFlag, 0xfffffffe, 0xffff8001}, {NoFlag, 0xffffffff, 0xfffffffe}, 219 {NoFlag, 0xcccccccc, 0x55555555}, {NoFlag, 0x00000020, 0xffffff83}, 220 {NoFlag, 0xffffff83, 0xffff8001}, {NoFlag, 0xffffff83, 0xffff8000}, 221 {NoFlag, 0x00007fff, 0x00000002}, {NoFlag, 0x55555555, 0xffff8000}, 222 {NoFlag, 0x80000001, 0xffffff81}, {NoFlag, 0x00000002, 0x00000000}, 223 {NoFlag, 0x33333333, 0xffffff81}, {NoFlag, 0xffff8001, 0xffffff82}, 224 {NoFlag, 0xcccccccc, 0xffff8003}, {NoFlag, 0xffff8003, 0x7ffffffd}, 225 {NoFlag, 0x0000007d, 0x00007ffe}, {NoFlag, 0xffffff80, 0x0000007d}, 226 {NoFlag, 0xaaaaaaaa, 0x00007ffd}, {NoFlag, 0x80000000, 0xffffff82}, 227 {NoFlag, 0x00000002, 0x7ffffffe}, {NoFlag, 0x00000002, 0xffffff83}, 228 {NoFlag, 0x55555555, 0x00000002}, {NoFlag, 0xffffffff, 0xffffff82}, 229 {NoFlag, 0xaaaaaaaa, 0x00000020}, {NoFlag, 0x00000001, 0xffffff82}, 230 {NoFlag, 0x0000007f, 0xffffff82}, {NoFlag, 0x7ffffffd, 0xaaaaaaaa}, 231 {NoFlag, 0x00007ffe, 0x00000001}, {NoFlag, 0xfffffffd, 0xffffffe0}, 232 {NoFlag, 0xffffff81, 0xffffff83}, {NoFlag, 0x0000007d, 0x00000000}, 233 {NoFlag, 0x0000007d, 0xffff8000}, {NoFlag, 0xffffff81, 0x7fffffff}, 234 {NoFlag, 0xffffffff, 0x80000000}, {NoFlag, 0x00000000, 0x00000001}, 235 {NoFlag, 0x55555555, 0xffffff82}, {NoFlag, 0x00007ffe, 0x00007ffe}, 236 {NoFlag, 0x80000001, 0xfffffffd}, {NoFlag, 0x00007fff, 0x33333333}, 237 {NoFlag, 0x00007fff, 0x80000000}, {NoFlag, 0xcccccccc, 0x00007fff}, 238 {NoFlag, 0xfffffffe, 0xffffffe0}, {NoFlag, 0x7ffffffe, 0x0000007f}, 239 {NoFlag, 0x00007ffd, 0xffff8001}, {NoFlag, 0x00000002, 0x00000001}, 240 {NoFlag, 0x80000000, 0xffffffff}, {NoFlag, 0xffffff83, 0xcccccccc}, 241 {NoFlag, 0xffff8002, 0x7ffffffe}, {NoFlag, 0xaaaaaaaa, 0x00000000}, 242 {NoFlag, 0xffffff80, 0xcccccccc}, {NoFlag, 0x33333333, 0xffffff83}, 243 {NoFlag, 0x0000007e, 0xffffffe0}, {NoFlag, 0x0000007e, 0x00007fff}, 244 {NoFlag, 0x0000007f, 0x00000002}, {NoFlag, 0x7ffffffe, 0xcccccccc}, 245 {NoFlag, 0x0000007d, 0xffffff80}, {NoFlag, 0x00007fff, 0x00000020}, 246 {NoFlag, 0x7ffffffe, 0xfffffffe}, {NoFlag, 0xfffffffe, 0xffffff81}, 247 {NoFlag, 0xffffffff, 0x0000007f}, {NoFlag, 0xffff8002, 0x7ffffffd}, 248 {NoFlag, 0xffff8001, 0xfffffffe}, {NoFlag, 0x33333333, 0xffff8002}, 249 {NoFlag, 0x00000000, 0xffffffff}, {NoFlag, 0x33333333, 0xffffff80}, 250 {NoFlag, 0x0000007f, 0x00007fff}, {NoFlag, 0xffffffff, 0xffff8001}, 251 {NoFlag, 0x7fffffff, 0xffff8002}, {NoFlag, 0x7ffffffd, 0xffffff83}, 252 {NoFlag, 0x7fffffff, 0x0000007f}, {NoFlag, 0xffffff83, 0xfffffffe}, 253 {NoFlag, 0x7ffffffe, 0xffff8003}, {NoFlag, 0xffff8002, 0xffff8002}, 254 {NoFlag, 0x80000001, 0x0000007f}, {NoFlag, 0x00000020, 0x00000002}, 255 {NoFlag, 0xffffff82, 0xffff8001}, {NoFlag, 0xffffffff, 0x00000001}, 256 {NoFlag, 0xffffff80, 0xffff8002}, {NoFlag, 0xffff8003, 0x7fffffff}, 257 {NoFlag, 0xffffffff, 0xffff8000}, {NoFlag, 0xffff8002, 0x00007ffd}, 258 {NoFlag, 0x00000020, 0xffffff81}, {NoFlag, 0x00000001, 0x55555555}, 259 {NoFlag, 0x7ffffffe, 0x00000020}, {NoFlag, 0x80000000, 0x00000001}, 260 {NoFlag, 0x00007ffd, 0xffff8002}, {NoFlag, 0x7fffffff, 0xfffffffe}, 261 {NoFlag, 0xcccccccc, 0x00007ffd}, {NoFlag, 0x00000000, 0xfffffffd}, 262 {NoFlag, 0xffff8003, 0xffffff80}, {NoFlag, 0x80000001, 0xffffff80}, 263 {NoFlag, 0xffffffff, 0xffff8002}, {NoFlag, 0x00007ffe, 0xffff8002}, 264 {NoFlag, 0xffffff80, 0x00007ffe}, {NoFlag, 0x80000001, 0xffff8001}, 265 {NoFlag, 0x0000007f, 0xffffff80}, {NoFlag, 0xffffff81, 0x80000000}, 266 {NoFlag, 0x00007fff, 0x00007ffe}, {NoFlag, 0x33333333, 0xffff8000}, 267 {NoFlag, 0x33333333, 0x00007fff}, {NoFlag, 0x00000000, 0x0000007d}, 268 {NoFlag, 0x80000001, 0x00000000}, {NoFlag, 0xffffffff, 0x55555555}, 269 {NoFlag, 0x80000001, 0x80000000}, {NoFlag, 0xffffffff, 0xffffff80}, 270 {NoFlag, 0xffffff81, 0xffff8003}, {NoFlag, 0x55555555, 0x80000001}, 271 {NoFlag, 0x7fffffff, 0xffff8001}, {NoFlag, 0xffffff83, 0x00000002}, 272 {NoFlag, 0x0000007e, 0xffffff81}, {NoFlag, 0x80000000, 0xffff8001}, 273 {NoFlag, 0xffffff80, 0xfffffffe}, {NoFlag, 0x0000007e, 0xfffffffd}, 274 {NoFlag, 0xffffffe0, 0xffffffff}, {NoFlag, 0x55555555, 0x80000000}, 275 {NoFlag, 0x0000007d, 0x80000001}, {NoFlag, 0xffffffe0, 0x7ffffffd}, 276 {NoFlag, 0x00000000, 0x00000000}, {NoFlag, 0x55555555, 0x00000001}, 277 {NoFlag, 0x00007ffd, 0x7fffffff}, {NoFlag, 0x55555555, 0xffffffff}, 278 {NoFlag, 0xffff8003, 0x00007fff}, {NoFlag, 0xffffff82, 0x00007fff}, 279 {NoFlag, 0x33333333, 0x55555555}, {NoFlag, 0x00000020, 0x33333333}, 280 {NoFlag, 0x7ffffffe, 0xfffffffd}, {NoFlag, 0x7ffffffe, 0x00000001}, 281 {NoFlag, 0xffffff83, 0xffffffe0}, {NoFlag, 0xfffffffe, 0xaaaaaaaa}, 282 {NoFlag, 0xffff8002, 0x33333333}, {NoFlag, 0xffff8002, 0xffff8003}, 283 {NoFlag, 0x33333333, 0x7fffffff}, {NoFlag, 0xfffffffd, 0xffffff83}, 284 {NoFlag, 0x00000000, 0xffff8000}, {NoFlag, 0xffffff82, 0x55555555}, 285 {NoFlag, 0xffffff82, 0xffffff81}, {NoFlag, 0xcccccccc, 0xfffffffe}, 286 {NoFlag, 0xfffffffd, 0x7fffffff}, {NoFlag, 0x00007fff, 0x7fffffff}, 287 {NoFlag, 0xffffff83, 0xffff8003}, {NoFlag, 0xfffffffe, 0xffffffff}, 288 {NoFlag, 0x7ffffffd, 0x00007ffd}, {NoFlag, 0x7ffffffd, 0x00007fff}, 289 {NoFlag, 0x00007ffd, 0xffffffff}, {NoFlag, 0x00000001, 0xffff8003}, 290 {NoFlag, 0xffffff80, 0xfffffffd}, {NoFlag, 0x33333333, 0x80000000}, 291 {NoFlag, 0xffff8001, 0x00000020}, {NoFlag, 0xcccccccc, 0x00000002}, 292 {NoFlag, 0x00000000, 0x00000002}, {NoFlag, 0x0000007d, 0x00007fff}, 293 {NoFlag, 0xcccccccc, 0x00000001}, {NoFlag, 0xffffff83, 0x00007fff}, 294 {NoFlag, 0x80000001, 0x00000020}, {NoFlag, 0xffff8003, 0xffffffe0}, 295 {NoFlag, 0x00007ffd, 0xaaaaaaaa}, {NoFlag, 0x33333333, 0xffff8001}, 296 {NoFlag, 0xffffff83, 0x80000001}, {NoFlag, 0xffff8000, 0xffff8000}, 297 {NoFlag, 0x00007ffe, 0xffff8001}, {NoFlag, 0x7ffffffd, 0x00000000}, 298 {NoFlag, 0x00007ffe, 0x33333333}, {NoFlag, 0xffff8001, 0xffffff80}, 299 {NoFlag, 0xfffffffe, 0x55555555}, {NoFlag, 0xffffff82, 0xffffffff}}; 300 301 static const Inputs kRotations[] = 302 {{NoFlag, 0xabababab, 0x00000000}, {NoFlag, 0xabababab, 0x00000001}, 303 {NoFlag, 0xabababab, 0x00000002}, {NoFlag, 0xabababab, 0x00000020}, 304 {NoFlag, 0xabababab, 0x0000007d}, {NoFlag, 0xabababab, 0x0000007e}, 305 {NoFlag, 0xabababab, 0x0000007f}, {NoFlag, 0xabababab, 0x00007ffd}, 306 {NoFlag, 0xabababab, 0x00007ffe}, {NoFlag, 0xabababab, 0x00007fff}, 307 {NoFlag, 0xabababab, 0x33333333}, {NoFlag, 0xabababab, 0x55555555}, 308 {NoFlag, 0xabababab, 0x7ffffffd}, {NoFlag, 0xabababab, 0x7ffffffe}, 309 {NoFlag, 0xabababab, 0x7fffffff}, {NoFlag, 0xabababab, 0x80000000}, 310 {NoFlag, 0xabababab, 0x80000001}, {NoFlag, 0xabababab, 0xaaaaaaaa}, 311 {NoFlag, 0xabababab, 0xcccccccc}, {NoFlag, 0xabababab, 0xffff8000}, 312 {NoFlag, 0xabababab, 0xffff8001}, {NoFlag, 0xabababab, 0xffff8002}, 313 {NoFlag, 0xabababab, 0xffff8003}, {NoFlag, 0xabababab, 0xffffff80}, 314 {NoFlag, 0xabababab, 0xffffff81}, {NoFlag, 0xabababab, 0xffffff82}, 315 {NoFlag, 0xabababab, 0xffffff83}, {NoFlag, 0xabababab, 0xffffffe0}, 316 {NoFlag, 0xabababab, 0xfffffffd}, {NoFlag, 0xabababab, 0xfffffffe}, 317 {NoFlag, 0xabababab, 0xffffffff}}; 318 319 320 // A loop will be generated for each element of this array. 321 const TestLoopData kTests[] = {{{eq, r0, r0, ROR, 0}, 322 "eq r0 r0 ROR 0", 323 "Condition_eq_r0_r0_ROR_0", 324 ARRAY_SIZE(kCondition), 325 kCondition}, 326 {{ne, r0, r0, ROR, 0}, 327 "ne r0 r0 ROR 0", 328 "Condition_ne_r0_r0_ROR_0", 329 ARRAY_SIZE(kCondition), 330 kCondition}, 331 {{cs, r0, r0, ROR, 0}, 332 "cs r0 r0 ROR 0", 333 "Condition_cs_r0_r0_ROR_0", 334 ARRAY_SIZE(kCondition), 335 kCondition}, 336 {{cc, r0, r0, ROR, 0}, 337 "cc r0 r0 ROR 0", 338 "Condition_cc_r0_r0_ROR_0", 339 ARRAY_SIZE(kCondition), 340 kCondition}, 341 {{mi, r0, r0, ROR, 0}, 342 "mi r0 r0 ROR 0", 343 "Condition_mi_r0_r0_ROR_0", 344 ARRAY_SIZE(kCondition), 345 kCondition}, 346 {{pl, r0, r0, ROR, 0}, 347 "pl r0 r0 ROR 0", 348 "Condition_pl_r0_r0_ROR_0", 349 ARRAY_SIZE(kCondition), 350 kCondition}, 351 {{vs, r0, r0, ROR, 0}, 352 "vs r0 r0 ROR 0", 353 "Condition_vs_r0_r0_ROR_0", 354 ARRAY_SIZE(kCondition), 355 kCondition}, 356 {{vc, r0, r0, ROR, 0}, 357 "vc r0 r0 ROR 0", 358 "Condition_vc_r0_r0_ROR_0", 359 ARRAY_SIZE(kCondition), 360 kCondition}, 361 {{hi, r0, r0, ROR, 0}, 362 "hi r0 r0 ROR 0", 363 "Condition_hi_r0_r0_ROR_0", 364 ARRAY_SIZE(kCondition), 365 kCondition}, 366 {{ls, r0, r0, ROR, 0}, 367 "ls r0 r0 ROR 0", 368 "Condition_ls_r0_r0_ROR_0", 369 ARRAY_SIZE(kCondition), 370 kCondition}, 371 {{ge, r0, r0, ROR, 0}, 372 "ge r0 r0 ROR 0", 373 "Condition_ge_r0_r0_ROR_0", 374 ARRAY_SIZE(kCondition), 375 kCondition}, 376 {{lt, r0, r0, ROR, 0}, 377 "lt r0 r0 ROR 0", 378 "Condition_lt_r0_r0_ROR_0", 379 ARRAY_SIZE(kCondition), 380 kCondition}, 381 {{gt, r0, r0, ROR, 0}, 382 "gt r0 r0 ROR 0", 383 "Condition_gt_r0_r0_ROR_0", 384 ARRAY_SIZE(kCondition), 385 kCondition}, 386 {{le, r0, r0, ROR, 0}, 387 "le r0 r0 ROR 0", 388 "Condition_le_r0_r0_ROR_0", 389 ARRAY_SIZE(kCondition), 390 kCondition}, 391 {{al, r0, r0, ROR, 0}, 392 "al r0 r0 ROR 0", 393 "Condition_al_r0_r0_ROR_0", 394 ARRAY_SIZE(kCondition), 395 kCondition}, 396 {{al, r0, r0, ROR, 0}, 397 "al r0 r0 ROR 0", 398 "RdIsRn_al_r0_r0_ROR_0", 399 ARRAY_SIZE(kRdIsRn), 400 kRdIsRn}, 401 {{al, r1, r1, ROR, 0}, 402 "al r1 r1 ROR 0", 403 "RdIsRn_al_r1_r1_ROR_0", 404 ARRAY_SIZE(kRdIsRn), 405 kRdIsRn}, 406 {{al, r2, r2, ROR, 0}, 407 "al r2 r2 ROR 0", 408 "RdIsRn_al_r2_r2_ROR_0", 409 ARRAY_SIZE(kRdIsRn), 410 kRdIsRn}, 411 {{al, r3, r3, ROR, 0}, 412 "al r3 r3 ROR 0", 413 "RdIsRn_al_r3_r3_ROR_0", 414 ARRAY_SIZE(kRdIsRn), 415 kRdIsRn}, 416 {{al, r4, r4, ROR, 0}, 417 "al r4 r4 ROR 0", 418 "RdIsRn_al_r4_r4_ROR_0", 419 ARRAY_SIZE(kRdIsRn), 420 kRdIsRn}, 421 {{al, r5, r5, ROR, 0}, 422 "al r5 r5 ROR 0", 423 "RdIsRn_al_r5_r5_ROR_0", 424 ARRAY_SIZE(kRdIsRn), 425 kRdIsRn}, 426 {{al, r6, r6, ROR, 0}, 427 "al r6 r6 ROR 0", 428 "RdIsRn_al_r6_r6_ROR_0", 429 ARRAY_SIZE(kRdIsRn), 430 kRdIsRn}, 431 {{al, r7, r7, ROR, 0}, 432 "al r7 r7 ROR 0", 433 "RdIsRn_al_r7_r7_ROR_0", 434 ARRAY_SIZE(kRdIsRn), 435 kRdIsRn}, 436 {{al, r8, r8, ROR, 0}, 437 "al r8 r8 ROR 0", 438 "RdIsRn_al_r8_r8_ROR_0", 439 ARRAY_SIZE(kRdIsRn), 440 kRdIsRn}, 441 {{al, r9, r9, ROR, 0}, 442 "al r9 r9 ROR 0", 443 "RdIsRn_al_r9_r9_ROR_0", 444 ARRAY_SIZE(kRdIsRn), 445 kRdIsRn}, 446 {{al, r10, r10, ROR, 0}, 447 "al r10 r10 ROR 0", 448 "RdIsRn_al_r10_r10_ROR_0", 449 ARRAY_SIZE(kRdIsRn), 450 kRdIsRn}, 451 {{al, r11, r11, ROR, 0}, 452 "al r11 r11 ROR 0", 453 "RdIsRn_al_r11_r11_ROR_0", 454 ARRAY_SIZE(kRdIsRn), 455 kRdIsRn}, 456 {{al, r12, r12, ROR, 0}, 457 "al r12 r12 ROR 0", 458 "RdIsRn_al_r12_r12_ROR_0", 459 ARRAY_SIZE(kRdIsRn), 460 kRdIsRn}, 461 {{al, r14, r14, ROR, 0}, 462 "al r14 r14 ROR 0", 463 "RdIsRn_al_r14_r14_ROR_0", 464 ARRAY_SIZE(kRdIsRn), 465 kRdIsRn}, 466 {{al, r1, r8, ROR, 0}, 467 "al r1 r8 ROR 0", 468 "RdIsNotRn_al_r1_r8_ROR_0", 469 ARRAY_SIZE(kRdIsNotRn), 470 kRdIsNotRn}, 471 {{al, r7, r4, ROR, 0}, 472 "al r7 r4 ROR 0", 473 "RdIsNotRn_al_r7_r4_ROR_0", 474 ARRAY_SIZE(kRdIsNotRn), 475 kRdIsNotRn}, 476 {{al, r14, r10, ROR, 0}, 477 "al r14 r10 ROR 0", 478 "RdIsNotRn_al_r14_r10_ROR_0", 479 ARRAY_SIZE(kRdIsNotRn), 480 kRdIsNotRn}, 481 {{al, r10, r6, ROR, 0}, 482 "al r10 r6 ROR 0", 483 "RdIsNotRn_al_r10_r6_ROR_0", 484 ARRAY_SIZE(kRdIsNotRn), 485 kRdIsNotRn}, 486 {{al, r6, r5, ROR, 0}, 487 "al r6 r5 ROR 0", 488 "RdIsNotRn_al_r6_r5_ROR_0", 489 ARRAY_SIZE(kRdIsNotRn), 490 kRdIsNotRn}, 491 {{al, r12, r2, ROR, 0}, 492 "al r12 r2 ROR 0", 493 "RdIsNotRn_al_r12_r2_ROR_0", 494 ARRAY_SIZE(kRdIsNotRn), 495 kRdIsNotRn}, 496 {{al, r0, r11, ROR, 0}, 497 "al r0 r11 ROR 0", 498 "RdIsNotRn_al_r0_r11_ROR_0", 499 ARRAY_SIZE(kRdIsNotRn), 500 kRdIsNotRn}, 501 {{al, r10, r14, ROR, 0}, 502 "al r10 r14 ROR 0", 503 "RdIsNotRn_al_r10_r14_ROR_0", 504 ARRAY_SIZE(kRdIsNotRn), 505 kRdIsNotRn}, 506 {{al, r0, r5, ROR, 0}, 507 "al r0 r5 ROR 0", 508 "RdIsNotRn_al_r0_r5_ROR_0", 509 ARRAY_SIZE(kRdIsNotRn), 510 kRdIsNotRn}, 511 {{al, r0, r3, ROR, 0}, 512 "al r0 r3 ROR 0", 513 "RdIsNotRn_al_r0_r3_ROR_0", 514 ARRAY_SIZE(kRdIsNotRn), 515 kRdIsNotRn}, 516 {{al, r0, r1, ROR, 0}, 517 "al r0 r1 ROR 0", 518 "Rotations_al_r0_r1_ROR_0", 519 ARRAY_SIZE(kRotations), 520 kRotations}, 521 {{al, r0, r1, ROR, 8}, 522 "al r0 r1 ROR 8", 523 "Rotations_al_r0_r1_ROR_8", 524 ARRAY_SIZE(kRotations), 525 kRotations}, 526 {{al, r0, r1, ROR, 16}, 527 "al r0 r1 ROR 16", 528 "Rotations_al_r0_r1_ROR_16", 529 ARRAY_SIZE(kRotations), 530 kRotations}, 531 {{al, r0, r1, ROR, 24}, 532 "al r0 r1 ROR 24", 533 "Rotations_al_r0_r1_ROR_24", 534 ARRAY_SIZE(kRotations), 535 kRotations}}; 536 537 // We record all inputs to the instructions as outputs. This way, we also check 538 // that what shouldn't change didn't change. 539 struct TestResult { 540 size_t output_size; 541 const Inputs* outputs; 542 }; 543 544 // These headers each contain an array of `TestResult` with the reference output 545 // values. The reference arrays are names `kReference{mnemonic}`. 546 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-sxtb-t32.h" 547 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-sxtb16-t32.h" 548 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-sxth-t32.h" 549 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-uxtb-t32.h" 550 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-uxtb16-t32.h" 551 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-uxth-t32.h" 552 553 554 // The maximum number of errors to report in detail for each test. 555 const unsigned kErrorReportLimit = 8; 556 557 typedef void (MacroAssembler::*Fn)(Condition cond, 558 Register rd, 559 const Operand& op); 560 561 void TestHelper(Fn instruction, 562 const char* mnemonic, 563 const TestResult reference[]) { 564 SETUP(); 565 masm.UseT32(); 566 START(); 567 568 // Data to compare to `reference`. 569 TestResult* results[ARRAY_SIZE(kTests)]; 570 571 // Test cases for memory bound instructions may allocate a buffer and save its 572 // address in this array. 573 byte* scratch_memory_buffers[ARRAY_SIZE(kTests)]; 574 575 // Generate a loop for each element in `kTests`. Each loop tests one specific 576 // instruction. 577 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) { 578 // Allocate results on the heap for this test. 579 results[i] = new TestResult; 580 results[i]->outputs = new Inputs[kTests[i].input_size]; 581 results[i]->output_size = kTests[i].input_size; 582 583 size_t input_stride = sizeof(kTests[i].inputs[0]) * kTests[i].input_size; 584 VIXL_ASSERT(IsUint32(input_stride)); 585 586 scratch_memory_buffers[i] = NULL; 587 588 Label loop; 589 UseScratchRegisterScope scratch_registers(&masm); 590 // Include all registers from r0 ro r12. 591 scratch_registers.Include(RegisterList(0x1fff)); 592 593 // Values to pass to the macro-assembler. 594 Condition cond = kTests[i].operands.cond; 595 Register rd = kTests[i].operands.rd; 596 Register rn = kTests[i].operands.rn; 597 ShiftType ror = kTests[i].operands.ror; 598 uint32_t amount = kTests[i].operands.amount; 599 Operand op(rn, ror, amount); 600 scratch_registers.Exclude(rd); 601 scratch_registers.Exclude(rn); 602 603 // Allocate reserved registers for our own use. 604 Register input_ptr = scratch_registers.Acquire(); 605 Register input_end = scratch_registers.Acquire(); 606 Register result_ptr = scratch_registers.Acquire(); 607 608 // Initialize `input_ptr` to the first element and `input_end` the address 609 // after the array. 610 __ Mov(input_ptr, Operand::From(kTests[i].inputs)); 611 __ Add(input_end, input_ptr, static_cast<uint32_t>(input_stride)); 612 __ Mov(result_ptr, Operand::From(results[i]->outputs)); 613 __ Bind(&loop); 614 615 { 616 UseScratchRegisterScope temp_registers(&masm); 617 Register nzcv_bits = temp_registers.Acquire(); 618 Register saved_q_bit = temp_registers.Acquire(); 619 // Save the `Q` bit flag. 620 __ Mrs(saved_q_bit, APSR); 621 __ And(saved_q_bit, saved_q_bit, QFlag); 622 // Set the `NZCV` and `Q` flags together. 623 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr))); 624 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); 625 __ Msr(APSR_nzcvq, nzcv_bits); 626 } 627 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd))); 628 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn))); 629 630 (masm.*instruction)(cond, rd, op); 631 632 { 633 UseScratchRegisterScope temp_registers(&masm); 634 Register nzcv_bits = temp_registers.Acquire(); 635 __ Mrs(nzcv_bits, APSR); 636 // Only record the NZCV bits. 637 __ And(nzcv_bits, nzcv_bits, NZCVFlag); 638 __ Str(nzcv_bits, MemOperand(result_ptr, offsetof(Inputs, apsr))); 639 } 640 __ Str(rd, MemOperand(result_ptr, offsetof(Inputs, rd))); 641 __ Str(rn, MemOperand(result_ptr, offsetof(Inputs, rn))); 642 643 // Advance the result pointer. 644 __ Add(result_ptr, result_ptr, Operand::From(sizeof(kTests[i].inputs[0]))); 645 // Loop back until `input_ptr` is lower than `input_base`. 646 __ Add(input_ptr, input_ptr, Operand::From(sizeof(kTests[i].inputs[0]))); 647 __ Cmp(input_ptr, input_end); 648 __ B(ne, &loop); 649 } 650 651 END(); 652 653 RUN(); 654 655 if (Test::generate_test_trace()) { 656 // Print the results. 657 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 658 printf("const Inputs kOutputs_%s_%s[] = {\n", 659 mnemonic, 660 kTests[i].identifier); 661 for (size_t j = 0; j < results[i]->output_size; j++) { 662 printf(" { "); 663 printf("0x%08" PRIx32, results[i]->outputs[j].apsr); 664 printf(", "); 665 printf("0x%08" PRIx32, results[i]->outputs[j].rd); 666 printf(", "); 667 printf("0x%08" PRIx32, results[i]->outputs[j].rn); 668 printf(" },\n"); 669 } 670 printf("};\n"); 671 } 672 printf("const TestResult kReference%s[] = {\n", mnemonic); 673 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 674 printf(" {\n"); 675 printf(" ARRAY_SIZE(kOutputs_%s_%s),\n", 676 mnemonic, 677 kTests[i].identifier); 678 printf(" kOutputs_%s_%s,\n", mnemonic, kTests[i].identifier); 679 printf(" },\n"); 680 } 681 printf("};\n"); 682 } else if (kCheckSimulatorTestResults) { 683 // Check the results. 684 unsigned total_error_count = 0; 685 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 686 bool instruction_has_errors = false; 687 for (size_t j = 0; j < kTests[i].input_size; j++) { 688 uint32_t apsr = results[i]->outputs[j].apsr; 689 uint32_t rd = results[i]->outputs[j].rd; 690 uint32_t rn = results[i]->outputs[j].rn; 691 uint32_t apsr_input = kTests[i].inputs[j].apsr; 692 uint32_t rd_input = kTests[i].inputs[j].rd; 693 uint32_t rn_input = kTests[i].inputs[j].rn; 694 uint32_t apsr_ref = reference[i].outputs[j].apsr; 695 uint32_t rd_ref = reference[i].outputs[j].rd; 696 uint32_t rn_ref = reference[i].outputs[j].rn; 697 698 if (((apsr != apsr_ref) || (rd != rd_ref) || (rn != rn_ref)) && 699 (++total_error_count <= kErrorReportLimit)) { 700 // Print the instruction once even if it triggered multiple failures. 701 if (!instruction_has_errors) { 702 printf("Error(s) when testing \"%s %s\":\n", 703 mnemonic, 704 kTests[i].operands_description); 705 instruction_has_errors = true; 706 } 707 // Print subsequent errors. 708 printf(" Input: "); 709 printf("0x%08" PRIx32, apsr_input); 710 printf(", "); 711 printf("0x%08" PRIx32, rd_input); 712 printf(", "); 713 printf("0x%08" PRIx32, rn_input); 714 printf("\n"); 715 printf(" Expected: "); 716 printf("0x%08" PRIx32, apsr_ref); 717 printf(", "); 718 printf("0x%08" PRIx32, rd_ref); 719 printf(", "); 720 printf("0x%08" PRIx32, rn_ref); 721 printf("\n"); 722 printf(" Found: "); 723 printf("0x%08" PRIx32, apsr); 724 printf(", "); 725 printf("0x%08" PRIx32, rd); 726 printf(", "); 727 printf("0x%08" PRIx32, rn); 728 printf("\n\n"); 729 } 730 } 731 } 732 733 if (total_error_count > kErrorReportLimit) { 734 printf("%u other errors follow.\n", 735 total_error_count - kErrorReportLimit); 736 } 737 VIXL_CHECK(total_error_count == 0); 738 } else { 739 VIXL_WARNING("Assembled the code, but did not run anything.\n"); 740 } 741 742 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) { 743 delete[] results[i]->outputs; 744 delete results[i]; 745 delete[] scratch_memory_buffers[i]; 746 } 747 } 748 749 // Instantiate tests for each instruction in the list. 750 // TODO: Remove this limitation by having a sandboxing mechanism. 751 #if defined(VIXL_HOST_POINTER_32) 752 #define TEST(mnemonic) \ 753 void Test_##mnemonic() { \ 754 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \ 755 } \ 756 Test test_##mnemonic( \ 757 "AARCH32_SIMULATOR_COND_RD_OPERAND_RN_ROR_AMOUNT_" #mnemonic "_T32", \ 758 &Test_##mnemonic); 759 #else 760 #define TEST(mnemonic) \ 761 void Test_##mnemonic() { \ 762 VIXL_WARNING("This test can only run on a 32-bit host.\n"); \ 763 USE(TestHelper); \ 764 } \ 765 Test test_##mnemonic( \ 766 "AARCH32_SIMULATOR_COND_RD_OPERAND_RN_ROR_AMOUNT_" #mnemonic "_T32", \ 767 &Test_##mnemonic); 768 #endif 769 770 FOREACH_INSTRUCTION(TEST) 771 #undef TEST 772 773 } // namespace 774 #endif 775 776 } // namespace aarch32 777 } // namespace vixl 778
