/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
SIInsertSkips.cpp | 169 .addReg(AMDGPU::VGPR0, RegState::Undef) 170 .addReg(AMDGPU::VGPR0, RegState::Undef) 171 .addReg(AMDGPU::VGPR0, RegState::Undef) 172 .addReg(AMDGPU::VGPR0, RegState::Undef)
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SIMachineFunctionInfo.cpp | 319 return AMDGPU::VGPR0;
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SIInsertWaitcnts.cpp | 91 unsigned VGPR0; 493 assert(Reg >= RegisterEncoding.VGPR0 && Reg <= RegisterEncoding.VGPRL); 494 Result.first = Reg - RegisterEncoding.VGPR0; [all...] |
SIRegisterInfo.cpp | 77 classifyPressureSet(i, AMDGPU::VGPR0, VGPRPressureSets); [all...] |
SIISelLowering.cpp | [all...] |
/external/llvm/lib/Target/AMDGPU/ |
SILowerControlFlow.cpp | 26 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 28 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0 39 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch 46 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN bloc [all...] |
SIMachineFunctionInfo.h | 405 return AMDGPU::VGPR0;
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SIRegisterInfo.cpp | 107 classifyPressureSet(i, AMDGPU::VGPR0, VGPRPressureSets); [all...] |
SIISelLowering.cpp | 678 CCInfo.AllocateReg(AMDGPU::VGPR0); [all...] |