| /external/libxaac/decoder/armv8/ |
| ixheaacd_shiftrountine_with_round.s | 8 stp X27, X28, [sp, #-16]!
15 ldp X27, X28, [sp], #16
|
| ixheaacd_shiftrountine_with_round_eld.s | 8 stp X27, X28, [sp, #-16]!
15 ldp X27, X28, [sp], #16
|
| ixheaacd_post_twiddle_overlap.s | 17 stp X26, X27, [sp, #-16]!
25 ldp X26, X27, [sp], #16
[all...] |
| /art/runtime/arch/arm64/ |
| registers_arm64.h | 54 X27 = 27,
|
| callee_save_frame_arm64.h | 41 (1 << art::arm64::X26) | (1 << art::arm64::X27) | (1 << art::arm64::X28) |
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| PPCBaseInfo.h | 58 case R27: case X27: case F27: case V27: case CR6UN: return 27;
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 59 case AArch64::X27: return AArch64::W27;
99 case AArch64::W27: return AArch64::X27;
|
| /art/compiler/jni/quick/arm64/ |
| calling_convention_arm64.cc | 71 Arm64ManagedRegister::FromXRegister(X27),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCFrameLowering.h | 256 {PPC::X27, -40},
|
| PPCRegisterInfo.cpp | 163 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
189 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 59 case AArch64::X27: return AArch64::W27;
99 case AArch64::W27: return AArch64::X27;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/Disassembler/ |
| RISCVDisassembler.cpp | 65 RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27,
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/ |
| DefaultExceptionHandler.c | 226 DEBUG ((EFI_D_ERROR, " X24 0x%016lx X25 0x%016lx X26 0x%016lx X27 0x%016lx\n", SystemContext.SystemContextAArch64->X24, SystemContext.SystemContextAArch64->X25, SystemContext.SystemContextAArch64->X26, SystemContext.SystemContextAArch64->X27));
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 463 // X27/X28 pair = 0x00000010
479 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/Disassembler/ |
| PPCDisassembler.cpp | 203 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
214 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| AArch64GenRegisterInfo.inc | 263 X27 = 243,
[all...] |
| AArch64GenCallingConv.inc | 708 AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28
[all...] |
| /device/linaro/bootloader/edk2/MdePkg/Include/Protocol/ |
| DebugSupport.h | 565 UINT64 X27;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 520 // X27/X28 pair = 0x00000010
536 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
|
| /external/guava/guava-tests/benchmark/com/google/common/base/ |
| EnumsBenchmark.java | 80 X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, X32, X33, X34, X35, X36, X37,
89 X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, X32, X33, X34, X35, X36, X37, X38, X39,
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| PPCDisassembler.cpp | 192 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 62 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
73 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 62 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
73 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
[all...] |
| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | 622 EXPECT_TRUE(vixl::aarch64::x27.Is(Arm64Assembler::reg_x(X27)));
[all...] |
| /device/linaro/bootloader/edk2/MdePkg/Include/Library/ |
| BaseLib.h | 160 UINT64 X27;
[all...] |
