1 /* 2 * Copyright 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 /* THIS FILE HAS BEEN GENERATED, DO NOT HAND EDIT. 25 * 26 * Sizes of bitfields in genxml instructions, structures, and registers. 27 */ 28 29 #ifndef GENX_BITS_H 30 #define GENX_BITS_H 31 32 #include <stdint.h> 33 34 #include "common/gen_device_info.h" 35 #include "util/macros.h" 36 37 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /* 3DPRIMITIVE */ 44 45 46 #define GEN10_3DPRIMITIVE_length 7 47 #define GEN9_3DPRIMITIVE_length 7 48 #define GEN8_3DPRIMITIVE_length 7 49 #define GEN75_3DPRIMITIVE_length 7 50 #define GEN7_3DPRIMITIVE_length 7 51 #define GEN6_3DPRIMITIVE_length 6 52 #define GEN5_3DPRIMITIVE_length 6 53 #define GEN45_3DPRIMITIVE_length 6 54 #define GEN4_3DPRIMITIVE_length 6 55 56 static inline uint32_t ATTRIBUTE_PURE 57 _3DPRIMITIVE_length(const struct gen_device_info *devinfo) 58 { 59 switch (devinfo->gen) { 60 case 10: return 7; 61 case 9: return 7; 62 case 8: return 7; 63 case 7: 64 if (devinfo->is_haswell) { 65 return 7; 66 } else { 67 return 7; 68 } 69 case 6: return 6; 70 case 5: return 6; 71 case 4: 72 if (devinfo->is_g4x) { 73 return 6; 74 } else { 75 return 6; 76 } 77 default: 78 unreachable("Invalid hardware generation"); 79 } 80 } 81 82 83 84 /* 3DPRIMITIVE::3D Command Opcode */ 85 86 87 #define GEN10_3DPRIMITIVE_3DCommandOpcode_bits 3 88 #define GEN9_3DPRIMITIVE_3DCommandOpcode_bits 3 89 #define GEN8_3DPRIMITIVE_3DCommandOpcode_bits 3 90 #define GEN75_3DPRIMITIVE_3DCommandOpcode_bits 3 91 #define GEN7_3DPRIMITIVE_3DCommandOpcode_bits 3 92 #define GEN6_3DPRIMITIVE_3DCommandOpcode_bits 3 93 #define GEN5_3DPRIMITIVE_3DCommandOpcode_bits 3 94 #define GEN45_3DPRIMITIVE_3DCommandOpcode_bits 3 95 #define GEN4_3DPRIMITIVE_3DCommandOpcode_bits 3 96 97 static inline uint32_t ATTRIBUTE_PURE 98 _3DPRIMITIVE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 99 { 100 switch (devinfo->gen) { 101 case 10: return 3; 102 case 9: return 3; 103 case 8: return 3; 104 case 7: 105 if (devinfo->is_haswell) { 106 return 3; 107 } else { 108 return 3; 109 } 110 case 6: return 3; 111 case 5: return 3; 112 case 4: 113 if (devinfo->is_g4x) { 114 return 3; 115 } else { 116 return 3; 117 } 118 default: 119 unreachable("Invalid hardware generation"); 120 } 121 } 122 123 124 125 #define GEN10_3DPRIMITIVE_3DCommandOpcode_start 24 126 #define GEN9_3DPRIMITIVE_3DCommandOpcode_start 24 127 #define GEN8_3DPRIMITIVE_3DCommandOpcode_start 24 128 #define GEN75_3DPRIMITIVE_3DCommandOpcode_start 24 129 #define GEN7_3DPRIMITIVE_3DCommandOpcode_start 24 130 #define GEN6_3DPRIMITIVE_3DCommandOpcode_start 24 131 #define GEN5_3DPRIMITIVE_3DCommandOpcode_start 24 132 #define GEN45_3DPRIMITIVE_3DCommandOpcode_start 24 133 #define GEN4_3DPRIMITIVE_3DCommandOpcode_start 24 134 135 static inline uint32_t ATTRIBUTE_PURE 136 _3DPRIMITIVE_3DCommandOpcode_start(const struct gen_device_info *devinfo) 137 { 138 switch (devinfo->gen) { 139 case 10: return 24; 140 case 9: return 24; 141 case 8: return 24; 142 case 7: 143 if (devinfo->is_haswell) { 144 return 24; 145 } else { 146 return 24; 147 } 148 case 6: return 24; 149 case 5: return 24; 150 case 4: 151 if (devinfo->is_g4x) { 152 return 24; 153 } else { 154 return 24; 155 } 156 default: 157 unreachable("Invalid hardware generation"); 158 } 159 } 160 161 162 163 /* 3DPRIMITIVE::3D Command Sub Opcode */ 164 165 166 #define GEN10_3DPRIMITIVE_3DCommandSubOpcode_bits 8 167 #define GEN9_3DPRIMITIVE_3DCommandSubOpcode_bits 8 168 #define GEN8_3DPRIMITIVE_3DCommandSubOpcode_bits 8 169 #define GEN75_3DPRIMITIVE_3DCommandSubOpcode_bits 8 170 #define GEN7_3DPRIMITIVE_3DCommandSubOpcode_bits 8 171 #define GEN6_3DPRIMITIVE_3DCommandSubOpcode_bits 8 172 #define GEN5_3DPRIMITIVE_3DCommandSubOpcode_bits 8 173 #define GEN45_3DPRIMITIVE_3DCommandSubOpcode_bits 8 174 #define GEN4_3DPRIMITIVE_3DCommandSubOpcode_bits 8 175 176 static inline uint32_t ATTRIBUTE_PURE 177 _3DPRIMITIVE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 178 { 179 switch (devinfo->gen) { 180 case 10: return 8; 181 case 9: return 8; 182 case 8: return 8; 183 case 7: 184 if (devinfo->is_haswell) { 185 return 8; 186 } else { 187 return 8; 188 } 189 case 6: return 8; 190 case 5: return 8; 191 case 4: 192 if (devinfo->is_g4x) { 193 return 8; 194 } else { 195 return 8; 196 } 197 default: 198 unreachable("Invalid hardware generation"); 199 } 200 } 201 202 203 204 #define GEN10_3DPRIMITIVE_3DCommandSubOpcode_start 16 205 #define GEN9_3DPRIMITIVE_3DCommandSubOpcode_start 16 206 #define GEN8_3DPRIMITIVE_3DCommandSubOpcode_start 16 207 #define GEN75_3DPRIMITIVE_3DCommandSubOpcode_start 16 208 #define GEN7_3DPRIMITIVE_3DCommandSubOpcode_start 16 209 #define GEN6_3DPRIMITIVE_3DCommandSubOpcode_start 16 210 #define GEN5_3DPRIMITIVE_3DCommandSubOpcode_start 16 211 #define GEN45_3DPRIMITIVE_3DCommandSubOpcode_start 16 212 #define GEN4_3DPRIMITIVE_3DCommandSubOpcode_start 16 213 214 static inline uint32_t ATTRIBUTE_PURE 215 _3DPRIMITIVE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 216 { 217 switch (devinfo->gen) { 218 case 10: return 16; 219 case 9: return 16; 220 case 8: return 16; 221 case 7: 222 if (devinfo->is_haswell) { 223 return 16; 224 } else { 225 return 16; 226 } 227 case 6: return 16; 228 case 5: return 16; 229 case 4: 230 if (devinfo->is_g4x) { 231 return 16; 232 } else { 233 return 16; 234 } 235 default: 236 unreachable("Invalid hardware generation"); 237 } 238 } 239 240 241 242 /* 3DPRIMITIVE::Base Vertex Location */ 243 244 245 #define GEN10_3DPRIMITIVE_BaseVertexLocation_bits 32 246 #define GEN9_3DPRIMITIVE_BaseVertexLocation_bits 32 247 #define GEN8_3DPRIMITIVE_BaseVertexLocation_bits 32 248 #define GEN75_3DPRIMITIVE_BaseVertexLocation_bits 32 249 #define GEN7_3DPRIMITIVE_BaseVertexLocation_bits 32 250 #define GEN6_3DPRIMITIVE_BaseVertexLocation_bits 32 251 #define GEN5_3DPRIMITIVE_BaseVertexLocation_bits 32 252 #define GEN45_3DPRIMITIVE_BaseVertexLocation_bits 32 253 #define GEN4_3DPRIMITIVE_BaseVertexLocation_bits 32 254 255 static inline uint32_t ATTRIBUTE_PURE 256 _3DPRIMITIVE_BaseVertexLocation_bits(const struct gen_device_info *devinfo) 257 { 258 switch (devinfo->gen) { 259 case 10: return 32; 260 case 9: return 32; 261 case 8: return 32; 262 case 7: 263 if (devinfo->is_haswell) { 264 return 32; 265 } else { 266 return 32; 267 } 268 case 6: return 32; 269 case 5: return 32; 270 case 4: 271 if (devinfo->is_g4x) { 272 return 32; 273 } else { 274 return 32; 275 } 276 default: 277 unreachable("Invalid hardware generation"); 278 } 279 } 280 281 282 283 #define GEN10_3DPRIMITIVE_BaseVertexLocation_start 192 284 #define GEN9_3DPRIMITIVE_BaseVertexLocation_start 192 285 #define GEN8_3DPRIMITIVE_BaseVertexLocation_start 192 286 #define GEN75_3DPRIMITIVE_BaseVertexLocation_start 192 287 #define GEN7_3DPRIMITIVE_BaseVertexLocation_start 192 288 #define GEN6_3DPRIMITIVE_BaseVertexLocation_start 160 289 #define GEN5_3DPRIMITIVE_BaseVertexLocation_start 160 290 #define GEN45_3DPRIMITIVE_BaseVertexLocation_start 160 291 #define GEN4_3DPRIMITIVE_BaseVertexLocation_start 160 292 293 static inline uint32_t ATTRIBUTE_PURE 294 _3DPRIMITIVE_BaseVertexLocation_start(const struct gen_device_info *devinfo) 295 { 296 switch (devinfo->gen) { 297 case 10: return 192; 298 case 9: return 192; 299 case 8: return 192; 300 case 7: 301 if (devinfo->is_haswell) { 302 return 192; 303 } else { 304 return 192; 305 } 306 case 6: return 160; 307 case 5: return 160; 308 case 4: 309 if (devinfo->is_g4x) { 310 return 160; 311 } else { 312 return 160; 313 } 314 default: 315 unreachable("Invalid hardware generation"); 316 } 317 } 318 319 320 321 /* 3DPRIMITIVE::Command SubType */ 322 323 324 #define GEN10_3DPRIMITIVE_CommandSubType_bits 2 325 #define GEN9_3DPRIMITIVE_CommandSubType_bits 2 326 #define GEN8_3DPRIMITIVE_CommandSubType_bits 2 327 #define GEN75_3DPRIMITIVE_CommandSubType_bits 2 328 #define GEN7_3DPRIMITIVE_CommandSubType_bits 2 329 #define GEN6_3DPRIMITIVE_CommandSubType_bits 2 330 #define GEN5_3DPRIMITIVE_CommandSubType_bits 2 331 #define GEN45_3DPRIMITIVE_CommandSubType_bits 2 332 #define GEN4_3DPRIMITIVE_CommandSubType_bits 2 333 334 static inline uint32_t ATTRIBUTE_PURE 335 _3DPRIMITIVE_CommandSubType_bits(const struct gen_device_info *devinfo) 336 { 337 switch (devinfo->gen) { 338 case 10: return 2; 339 case 9: return 2; 340 case 8: return 2; 341 case 7: 342 if (devinfo->is_haswell) { 343 return 2; 344 } else { 345 return 2; 346 } 347 case 6: return 2; 348 case 5: return 2; 349 case 4: 350 if (devinfo->is_g4x) { 351 return 2; 352 } else { 353 return 2; 354 } 355 default: 356 unreachable("Invalid hardware generation"); 357 } 358 } 359 360 361 362 #define GEN10_3DPRIMITIVE_CommandSubType_start 27 363 #define GEN9_3DPRIMITIVE_CommandSubType_start 27 364 #define GEN8_3DPRIMITIVE_CommandSubType_start 27 365 #define GEN75_3DPRIMITIVE_CommandSubType_start 27 366 #define GEN7_3DPRIMITIVE_CommandSubType_start 27 367 #define GEN6_3DPRIMITIVE_CommandSubType_start 27 368 #define GEN5_3DPRIMITIVE_CommandSubType_start 27 369 #define GEN45_3DPRIMITIVE_CommandSubType_start 27 370 #define GEN4_3DPRIMITIVE_CommandSubType_start 27 371 372 static inline uint32_t ATTRIBUTE_PURE 373 _3DPRIMITIVE_CommandSubType_start(const struct gen_device_info *devinfo) 374 { 375 switch (devinfo->gen) { 376 case 10: return 27; 377 case 9: return 27; 378 case 8: return 27; 379 case 7: 380 if (devinfo->is_haswell) { 381 return 27; 382 } else { 383 return 27; 384 } 385 case 6: return 27; 386 case 5: return 27; 387 case 4: 388 if (devinfo->is_g4x) { 389 return 27; 390 } else { 391 return 27; 392 } 393 default: 394 unreachable("Invalid hardware generation"); 395 } 396 } 397 398 399 400 /* 3DPRIMITIVE::Command Type */ 401 402 403 #define GEN10_3DPRIMITIVE_CommandType_bits 3 404 #define GEN9_3DPRIMITIVE_CommandType_bits 3 405 #define GEN8_3DPRIMITIVE_CommandType_bits 3 406 #define GEN75_3DPRIMITIVE_CommandType_bits 3 407 #define GEN7_3DPRIMITIVE_CommandType_bits 3 408 #define GEN6_3DPRIMITIVE_CommandType_bits 3 409 #define GEN5_3DPRIMITIVE_CommandType_bits 3 410 #define GEN45_3DPRIMITIVE_CommandType_bits 3 411 #define GEN4_3DPRIMITIVE_CommandType_bits 3 412 413 static inline uint32_t ATTRIBUTE_PURE 414 _3DPRIMITIVE_CommandType_bits(const struct gen_device_info *devinfo) 415 { 416 switch (devinfo->gen) { 417 case 10: return 3; 418 case 9: return 3; 419 case 8: return 3; 420 case 7: 421 if (devinfo->is_haswell) { 422 return 3; 423 } else { 424 return 3; 425 } 426 case 6: return 3; 427 case 5: return 3; 428 case 4: 429 if (devinfo->is_g4x) { 430 return 3; 431 } else { 432 return 3; 433 } 434 default: 435 unreachable("Invalid hardware generation"); 436 } 437 } 438 439 440 441 #define GEN10_3DPRIMITIVE_CommandType_start 29 442 #define GEN9_3DPRIMITIVE_CommandType_start 29 443 #define GEN8_3DPRIMITIVE_CommandType_start 29 444 #define GEN75_3DPRIMITIVE_CommandType_start 29 445 #define GEN7_3DPRIMITIVE_CommandType_start 29 446 #define GEN6_3DPRIMITIVE_CommandType_start 29 447 #define GEN5_3DPRIMITIVE_CommandType_start 29 448 #define GEN45_3DPRIMITIVE_CommandType_start 29 449 #define GEN4_3DPRIMITIVE_CommandType_start 29 450 451 static inline uint32_t ATTRIBUTE_PURE 452 _3DPRIMITIVE_CommandType_start(const struct gen_device_info *devinfo) 453 { 454 switch (devinfo->gen) { 455 case 10: return 29; 456 case 9: return 29; 457 case 8: return 29; 458 case 7: 459 if (devinfo->is_haswell) { 460 return 29; 461 } else { 462 return 29; 463 } 464 case 6: return 29; 465 case 5: return 29; 466 case 4: 467 if (devinfo->is_g4x) { 468 return 29; 469 } else { 470 return 29; 471 } 472 default: 473 unreachable("Invalid hardware generation"); 474 } 475 } 476 477 478 479 /* 3DPRIMITIVE::DWord Length */ 480 481 482 #define GEN10_3DPRIMITIVE_DWordLength_bits 8 483 #define GEN9_3DPRIMITIVE_DWordLength_bits 8 484 #define GEN8_3DPRIMITIVE_DWordLength_bits 8 485 #define GEN75_3DPRIMITIVE_DWordLength_bits 8 486 #define GEN7_3DPRIMITIVE_DWordLength_bits 8 487 #define GEN6_3DPRIMITIVE_DWordLength_bits 8 488 #define GEN5_3DPRIMITIVE_DWordLength_bits 8 489 #define GEN45_3DPRIMITIVE_DWordLength_bits 8 490 #define GEN4_3DPRIMITIVE_DWordLength_bits 8 491 492 static inline uint32_t ATTRIBUTE_PURE 493 _3DPRIMITIVE_DWordLength_bits(const struct gen_device_info *devinfo) 494 { 495 switch (devinfo->gen) { 496 case 10: return 8; 497 case 9: return 8; 498 case 8: return 8; 499 case 7: 500 if (devinfo->is_haswell) { 501 return 8; 502 } else { 503 return 8; 504 } 505 case 6: return 8; 506 case 5: return 8; 507 case 4: 508 if (devinfo->is_g4x) { 509 return 8; 510 } else { 511 return 8; 512 } 513 default: 514 unreachable("Invalid hardware generation"); 515 } 516 } 517 518 519 520 #define GEN10_3DPRIMITIVE_DWordLength_start 0 521 #define GEN9_3DPRIMITIVE_DWordLength_start 0 522 #define GEN8_3DPRIMITIVE_DWordLength_start 0 523 #define GEN75_3DPRIMITIVE_DWordLength_start 0 524 #define GEN7_3DPRIMITIVE_DWordLength_start 0 525 #define GEN6_3DPRIMITIVE_DWordLength_start 0 526 #define GEN5_3DPRIMITIVE_DWordLength_start 0 527 #define GEN45_3DPRIMITIVE_DWordLength_start 0 528 #define GEN4_3DPRIMITIVE_DWordLength_start 0 529 530 static inline uint32_t ATTRIBUTE_PURE 531 _3DPRIMITIVE_DWordLength_start(const struct gen_device_info *devinfo) 532 { 533 switch (devinfo->gen) { 534 case 10: return 0; 535 case 9: return 0; 536 case 8: return 0; 537 case 7: 538 if (devinfo->is_haswell) { 539 return 0; 540 } else { 541 return 0; 542 } 543 case 6: return 0; 544 case 5: return 0; 545 case 4: 546 if (devinfo->is_g4x) { 547 return 0; 548 } else { 549 return 0; 550 } 551 default: 552 unreachable("Invalid hardware generation"); 553 } 554 } 555 556 557 558 /* 3DPRIMITIVE::End Offset Enable */ 559 560 561 #define GEN10_3DPRIMITIVE_EndOffsetEnable_bits 1 562 #define GEN9_3DPRIMITIVE_EndOffsetEnable_bits 1 563 #define GEN8_3DPRIMITIVE_EndOffsetEnable_bits 1 564 #define GEN75_3DPRIMITIVE_EndOffsetEnable_bits 1 565 #define GEN7_3DPRIMITIVE_EndOffsetEnable_bits 1 566 567 static inline uint32_t ATTRIBUTE_PURE 568 _3DPRIMITIVE_EndOffsetEnable_bits(const struct gen_device_info *devinfo) 569 { 570 switch (devinfo->gen) { 571 case 10: return 1; 572 case 9: return 1; 573 case 8: return 1; 574 case 7: 575 if (devinfo->is_haswell) { 576 return 1; 577 } else { 578 return 1; 579 } 580 case 6: return 0; 581 case 5: return 0; 582 case 4: 583 if (devinfo->is_g4x) { 584 return 0; 585 } else { 586 return 0; 587 } 588 default: 589 unreachable("Invalid hardware generation"); 590 } 591 } 592 593 594 595 #define GEN10_3DPRIMITIVE_EndOffsetEnable_start 41 596 #define GEN9_3DPRIMITIVE_EndOffsetEnable_start 41 597 #define GEN8_3DPRIMITIVE_EndOffsetEnable_start 41 598 #define GEN75_3DPRIMITIVE_EndOffsetEnable_start 41 599 #define GEN7_3DPRIMITIVE_EndOffsetEnable_start 41 600 601 static inline uint32_t ATTRIBUTE_PURE 602 _3DPRIMITIVE_EndOffsetEnable_start(const struct gen_device_info *devinfo) 603 { 604 switch (devinfo->gen) { 605 case 10: return 41; 606 case 9: return 41; 607 case 8: return 41; 608 case 7: 609 if (devinfo->is_haswell) { 610 return 41; 611 } else { 612 return 41; 613 } 614 case 6: return 0; 615 case 5: return 0; 616 case 4: 617 if (devinfo->is_g4x) { 618 return 0; 619 } else { 620 return 0; 621 } 622 default: 623 unreachable("Invalid hardware generation"); 624 } 625 } 626 627 628 629 /* 3DPRIMITIVE::Extended Parameter 0 */ 630 631 632 #define GEN10_3DPRIMITIVE_ExtendedParameter0_bits 32 633 634 static inline uint32_t ATTRIBUTE_PURE 635 _3DPRIMITIVE_ExtendedParameter0_bits(const struct gen_device_info *devinfo) 636 { 637 switch (devinfo->gen) { 638 case 10: return 32; 639 case 9: return 0; 640 case 8: return 0; 641 case 7: 642 if (devinfo->is_haswell) { 643 return 0; 644 } else { 645 return 0; 646 } 647 case 6: return 0; 648 case 5: return 0; 649 case 4: 650 if (devinfo->is_g4x) { 651 return 0; 652 } else { 653 return 0; 654 } 655 default: 656 unreachable("Invalid hardware generation"); 657 } 658 } 659 660 661 662 #define GEN10_3DPRIMITIVE_ExtendedParameter0_start 224 663 664 static inline uint32_t ATTRIBUTE_PURE 665 _3DPRIMITIVE_ExtendedParameter0_start(const struct gen_device_info *devinfo) 666 { 667 switch (devinfo->gen) { 668 case 10: return 224; 669 case 9: return 0; 670 case 8: return 0; 671 case 7: 672 if (devinfo->is_haswell) { 673 return 0; 674 } else { 675 return 0; 676 } 677 case 6: return 0; 678 case 5: return 0; 679 case 4: 680 if (devinfo->is_g4x) { 681 return 0; 682 } else { 683 return 0; 684 } 685 default: 686 unreachable("Invalid hardware generation"); 687 } 688 } 689 690 691 692 /* 3DPRIMITIVE::Extended Parameter 1 */ 693 694 695 #define GEN10_3DPRIMITIVE_ExtendedParameter1_bits 32 696 697 static inline uint32_t ATTRIBUTE_PURE 698 _3DPRIMITIVE_ExtendedParameter1_bits(const struct gen_device_info *devinfo) 699 { 700 switch (devinfo->gen) { 701 case 10: return 32; 702 case 9: return 0; 703 case 8: return 0; 704 case 7: 705 if (devinfo->is_haswell) { 706 return 0; 707 } else { 708 return 0; 709 } 710 case 6: return 0; 711 case 5: return 0; 712 case 4: 713 if (devinfo->is_g4x) { 714 return 0; 715 } else { 716 return 0; 717 } 718 default: 719 unreachable("Invalid hardware generation"); 720 } 721 } 722 723 724 725 #define GEN10_3DPRIMITIVE_ExtendedParameter1_start 256 726 727 static inline uint32_t ATTRIBUTE_PURE 728 _3DPRIMITIVE_ExtendedParameter1_start(const struct gen_device_info *devinfo) 729 { 730 switch (devinfo->gen) { 731 case 10: return 256; 732 case 9: return 0; 733 case 8: return 0; 734 case 7: 735 if (devinfo->is_haswell) { 736 return 0; 737 } else { 738 return 0; 739 } 740 case 6: return 0; 741 case 5: return 0; 742 case 4: 743 if (devinfo->is_g4x) { 744 return 0; 745 } else { 746 return 0; 747 } 748 default: 749 unreachable("Invalid hardware generation"); 750 } 751 } 752 753 754 755 /* 3DPRIMITIVE::Extended Parameter 2 */ 756 757 758 #define GEN10_3DPRIMITIVE_ExtendedParameter2_bits 32 759 760 static inline uint32_t ATTRIBUTE_PURE 761 _3DPRIMITIVE_ExtendedParameter2_bits(const struct gen_device_info *devinfo) 762 { 763 switch (devinfo->gen) { 764 case 10: return 32; 765 case 9: return 0; 766 case 8: return 0; 767 case 7: 768 if (devinfo->is_haswell) { 769 return 0; 770 } else { 771 return 0; 772 } 773 case 6: return 0; 774 case 5: return 0; 775 case 4: 776 if (devinfo->is_g4x) { 777 return 0; 778 } else { 779 return 0; 780 } 781 default: 782 unreachable("Invalid hardware generation"); 783 } 784 } 785 786 787 788 #define GEN10_3DPRIMITIVE_ExtendedParameter2_start 288 789 790 static inline uint32_t ATTRIBUTE_PURE 791 _3DPRIMITIVE_ExtendedParameter2_start(const struct gen_device_info *devinfo) 792 { 793 switch (devinfo->gen) { 794 case 10: return 288; 795 case 9: return 0; 796 case 8: return 0; 797 case 7: 798 if (devinfo->is_haswell) { 799 return 0; 800 } else { 801 return 0; 802 } 803 case 6: return 0; 804 case 5: return 0; 805 case 4: 806 if (devinfo->is_g4x) { 807 return 0; 808 } else { 809 return 0; 810 } 811 default: 812 unreachable("Invalid hardware generation"); 813 } 814 } 815 816 817 818 /* 3DPRIMITIVE::Extended Parameters Present */ 819 820 821 #define GEN10_3DPRIMITIVE_ExtendedParametersPresent_bits 1 822 823 static inline uint32_t ATTRIBUTE_PURE 824 _3DPRIMITIVE_ExtendedParametersPresent_bits(const struct gen_device_info *devinfo) 825 { 826 switch (devinfo->gen) { 827 case 10: return 1; 828 case 9: return 0; 829 case 8: return 0; 830 case 7: 831 if (devinfo->is_haswell) { 832 return 0; 833 } else { 834 return 0; 835 } 836 case 6: return 0; 837 case 5: return 0; 838 case 4: 839 if (devinfo->is_g4x) { 840 return 0; 841 } else { 842 return 0; 843 } 844 default: 845 unreachable("Invalid hardware generation"); 846 } 847 } 848 849 850 851 #define GEN10_3DPRIMITIVE_ExtendedParametersPresent_start 11 852 853 static inline uint32_t ATTRIBUTE_PURE 854 _3DPRIMITIVE_ExtendedParametersPresent_start(const struct gen_device_info *devinfo) 855 { 856 switch (devinfo->gen) { 857 case 10: return 11; 858 case 9: return 0; 859 case 8: return 0; 860 case 7: 861 if (devinfo->is_haswell) { 862 return 0; 863 } else { 864 return 0; 865 } 866 case 6: return 0; 867 case 5: return 0; 868 case 4: 869 if (devinfo->is_g4x) { 870 return 0; 871 } else { 872 return 0; 873 } 874 default: 875 unreachable("Invalid hardware generation"); 876 } 877 } 878 879 880 881 /* 3DPRIMITIVE::Indirect Parameter Enable */ 882 883 884 #define GEN10_3DPRIMITIVE_IndirectParameterEnable_bits 1 885 #define GEN9_3DPRIMITIVE_IndirectParameterEnable_bits 1 886 #define GEN8_3DPRIMITIVE_IndirectParameterEnable_bits 1 887 #define GEN75_3DPRIMITIVE_IndirectParameterEnable_bits 1 888 #define GEN7_3DPRIMITIVE_IndirectParameterEnable_bits 1 889 890 static inline uint32_t ATTRIBUTE_PURE 891 _3DPRIMITIVE_IndirectParameterEnable_bits(const struct gen_device_info *devinfo) 892 { 893 switch (devinfo->gen) { 894 case 10: return 1; 895 case 9: return 1; 896 case 8: return 1; 897 case 7: 898 if (devinfo->is_haswell) { 899 return 1; 900 } else { 901 return 1; 902 } 903 case 6: return 0; 904 case 5: return 0; 905 case 4: 906 if (devinfo->is_g4x) { 907 return 0; 908 } else { 909 return 0; 910 } 911 default: 912 unreachable("Invalid hardware generation"); 913 } 914 } 915 916 917 918 #define GEN10_3DPRIMITIVE_IndirectParameterEnable_start 10 919 #define GEN9_3DPRIMITIVE_IndirectParameterEnable_start 10 920 #define GEN8_3DPRIMITIVE_IndirectParameterEnable_start 10 921 #define GEN75_3DPRIMITIVE_IndirectParameterEnable_start 10 922 #define GEN7_3DPRIMITIVE_IndirectParameterEnable_start 10 923 924 static inline uint32_t ATTRIBUTE_PURE 925 _3DPRIMITIVE_IndirectParameterEnable_start(const struct gen_device_info *devinfo) 926 { 927 switch (devinfo->gen) { 928 case 10: return 10; 929 case 9: return 10; 930 case 8: return 10; 931 case 7: 932 if (devinfo->is_haswell) { 933 return 10; 934 } else { 935 return 10; 936 } 937 case 6: return 0; 938 case 5: return 0; 939 case 4: 940 if (devinfo->is_g4x) { 941 return 0; 942 } else { 943 return 0; 944 } 945 default: 946 unreachable("Invalid hardware generation"); 947 } 948 } 949 950 951 952 /* 3DPRIMITIVE::Indirect Vertex Count */ 953 954 955 #define GEN5_3DPRIMITIVE_IndirectVertexCount_bits 1 956 #define GEN45_3DPRIMITIVE_IndirectVertexCount_bits 1 957 958 static inline uint32_t ATTRIBUTE_PURE 959 _3DPRIMITIVE_IndirectVertexCount_bits(const struct gen_device_info *devinfo) 960 { 961 switch (devinfo->gen) { 962 case 10: return 0; 963 case 9: return 0; 964 case 8: return 0; 965 case 7: 966 if (devinfo->is_haswell) { 967 return 0; 968 } else { 969 return 0; 970 } 971 case 6: return 0; 972 case 5: return 1; 973 case 4: 974 if (devinfo->is_g4x) { 975 return 1; 976 } else { 977 return 0; 978 } 979 default: 980 unreachable("Invalid hardware generation"); 981 } 982 } 983 984 985 986 #define GEN5_3DPRIMITIVE_IndirectVertexCount_start 9 987 #define GEN45_3DPRIMITIVE_IndirectVertexCount_start 9 988 989 static inline uint32_t ATTRIBUTE_PURE 990 _3DPRIMITIVE_IndirectVertexCount_start(const struct gen_device_info *devinfo) 991 { 992 switch (devinfo->gen) { 993 case 10: return 0; 994 case 9: return 0; 995 case 8: return 0; 996 case 7: 997 if (devinfo->is_haswell) { 998 return 0; 999 } else { 1000 return 0; 1001 } 1002 case 6: return 0; 1003 case 5: return 9; 1004 case 4: 1005 if (devinfo->is_g4x) { 1006 return 9; 1007 } else { 1008 return 0; 1009 } 1010 default: 1011 unreachable("Invalid hardware generation"); 1012 } 1013 } 1014 1015 1016 1017 /* 3DPRIMITIVE::Instance Count */ 1018 1019 1020 #define GEN10_3DPRIMITIVE_InstanceCount_bits 32 1021 #define GEN9_3DPRIMITIVE_InstanceCount_bits 32 1022 #define GEN8_3DPRIMITIVE_InstanceCount_bits 32 1023 #define GEN75_3DPRIMITIVE_InstanceCount_bits 32 1024 #define GEN7_3DPRIMITIVE_InstanceCount_bits 32 1025 #define GEN6_3DPRIMITIVE_InstanceCount_bits 32 1026 #define GEN5_3DPRIMITIVE_InstanceCount_bits 32 1027 #define GEN45_3DPRIMITIVE_InstanceCount_bits 32 1028 #define GEN4_3DPRIMITIVE_InstanceCount_bits 32 1029 1030 static inline uint32_t ATTRIBUTE_PURE 1031 _3DPRIMITIVE_InstanceCount_bits(const struct gen_device_info *devinfo) 1032 { 1033 switch (devinfo->gen) { 1034 case 10: return 32; 1035 case 9: return 32; 1036 case 8: return 32; 1037 case 7: 1038 if (devinfo->is_haswell) { 1039 return 32; 1040 } else { 1041 return 32; 1042 } 1043 case 6: return 32; 1044 case 5: return 32; 1045 case 4: 1046 if (devinfo->is_g4x) { 1047 return 32; 1048 } else { 1049 return 32; 1050 } 1051 default: 1052 unreachable("Invalid hardware generation"); 1053 } 1054 } 1055 1056 1057 1058 #define GEN10_3DPRIMITIVE_InstanceCount_start 128 1059 #define GEN9_3DPRIMITIVE_InstanceCount_start 128 1060 #define GEN8_3DPRIMITIVE_InstanceCount_start 128 1061 #define GEN75_3DPRIMITIVE_InstanceCount_start 128 1062 #define GEN7_3DPRIMITIVE_InstanceCount_start 128 1063 #define GEN6_3DPRIMITIVE_InstanceCount_start 96 1064 #define GEN5_3DPRIMITIVE_InstanceCount_start 96 1065 #define GEN45_3DPRIMITIVE_InstanceCount_start 96 1066 #define GEN4_3DPRIMITIVE_InstanceCount_start 96 1067 1068 static inline uint32_t ATTRIBUTE_PURE 1069 _3DPRIMITIVE_InstanceCount_start(const struct gen_device_info *devinfo) 1070 { 1071 switch (devinfo->gen) { 1072 case 10: return 128; 1073 case 9: return 128; 1074 case 8: return 128; 1075 case 7: 1076 if (devinfo->is_haswell) { 1077 return 128; 1078 } else { 1079 return 128; 1080 } 1081 case 6: return 96; 1082 case 5: return 96; 1083 case 4: 1084 if (devinfo->is_g4x) { 1085 return 96; 1086 } else { 1087 return 96; 1088 } 1089 default: 1090 unreachable("Invalid hardware generation"); 1091 } 1092 } 1093 1094 1095 1096 /* 3DPRIMITIVE::Internal Vertex Count */ 1097 1098 1099 #define GEN6_3DPRIMITIVE_InternalVertexCount_bits 1 1100 1101 static inline uint32_t ATTRIBUTE_PURE 1102 _3DPRIMITIVE_InternalVertexCount_bits(const struct gen_device_info *devinfo) 1103 { 1104 switch (devinfo->gen) { 1105 case 10: return 0; 1106 case 9: return 0; 1107 case 8: return 0; 1108 case 7: 1109 if (devinfo->is_haswell) { 1110 return 0; 1111 } else { 1112 return 0; 1113 } 1114 case 6: return 1; 1115 case 5: return 0; 1116 case 4: 1117 if (devinfo->is_g4x) { 1118 return 0; 1119 } else { 1120 return 0; 1121 } 1122 default: 1123 unreachable("Invalid hardware generation"); 1124 } 1125 } 1126 1127 1128 1129 #define GEN6_3DPRIMITIVE_InternalVertexCount_start 9 1130 1131 static inline uint32_t ATTRIBUTE_PURE 1132 _3DPRIMITIVE_InternalVertexCount_start(const struct gen_device_info *devinfo) 1133 { 1134 switch (devinfo->gen) { 1135 case 10: return 0; 1136 case 9: return 0; 1137 case 8: return 0; 1138 case 7: 1139 if (devinfo->is_haswell) { 1140 return 0; 1141 } else { 1142 return 0; 1143 } 1144 case 6: return 9; 1145 case 5: return 0; 1146 case 4: 1147 if (devinfo->is_g4x) { 1148 return 0; 1149 } else { 1150 return 0; 1151 } 1152 default: 1153 unreachable("Invalid hardware generation"); 1154 } 1155 } 1156 1157 1158 1159 /* 3DPRIMITIVE::Predicate Enable */ 1160 1161 1162 #define GEN10_3DPRIMITIVE_PredicateEnable_bits 1 1163 #define GEN9_3DPRIMITIVE_PredicateEnable_bits 1 1164 #define GEN8_3DPRIMITIVE_PredicateEnable_bits 1 1165 #define GEN75_3DPRIMITIVE_PredicateEnable_bits 1 1166 #define GEN7_3DPRIMITIVE_PredicateEnable_bits 1 1167 1168 static inline uint32_t ATTRIBUTE_PURE 1169 _3DPRIMITIVE_PredicateEnable_bits(const struct gen_device_info *devinfo) 1170 { 1171 switch (devinfo->gen) { 1172 case 10: return 1; 1173 case 9: return 1; 1174 case 8: return 1; 1175 case 7: 1176 if (devinfo->is_haswell) { 1177 return 1; 1178 } else { 1179 return 1; 1180 } 1181 case 6: return 0; 1182 case 5: return 0; 1183 case 4: 1184 if (devinfo->is_g4x) { 1185 return 0; 1186 } else { 1187 return 0; 1188 } 1189 default: 1190 unreachable("Invalid hardware generation"); 1191 } 1192 } 1193 1194 1195 1196 #define GEN10_3DPRIMITIVE_PredicateEnable_start 8 1197 #define GEN9_3DPRIMITIVE_PredicateEnable_start 8 1198 #define GEN8_3DPRIMITIVE_PredicateEnable_start 8 1199 #define GEN75_3DPRIMITIVE_PredicateEnable_start 8 1200 #define GEN7_3DPRIMITIVE_PredicateEnable_start 8 1201 1202 static inline uint32_t ATTRIBUTE_PURE 1203 _3DPRIMITIVE_PredicateEnable_start(const struct gen_device_info *devinfo) 1204 { 1205 switch (devinfo->gen) { 1206 case 10: return 8; 1207 case 9: return 8; 1208 case 8: return 8; 1209 case 7: 1210 if (devinfo->is_haswell) { 1211 return 8; 1212 } else { 1213 return 8; 1214 } 1215 case 6: return 0; 1216 case 5: return 0; 1217 case 4: 1218 if (devinfo->is_g4x) { 1219 return 0; 1220 } else { 1221 return 0; 1222 } 1223 default: 1224 unreachable("Invalid hardware generation"); 1225 } 1226 } 1227 1228 1229 1230 /* 3DPRIMITIVE::Primitive Topology Type */ 1231 1232 1233 #define GEN10_3DPRIMITIVE_PrimitiveTopologyType_bits 6 1234 #define GEN9_3DPRIMITIVE_PrimitiveTopologyType_bits 6 1235 #define GEN8_3DPRIMITIVE_PrimitiveTopologyType_bits 6 1236 #define GEN75_3DPRIMITIVE_PrimitiveTopologyType_bits 6 1237 #define GEN7_3DPRIMITIVE_PrimitiveTopologyType_bits 6 1238 #define GEN6_3DPRIMITIVE_PrimitiveTopologyType_bits 5 1239 #define GEN5_3DPRIMITIVE_PrimitiveTopologyType_bits 5 1240 #define GEN45_3DPRIMITIVE_PrimitiveTopologyType_bits 5 1241 #define GEN4_3DPRIMITIVE_PrimitiveTopologyType_bits 5 1242 1243 static inline uint32_t ATTRIBUTE_PURE 1244 _3DPRIMITIVE_PrimitiveTopologyType_bits(const struct gen_device_info *devinfo) 1245 { 1246 switch (devinfo->gen) { 1247 case 10: return 6; 1248 case 9: return 6; 1249 case 8: return 6; 1250 case 7: 1251 if (devinfo->is_haswell) { 1252 return 6; 1253 } else { 1254 return 6; 1255 } 1256 case 6: return 5; 1257 case 5: return 5; 1258 case 4: 1259 if (devinfo->is_g4x) { 1260 return 5; 1261 } else { 1262 return 5; 1263 } 1264 default: 1265 unreachable("Invalid hardware generation"); 1266 } 1267 } 1268 1269 1270 1271 #define GEN10_3DPRIMITIVE_PrimitiveTopologyType_start 32 1272 #define GEN9_3DPRIMITIVE_PrimitiveTopologyType_start 32 1273 #define GEN8_3DPRIMITIVE_PrimitiveTopologyType_start 32 1274 #define GEN75_3DPRIMITIVE_PrimitiveTopologyType_start 32 1275 #define GEN7_3DPRIMITIVE_PrimitiveTopologyType_start 32 1276 #define GEN6_3DPRIMITIVE_PrimitiveTopologyType_start 10 1277 #define GEN5_3DPRIMITIVE_PrimitiveTopologyType_start 10 1278 #define GEN45_3DPRIMITIVE_PrimitiveTopologyType_start 10 1279 #define GEN4_3DPRIMITIVE_PrimitiveTopologyType_start 10 1280 1281 static inline uint32_t ATTRIBUTE_PURE 1282 _3DPRIMITIVE_PrimitiveTopologyType_start(const struct gen_device_info *devinfo) 1283 { 1284 switch (devinfo->gen) { 1285 case 10: return 32; 1286 case 9: return 32; 1287 case 8: return 32; 1288 case 7: 1289 if (devinfo->is_haswell) { 1290 return 32; 1291 } else { 1292 return 32; 1293 } 1294 case 6: return 10; 1295 case 5: return 10; 1296 case 4: 1297 if (devinfo->is_g4x) { 1298 return 10; 1299 } else { 1300 return 10; 1301 } 1302 default: 1303 unreachable("Invalid hardware generation"); 1304 } 1305 } 1306 1307 1308 1309 /* 3DPRIMITIVE::Start Instance Location */ 1310 1311 1312 #define GEN10_3DPRIMITIVE_StartInstanceLocation_bits 32 1313 #define GEN9_3DPRIMITIVE_StartInstanceLocation_bits 32 1314 #define GEN8_3DPRIMITIVE_StartInstanceLocation_bits 32 1315 #define GEN75_3DPRIMITIVE_StartInstanceLocation_bits 32 1316 #define GEN7_3DPRIMITIVE_StartInstanceLocation_bits 32 1317 #define GEN6_3DPRIMITIVE_StartInstanceLocation_bits 32 1318 #define GEN5_3DPRIMITIVE_StartInstanceLocation_bits 32 1319 #define GEN45_3DPRIMITIVE_StartInstanceLocation_bits 32 1320 1321 static inline uint32_t ATTRIBUTE_PURE 1322 _3DPRIMITIVE_StartInstanceLocation_bits(const struct gen_device_info *devinfo) 1323 { 1324 switch (devinfo->gen) { 1325 case 10: return 32; 1326 case 9: return 32; 1327 case 8: return 32; 1328 case 7: 1329 if (devinfo->is_haswell) { 1330 return 32; 1331 } else { 1332 return 32; 1333 } 1334 case 6: return 32; 1335 case 5: return 32; 1336 case 4: 1337 if (devinfo->is_g4x) { 1338 return 32; 1339 } else { 1340 return 0; 1341 } 1342 default: 1343 unreachable("Invalid hardware generation"); 1344 } 1345 } 1346 1347 1348 1349 #define GEN10_3DPRIMITIVE_StartInstanceLocation_start 160 1350 #define GEN9_3DPRIMITIVE_StartInstanceLocation_start 160 1351 #define GEN8_3DPRIMITIVE_StartInstanceLocation_start 160 1352 #define GEN75_3DPRIMITIVE_StartInstanceLocation_start 160 1353 #define GEN7_3DPRIMITIVE_StartInstanceLocation_start 160 1354 #define GEN6_3DPRIMITIVE_StartInstanceLocation_start 128 1355 #define GEN5_3DPRIMITIVE_StartInstanceLocation_start 128 1356 #define GEN45_3DPRIMITIVE_StartInstanceLocation_start 128 1357 1358 static inline uint32_t ATTRIBUTE_PURE 1359 _3DPRIMITIVE_StartInstanceLocation_start(const struct gen_device_info *devinfo) 1360 { 1361 switch (devinfo->gen) { 1362 case 10: return 160; 1363 case 9: return 160; 1364 case 8: return 160; 1365 case 7: 1366 if (devinfo->is_haswell) { 1367 return 160; 1368 } else { 1369 return 160; 1370 } 1371 case 6: return 128; 1372 case 5: return 128; 1373 case 4: 1374 if (devinfo->is_g4x) { 1375 return 128; 1376 } else { 1377 return 0; 1378 } 1379 default: 1380 unreachable("Invalid hardware generation"); 1381 } 1382 } 1383 1384 1385 1386 /* 3DPRIMITIVE::Start Vertex Location */ 1387 1388 1389 #define GEN10_3DPRIMITIVE_StartVertexLocation_bits 32 1390 #define GEN9_3DPRIMITIVE_StartVertexLocation_bits 32 1391 #define GEN8_3DPRIMITIVE_StartVertexLocation_bits 32 1392 #define GEN75_3DPRIMITIVE_StartVertexLocation_bits 32 1393 #define GEN7_3DPRIMITIVE_StartVertexLocation_bits 32 1394 #define GEN6_3DPRIMITIVE_StartVertexLocation_bits 32 1395 #define GEN5_3DPRIMITIVE_StartVertexLocation_bits 32 1396 #define GEN45_3DPRIMITIVE_StartVertexLocation_bits 32 1397 #define GEN4_3DPRIMITIVE_StartVertexLocation_bits 32 1398 1399 static inline uint32_t ATTRIBUTE_PURE 1400 _3DPRIMITIVE_StartVertexLocation_bits(const struct gen_device_info *devinfo) 1401 { 1402 switch (devinfo->gen) { 1403 case 10: return 32; 1404 case 9: return 32; 1405 case 8: return 32; 1406 case 7: 1407 if (devinfo->is_haswell) { 1408 return 32; 1409 } else { 1410 return 32; 1411 } 1412 case 6: return 32; 1413 case 5: return 32; 1414 case 4: 1415 if (devinfo->is_g4x) { 1416 return 32; 1417 } else { 1418 return 32; 1419 } 1420 default: 1421 unreachable("Invalid hardware generation"); 1422 } 1423 } 1424 1425 1426 1427 #define GEN10_3DPRIMITIVE_StartVertexLocation_start 96 1428 #define GEN9_3DPRIMITIVE_StartVertexLocation_start 96 1429 #define GEN8_3DPRIMITIVE_StartVertexLocation_start 96 1430 #define GEN75_3DPRIMITIVE_StartVertexLocation_start 96 1431 #define GEN7_3DPRIMITIVE_StartVertexLocation_start 96 1432 #define GEN6_3DPRIMITIVE_StartVertexLocation_start 64 1433 #define GEN5_3DPRIMITIVE_StartVertexLocation_start 64 1434 #define GEN45_3DPRIMITIVE_StartVertexLocation_start 64 1435 #define GEN4_3DPRIMITIVE_StartVertexLocation_start 64 1436 1437 static inline uint32_t ATTRIBUTE_PURE 1438 _3DPRIMITIVE_StartVertexLocation_start(const struct gen_device_info *devinfo) 1439 { 1440 switch (devinfo->gen) { 1441 case 10: return 96; 1442 case 9: return 96; 1443 case 8: return 96; 1444 case 7: 1445 if (devinfo->is_haswell) { 1446 return 96; 1447 } else { 1448 return 96; 1449 } 1450 case 6: return 64; 1451 case 5: return 64; 1452 case 4: 1453 if (devinfo->is_g4x) { 1454 return 64; 1455 } else { 1456 return 64; 1457 } 1458 default: 1459 unreachable("Invalid hardware generation"); 1460 } 1461 } 1462 1463 1464 1465 /* 3DPRIMITIVE::UAV Coherency Required */ 1466 1467 1468 #define GEN10_3DPRIMITIVE_UAVCoherencyRequired_bits 1 1469 #define GEN9_3DPRIMITIVE_UAVCoherencyRequired_bits 1 1470 #define GEN8_3DPRIMITIVE_UAVCoherencyRequired_bits 1 1471 #define GEN75_3DPRIMITIVE_UAVCoherencyRequired_bits 1 1472 1473 static inline uint32_t ATTRIBUTE_PURE 1474 _3DPRIMITIVE_UAVCoherencyRequired_bits(const struct gen_device_info *devinfo) 1475 { 1476 switch (devinfo->gen) { 1477 case 10: return 1; 1478 case 9: return 1; 1479 case 8: return 1; 1480 case 7: 1481 if (devinfo->is_haswell) { 1482 return 1; 1483 } else { 1484 return 0; 1485 } 1486 case 6: return 0; 1487 case 5: return 0; 1488 case 4: 1489 if (devinfo->is_g4x) { 1490 return 0; 1491 } else { 1492 return 0; 1493 } 1494 default: 1495 unreachable("Invalid hardware generation"); 1496 } 1497 } 1498 1499 1500 1501 #define GEN10_3DPRIMITIVE_UAVCoherencyRequired_start 9 1502 #define GEN9_3DPRIMITIVE_UAVCoherencyRequired_start 9 1503 #define GEN8_3DPRIMITIVE_UAVCoherencyRequired_start 9 1504 #define GEN75_3DPRIMITIVE_UAVCoherencyRequired_start 9 1505 1506 static inline uint32_t ATTRIBUTE_PURE 1507 _3DPRIMITIVE_UAVCoherencyRequired_start(const struct gen_device_info *devinfo) 1508 { 1509 switch (devinfo->gen) { 1510 case 10: return 9; 1511 case 9: return 9; 1512 case 8: return 9; 1513 case 7: 1514 if (devinfo->is_haswell) { 1515 return 9; 1516 } else { 1517 return 0; 1518 } 1519 case 6: return 0; 1520 case 5: return 0; 1521 case 4: 1522 if (devinfo->is_g4x) { 1523 return 0; 1524 } else { 1525 return 0; 1526 } 1527 default: 1528 unreachable("Invalid hardware generation"); 1529 } 1530 } 1531 1532 1533 1534 /* 3DPRIMITIVE::Vertex Access Type */ 1535 1536 1537 #define GEN10_3DPRIMITIVE_VertexAccessType_bits 1 1538 #define GEN9_3DPRIMITIVE_VertexAccessType_bits 1 1539 #define GEN8_3DPRIMITIVE_VertexAccessType_bits 1 1540 #define GEN75_3DPRIMITIVE_VertexAccessType_bits 1 1541 #define GEN7_3DPRIMITIVE_VertexAccessType_bits 1 1542 #define GEN6_3DPRIMITIVE_VertexAccessType_bits 1 1543 #define GEN5_3DPRIMITIVE_VertexAccessType_bits 1 1544 #define GEN45_3DPRIMITIVE_VertexAccessType_bits 1 1545 #define GEN4_3DPRIMITIVE_VertexAccessType_bits 1 1546 1547 static inline uint32_t ATTRIBUTE_PURE 1548 _3DPRIMITIVE_VertexAccessType_bits(const struct gen_device_info *devinfo) 1549 { 1550 switch (devinfo->gen) { 1551 case 10: return 1; 1552 case 9: return 1; 1553 case 8: return 1; 1554 case 7: 1555 if (devinfo->is_haswell) { 1556 return 1; 1557 } else { 1558 return 1; 1559 } 1560 case 6: return 1; 1561 case 5: return 1; 1562 case 4: 1563 if (devinfo->is_g4x) { 1564 return 1; 1565 } else { 1566 return 1; 1567 } 1568 default: 1569 unreachable("Invalid hardware generation"); 1570 } 1571 } 1572 1573 1574 1575 #define GEN10_3DPRIMITIVE_VertexAccessType_start 40 1576 #define GEN9_3DPRIMITIVE_VertexAccessType_start 40 1577 #define GEN8_3DPRIMITIVE_VertexAccessType_start 40 1578 #define GEN75_3DPRIMITIVE_VertexAccessType_start 40 1579 #define GEN7_3DPRIMITIVE_VertexAccessType_start 40 1580 #define GEN6_3DPRIMITIVE_VertexAccessType_start 15 1581 #define GEN5_3DPRIMITIVE_VertexAccessType_start 15 1582 #define GEN45_3DPRIMITIVE_VertexAccessType_start 15 1583 #define GEN4_3DPRIMITIVE_VertexAccessType_start 15 1584 1585 static inline uint32_t ATTRIBUTE_PURE 1586 _3DPRIMITIVE_VertexAccessType_start(const struct gen_device_info *devinfo) 1587 { 1588 switch (devinfo->gen) { 1589 case 10: return 40; 1590 case 9: return 40; 1591 case 8: return 40; 1592 case 7: 1593 if (devinfo->is_haswell) { 1594 return 40; 1595 } else { 1596 return 40; 1597 } 1598 case 6: return 15; 1599 case 5: return 15; 1600 case 4: 1601 if (devinfo->is_g4x) { 1602 return 15; 1603 } else { 1604 return 15; 1605 } 1606 default: 1607 unreachable("Invalid hardware generation"); 1608 } 1609 } 1610 1611 1612 1613 /* 3DPRIMITIVE::Vertex Count Per Instance */ 1614 1615 1616 #define GEN10_3DPRIMITIVE_VertexCountPerInstance_bits 32 1617 #define GEN9_3DPRIMITIVE_VertexCountPerInstance_bits 32 1618 #define GEN8_3DPRIMITIVE_VertexCountPerInstance_bits 32 1619 #define GEN75_3DPRIMITIVE_VertexCountPerInstance_bits 32 1620 #define GEN7_3DPRIMITIVE_VertexCountPerInstance_bits 32 1621 #define GEN6_3DPRIMITIVE_VertexCountPerInstance_bits 32 1622 #define GEN5_3DPRIMITIVE_VertexCountPerInstance_bits 32 1623 #define GEN45_3DPRIMITIVE_VertexCountPerInstance_bits 32 1624 #define GEN4_3DPRIMITIVE_VertexCountPerInstance_bits 32 1625 1626 static inline uint32_t ATTRIBUTE_PURE 1627 _3DPRIMITIVE_VertexCountPerInstance_bits(const struct gen_device_info *devinfo) 1628 { 1629 switch (devinfo->gen) { 1630 case 10: return 32; 1631 case 9: return 32; 1632 case 8: return 32; 1633 case 7: 1634 if (devinfo->is_haswell) { 1635 return 32; 1636 } else { 1637 return 32; 1638 } 1639 case 6: return 32; 1640 case 5: return 32; 1641 case 4: 1642 if (devinfo->is_g4x) { 1643 return 32; 1644 } else { 1645 return 32; 1646 } 1647 default: 1648 unreachable("Invalid hardware generation"); 1649 } 1650 } 1651 1652 1653 1654 #define GEN10_3DPRIMITIVE_VertexCountPerInstance_start 64 1655 #define GEN9_3DPRIMITIVE_VertexCountPerInstance_start 64 1656 #define GEN8_3DPRIMITIVE_VertexCountPerInstance_start 64 1657 #define GEN75_3DPRIMITIVE_VertexCountPerInstance_start 64 1658 #define GEN7_3DPRIMITIVE_VertexCountPerInstance_start 64 1659 #define GEN6_3DPRIMITIVE_VertexCountPerInstance_start 32 1660 #define GEN5_3DPRIMITIVE_VertexCountPerInstance_start 32 1661 #define GEN45_3DPRIMITIVE_VertexCountPerInstance_start 32 1662 #define GEN4_3DPRIMITIVE_VertexCountPerInstance_start 32 1663 1664 static inline uint32_t ATTRIBUTE_PURE 1665 _3DPRIMITIVE_VertexCountPerInstance_start(const struct gen_device_info *devinfo) 1666 { 1667 switch (devinfo->gen) { 1668 case 10: return 64; 1669 case 9: return 64; 1670 case 8: return 64; 1671 case 7: 1672 if (devinfo->is_haswell) { 1673 return 64; 1674 } else { 1675 return 64; 1676 } 1677 case 6: return 32; 1678 case 5: return 32; 1679 case 4: 1680 if (devinfo->is_g4x) { 1681 return 32; 1682 } else { 1683 return 32; 1684 } 1685 default: 1686 unreachable("Invalid hardware generation"); 1687 } 1688 } 1689 1690 1691 1692 /* 3DSTATE_AA_LINE_PARAMETERS */ 1693 1694 1695 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_length 3 1696 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_length 3 1697 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_length 3 1698 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_length 3 1699 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_length 3 1700 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_length 3 1701 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_length 3 1702 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_length 3 1703 1704 static inline uint32_t ATTRIBUTE_PURE 1705 _3DSTATE_AA_LINE_PARAMETERS_length(const struct gen_device_info *devinfo) 1706 { 1707 switch (devinfo->gen) { 1708 case 10: return 3; 1709 case 9: return 3; 1710 case 8: return 3; 1711 case 7: 1712 if (devinfo->is_haswell) { 1713 return 3; 1714 } else { 1715 return 3; 1716 } 1717 case 6: return 3; 1718 case 5: return 3; 1719 case 4: 1720 if (devinfo->is_g4x) { 1721 return 3; 1722 } else { 1723 return 0; 1724 } 1725 default: 1726 unreachable("Invalid hardware generation"); 1727 } 1728 } 1729 1730 1731 1732 /* 3DSTATE_AA_LINE_PARAMETERS::3D Command Opcode */ 1733 1734 1735 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1736 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1737 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1738 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1739 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1740 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1741 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1742 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1743 1744 static inline uint32_t ATTRIBUTE_PURE 1745 _3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 1746 { 1747 switch (devinfo->gen) { 1748 case 10: return 3; 1749 case 9: return 3; 1750 case 8: return 3; 1751 case 7: 1752 if (devinfo->is_haswell) { 1753 return 3; 1754 } else { 1755 return 3; 1756 } 1757 case 6: return 3; 1758 case 5: return 3; 1759 case 4: 1760 if (devinfo->is_g4x) { 1761 return 3; 1762 } else { 1763 return 0; 1764 } 1765 default: 1766 unreachable("Invalid hardware generation"); 1767 } 1768 } 1769 1770 1771 1772 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1773 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1774 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1775 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1776 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1777 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1778 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1779 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1780 1781 static inline uint32_t ATTRIBUTE_PURE 1782 _3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 1783 { 1784 switch (devinfo->gen) { 1785 case 10: return 24; 1786 case 9: return 24; 1787 case 8: return 24; 1788 case 7: 1789 if (devinfo->is_haswell) { 1790 return 24; 1791 } else { 1792 return 24; 1793 } 1794 case 6: return 24; 1795 case 5: return 24; 1796 case 4: 1797 if (devinfo->is_g4x) { 1798 return 24; 1799 } else { 1800 return 0; 1801 } 1802 default: 1803 unreachable("Invalid hardware generation"); 1804 } 1805 } 1806 1807 1808 1809 /* 3DSTATE_AA_LINE_PARAMETERS::3D Command Sub Opcode */ 1810 1811 1812 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1813 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1814 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1815 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1816 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1817 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1818 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1819 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1820 1821 static inline uint32_t ATTRIBUTE_PURE 1822 _3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 1823 { 1824 switch (devinfo->gen) { 1825 case 10: return 8; 1826 case 9: return 8; 1827 case 8: return 8; 1828 case 7: 1829 if (devinfo->is_haswell) { 1830 return 8; 1831 } else { 1832 return 8; 1833 } 1834 case 6: return 8; 1835 case 5: return 8; 1836 case 4: 1837 if (devinfo->is_g4x) { 1838 return 8; 1839 } else { 1840 return 0; 1841 } 1842 default: 1843 unreachable("Invalid hardware generation"); 1844 } 1845 } 1846 1847 1848 1849 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1850 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1851 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1852 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1853 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1854 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1855 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1856 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1857 1858 static inline uint32_t ATTRIBUTE_PURE 1859 _3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 1860 { 1861 switch (devinfo->gen) { 1862 case 10: return 16; 1863 case 9: return 16; 1864 case 8: return 16; 1865 case 7: 1866 if (devinfo->is_haswell) { 1867 return 16; 1868 } else { 1869 return 16; 1870 } 1871 case 6: return 16; 1872 case 5: return 16; 1873 case 4: 1874 if (devinfo->is_g4x) { 1875 return 16; 1876 } else { 1877 return 0; 1878 } 1879 default: 1880 unreachable("Invalid hardware generation"); 1881 } 1882 } 1883 1884 1885 1886 /* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage Bias */ 1887 1888 1889 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1890 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1891 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1892 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1893 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1894 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1895 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1896 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1897 1898 static inline uint32_t ATTRIBUTE_PURE 1899 _3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits(const struct gen_device_info *devinfo) 1900 { 1901 switch (devinfo->gen) { 1902 case 10: return 8; 1903 case 9: return 8; 1904 case 8: return 8; 1905 case 7: 1906 if (devinfo->is_haswell) { 1907 return 8; 1908 } else { 1909 return 8; 1910 } 1911 case 6: return 8; 1912 case 5: return 8; 1913 case 4: 1914 if (devinfo->is_g4x) { 1915 return 8; 1916 } else { 1917 return 0; 1918 } 1919 default: 1920 unreachable("Invalid hardware generation"); 1921 } 1922 } 1923 1924 1925 1926 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1927 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1928 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1929 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1930 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1931 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1932 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1933 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1934 1935 static inline uint32_t ATTRIBUTE_PURE 1936 _3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start(const struct gen_device_info *devinfo) 1937 { 1938 switch (devinfo->gen) { 1939 case 10: return 48; 1940 case 9: return 48; 1941 case 8: return 48; 1942 case 7: 1943 if (devinfo->is_haswell) { 1944 return 48; 1945 } else { 1946 return 48; 1947 } 1948 case 6: return 48; 1949 case 5: return 48; 1950 case 4: 1951 if (devinfo->is_g4x) { 1952 return 48; 1953 } else { 1954 return 0; 1955 } 1956 default: 1957 unreachable("Invalid hardware generation"); 1958 } 1959 } 1960 1961 1962 1963 /* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage EndCap Bias */ 1964 1965 1966 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1967 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1968 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1969 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1970 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1971 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1972 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1973 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1974 1975 static inline uint32_t ATTRIBUTE_PURE 1976 _3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits(const struct gen_device_info *devinfo) 1977 { 1978 switch (devinfo->gen) { 1979 case 10: return 8; 1980 case 9: return 8; 1981 case 8: return 8; 1982 case 7: 1983 if (devinfo->is_haswell) { 1984 return 8; 1985 } else { 1986 return 8; 1987 } 1988 case 6: return 8; 1989 case 5: return 8; 1990 case 4: 1991 if (devinfo->is_g4x) { 1992 return 8; 1993 } else { 1994 return 0; 1995 } 1996 default: 1997 unreachable("Invalid hardware generation"); 1998 } 1999 } 2000 2001 2002 2003 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2004 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2005 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2006 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2007 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2008 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2009 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2010 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2011 2012 static inline uint32_t ATTRIBUTE_PURE 2013 _3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start(const struct gen_device_info *devinfo) 2014 { 2015 switch (devinfo->gen) { 2016 case 10: return 80; 2017 case 9: return 80; 2018 case 8: return 80; 2019 case 7: 2020 if (devinfo->is_haswell) { 2021 return 80; 2022 } else { 2023 return 80; 2024 } 2025 case 6: return 80; 2026 case 5: return 80; 2027 case 4: 2028 if (devinfo->is_g4x) { 2029 return 80; 2030 } else { 2031 return 0; 2032 } 2033 default: 2034 unreachable("Invalid hardware generation"); 2035 } 2036 } 2037 2038 2039 2040 /* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage EndCap Slope */ 2041 2042 2043 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2044 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2045 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2046 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2047 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2048 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2049 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2050 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2051 2052 static inline uint32_t ATTRIBUTE_PURE 2053 _3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits(const struct gen_device_info *devinfo) 2054 { 2055 switch (devinfo->gen) { 2056 case 10: return 8; 2057 case 9: return 8; 2058 case 8: return 8; 2059 case 7: 2060 if (devinfo->is_haswell) { 2061 return 8; 2062 } else { 2063 return 8; 2064 } 2065 case 6: return 8; 2066 case 5: return 8; 2067 case 4: 2068 if (devinfo->is_g4x) { 2069 return 8; 2070 } else { 2071 return 0; 2072 } 2073 default: 2074 unreachable("Invalid hardware generation"); 2075 } 2076 } 2077 2078 2079 2080 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2081 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2082 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2083 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2084 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2085 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2086 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2087 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2088 2089 static inline uint32_t ATTRIBUTE_PURE 2090 _3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start(const struct gen_device_info *devinfo) 2091 { 2092 switch (devinfo->gen) { 2093 case 10: return 64; 2094 case 9: return 64; 2095 case 8: return 64; 2096 case 7: 2097 if (devinfo->is_haswell) { 2098 return 64; 2099 } else { 2100 return 64; 2101 } 2102 case 6: return 64; 2103 case 5: return 64; 2104 case 4: 2105 if (devinfo->is_g4x) { 2106 return 64; 2107 } else { 2108 return 0; 2109 } 2110 default: 2111 unreachable("Invalid hardware generation"); 2112 } 2113 } 2114 2115 2116 2117 /* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage Slope */ 2118 2119 2120 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2121 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2122 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2123 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2124 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2125 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2126 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2127 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2128 2129 static inline uint32_t ATTRIBUTE_PURE 2130 _3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits(const struct gen_device_info *devinfo) 2131 { 2132 switch (devinfo->gen) { 2133 case 10: return 8; 2134 case 9: return 8; 2135 case 8: return 8; 2136 case 7: 2137 if (devinfo->is_haswell) { 2138 return 8; 2139 } else { 2140 return 8; 2141 } 2142 case 6: return 8; 2143 case 5: return 8; 2144 case 4: 2145 if (devinfo->is_g4x) { 2146 return 8; 2147 } else { 2148 return 0; 2149 } 2150 default: 2151 unreachable("Invalid hardware generation"); 2152 } 2153 } 2154 2155 2156 2157 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2158 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2159 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2160 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2161 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2162 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2163 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2164 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2165 2166 static inline uint32_t ATTRIBUTE_PURE 2167 _3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start(const struct gen_device_info *devinfo) 2168 { 2169 switch (devinfo->gen) { 2170 case 10: return 32; 2171 case 9: return 32; 2172 case 8: return 32; 2173 case 7: 2174 if (devinfo->is_haswell) { 2175 return 32; 2176 } else { 2177 return 32; 2178 } 2179 case 6: return 32; 2180 case 5: return 32; 2181 case 4: 2182 if (devinfo->is_g4x) { 2183 return 32; 2184 } else { 2185 return 0; 2186 } 2187 default: 2188 unreachable("Invalid hardware generation"); 2189 } 2190 } 2191 2192 2193 2194 /* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage Bias */ 2195 2196 2197 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 2198 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 2199 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 2200 2201 static inline uint32_t ATTRIBUTE_PURE 2202 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits(const struct gen_device_info *devinfo) 2203 { 2204 switch (devinfo->gen) { 2205 case 10: return 8; 2206 case 9: return 8; 2207 case 8: return 8; 2208 case 7: 2209 if (devinfo->is_haswell) { 2210 return 0; 2211 } else { 2212 return 0; 2213 } 2214 case 6: return 0; 2215 case 5: return 0; 2216 case 4: 2217 if (devinfo->is_g4x) { 2218 return 0; 2219 } else { 2220 return 0; 2221 } 2222 default: 2223 unreachable("Invalid hardware generation"); 2224 } 2225 } 2226 2227 2228 2229 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 2230 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 2231 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 2232 2233 static inline uint32_t ATTRIBUTE_PURE 2234 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start(const struct gen_device_info *devinfo) 2235 { 2236 switch (devinfo->gen) { 2237 case 10: return 56; 2238 case 9: return 56; 2239 case 8: return 56; 2240 case 7: 2241 if (devinfo->is_haswell) { 2242 return 0; 2243 } else { 2244 return 0; 2245 } 2246 case 6: return 0; 2247 case 5: return 0; 2248 case 4: 2249 if (devinfo->is_g4x) { 2250 return 0; 2251 } else { 2252 return 0; 2253 } 2254 default: 2255 unreachable("Invalid hardware generation"); 2256 } 2257 } 2258 2259 2260 2261 /* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage EndCap Bias */ 2262 2263 2264 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 2265 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 2266 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 2267 2268 static inline uint32_t ATTRIBUTE_PURE 2269 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits(const struct gen_device_info *devinfo) 2270 { 2271 switch (devinfo->gen) { 2272 case 10: return 8; 2273 case 9: return 8; 2274 case 8: return 8; 2275 case 7: 2276 if (devinfo->is_haswell) { 2277 return 0; 2278 } else { 2279 return 0; 2280 } 2281 case 6: return 0; 2282 case 5: return 0; 2283 case 4: 2284 if (devinfo->is_g4x) { 2285 return 0; 2286 } else { 2287 return 0; 2288 } 2289 default: 2290 unreachable("Invalid hardware generation"); 2291 } 2292 } 2293 2294 2295 2296 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 2297 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 2298 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 2299 2300 static inline uint32_t ATTRIBUTE_PURE 2301 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start(const struct gen_device_info *devinfo) 2302 { 2303 switch (devinfo->gen) { 2304 case 10: return 88; 2305 case 9: return 88; 2306 case 8: return 88; 2307 case 7: 2308 if (devinfo->is_haswell) { 2309 return 0; 2310 } else { 2311 return 0; 2312 } 2313 case 6: return 0; 2314 case 5: return 0; 2315 case 4: 2316 if (devinfo->is_g4x) { 2317 return 0; 2318 } else { 2319 return 0; 2320 } 2321 default: 2322 unreachable("Invalid hardware generation"); 2323 } 2324 } 2325 2326 2327 2328 /* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage EndCap Slope */ 2329 2330 2331 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 2332 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 2333 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 2334 2335 static inline uint32_t ATTRIBUTE_PURE 2336 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits(const struct gen_device_info *devinfo) 2337 { 2338 switch (devinfo->gen) { 2339 case 10: return 8; 2340 case 9: return 8; 2341 case 8: return 8; 2342 case 7: 2343 if (devinfo->is_haswell) { 2344 return 0; 2345 } else { 2346 return 0; 2347 } 2348 case 6: return 0; 2349 case 5: return 0; 2350 case 4: 2351 if (devinfo->is_g4x) { 2352 return 0; 2353 } else { 2354 return 0; 2355 } 2356 default: 2357 unreachable("Invalid hardware generation"); 2358 } 2359 } 2360 2361 2362 2363 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 2364 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 2365 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 2366 2367 static inline uint32_t ATTRIBUTE_PURE 2368 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start(const struct gen_device_info *devinfo) 2369 { 2370 switch (devinfo->gen) { 2371 case 10: return 72; 2372 case 9: return 72; 2373 case 8: return 72; 2374 case 7: 2375 if (devinfo->is_haswell) { 2376 return 0; 2377 } else { 2378 return 0; 2379 } 2380 case 6: return 0; 2381 case 5: return 0; 2382 case 4: 2383 if (devinfo->is_g4x) { 2384 return 0; 2385 } else { 2386 return 0; 2387 } 2388 default: 2389 unreachable("Invalid hardware generation"); 2390 } 2391 } 2392 2393 2394 2395 /* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage Slope */ 2396 2397 2398 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 2399 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 2400 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 2401 2402 static inline uint32_t ATTRIBUTE_PURE 2403 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits(const struct gen_device_info *devinfo) 2404 { 2405 switch (devinfo->gen) { 2406 case 10: return 8; 2407 case 9: return 8; 2408 case 8: return 8; 2409 case 7: 2410 if (devinfo->is_haswell) { 2411 return 0; 2412 } else { 2413 return 0; 2414 } 2415 case 6: return 0; 2416 case 5: return 0; 2417 case 4: 2418 if (devinfo->is_g4x) { 2419 return 0; 2420 } else { 2421 return 0; 2422 } 2423 default: 2424 unreachable("Invalid hardware generation"); 2425 } 2426 } 2427 2428 2429 2430 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 2431 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 2432 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 2433 2434 static inline uint32_t ATTRIBUTE_PURE 2435 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start(const struct gen_device_info *devinfo) 2436 { 2437 switch (devinfo->gen) { 2438 case 10: return 40; 2439 case 9: return 40; 2440 case 8: return 40; 2441 case 7: 2442 if (devinfo->is_haswell) { 2443 return 0; 2444 } else { 2445 return 0; 2446 } 2447 case 6: return 0; 2448 case 5: return 0; 2449 case 4: 2450 if (devinfo->is_g4x) { 2451 return 0; 2452 } else { 2453 return 0; 2454 } 2455 default: 2456 unreachable("Invalid hardware generation"); 2457 } 2458 } 2459 2460 2461 2462 /* 3DSTATE_AA_LINE_PARAMETERS::Command SubType */ 2463 2464 2465 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2466 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2467 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2468 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2469 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2470 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2471 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2472 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2473 2474 static inline uint32_t ATTRIBUTE_PURE 2475 _3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits(const struct gen_device_info *devinfo) 2476 { 2477 switch (devinfo->gen) { 2478 case 10: return 2; 2479 case 9: return 2; 2480 case 8: return 2; 2481 case 7: 2482 if (devinfo->is_haswell) { 2483 return 2; 2484 } else { 2485 return 2; 2486 } 2487 case 6: return 2; 2488 case 5: return 2; 2489 case 4: 2490 if (devinfo->is_g4x) { 2491 return 2; 2492 } else { 2493 return 0; 2494 } 2495 default: 2496 unreachable("Invalid hardware generation"); 2497 } 2498 } 2499 2500 2501 2502 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2503 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2504 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2505 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2506 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2507 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2508 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2509 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2510 2511 static inline uint32_t ATTRIBUTE_PURE 2512 _3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start(const struct gen_device_info *devinfo) 2513 { 2514 switch (devinfo->gen) { 2515 case 10: return 27; 2516 case 9: return 27; 2517 case 8: return 27; 2518 case 7: 2519 if (devinfo->is_haswell) { 2520 return 27; 2521 } else { 2522 return 27; 2523 } 2524 case 6: return 27; 2525 case 5: return 27; 2526 case 4: 2527 if (devinfo->is_g4x) { 2528 return 27; 2529 } else { 2530 return 0; 2531 } 2532 default: 2533 unreachable("Invalid hardware generation"); 2534 } 2535 } 2536 2537 2538 2539 /* 3DSTATE_AA_LINE_PARAMETERS::Command Type */ 2540 2541 2542 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2543 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2544 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2545 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2546 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2547 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2548 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2549 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2550 2551 static inline uint32_t ATTRIBUTE_PURE 2552 _3DSTATE_AA_LINE_PARAMETERS_CommandType_bits(const struct gen_device_info *devinfo) 2553 { 2554 switch (devinfo->gen) { 2555 case 10: return 3; 2556 case 9: return 3; 2557 case 8: return 3; 2558 case 7: 2559 if (devinfo->is_haswell) { 2560 return 3; 2561 } else { 2562 return 3; 2563 } 2564 case 6: return 3; 2565 case 5: return 3; 2566 case 4: 2567 if (devinfo->is_g4x) { 2568 return 3; 2569 } else { 2570 return 0; 2571 } 2572 default: 2573 unreachable("Invalid hardware generation"); 2574 } 2575 } 2576 2577 2578 2579 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2580 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2581 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2582 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2583 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2584 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2585 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2586 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2587 2588 static inline uint32_t ATTRIBUTE_PURE 2589 _3DSTATE_AA_LINE_PARAMETERS_CommandType_start(const struct gen_device_info *devinfo) 2590 { 2591 switch (devinfo->gen) { 2592 case 10: return 29; 2593 case 9: return 29; 2594 case 8: return 29; 2595 case 7: 2596 if (devinfo->is_haswell) { 2597 return 29; 2598 } else { 2599 return 29; 2600 } 2601 case 6: return 29; 2602 case 5: return 29; 2603 case 4: 2604 if (devinfo->is_g4x) { 2605 return 29; 2606 } else { 2607 return 0; 2608 } 2609 default: 2610 unreachable("Invalid hardware generation"); 2611 } 2612 } 2613 2614 2615 2616 /* 3DSTATE_AA_LINE_PARAMETERS::DWord Length */ 2617 2618 2619 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2620 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2621 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2622 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2623 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2624 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2625 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2626 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2627 2628 static inline uint32_t ATTRIBUTE_PURE 2629 _3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits(const struct gen_device_info *devinfo) 2630 { 2631 switch (devinfo->gen) { 2632 case 10: return 8; 2633 case 9: return 8; 2634 case 8: return 8; 2635 case 7: 2636 if (devinfo->is_haswell) { 2637 return 8; 2638 } else { 2639 return 8; 2640 } 2641 case 6: return 8; 2642 case 5: return 8; 2643 case 4: 2644 if (devinfo->is_g4x) { 2645 return 8; 2646 } else { 2647 return 0; 2648 } 2649 default: 2650 unreachable("Invalid hardware generation"); 2651 } 2652 } 2653 2654 2655 2656 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2657 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2658 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2659 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2660 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2661 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2662 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2663 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2664 2665 static inline uint32_t ATTRIBUTE_PURE 2666 _3DSTATE_AA_LINE_PARAMETERS_DWordLength_start(const struct gen_device_info *devinfo) 2667 { 2668 switch (devinfo->gen) { 2669 case 10: return 0; 2670 case 9: return 0; 2671 case 8: return 0; 2672 case 7: 2673 if (devinfo->is_haswell) { 2674 return 0; 2675 } else { 2676 return 0; 2677 } 2678 case 6: return 0; 2679 case 5: return 0; 2680 case 4: 2681 if (devinfo->is_g4x) { 2682 return 0; 2683 } else { 2684 return 0; 2685 } 2686 default: 2687 unreachable("Invalid hardware generation"); 2688 } 2689 } 2690 2691 2692 2693 /* 3DSTATE_BINDING_TABLE_EDIT_DS */ 2694 2695 2696 2697 2698 2699 /* 3DSTATE_BINDING_TABLE_EDIT_DS::3D Command Opcode */ 2700 2701 2702 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 2703 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 2704 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 2705 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 2706 2707 static inline uint32_t ATTRIBUTE_PURE 2708 _3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 2709 { 2710 switch (devinfo->gen) { 2711 case 10: return 3; 2712 case 9: return 3; 2713 case 8: return 3; 2714 case 7: 2715 if (devinfo->is_haswell) { 2716 return 3; 2717 } else { 2718 return 0; 2719 } 2720 case 6: return 0; 2721 case 5: return 0; 2722 case 4: 2723 if (devinfo->is_g4x) { 2724 return 0; 2725 } else { 2726 return 0; 2727 } 2728 default: 2729 unreachable("Invalid hardware generation"); 2730 } 2731 } 2732 2733 2734 2735 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 2736 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 2737 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 2738 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 2739 2740 static inline uint32_t ATTRIBUTE_PURE 2741 _3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 2742 { 2743 switch (devinfo->gen) { 2744 case 10: return 24; 2745 case 9: return 24; 2746 case 8: return 24; 2747 case 7: 2748 if (devinfo->is_haswell) { 2749 return 24; 2750 } else { 2751 return 0; 2752 } 2753 case 6: return 0; 2754 case 5: return 0; 2755 case 4: 2756 if (devinfo->is_g4x) { 2757 return 0; 2758 } else { 2759 return 0; 2760 } 2761 default: 2762 unreachable("Invalid hardware generation"); 2763 } 2764 } 2765 2766 2767 2768 /* 3DSTATE_BINDING_TABLE_EDIT_DS::3D Command Sub Opcode */ 2769 2770 2771 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 2772 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 2773 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 2774 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 2775 2776 static inline uint32_t ATTRIBUTE_PURE 2777 _3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 2778 { 2779 switch (devinfo->gen) { 2780 case 10: return 8; 2781 case 9: return 8; 2782 case 8: return 8; 2783 case 7: 2784 if (devinfo->is_haswell) { 2785 return 8; 2786 } else { 2787 return 0; 2788 } 2789 case 6: return 0; 2790 case 5: return 0; 2791 case 4: 2792 if (devinfo->is_g4x) { 2793 return 0; 2794 } else { 2795 return 0; 2796 } 2797 default: 2798 unreachable("Invalid hardware generation"); 2799 } 2800 } 2801 2802 2803 2804 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 2805 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 2806 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 2807 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 2808 2809 static inline uint32_t ATTRIBUTE_PURE 2810 _3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 2811 { 2812 switch (devinfo->gen) { 2813 case 10: return 16; 2814 case 9: return 16; 2815 case 8: return 16; 2816 case 7: 2817 if (devinfo->is_haswell) { 2818 return 16; 2819 } else { 2820 return 0; 2821 } 2822 case 6: return 0; 2823 case 5: return 0; 2824 case 4: 2825 if (devinfo->is_g4x) { 2826 return 0; 2827 } else { 2828 return 0; 2829 } 2830 default: 2831 unreachable("Invalid hardware generation"); 2832 } 2833 } 2834 2835 2836 2837 /* 3DSTATE_BINDING_TABLE_EDIT_DS::Binding Table Block Clear */ 2838 2839 2840 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 2841 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 2842 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 2843 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 2844 2845 static inline uint32_t ATTRIBUTE_PURE 2846 _3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) 2847 { 2848 switch (devinfo->gen) { 2849 case 10: return 16; 2850 case 9: return 16; 2851 case 8: return 16; 2852 case 7: 2853 if (devinfo->is_haswell) { 2854 return 16; 2855 } else { 2856 return 0; 2857 } 2858 case 6: return 0; 2859 case 5: return 0; 2860 case 4: 2861 if (devinfo->is_g4x) { 2862 return 0; 2863 } else { 2864 return 0; 2865 } 2866 default: 2867 unreachable("Invalid hardware generation"); 2868 } 2869 } 2870 2871 2872 2873 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 2874 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 2875 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 2876 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 2877 2878 static inline uint32_t ATTRIBUTE_PURE 2879 _3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) 2880 { 2881 switch (devinfo->gen) { 2882 case 10: return 48; 2883 case 9: return 48; 2884 case 8: return 48; 2885 case 7: 2886 if (devinfo->is_haswell) { 2887 return 48; 2888 } else { 2889 return 0; 2890 } 2891 case 6: return 0; 2892 case 5: return 0; 2893 case 4: 2894 if (devinfo->is_g4x) { 2895 return 0; 2896 } else { 2897 return 0; 2898 } 2899 default: 2900 unreachable("Invalid hardware generation"); 2901 } 2902 } 2903 2904 2905 2906 /* 3DSTATE_BINDING_TABLE_EDIT_DS::Binding Table Edit Target */ 2907 2908 2909 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 2910 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 2911 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 2912 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 2913 2914 static inline uint32_t ATTRIBUTE_PURE 2915 _3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) 2916 { 2917 switch (devinfo->gen) { 2918 case 10: return 2; 2919 case 9: return 2; 2920 case 8: return 2; 2921 case 7: 2922 if (devinfo->is_haswell) { 2923 return 2; 2924 } else { 2925 return 0; 2926 } 2927 case 6: return 0; 2928 case 5: return 0; 2929 case 4: 2930 if (devinfo->is_g4x) { 2931 return 0; 2932 } else { 2933 return 0; 2934 } 2935 default: 2936 unreachable("Invalid hardware generation"); 2937 } 2938 } 2939 2940 2941 2942 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 2943 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 2944 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 2945 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 2946 2947 static inline uint32_t ATTRIBUTE_PURE 2948 _3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) 2949 { 2950 switch (devinfo->gen) { 2951 case 10: return 32; 2952 case 9: return 32; 2953 case 8: return 32; 2954 case 7: 2955 if (devinfo->is_haswell) { 2956 return 32; 2957 } else { 2958 return 0; 2959 } 2960 case 6: return 0; 2961 case 5: return 0; 2962 case 4: 2963 if (devinfo->is_g4x) { 2964 return 0; 2965 } else { 2966 return 0; 2967 } 2968 default: 2969 unreachable("Invalid hardware generation"); 2970 } 2971 } 2972 2973 2974 2975 /* 3DSTATE_BINDING_TABLE_EDIT_DS::Command SubType */ 2976 2977 2978 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 2979 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 2980 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 2981 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 2982 2983 static inline uint32_t ATTRIBUTE_PURE 2984 _3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits(const struct gen_device_info *devinfo) 2985 { 2986 switch (devinfo->gen) { 2987 case 10: return 2; 2988 case 9: return 2; 2989 case 8: return 2; 2990 case 7: 2991 if (devinfo->is_haswell) { 2992 return 2; 2993 } else { 2994 return 0; 2995 } 2996 case 6: return 0; 2997 case 5: return 0; 2998 case 4: 2999 if (devinfo->is_g4x) { 3000 return 0; 3001 } else { 3002 return 0; 3003 } 3004 default: 3005 unreachable("Invalid hardware generation"); 3006 } 3007 } 3008 3009 3010 3011 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 3012 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 3013 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 3014 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 3015 3016 static inline uint32_t ATTRIBUTE_PURE 3017 _3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start(const struct gen_device_info *devinfo) 3018 { 3019 switch (devinfo->gen) { 3020 case 10: return 27; 3021 case 9: return 27; 3022 case 8: return 27; 3023 case 7: 3024 if (devinfo->is_haswell) { 3025 return 27; 3026 } else { 3027 return 0; 3028 } 3029 case 6: return 0; 3030 case 5: return 0; 3031 case 4: 3032 if (devinfo->is_g4x) { 3033 return 0; 3034 } else { 3035 return 0; 3036 } 3037 default: 3038 unreachable("Invalid hardware generation"); 3039 } 3040 } 3041 3042 3043 3044 /* 3DSTATE_BINDING_TABLE_EDIT_DS::Command Type */ 3045 3046 3047 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 3048 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 3049 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 3050 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 3051 3052 static inline uint32_t ATTRIBUTE_PURE 3053 _3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits(const struct gen_device_info *devinfo) 3054 { 3055 switch (devinfo->gen) { 3056 case 10: return 3; 3057 case 9: return 3; 3058 case 8: return 3; 3059 case 7: 3060 if (devinfo->is_haswell) { 3061 return 3; 3062 } else { 3063 return 0; 3064 } 3065 case 6: return 0; 3066 case 5: return 0; 3067 case 4: 3068 if (devinfo->is_g4x) { 3069 return 0; 3070 } else { 3071 return 0; 3072 } 3073 default: 3074 unreachable("Invalid hardware generation"); 3075 } 3076 } 3077 3078 3079 3080 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 3081 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 3082 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 3083 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 3084 3085 static inline uint32_t ATTRIBUTE_PURE 3086 _3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start(const struct gen_device_info *devinfo) 3087 { 3088 switch (devinfo->gen) { 3089 case 10: return 29; 3090 case 9: return 29; 3091 case 8: return 29; 3092 case 7: 3093 if (devinfo->is_haswell) { 3094 return 29; 3095 } else { 3096 return 0; 3097 } 3098 case 6: return 0; 3099 case 5: return 0; 3100 case 4: 3101 if (devinfo->is_g4x) { 3102 return 0; 3103 } else { 3104 return 0; 3105 } 3106 default: 3107 unreachable("Invalid hardware generation"); 3108 } 3109 } 3110 3111 3112 3113 /* 3DSTATE_BINDING_TABLE_EDIT_DS::DWord Length */ 3114 3115 3116 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 3117 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 3118 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 3119 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 3120 3121 static inline uint32_t ATTRIBUTE_PURE 3122 _3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits(const struct gen_device_info *devinfo) 3123 { 3124 switch (devinfo->gen) { 3125 case 10: return 9; 3126 case 9: return 9; 3127 case 8: return 9; 3128 case 7: 3129 if (devinfo->is_haswell) { 3130 return 9; 3131 } else { 3132 return 0; 3133 } 3134 case 6: return 0; 3135 case 5: return 0; 3136 case 4: 3137 if (devinfo->is_g4x) { 3138 return 0; 3139 } else { 3140 return 0; 3141 } 3142 default: 3143 unreachable("Invalid hardware generation"); 3144 } 3145 } 3146 3147 3148 3149 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 3150 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 3151 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 3152 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 3153 3154 static inline uint32_t ATTRIBUTE_PURE 3155 _3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start(const struct gen_device_info *devinfo) 3156 { 3157 switch (devinfo->gen) { 3158 case 10: return 0; 3159 case 9: return 0; 3160 case 8: return 0; 3161 case 7: 3162 if (devinfo->is_haswell) { 3163 return 0; 3164 } else { 3165 return 0; 3166 } 3167 case 6: return 0; 3168 case 5: return 0; 3169 case 4: 3170 if (devinfo->is_g4x) { 3171 return 0; 3172 } else { 3173 return 0; 3174 } 3175 default: 3176 unreachable("Invalid hardware generation"); 3177 } 3178 } 3179 3180 3181 3182 /* 3DSTATE_BINDING_TABLE_EDIT_DS::Entry [n] */ 3183 3184 3185 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 3186 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 3187 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 3188 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 3189 3190 static inline uint32_t ATTRIBUTE_PURE 3191 _3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits(const struct gen_device_info *devinfo) 3192 { 3193 switch (devinfo->gen) { 3194 case 10: return 32; 3195 case 9: return 32; 3196 case 8: return 32; 3197 case 7: 3198 if (devinfo->is_haswell) { 3199 return 32; 3200 } else { 3201 return 0; 3202 } 3203 case 6: return 0; 3204 case 5: return 0; 3205 case 4: 3206 if (devinfo->is_g4x) { 3207 return 0; 3208 } else { 3209 return 0; 3210 } 3211 default: 3212 unreachable("Invalid hardware generation"); 3213 } 3214 } 3215 3216 3217 3218 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 3219 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 3220 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 3221 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 3222 3223 static inline uint32_t ATTRIBUTE_PURE 3224 _3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start(const struct gen_device_info *devinfo) 3225 { 3226 switch (devinfo->gen) { 3227 case 10: return 0; 3228 case 9: return 0; 3229 case 8: return 0; 3230 case 7: 3231 if (devinfo->is_haswell) { 3232 return 0; 3233 } else { 3234 return 0; 3235 } 3236 case 6: return 0; 3237 case 5: return 0; 3238 case 4: 3239 if (devinfo->is_g4x) { 3240 return 0; 3241 } else { 3242 return 0; 3243 } 3244 default: 3245 unreachable("Invalid hardware generation"); 3246 } 3247 } 3248 3249 3250 3251 /* 3DSTATE_BINDING_TABLE_EDIT_GS */ 3252 3253 3254 3255 3256 3257 /* 3DSTATE_BINDING_TABLE_EDIT_GS::3D Command Opcode */ 3258 3259 3260 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 3261 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 3262 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 3263 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 3264 3265 static inline uint32_t ATTRIBUTE_PURE 3266 _3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 3267 { 3268 switch (devinfo->gen) { 3269 case 10: return 3; 3270 case 9: return 3; 3271 case 8: return 3; 3272 case 7: 3273 if (devinfo->is_haswell) { 3274 return 3; 3275 } else { 3276 return 0; 3277 } 3278 case 6: return 0; 3279 case 5: return 0; 3280 case 4: 3281 if (devinfo->is_g4x) { 3282 return 0; 3283 } else { 3284 return 0; 3285 } 3286 default: 3287 unreachable("Invalid hardware generation"); 3288 } 3289 } 3290 3291 3292 3293 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 3294 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 3295 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 3296 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 3297 3298 static inline uint32_t ATTRIBUTE_PURE 3299 _3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 3300 { 3301 switch (devinfo->gen) { 3302 case 10: return 24; 3303 case 9: return 24; 3304 case 8: return 24; 3305 case 7: 3306 if (devinfo->is_haswell) { 3307 return 24; 3308 } else { 3309 return 0; 3310 } 3311 case 6: return 0; 3312 case 5: return 0; 3313 case 4: 3314 if (devinfo->is_g4x) { 3315 return 0; 3316 } else { 3317 return 0; 3318 } 3319 default: 3320 unreachable("Invalid hardware generation"); 3321 } 3322 } 3323 3324 3325 3326 /* 3DSTATE_BINDING_TABLE_EDIT_GS::3D Command Sub Opcode */ 3327 3328 3329 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 3330 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 3331 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 3332 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 3333 3334 static inline uint32_t ATTRIBUTE_PURE 3335 _3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 3336 { 3337 switch (devinfo->gen) { 3338 case 10: return 8; 3339 case 9: return 8; 3340 case 8: return 8; 3341 case 7: 3342 if (devinfo->is_haswell) { 3343 return 8; 3344 } else { 3345 return 0; 3346 } 3347 case 6: return 0; 3348 case 5: return 0; 3349 case 4: 3350 if (devinfo->is_g4x) { 3351 return 0; 3352 } else { 3353 return 0; 3354 } 3355 default: 3356 unreachable("Invalid hardware generation"); 3357 } 3358 } 3359 3360 3361 3362 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 3363 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 3364 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 3365 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 3366 3367 static inline uint32_t ATTRIBUTE_PURE 3368 _3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 3369 { 3370 switch (devinfo->gen) { 3371 case 10: return 16; 3372 case 9: return 16; 3373 case 8: return 16; 3374 case 7: 3375 if (devinfo->is_haswell) { 3376 return 16; 3377 } else { 3378 return 0; 3379 } 3380 case 6: return 0; 3381 case 5: return 0; 3382 case 4: 3383 if (devinfo->is_g4x) { 3384 return 0; 3385 } else { 3386 return 0; 3387 } 3388 default: 3389 unreachable("Invalid hardware generation"); 3390 } 3391 } 3392 3393 3394 3395 /* 3DSTATE_BINDING_TABLE_EDIT_GS::Binding Table Block Clear */ 3396 3397 3398 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 3399 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 3400 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 3401 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 3402 3403 static inline uint32_t ATTRIBUTE_PURE 3404 _3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) 3405 { 3406 switch (devinfo->gen) { 3407 case 10: return 16; 3408 case 9: return 16; 3409 case 8: return 16; 3410 case 7: 3411 if (devinfo->is_haswell) { 3412 return 16; 3413 } else { 3414 return 0; 3415 } 3416 case 6: return 0; 3417 case 5: return 0; 3418 case 4: 3419 if (devinfo->is_g4x) { 3420 return 0; 3421 } else { 3422 return 0; 3423 } 3424 default: 3425 unreachable("Invalid hardware generation"); 3426 } 3427 } 3428 3429 3430 3431 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 3432 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 3433 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 3434 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 3435 3436 static inline uint32_t ATTRIBUTE_PURE 3437 _3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) 3438 { 3439 switch (devinfo->gen) { 3440 case 10: return 48; 3441 case 9: return 48; 3442 case 8: return 48; 3443 case 7: 3444 if (devinfo->is_haswell) { 3445 return 48; 3446 } else { 3447 return 0; 3448 } 3449 case 6: return 0; 3450 case 5: return 0; 3451 case 4: 3452 if (devinfo->is_g4x) { 3453 return 0; 3454 } else { 3455 return 0; 3456 } 3457 default: 3458 unreachable("Invalid hardware generation"); 3459 } 3460 } 3461 3462 3463 3464 /* 3DSTATE_BINDING_TABLE_EDIT_GS::Binding Table Edit Target */ 3465 3466 3467 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 3468 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 3469 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 3470 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 3471 3472 static inline uint32_t ATTRIBUTE_PURE 3473 _3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) 3474 { 3475 switch (devinfo->gen) { 3476 case 10: return 2; 3477 case 9: return 2; 3478 case 8: return 2; 3479 case 7: 3480 if (devinfo->is_haswell) { 3481 return 2; 3482 } else { 3483 return 0; 3484 } 3485 case 6: return 0; 3486 case 5: return 0; 3487 case 4: 3488 if (devinfo->is_g4x) { 3489 return 0; 3490 } else { 3491 return 0; 3492 } 3493 default: 3494 unreachable("Invalid hardware generation"); 3495 } 3496 } 3497 3498 3499 3500 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 3501 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 3502 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 3503 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 3504 3505 static inline uint32_t ATTRIBUTE_PURE 3506 _3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) 3507 { 3508 switch (devinfo->gen) { 3509 case 10: return 32; 3510 case 9: return 32; 3511 case 8: return 32; 3512 case 7: 3513 if (devinfo->is_haswell) { 3514 return 32; 3515 } else { 3516 return 0; 3517 } 3518 case 6: return 0; 3519 case 5: return 0; 3520 case 4: 3521 if (devinfo->is_g4x) { 3522 return 0; 3523 } else { 3524 return 0; 3525 } 3526 default: 3527 unreachable("Invalid hardware generation"); 3528 } 3529 } 3530 3531 3532 3533 /* 3DSTATE_BINDING_TABLE_EDIT_GS::Command SubType */ 3534 3535 3536 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 3537 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 3538 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 3539 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 3540 3541 static inline uint32_t ATTRIBUTE_PURE 3542 _3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits(const struct gen_device_info *devinfo) 3543 { 3544 switch (devinfo->gen) { 3545 case 10: return 2; 3546 case 9: return 2; 3547 case 8: return 2; 3548 case 7: 3549 if (devinfo->is_haswell) { 3550 return 2; 3551 } else { 3552 return 0; 3553 } 3554 case 6: return 0; 3555 case 5: return 0; 3556 case 4: 3557 if (devinfo->is_g4x) { 3558 return 0; 3559 } else { 3560 return 0; 3561 } 3562 default: 3563 unreachable("Invalid hardware generation"); 3564 } 3565 } 3566 3567 3568 3569 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 3570 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 3571 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 3572 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 3573 3574 static inline uint32_t ATTRIBUTE_PURE 3575 _3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start(const struct gen_device_info *devinfo) 3576 { 3577 switch (devinfo->gen) { 3578 case 10: return 27; 3579 case 9: return 27; 3580 case 8: return 27; 3581 case 7: 3582 if (devinfo->is_haswell) { 3583 return 27; 3584 } else { 3585 return 0; 3586 } 3587 case 6: return 0; 3588 case 5: return 0; 3589 case 4: 3590 if (devinfo->is_g4x) { 3591 return 0; 3592 } else { 3593 return 0; 3594 } 3595 default: 3596 unreachable("Invalid hardware generation"); 3597 } 3598 } 3599 3600 3601 3602 /* 3DSTATE_BINDING_TABLE_EDIT_GS::Command Type */ 3603 3604 3605 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 3606 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 3607 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 3608 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 3609 3610 static inline uint32_t ATTRIBUTE_PURE 3611 _3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits(const struct gen_device_info *devinfo) 3612 { 3613 switch (devinfo->gen) { 3614 case 10: return 3; 3615 case 9: return 3; 3616 case 8: return 3; 3617 case 7: 3618 if (devinfo->is_haswell) { 3619 return 3; 3620 } else { 3621 return 0; 3622 } 3623 case 6: return 0; 3624 case 5: return 0; 3625 case 4: 3626 if (devinfo->is_g4x) { 3627 return 0; 3628 } else { 3629 return 0; 3630 } 3631 default: 3632 unreachable("Invalid hardware generation"); 3633 } 3634 } 3635 3636 3637 3638 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 3639 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 3640 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 3641 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 3642 3643 static inline uint32_t ATTRIBUTE_PURE 3644 _3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start(const struct gen_device_info *devinfo) 3645 { 3646 switch (devinfo->gen) { 3647 case 10: return 29; 3648 case 9: return 29; 3649 case 8: return 29; 3650 case 7: 3651 if (devinfo->is_haswell) { 3652 return 29; 3653 } else { 3654 return 0; 3655 } 3656 case 6: return 0; 3657 case 5: return 0; 3658 case 4: 3659 if (devinfo->is_g4x) { 3660 return 0; 3661 } else { 3662 return 0; 3663 } 3664 default: 3665 unreachable("Invalid hardware generation"); 3666 } 3667 } 3668 3669 3670 3671 /* 3DSTATE_BINDING_TABLE_EDIT_GS::DWord Length */ 3672 3673 3674 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 3675 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 3676 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 3677 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 3678 3679 static inline uint32_t ATTRIBUTE_PURE 3680 _3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits(const struct gen_device_info *devinfo) 3681 { 3682 switch (devinfo->gen) { 3683 case 10: return 9; 3684 case 9: return 9; 3685 case 8: return 9; 3686 case 7: 3687 if (devinfo->is_haswell) { 3688 return 9; 3689 } else { 3690 return 0; 3691 } 3692 case 6: return 0; 3693 case 5: return 0; 3694 case 4: 3695 if (devinfo->is_g4x) { 3696 return 0; 3697 } else { 3698 return 0; 3699 } 3700 default: 3701 unreachable("Invalid hardware generation"); 3702 } 3703 } 3704 3705 3706 3707 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 3708 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 3709 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 3710 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 3711 3712 static inline uint32_t ATTRIBUTE_PURE 3713 _3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start(const struct gen_device_info *devinfo) 3714 { 3715 switch (devinfo->gen) { 3716 case 10: return 0; 3717 case 9: return 0; 3718 case 8: return 0; 3719 case 7: 3720 if (devinfo->is_haswell) { 3721 return 0; 3722 } else { 3723 return 0; 3724 } 3725 case 6: return 0; 3726 case 5: return 0; 3727 case 4: 3728 if (devinfo->is_g4x) { 3729 return 0; 3730 } else { 3731 return 0; 3732 } 3733 default: 3734 unreachable("Invalid hardware generation"); 3735 } 3736 } 3737 3738 3739 3740 /* 3DSTATE_BINDING_TABLE_EDIT_GS::Entry [n] */ 3741 3742 3743 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 3744 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 3745 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 3746 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 3747 3748 static inline uint32_t ATTRIBUTE_PURE 3749 _3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits(const struct gen_device_info *devinfo) 3750 { 3751 switch (devinfo->gen) { 3752 case 10: return 32; 3753 case 9: return 32; 3754 case 8: return 32; 3755 case 7: 3756 if (devinfo->is_haswell) { 3757 return 32; 3758 } else { 3759 return 0; 3760 } 3761 case 6: return 0; 3762 case 5: return 0; 3763 case 4: 3764 if (devinfo->is_g4x) { 3765 return 0; 3766 } else { 3767 return 0; 3768 } 3769 default: 3770 unreachable("Invalid hardware generation"); 3771 } 3772 } 3773 3774 3775 3776 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 3777 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 3778 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 3779 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 3780 3781 static inline uint32_t ATTRIBUTE_PURE 3782 _3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start(const struct gen_device_info *devinfo) 3783 { 3784 switch (devinfo->gen) { 3785 case 10: return 0; 3786 case 9: return 0; 3787 case 8: return 0; 3788 case 7: 3789 if (devinfo->is_haswell) { 3790 return 0; 3791 } else { 3792 return 0; 3793 } 3794 case 6: return 0; 3795 case 5: return 0; 3796 case 4: 3797 if (devinfo->is_g4x) { 3798 return 0; 3799 } else { 3800 return 0; 3801 } 3802 default: 3803 unreachable("Invalid hardware generation"); 3804 } 3805 } 3806 3807 3808 3809 /* 3DSTATE_BINDING_TABLE_EDIT_HS */ 3810 3811 3812 3813 3814 3815 /* 3DSTATE_BINDING_TABLE_EDIT_HS::3D Command Opcode */ 3816 3817 3818 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 3819 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 3820 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 3821 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 3822 3823 static inline uint32_t ATTRIBUTE_PURE 3824 _3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 3825 { 3826 switch (devinfo->gen) { 3827 case 10: return 3; 3828 case 9: return 3; 3829 case 8: return 3; 3830 case 7: 3831 if (devinfo->is_haswell) { 3832 return 3; 3833 } else { 3834 return 0; 3835 } 3836 case 6: return 0; 3837 case 5: return 0; 3838 case 4: 3839 if (devinfo->is_g4x) { 3840 return 0; 3841 } else { 3842 return 0; 3843 } 3844 default: 3845 unreachable("Invalid hardware generation"); 3846 } 3847 } 3848 3849 3850 3851 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 3852 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 3853 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 3854 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 3855 3856 static inline uint32_t ATTRIBUTE_PURE 3857 _3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 3858 { 3859 switch (devinfo->gen) { 3860 case 10: return 24; 3861 case 9: return 24; 3862 case 8: return 24; 3863 case 7: 3864 if (devinfo->is_haswell) { 3865 return 24; 3866 } else { 3867 return 0; 3868 } 3869 case 6: return 0; 3870 case 5: return 0; 3871 case 4: 3872 if (devinfo->is_g4x) { 3873 return 0; 3874 } else { 3875 return 0; 3876 } 3877 default: 3878 unreachable("Invalid hardware generation"); 3879 } 3880 } 3881 3882 3883 3884 /* 3DSTATE_BINDING_TABLE_EDIT_HS::3D Command Sub Opcode */ 3885 3886 3887 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 3888 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 3889 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 3890 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 3891 3892 static inline uint32_t ATTRIBUTE_PURE 3893 _3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 3894 { 3895 switch (devinfo->gen) { 3896 case 10: return 8; 3897 case 9: return 8; 3898 case 8: return 8; 3899 case 7: 3900 if (devinfo->is_haswell) { 3901 return 8; 3902 } else { 3903 return 0; 3904 } 3905 case 6: return 0; 3906 case 5: return 0; 3907 case 4: 3908 if (devinfo->is_g4x) { 3909 return 0; 3910 } else { 3911 return 0; 3912 } 3913 default: 3914 unreachable("Invalid hardware generation"); 3915 } 3916 } 3917 3918 3919 3920 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 3921 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 3922 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 3923 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 3924 3925 static inline uint32_t ATTRIBUTE_PURE 3926 _3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 3927 { 3928 switch (devinfo->gen) { 3929 case 10: return 16; 3930 case 9: return 16; 3931 case 8: return 16; 3932 case 7: 3933 if (devinfo->is_haswell) { 3934 return 16; 3935 } else { 3936 return 0; 3937 } 3938 case 6: return 0; 3939 case 5: return 0; 3940 case 4: 3941 if (devinfo->is_g4x) { 3942 return 0; 3943 } else { 3944 return 0; 3945 } 3946 default: 3947 unreachable("Invalid hardware generation"); 3948 } 3949 } 3950 3951 3952 3953 /* 3DSTATE_BINDING_TABLE_EDIT_HS::Binding Table Block Clear */ 3954 3955 3956 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 3957 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 3958 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 3959 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 3960 3961 static inline uint32_t ATTRIBUTE_PURE 3962 _3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) 3963 { 3964 switch (devinfo->gen) { 3965 case 10: return 16; 3966 case 9: return 16; 3967 case 8: return 16; 3968 case 7: 3969 if (devinfo->is_haswell) { 3970 return 16; 3971 } else { 3972 return 0; 3973 } 3974 case 6: return 0; 3975 case 5: return 0; 3976 case 4: 3977 if (devinfo->is_g4x) { 3978 return 0; 3979 } else { 3980 return 0; 3981 } 3982 default: 3983 unreachable("Invalid hardware generation"); 3984 } 3985 } 3986 3987 3988 3989 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 3990 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 3991 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 3992 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 3993 3994 static inline uint32_t ATTRIBUTE_PURE 3995 _3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) 3996 { 3997 switch (devinfo->gen) { 3998 case 10: return 48; 3999 case 9: return 48; 4000 case 8: return 48; 4001 case 7: 4002 if (devinfo->is_haswell) { 4003 return 48; 4004 } else { 4005 return 0; 4006 } 4007 case 6: return 0; 4008 case 5: return 0; 4009 case 4: 4010 if (devinfo->is_g4x) { 4011 return 0; 4012 } else { 4013 return 0; 4014 } 4015 default: 4016 unreachable("Invalid hardware generation"); 4017 } 4018 } 4019 4020 4021 4022 /* 3DSTATE_BINDING_TABLE_EDIT_HS::Binding Table Edit Target */ 4023 4024 4025 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 4026 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 4027 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 4028 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 4029 4030 static inline uint32_t ATTRIBUTE_PURE 4031 _3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) 4032 { 4033 switch (devinfo->gen) { 4034 case 10: return 2; 4035 case 9: return 2; 4036 case 8: return 2; 4037 case 7: 4038 if (devinfo->is_haswell) { 4039 return 2; 4040 } else { 4041 return 0; 4042 } 4043 case 6: return 0; 4044 case 5: return 0; 4045 case 4: 4046 if (devinfo->is_g4x) { 4047 return 0; 4048 } else { 4049 return 0; 4050 } 4051 default: 4052 unreachable("Invalid hardware generation"); 4053 } 4054 } 4055 4056 4057 4058 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 4059 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 4060 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 4061 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 4062 4063 static inline uint32_t ATTRIBUTE_PURE 4064 _3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) 4065 { 4066 switch (devinfo->gen) { 4067 case 10: return 32; 4068 case 9: return 32; 4069 case 8: return 32; 4070 case 7: 4071 if (devinfo->is_haswell) { 4072 return 32; 4073 } else { 4074 return 0; 4075 } 4076 case 6: return 0; 4077 case 5: return 0; 4078 case 4: 4079 if (devinfo->is_g4x) { 4080 return 0; 4081 } else { 4082 return 0; 4083 } 4084 default: 4085 unreachable("Invalid hardware generation"); 4086 } 4087 } 4088 4089 4090 4091 /* 3DSTATE_BINDING_TABLE_EDIT_HS::Command SubType */ 4092 4093 4094 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 4095 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 4096 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 4097 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 4098 4099 static inline uint32_t ATTRIBUTE_PURE 4100 _3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits(const struct gen_device_info *devinfo) 4101 { 4102 switch (devinfo->gen) { 4103 case 10: return 2; 4104 case 9: return 2; 4105 case 8: return 2; 4106 case 7: 4107 if (devinfo->is_haswell) { 4108 return 2; 4109 } else { 4110 return 0; 4111 } 4112 case 6: return 0; 4113 case 5: return 0; 4114 case 4: 4115 if (devinfo->is_g4x) { 4116 return 0; 4117 } else { 4118 return 0; 4119 } 4120 default: 4121 unreachable("Invalid hardware generation"); 4122 } 4123 } 4124 4125 4126 4127 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 4128 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 4129 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 4130 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 4131 4132 static inline uint32_t ATTRIBUTE_PURE 4133 _3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start(const struct gen_device_info *devinfo) 4134 { 4135 switch (devinfo->gen) { 4136 case 10: return 27; 4137 case 9: return 27; 4138 case 8: return 27; 4139 case 7: 4140 if (devinfo->is_haswell) { 4141 return 27; 4142 } else { 4143 return 0; 4144 } 4145 case 6: return 0; 4146 case 5: return 0; 4147 case 4: 4148 if (devinfo->is_g4x) { 4149 return 0; 4150 } else { 4151 return 0; 4152 } 4153 default: 4154 unreachable("Invalid hardware generation"); 4155 } 4156 } 4157 4158 4159 4160 /* 3DSTATE_BINDING_TABLE_EDIT_HS::Command Type */ 4161 4162 4163 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 4164 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 4165 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 4166 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 4167 4168 static inline uint32_t ATTRIBUTE_PURE 4169 _3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits(const struct gen_device_info *devinfo) 4170 { 4171 switch (devinfo->gen) { 4172 case 10: return 3; 4173 case 9: return 3; 4174 case 8: return 3; 4175 case 7: 4176 if (devinfo->is_haswell) { 4177 return 3; 4178 } else { 4179 return 0; 4180 } 4181 case 6: return 0; 4182 case 5: return 0; 4183 case 4: 4184 if (devinfo->is_g4x) { 4185 return 0; 4186 } else { 4187 return 0; 4188 } 4189 default: 4190 unreachable("Invalid hardware generation"); 4191 } 4192 } 4193 4194 4195 4196 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 4197 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 4198 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 4199 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 4200 4201 static inline uint32_t ATTRIBUTE_PURE 4202 _3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start(const struct gen_device_info *devinfo) 4203 { 4204 switch (devinfo->gen) { 4205 case 10: return 29; 4206 case 9: return 29; 4207 case 8: return 29; 4208 case 7: 4209 if (devinfo->is_haswell) { 4210 return 29; 4211 } else { 4212 return 0; 4213 } 4214 case 6: return 0; 4215 case 5: return 0; 4216 case 4: 4217 if (devinfo->is_g4x) { 4218 return 0; 4219 } else { 4220 return 0; 4221 } 4222 default: 4223 unreachable("Invalid hardware generation"); 4224 } 4225 } 4226 4227 4228 4229 /* 3DSTATE_BINDING_TABLE_EDIT_HS::DWord Length */ 4230 4231 4232 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 4233 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 4234 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 4235 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 4236 4237 static inline uint32_t ATTRIBUTE_PURE 4238 _3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits(const struct gen_device_info *devinfo) 4239 { 4240 switch (devinfo->gen) { 4241 case 10: return 9; 4242 case 9: return 9; 4243 case 8: return 9; 4244 case 7: 4245 if (devinfo->is_haswell) { 4246 return 9; 4247 } else { 4248 return 0; 4249 } 4250 case 6: return 0; 4251 case 5: return 0; 4252 case 4: 4253 if (devinfo->is_g4x) { 4254 return 0; 4255 } else { 4256 return 0; 4257 } 4258 default: 4259 unreachable("Invalid hardware generation"); 4260 } 4261 } 4262 4263 4264 4265 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 4266 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 4267 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 4268 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 4269 4270 static inline uint32_t ATTRIBUTE_PURE 4271 _3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start(const struct gen_device_info *devinfo) 4272 { 4273 switch (devinfo->gen) { 4274 case 10: return 0; 4275 case 9: return 0; 4276 case 8: return 0; 4277 case 7: 4278 if (devinfo->is_haswell) { 4279 return 0; 4280 } else { 4281 return 0; 4282 } 4283 case 6: return 0; 4284 case 5: return 0; 4285 case 4: 4286 if (devinfo->is_g4x) { 4287 return 0; 4288 } else { 4289 return 0; 4290 } 4291 default: 4292 unreachable("Invalid hardware generation"); 4293 } 4294 } 4295 4296 4297 4298 /* 3DSTATE_BINDING_TABLE_EDIT_HS::Entry [n] */ 4299 4300 4301 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 4302 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 4303 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 4304 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 4305 4306 static inline uint32_t ATTRIBUTE_PURE 4307 _3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits(const struct gen_device_info *devinfo) 4308 { 4309 switch (devinfo->gen) { 4310 case 10: return 32; 4311 case 9: return 32; 4312 case 8: return 32; 4313 case 7: 4314 if (devinfo->is_haswell) { 4315 return 32; 4316 } else { 4317 return 0; 4318 } 4319 case 6: return 0; 4320 case 5: return 0; 4321 case 4: 4322 if (devinfo->is_g4x) { 4323 return 0; 4324 } else { 4325 return 0; 4326 } 4327 default: 4328 unreachable("Invalid hardware generation"); 4329 } 4330 } 4331 4332 4333 4334 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 4335 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 4336 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 4337 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 4338 4339 static inline uint32_t ATTRIBUTE_PURE 4340 _3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start(const struct gen_device_info *devinfo) 4341 { 4342 switch (devinfo->gen) { 4343 case 10: return 0; 4344 case 9: return 0; 4345 case 8: return 0; 4346 case 7: 4347 if (devinfo->is_haswell) { 4348 return 0; 4349 } else { 4350 return 0; 4351 } 4352 case 6: return 0; 4353 case 5: return 0; 4354 case 4: 4355 if (devinfo->is_g4x) { 4356 return 0; 4357 } else { 4358 return 0; 4359 } 4360 default: 4361 unreachable("Invalid hardware generation"); 4362 } 4363 } 4364 4365 4366 4367 /* 3DSTATE_BINDING_TABLE_EDIT_PS */ 4368 4369 4370 4371 4372 4373 /* 3DSTATE_BINDING_TABLE_EDIT_PS::3D Command Opcode */ 4374 4375 4376 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 4377 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 4378 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 4379 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 4380 4381 static inline uint32_t ATTRIBUTE_PURE 4382 _3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 4383 { 4384 switch (devinfo->gen) { 4385 case 10: return 3; 4386 case 9: return 3; 4387 case 8: return 3; 4388 case 7: 4389 if (devinfo->is_haswell) { 4390 return 3; 4391 } else { 4392 return 0; 4393 } 4394 case 6: return 0; 4395 case 5: return 0; 4396 case 4: 4397 if (devinfo->is_g4x) { 4398 return 0; 4399 } else { 4400 return 0; 4401 } 4402 default: 4403 unreachable("Invalid hardware generation"); 4404 } 4405 } 4406 4407 4408 4409 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 4410 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 4411 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 4412 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 4413 4414 static inline uint32_t ATTRIBUTE_PURE 4415 _3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 4416 { 4417 switch (devinfo->gen) { 4418 case 10: return 24; 4419 case 9: return 24; 4420 case 8: return 24; 4421 case 7: 4422 if (devinfo->is_haswell) { 4423 return 24; 4424 } else { 4425 return 0; 4426 } 4427 case 6: return 0; 4428 case 5: return 0; 4429 case 4: 4430 if (devinfo->is_g4x) { 4431 return 0; 4432 } else { 4433 return 0; 4434 } 4435 default: 4436 unreachable("Invalid hardware generation"); 4437 } 4438 } 4439 4440 4441 4442 /* 3DSTATE_BINDING_TABLE_EDIT_PS::3D Command Sub Opcode */ 4443 4444 4445 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 4446 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 4447 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 4448 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 4449 4450 static inline uint32_t ATTRIBUTE_PURE 4451 _3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 4452 { 4453 switch (devinfo->gen) { 4454 case 10: return 8; 4455 case 9: return 8; 4456 case 8: return 8; 4457 case 7: 4458 if (devinfo->is_haswell) { 4459 return 8; 4460 } else { 4461 return 0; 4462 } 4463 case 6: return 0; 4464 case 5: return 0; 4465 case 4: 4466 if (devinfo->is_g4x) { 4467 return 0; 4468 } else { 4469 return 0; 4470 } 4471 default: 4472 unreachable("Invalid hardware generation"); 4473 } 4474 } 4475 4476 4477 4478 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 4479 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 4480 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 4481 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 4482 4483 static inline uint32_t ATTRIBUTE_PURE 4484 _3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 4485 { 4486 switch (devinfo->gen) { 4487 case 10: return 16; 4488 case 9: return 16; 4489 case 8: return 16; 4490 case 7: 4491 if (devinfo->is_haswell) { 4492 return 16; 4493 } else { 4494 return 0; 4495 } 4496 case 6: return 0; 4497 case 5: return 0; 4498 case 4: 4499 if (devinfo->is_g4x) { 4500 return 0; 4501 } else { 4502 return 0; 4503 } 4504 default: 4505 unreachable("Invalid hardware generation"); 4506 } 4507 } 4508 4509 4510 4511 /* 3DSTATE_BINDING_TABLE_EDIT_PS::Binding Table Block Clear */ 4512 4513 4514 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 4515 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 4516 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 4517 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 4518 4519 static inline uint32_t ATTRIBUTE_PURE 4520 _3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) 4521 { 4522 switch (devinfo->gen) { 4523 case 10: return 16; 4524 case 9: return 16; 4525 case 8: return 16; 4526 case 7: 4527 if (devinfo->is_haswell) { 4528 return 16; 4529 } else { 4530 return 0; 4531 } 4532 case 6: return 0; 4533 case 5: return 0; 4534 case 4: 4535 if (devinfo->is_g4x) { 4536 return 0; 4537 } else { 4538 return 0; 4539 } 4540 default: 4541 unreachable("Invalid hardware generation"); 4542 } 4543 } 4544 4545 4546 4547 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 4548 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 4549 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 4550 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 4551 4552 static inline uint32_t ATTRIBUTE_PURE 4553 _3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) 4554 { 4555 switch (devinfo->gen) { 4556 case 10: return 48; 4557 case 9: return 48; 4558 case 8: return 48; 4559 case 7: 4560 if (devinfo->is_haswell) { 4561 return 48; 4562 } else { 4563 return 0; 4564 } 4565 case 6: return 0; 4566 case 5: return 0; 4567 case 4: 4568 if (devinfo->is_g4x) { 4569 return 0; 4570 } else { 4571 return 0; 4572 } 4573 default: 4574 unreachable("Invalid hardware generation"); 4575 } 4576 } 4577 4578 4579 4580 /* 3DSTATE_BINDING_TABLE_EDIT_PS::Binding Table Edit Target */ 4581 4582 4583 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 4584 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 4585 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 4586 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 4587 4588 static inline uint32_t ATTRIBUTE_PURE 4589 _3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) 4590 { 4591 switch (devinfo->gen) { 4592 case 10: return 2; 4593 case 9: return 2; 4594 case 8: return 2; 4595 case 7: 4596 if (devinfo->is_haswell) { 4597 return 2; 4598 } else { 4599 return 0; 4600 } 4601 case 6: return 0; 4602 case 5: return 0; 4603 case 4: 4604 if (devinfo->is_g4x) { 4605 return 0; 4606 } else { 4607 return 0; 4608 } 4609 default: 4610 unreachable("Invalid hardware generation"); 4611 } 4612 } 4613 4614 4615 4616 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 4617 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 4618 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 4619 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 4620 4621 static inline uint32_t ATTRIBUTE_PURE 4622 _3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) 4623 { 4624 switch (devinfo->gen) { 4625 case 10: return 32; 4626 case 9: return 32; 4627 case 8: return 32; 4628 case 7: 4629 if (devinfo->is_haswell) { 4630 return 32; 4631 } else { 4632 return 0; 4633 } 4634 case 6: return 0; 4635 case 5: return 0; 4636 case 4: 4637 if (devinfo->is_g4x) { 4638 return 0; 4639 } else { 4640 return 0; 4641 } 4642 default: 4643 unreachable("Invalid hardware generation"); 4644 } 4645 } 4646 4647 4648 4649 /* 3DSTATE_BINDING_TABLE_EDIT_PS::Command SubType */ 4650 4651 4652 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 4653 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 4654 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 4655 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 4656 4657 static inline uint32_t ATTRIBUTE_PURE 4658 _3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits(const struct gen_device_info *devinfo) 4659 { 4660 switch (devinfo->gen) { 4661 case 10: return 2; 4662 case 9: return 2; 4663 case 8: return 2; 4664 case 7: 4665 if (devinfo->is_haswell) { 4666 return 2; 4667 } else { 4668 return 0; 4669 } 4670 case 6: return 0; 4671 case 5: return 0; 4672 case 4: 4673 if (devinfo->is_g4x) { 4674 return 0; 4675 } else { 4676 return 0; 4677 } 4678 default: 4679 unreachable("Invalid hardware generation"); 4680 } 4681 } 4682 4683 4684 4685 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 4686 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 4687 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 4688 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 4689 4690 static inline uint32_t ATTRIBUTE_PURE 4691 _3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start(const struct gen_device_info *devinfo) 4692 { 4693 switch (devinfo->gen) { 4694 case 10: return 27; 4695 case 9: return 27; 4696 case 8: return 27; 4697 case 7: 4698 if (devinfo->is_haswell) { 4699 return 27; 4700 } else { 4701 return 0; 4702 } 4703 case 6: return 0; 4704 case 5: return 0; 4705 case 4: 4706 if (devinfo->is_g4x) { 4707 return 0; 4708 } else { 4709 return 0; 4710 } 4711 default: 4712 unreachable("Invalid hardware generation"); 4713 } 4714 } 4715 4716 4717 4718 /* 3DSTATE_BINDING_TABLE_EDIT_PS::Command Type */ 4719 4720 4721 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 4722 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 4723 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 4724 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 4725 4726 static inline uint32_t ATTRIBUTE_PURE 4727 _3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits(const struct gen_device_info *devinfo) 4728 { 4729 switch (devinfo->gen) { 4730 case 10: return 3; 4731 case 9: return 3; 4732 case 8: return 3; 4733 case 7: 4734 if (devinfo->is_haswell) { 4735 return 3; 4736 } else { 4737 return 0; 4738 } 4739 case 6: return 0; 4740 case 5: return 0; 4741 case 4: 4742 if (devinfo->is_g4x) { 4743 return 0; 4744 } else { 4745 return 0; 4746 } 4747 default: 4748 unreachable("Invalid hardware generation"); 4749 } 4750 } 4751 4752 4753 4754 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 4755 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 4756 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 4757 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 4758 4759 static inline uint32_t ATTRIBUTE_PURE 4760 _3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start(const struct gen_device_info *devinfo) 4761 { 4762 switch (devinfo->gen) { 4763 case 10: return 29; 4764 case 9: return 29; 4765 case 8: return 29; 4766 case 7: 4767 if (devinfo->is_haswell) { 4768 return 29; 4769 } else { 4770 return 0; 4771 } 4772 case 6: return 0; 4773 case 5: return 0; 4774 case 4: 4775 if (devinfo->is_g4x) { 4776 return 0; 4777 } else { 4778 return 0; 4779 } 4780 default: 4781 unreachable("Invalid hardware generation"); 4782 } 4783 } 4784 4785 4786 4787 /* 3DSTATE_BINDING_TABLE_EDIT_PS::DWord Length */ 4788 4789 4790 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 4791 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 4792 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 4793 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 4794 4795 static inline uint32_t ATTRIBUTE_PURE 4796 _3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits(const struct gen_device_info *devinfo) 4797 { 4798 switch (devinfo->gen) { 4799 case 10: return 9; 4800 case 9: return 9; 4801 case 8: return 9; 4802 case 7: 4803 if (devinfo->is_haswell) { 4804 return 9; 4805 } else { 4806 return 0; 4807 } 4808 case 6: return 0; 4809 case 5: return 0; 4810 case 4: 4811 if (devinfo->is_g4x) { 4812 return 0; 4813 } else { 4814 return 0; 4815 } 4816 default: 4817 unreachable("Invalid hardware generation"); 4818 } 4819 } 4820 4821 4822 4823 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 4824 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 4825 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 4826 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 4827 4828 static inline uint32_t ATTRIBUTE_PURE 4829 _3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start(const struct gen_device_info *devinfo) 4830 { 4831 switch (devinfo->gen) { 4832 case 10: return 0; 4833 case 9: return 0; 4834 case 8: return 0; 4835 case 7: 4836 if (devinfo->is_haswell) { 4837 return 0; 4838 } else { 4839 return 0; 4840 } 4841 case 6: return 0; 4842 case 5: return 0; 4843 case 4: 4844 if (devinfo->is_g4x) { 4845 return 0; 4846 } else { 4847 return 0; 4848 } 4849 default: 4850 unreachable("Invalid hardware generation"); 4851 } 4852 } 4853 4854 4855 4856 /* 3DSTATE_BINDING_TABLE_EDIT_PS::Entry [n] */ 4857 4858 4859 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 4860 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 4861 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 4862 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 4863 4864 static inline uint32_t ATTRIBUTE_PURE 4865 _3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits(const struct gen_device_info *devinfo) 4866 { 4867 switch (devinfo->gen) { 4868 case 10: return 32; 4869 case 9: return 32; 4870 case 8: return 32; 4871 case 7: 4872 if (devinfo->is_haswell) { 4873 return 32; 4874 } else { 4875 return 0; 4876 } 4877 case 6: return 0; 4878 case 5: return 0; 4879 case 4: 4880 if (devinfo->is_g4x) { 4881 return 0; 4882 } else { 4883 return 0; 4884 } 4885 default: 4886 unreachable("Invalid hardware generation"); 4887 } 4888 } 4889 4890 4891 4892 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 4893 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 4894 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 4895 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 4896 4897 static inline uint32_t ATTRIBUTE_PURE 4898 _3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start(const struct gen_device_info *devinfo) 4899 { 4900 switch (devinfo->gen) { 4901 case 10: return 0; 4902 case 9: return 0; 4903 case 8: return 0; 4904 case 7: 4905 if (devinfo->is_haswell) { 4906 return 0; 4907 } else { 4908 return 0; 4909 } 4910 case 6: return 0; 4911 case 5: return 0; 4912 case 4: 4913 if (devinfo->is_g4x) { 4914 return 0; 4915 } else { 4916 return 0; 4917 } 4918 default: 4919 unreachable("Invalid hardware generation"); 4920 } 4921 } 4922 4923 4924 4925 /* 3DSTATE_BINDING_TABLE_EDIT_VS */ 4926 4927 4928 4929 4930 4931 /* 3DSTATE_BINDING_TABLE_EDIT_VS::3D Command Opcode */ 4932 4933 4934 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 4935 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 4936 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 4937 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 4938 4939 static inline uint32_t ATTRIBUTE_PURE 4940 _3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 4941 { 4942 switch (devinfo->gen) { 4943 case 10: return 3; 4944 case 9: return 3; 4945 case 8: return 3; 4946 case 7: 4947 if (devinfo->is_haswell) { 4948 return 3; 4949 } else { 4950 return 0; 4951 } 4952 case 6: return 0; 4953 case 5: return 0; 4954 case 4: 4955 if (devinfo->is_g4x) { 4956 return 0; 4957 } else { 4958 return 0; 4959 } 4960 default: 4961 unreachable("Invalid hardware generation"); 4962 } 4963 } 4964 4965 4966 4967 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 4968 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 4969 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 4970 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 4971 4972 static inline uint32_t ATTRIBUTE_PURE 4973 _3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 4974 { 4975 switch (devinfo->gen) { 4976 case 10: return 24; 4977 case 9: return 24; 4978 case 8: return 24; 4979 case 7: 4980 if (devinfo->is_haswell) { 4981 return 24; 4982 } else { 4983 return 0; 4984 } 4985 case 6: return 0; 4986 case 5: return 0; 4987 case 4: 4988 if (devinfo->is_g4x) { 4989 return 0; 4990 } else { 4991 return 0; 4992 } 4993 default: 4994 unreachable("Invalid hardware generation"); 4995 } 4996 } 4997 4998 4999 5000 /* 3DSTATE_BINDING_TABLE_EDIT_VS::3D Command Sub Opcode */ 5001 5002 5003 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 5004 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 5005 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 5006 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 5007 5008 static inline uint32_t ATTRIBUTE_PURE 5009 _3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 5010 { 5011 switch (devinfo->gen) { 5012 case 10: return 8; 5013 case 9: return 8; 5014 case 8: return 8; 5015 case 7: 5016 if (devinfo->is_haswell) { 5017 return 8; 5018 } else { 5019 return 0; 5020 } 5021 case 6: return 0; 5022 case 5: return 0; 5023 case 4: 5024 if (devinfo->is_g4x) { 5025 return 0; 5026 } else { 5027 return 0; 5028 } 5029 default: 5030 unreachable("Invalid hardware generation"); 5031 } 5032 } 5033 5034 5035 5036 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 5037 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 5038 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 5039 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 5040 5041 static inline uint32_t ATTRIBUTE_PURE 5042 _3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 5043 { 5044 switch (devinfo->gen) { 5045 case 10: return 16; 5046 case 9: return 16; 5047 case 8: return 16; 5048 case 7: 5049 if (devinfo->is_haswell) { 5050 return 16; 5051 } else { 5052 return 0; 5053 } 5054 case 6: return 0; 5055 case 5: return 0; 5056 case 4: 5057 if (devinfo->is_g4x) { 5058 return 0; 5059 } else { 5060 return 0; 5061 } 5062 default: 5063 unreachable("Invalid hardware generation"); 5064 } 5065 } 5066 5067 5068 5069 /* 3DSTATE_BINDING_TABLE_EDIT_VS::Binding Table Block Clear */ 5070 5071 5072 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 5073 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 5074 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 5075 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 5076 5077 static inline uint32_t ATTRIBUTE_PURE 5078 _3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) 5079 { 5080 switch (devinfo->gen) { 5081 case 10: return 16; 5082 case 9: return 16; 5083 case 8: return 16; 5084 case 7: 5085 if (devinfo->is_haswell) { 5086 return 16; 5087 } else { 5088 return 0; 5089 } 5090 case 6: return 0; 5091 case 5: return 0; 5092 case 4: 5093 if (devinfo->is_g4x) { 5094 return 0; 5095 } else { 5096 return 0; 5097 } 5098 default: 5099 unreachable("Invalid hardware generation"); 5100 } 5101 } 5102 5103 5104 5105 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 5106 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 5107 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 5108 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 5109 5110 static inline uint32_t ATTRIBUTE_PURE 5111 _3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) 5112 { 5113 switch (devinfo->gen) { 5114 case 10: return 48; 5115 case 9: return 48; 5116 case 8: return 48; 5117 case 7: 5118 if (devinfo->is_haswell) { 5119 return 48; 5120 } else { 5121 return 0; 5122 } 5123 case 6: return 0; 5124 case 5: return 0; 5125 case 4: 5126 if (devinfo->is_g4x) { 5127 return 0; 5128 } else { 5129 return 0; 5130 } 5131 default: 5132 unreachable("Invalid hardware generation"); 5133 } 5134 } 5135 5136 5137 5138 /* 3DSTATE_BINDING_TABLE_EDIT_VS::Binding Table Edit Target */ 5139 5140 5141 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 5142 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 5143 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 5144 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 5145 5146 static inline uint32_t ATTRIBUTE_PURE 5147 _3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) 5148 { 5149 switch (devinfo->gen) { 5150 case 10: return 2; 5151 case 9: return 2; 5152 case 8: return 2; 5153 case 7: 5154 if (devinfo->is_haswell) { 5155 return 2; 5156 } else { 5157 return 0; 5158 } 5159 case 6: return 0; 5160 case 5: return 0; 5161 case 4: 5162 if (devinfo->is_g4x) { 5163 return 0; 5164 } else { 5165 return 0; 5166 } 5167 default: 5168 unreachable("Invalid hardware generation"); 5169 } 5170 } 5171 5172 5173 5174 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 5175 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 5176 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 5177 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 5178 5179 static inline uint32_t ATTRIBUTE_PURE 5180 _3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) 5181 { 5182 switch (devinfo->gen) { 5183 case 10: return 32; 5184 case 9: return 32; 5185 case 8: return 32; 5186 case 7: 5187 if (devinfo->is_haswell) { 5188 return 32; 5189 } else { 5190 return 0; 5191 } 5192 case 6: return 0; 5193 case 5: return 0; 5194 case 4: 5195 if (devinfo->is_g4x) { 5196 return 0; 5197 } else { 5198 return 0; 5199 } 5200 default: 5201 unreachable("Invalid hardware generation"); 5202 } 5203 } 5204 5205 5206 5207 /* 3DSTATE_BINDING_TABLE_EDIT_VS::Command SubType */ 5208 5209 5210 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 5211 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 5212 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 5213 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 5214 5215 static inline uint32_t ATTRIBUTE_PURE 5216 _3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits(const struct gen_device_info *devinfo) 5217 { 5218 switch (devinfo->gen) { 5219 case 10: return 2; 5220 case 9: return 2; 5221 case 8: return 2; 5222 case 7: 5223 if (devinfo->is_haswell) { 5224 return 2; 5225 } else { 5226 return 0; 5227 } 5228 case 6: return 0; 5229 case 5: return 0; 5230 case 4: 5231 if (devinfo->is_g4x) { 5232 return 0; 5233 } else { 5234 return 0; 5235 } 5236 default: 5237 unreachable("Invalid hardware generation"); 5238 } 5239 } 5240 5241 5242 5243 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 5244 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 5245 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 5246 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 5247 5248 static inline uint32_t ATTRIBUTE_PURE 5249 _3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start(const struct gen_device_info *devinfo) 5250 { 5251 switch (devinfo->gen) { 5252 case 10: return 27; 5253 case 9: return 27; 5254 case 8: return 27; 5255 case 7: 5256 if (devinfo->is_haswell) { 5257 return 27; 5258 } else { 5259 return 0; 5260 } 5261 case 6: return 0; 5262 case 5: return 0; 5263 case 4: 5264 if (devinfo->is_g4x) { 5265 return 0; 5266 } else { 5267 return 0; 5268 } 5269 default: 5270 unreachable("Invalid hardware generation"); 5271 } 5272 } 5273 5274 5275 5276 /* 3DSTATE_BINDING_TABLE_EDIT_VS::Command Type */ 5277 5278 5279 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 5280 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 5281 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 5282 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 5283 5284 static inline uint32_t ATTRIBUTE_PURE 5285 _3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits(const struct gen_device_info *devinfo) 5286 { 5287 switch (devinfo->gen) { 5288 case 10: return 3; 5289 case 9: return 3; 5290 case 8: return 3; 5291 case 7: 5292 if (devinfo->is_haswell) { 5293 return 3; 5294 } else { 5295 return 0; 5296 } 5297 case 6: return 0; 5298 case 5: return 0; 5299 case 4: 5300 if (devinfo->is_g4x) { 5301 return 0; 5302 } else { 5303 return 0; 5304 } 5305 default: 5306 unreachable("Invalid hardware generation"); 5307 } 5308 } 5309 5310 5311 5312 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 5313 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 5314 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 5315 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 5316 5317 static inline uint32_t ATTRIBUTE_PURE 5318 _3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start(const struct gen_device_info *devinfo) 5319 { 5320 switch (devinfo->gen) { 5321 case 10: return 29; 5322 case 9: return 29; 5323 case 8: return 29; 5324 case 7: 5325 if (devinfo->is_haswell) { 5326 return 29; 5327 } else { 5328 return 0; 5329 } 5330 case 6: return 0; 5331 case 5: return 0; 5332 case 4: 5333 if (devinfo->is_g4x) { 5334 return 0; 5335 } else { 5336 return 0; 5337 } 5338 default: 5339 unreachable("Invalid hardware generation"); 5340 } 5341 } 5342 5343 5344 5345 /* 3DSTATE_BINDING_TABLE_EDIT_VS::DWord Length */ 5346 5347 5348 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 5349 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 5350 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 5351 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 5352 5353 static inline uint32_t ATTRIBUTE_PURE 5354 _3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits(const struct gen_device_info *devinfo) 5355 { 5356 switch (devinfo->gen) { 5357 case 10: return 9; 5358 case 9: return 9; 5359 case 8: return 9; 5360 case 7: 5361 if (devinfo->is_haswell) { 5362 return 9; 5363 } else { 5364 return 0; 5365 } 5366 case 6: return 0; 5367 case 5: return 0; 5368 case 4: 5369 if (devinfo->is_g4x) { 5370 return 0; 5371 } else { 5372 return 0; 5373 } 5374 default: 5375 unreachable("Invalid hardware generation"); 5376 } 5377 } 5378 5379 5380 5381 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 5382 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 5383 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 5384 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 5385 5386 static inline uint32_t ATTRIBUTE_PURE 5387 _3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start(const struct gen_device_info *devinfo) 5388 { 5389 switch (devinfo->gen) { 5390 case 10: return 0; 5391 case 9: return 0; 5392 case 8: return 0; 5393 case 7: 5394 if (devinfo->is_haswell) { 5395 return 0; 5396 } else { 5397 return 0; 5398 } 5399 case 6: return 0; 5400 case 5: return 0; 5401 case 4: 5402 if (devinfo->is_g4x) { 5403 return 0; 5404 } else { 5405 return 0; 5406 } 5407 default: 5408 unreachable("Invalid hardware generation"); 5409 } 5410 } 5411 5412 5413 5414 /* 3DSTATE_BINDING_TABLE_EDIT_VS::Entry [n] */ 5415 5416 5417 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 5418 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 5419 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 5420 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 5421 5422 static inline uint32_t ATTRIBUTE_PURE 5423 _3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits(const struct gen_device_info *devinfo) 5424 { 5425 switch (devinfo->gen) { 5426 case 10: return 32; 5427 case 9: return 32; 5428 case 8: return 32; 5429 case 7: 5430 if (devinfo->is_haswell) { 5431 return 32; 5432 } else { 5433 return 0; 5434 } 5435 case 6: return 0; 5436 case 5: return 0; 5437 case 4: 5438 if (devinfo->is_g4x) { 5439 return 0; 5440 } else { 5441 return 0; 5442 } 5443 default: 5444 unreachable("Invalid hardware generation"); 5445 } 5446 } 5447 5448 5449 5450 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 5451 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 5452 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 5453 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 5454 5455 static inline uint32_t ATTRIBUTE_PURE 5456 _3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start(const struct gen_device_info *devinfo) 5457 { 5458 switch (devinfo->gen) { 5459 case 10: return 0; 5460 case 9: return 0; 5461 case 8: return 0; 5462 case 7: 5463 if (devinfo->is_haswell) { 5464 return 0; 5465 } else { 5466 return 0; 5467 } 5468 case 6: return 0; 5469 case 5: return 0; 5470 case 4: 5471 if (devinfo->is_g4x) { 5472 return 0; 5473 } else { 5474 return 0; 5475 } 5476 default: 5477 unreachable("Invalid hardware generation"); 5478 } 5479 } 5480 5481 5482 5483 /* 3DSTATE_BINDING_TABLE_POINTERS */ 5484 5485 5486 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_length 4 5487 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_length 6 5488 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_length 6 5489 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_length 6 5490 5491 static inline uint32_t ATTRIBUTE_PURE 5492 _3DSTATE_BINDING_TABLE_POINTERS_length(const struct gen_device_info *devinfo) 5493 { 5494 switch (devinfo->gen) { 5495 case 10: return 0; 5496 case 9: return 0; 5497 case 8: return 0; 5498 case 7: 5499 if (devinfo->is_haswell) { 5500 return 0; 5501 } else { 5502 return 0; 5503 } 5504 case 6: return 4; 5505 case 5: return 6; 5506 case 4: 5507 if (devinfo->is_g4x) { 5508 return 6; 5509 } else { 5510 return 6; 5511 } 5512 default: 5513 unreachable("Invalid hardware generation"); 5514 } 5515 } 5516 5517 5518 5519 /* 3DSTATE_BINDING_TABLE_POINTERS::3D Command Opcode */ 5520 5521 5522 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 5523 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 5524 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 5525 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 5526 5527 static inline uint32_t ATTRIBUTE_PURE 5528 _3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 5529 { 5530 switch (devinfo->gen) { 5531 case 10: return 0; 5532 case 9: return 0; 5533 case 8: return 0; 5534 case 7: 5535 if (devinfo->is_haswell) { 5536 return 0; 5537 } else { 5538 return 0; 5539 } 5540 case 6: return 3; 5541 case 5: return 3; 5542 case 4: 5543 if (devinfo->is_g4x) { 5544 return 3; 5545 } else { 5546 return 3; 5547 } 5548 default: 5549 unreachable("Invalid hardware generation"); 5550 } 5551 } 5552 5553 5554 5555 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 5556 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 5557 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 5558 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 5559 5560 static inline uint32_t ATTRIBUTE_PURE 5561 _3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 5562 { 5563 switch (devinfo->gen) { 5564 case 10: return 0; 5565 case 9: return 0; 5566 case 8: return 0; 5567 case 7: 5568 if (devinfo->is_haswell) { 5569 return 0; 5570 } else { 5571 return 0; 5572 } 5573 case 6: return 24; 5574 case 5: return 24; 5575 case 4: 5576 if (devinfo->is_g4x) { 5577 return 24; 5578 } else { 5579 return 24; 5580 } 5581 default: 5582 unreachable("Invalid hardware generation"); 5583 } 5584 } 5585 5586 5587 5588 /* 3DSTATE_BINDING_TABLE_POINTERS::3D Command Sub Opcode */ 5589 5590 5591 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 5592 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 5593 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 5594 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 5595 5596 static inline uint32_t ATTRIBUTE_PURE 5597 _3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 5598 { 5599 switch (devinfo->gen) { 5600 case 10: return 0; 5601 case 9: return 0; 5602 case 8: return 0; 5603 case 7: 5604 if (devinfo->is_haswell) { 5605 return 0; 5606 } else { 5607 return 0; 5608 } 5609 case 6: return 8; 5610 case 5: return 8; 5611 case 4: 5612 if (devinfo->is_g4x) { 5613 return 8; 5614 } else { 5615 return 8; 5616 } 5617 default: 5618 unreachable("Invalid hardware generation"); 5619 } 5620 } 5621 5622 5623 5624 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 5625 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 5626 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 5627 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 5628 5629 static inline uint32_t ATTRIBUTE_PURE 5630 _3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 5631 { 5632 switch (devinfo->gen) { 5633 case 10: return 0; 5634 case 9: return 0; 5635 case 8: return 0; 5636 case 7: 5637 if (devinfo->is_haswell) { 5638 return 0; 5639 } else { 5640 return 0; 5641 } 5642 case 6: return 16; 5643 case 5: return 16; 5644 case 4: 5645 if (devinfo->is_g4x) { 5646 return 16; 5647 } else { 5648 return 16; 5649 } 5650 default: 5651 unreachable("Invalid hardware generation"); 5652 } 5653 } 5654 5655 5656 5657 /* 3DSTATE_BINDING_TABLE_POINTERS::Command SubType */ 5658 5659 5660 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 5661 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 5662 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 5663 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 5664 5665 static inline uint32_t ATTRIBUTE_PURE 5666 _3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) 5667 { 5668 switch (devinfo->gen) { 5669 case 10: return 0; 5670 case 9: return 0; 5671 case 8: return 0; 5672 case 7: 5673 if (devinfo->is_haswell) { 5674 return 0; 5675 } else { 5676 return 0; 5677 } 5678 case 6: return 2; 5679 case 5: return 2; 5680 case 4: 5681 if (devinfo->is_g4x) { 5682 return 2; 5683 } else { 5684 return 2; 5685 } 5686 default: 5687 unreachable("Invalid hardware generation"); 5688 } 5689 } 5690 5691 5692 5693 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 5694 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 5695 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 5696 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 5697 5698 static inline uint32_t ATTRIBUTE_PURE 5699 _3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) 5700 { 5701 switch (devinfo->gen) { 5702 case 10: return 0; 5703 case 9: return 0; 5704 case 8: return 0; 5705 case 7: 5706 if (devinfo->is_haswell) { 5707 return 0; 5708 } else { 5709 return 0; 5710 } 5711 case 6: return 27; 5712 case 5: return 27; 5713 case 4: 5714 if (devinfo->is_g4x) { 5715 return 27; 5716 } else { 5717 return 27; 5718 } 5719 default: 5720 unreachable("Invalid hardware generation"); 5721 } 5722 } 5723 5724 5725 5726 /* 3DSTATE_BINDING_TABLE_POINTERS::Command Type */ 5727 5728 5729 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 5730 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 5731 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 5732 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 5733 5734 static inline uint32_t ATTRIBUTE_PURE 5735 _3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) 5736 { 5737 switch (devinfo->gen) { 5738 case 10: return 0; 5739 case 9: return 0; 5740 case 8: return 0; 5741 case 7: 5742 if (devinfo->is_haswell) { 5743 return 0; 5744 } else { 5745 return 0; 5746 } 5747 case 6: return 3; 5748 case 5: return 3; 5749 case 4: 5750 if (devinfo->is_g4x) { 5751 return 3; 5752 } else { 5753 return 3; 5754 } 5755 default: 5756 unreachable("Invalid hardware generation"); 5757 } 5758 } 5759 5760 5761 5762 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 5763 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 5764 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 5765 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 5766 5767 static inline uint32_t ATTRIBUTE_PURE 5768 _3DSTATE_BINDING_TABLE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) 5769 { 5770 switch (devinfo->gen) { 5771 case 10: return 0; 5772 case 9: return 0; 5773 case 8: return 0; 5774 case 7: 5775 if (devinfo->is_haswell) { 5776 return 0; 5777 } else { 5778 return 0; 5779 } 5780 case 6: return 29; 5781 case 5: return 29; 5782 case 4: 5783 if (devinfo->is_g4x) { 5784 return 29; 5785 } else { 5786 return 29; 5787 } 5788 default: 5789 unreachable("Invalid hardware generation"); 5790 } 5791 } 5792 5793 5794 5795 /* 3DSTATE_BINDING_TABLE_POINTERS::DWord Length */ 5796 5797 5798 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 5799 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 5800 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 5801 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 5802 5803 static inline uint32_t ATTRIBUTE_PURE 5804 _3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) 5805 { 5806 switch (devinfo->gen) { 5807 case 10: return 0; 5808 case 9: return 0; 5809 case 8: return 0; 5810 case 7: 5811 if (devinfo->is_haswell) { 5812 return 0; 5813 } else { 5814 return 0; 5815 } 5816 case 6: return 8; 5817 case 5: return 8; 5818 case 4: 5819 if (devinfo->is_g4x) { 5820 return 8; 5821 } else { 5822 return 8; 5823 } 5824 default: 5825 unreachable("Invalid hardware generation"); 5826 } 5827 } 5828 5829 5830 5831 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 5832 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 5833 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 5834 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 5835 5836 static inline uint32_t ATTRIBUTE_PURE 5837 _3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) 5838 { 5839 switch (devinfo->gen) { 5840 case 10: return 0; 5841 case 9: return 0; 5842 case 8: return 0; 5843 case 7: 5844 if (devinfo->is_haswell) { 5845 return 0; 5846 } else { 5847 return 0; 5848 } 5849 case 6: return 0; 5850 case 5: return 0; 5851 case 4: 5852 if (devinfo->is_g4x) { 5853 return 0; 5854 } else { 5855 return 0; 5856 } 5857 default: 5858 unreachable("Invalid hardware generation"); 5859 } 5860 } 5861 5862 5863 5864 /* 3DSTATE_BINDING_TABLE_POINTERS::GS Binding Table Change */ 5865 5866 5867 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_bits 1 5868 5869 static inline uint32_t ATTRIBUTE_PURE 5870 _3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_bits(const struct gen_device_info *devinfo) 5871 { 5872 switch (devinfo->gen) { 5873 case 10: return 0; 5874 case 9: return 0; 5875 case 8: return 0; 5876 case 7: 5877 if (devinfo->is_haswell) { 5878 return 0; 5879 } else { 5880 return 0; 5881 } 5882 case 6: return 1; 5883 case 5: return 0; 5884 case 4: 5885 if (devinfo->is_g4x) { 5886 return 0; 5887 } else { 5888 return 0; 5889 } 5890 default: 5891 unreachable("Invalid hardware generation"); 5892 } 5893 } 5894 5895 5896 5897 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_start 9 5898 5899 static inline uint32_t ATTRIBUTE_PURE 5900 _3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_start(const struct gen_device_info *devinfo) 5901 { 5902 switch (devinfo->gen) { 5903 case 10: return 0; 5904 case 9: return 0; 5905 case 8: return 0; 5906 case 7: 5907 if (devinfo->is_haswell) { 5908 return 0; 5909 } else { 5910 return 0; 5911 } 5912 case 6: return 9; 5913 case 5: return 0; 5914 case 4: 5915 if (devinfo->is_g4x) { 5916 return 0; 5917 } else { 5918 return 0; 5919 } 5920 default: 5921 unreachable("Invalid hardware generation"); 5922 } 5923 } 5924 5925 5926 5927 /* 3DSTATE_BINDING_TABLE_POINTERS::PS Binding Table Change */ 5928 5929 5930 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_bits 1 5931 5932 static inline uint32_t ATTRIBUTE_PURE 5933 _3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_bits(const struct gen_device_info *devinfo) 5934 { 5935 switch (devinfo->gen) { 5936 case 10: return 0; 5937 case 9: return 0; 5938 case 8: return 0; 5939 case 7: 5940 if (devinfo->is_haswell) { 5941 return 0; 5942 } else { 5943 return 0; 5944 } 5945 case 6: return 1; 5946 case 5: return 0; 5947 case 4: 5948 if (devinfo->is_g4x) { 5949 return 0; 5950 } else { 5951 return 0; 5952 } 5953 default: 5954 unreachable("Invalid hardware generation"); 5955 } 5956 } 5957 5958 5959 5960 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_start 12 5961 5962 static inline uint32_t ATTRIBUTE_PURE 5963 _3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_start(const struct gen_device_info *devinfo) 5964 { 5965 switch (devinfo->gen) { 5966 case 10: return 0; 5967 case 9: return 0; 5968 case 8: return 0; 5969 case 7: 5970 if (devinfo->is_haswell) { 5971 return 0; 5972 } else { 5973 return 0; 5974 } 5975 case 6: return 12; 5976 case 5: return 0; 5977 case 4: 5978 if (devinfo->is_g4x) { 5979 return 0; 5980 } else { 5981 return 0; 5982 } 5983 default: 5984 unreachable("Invalid hardware generation"); 5985 } 5986 } 5987 5988 5989 5990 /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to CLIP Binding Table */ 5991 5992 5993 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits 27 5994 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits 27 5995 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits 27 5996 5997 static inline uint32_t ATTRIBUTE_PURE 5998 _3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits(const struct gen_device_info *devinfo) 5999 { 6000 switch (devinfo->gen) { 6001 case 10: return 0; 6002 case 9: return 0; 6003 case 8: return 0; 6004 case 7: 6005 if (devinfo->is_haswell) { 6006 return 0; 6007 } else { 6008 return 0; 6009 } 6010 case 6: return 0; 6011 case 5: return 27; 6012 case 4: 6013 if (devinfo->is_g4x) { 6014 return 27; 6015 } else { 6016 return 27; 6017 } 6018 default: 6019 unreachable("Invalid hardware generation"); 6020 } 6021 } 6022 6023 6024 6025 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start 101 6026 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start 101 6027 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start 101 6028 6029 static inline uint32_t ATTRIBUTE_PURE 6030 _3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start(const struct gen_device_info *devinfo) 6031 { 6032 switch (devinfo->gen) { 6033 case 10: return 0; 6034 case 9: return 0; 6035 case 8: return 0; 6036 case 7: 6037 if (devinfo->is_haswell) { 6038 return 0; 6039 } else { 6040 return 0; 6041 } 6042 case 6: return 0; 6043 case 5: return 101; 6044 case 4: 6045 if (devinfo->is_g4x) { 6046 return 101; 6047 } else { 6048 return 101; 6049 } 6050 default: 6051 unreachable("Invalid hardware generation"); 6052 } 6053 } 6054 6055 6056 6057 /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to GS Binding Table */ 6058 6059 6060 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 6061 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 6062 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 6063 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 6064 6065 static inline uint32_t ATTRIBUTE_PURE 6066 _3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits(const struct gen_device_info *devinfo) 6067 { 6068 switch (devinfo->gen) { 6069 case 10: return 0; 6070 case 9: return 0; 6071 case 8: return 0; 6072 case 7: 6073 if (devinfo->is_haswell) { 6074 return 0; 6075 } else { 6076 return 0; 6077 } 6078 case 6: return 27; 6079 case 5: return 27; 6080 case 4: 6081 if (devinfo->is_g4x) { 6082 return 27; 6083 } else { 6084 return 27; 6085 } 6086 default: 6087 unreachable("Invalid hardware generation"); 6088 } 6089 } 6090 6091 6092 6093 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 6094 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 6095 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 6096 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 6097 6098 static inline uint32_t ATTRIBUTE_PURE 6099 _3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start(const struct gen_device_info *devinfo) 6100 { 6101 switch (devinfo->gen) { 6102 case 10: return 0; 6103 case 9: return 0; 6104 case 8: return 0; 6105 case 7: 6106 if (devinfo->is_haswell) { 6107 return 0; 6108 } else { 6109 return 0; 6110 } 6111 case 6: return 69; 6112 case 5: return 69; 6113 case 4: 6114 if (devinfo->is_g4x) { 6115 return 69; 6116 } else { 6117 return 69; 6118 } 6119 default: 6120 unreachable("Invalid hardware generation"); 6121 } 6122 } 6123 6124 6125 6126 /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to PS Binding Table */ 6127 6128 6129 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 6130 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 6131 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 6132 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 6133 6134 static inline uint32_t ATTRIBUTE_PURE 6135 _3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits(const struct gen_device_info *devinfo) 6136 { 6137 switch (devinfo->gen) { 6138 case 10: return 0; 6139 case 9: return 0; 6140 case 8: return 0; 6141 case 7: 6142 if (devinfo->is_haswell) { 6143 return 0; 6144 } else { 6145 return 0; 6146 } 6147 case 6: return 27; 6148 case 5: return 27; 6149 case 4: 6150 if (devinfo->is_g4x) { 6151 return 27; 6152 } else { 6153 return 27; 6154 } 6155 default: 6156 unreachable("Invalid hardware generation"); 6157 } 6158 } 6159 6160 6161 6162 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 101 6163 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 165 6164 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 165 6165 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 165 6166 6167 static inline uint32_t ATTRIBUTE_PURE 6168 _3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start(const struct gen_device_info *devinfo) 6169 { 6170 switch (devinfo->gen) { 6171 case 10: return 0; 6172 case 9: return 0; 6173 case 8: return 0; 6174 case 7: 6175 if (devinfo->is_haswell) { 6176 return 0; 6177 } else { 6178 return 0; 6179 } 6180 case 6: return 101; 6181 case 5: return 165; 6182 case 4: 6183 if (devinfo->is_g4x) { 6184 return 165; 6185 } else { 6186 return 165; 6187 } 6188 default: 6189 unreachable("Invalid hardware generation"); 6190 } 6191 } 6192 6193 6194 6195 /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to SF Binding Table */ 6196 6197 6198 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits 27 6199 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits 27 6200 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits 27 6201 6202 static inline uint32_t ATTRIBUTE_PURE 6203 _3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits(const struct gen_device_info *devinfo) 6204 { 6205 switch (devinfo->gen) { 6206 case 10: return 0; 6207 case 9: return 0; 6208 case 8: return 0; 6209 case 7: 6210 if (devinfo->is_haswell) { 6211 return 0; 6212 } else { 6213 return 0; 6214 } 6215 case 6: return 0; 6216 case 5: return 27; 6217 case 4: 6218 if (devinfo->is_g4x) { 6219 return 27; 6220 } else { 6221 return 27; 6222 } 6223 default: 6224 unreachable("Invalid hardware generation"); 6225 } 6226 } 6227 6228 6229 6230 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start 133 6231 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start 133 6232 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start 133 6233 6234 static inline uint32_t ATTRIBUTE_PURE 6235 _3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start(const struct gen_device_info *devinfo) 6236 { 6237 switch (devinfo->gen) { 6238 case 10: return 0; 6239 case 9: return 0; 6240 case 8: return 0; 6241 case 7: 6242 if (devinfo->is_haswell) { 6243 return 0; 6244 } else { 6245 return 0; 6246 } 6247 case 6: return 0; 6248 case 5: return 133; 6249 case 4: 6250 if (devinfo->is_g4x) { 6251 return 133; 6252 } else { 6253 return 133; 6254 } 6255 default: 6256 unreachable("Invalid hardware generation"); 6257 } 6258 } 6259 6260 6261 6262 /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to VS Binding Table */ 6263 6264 6265 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 6266 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 6267 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 6268 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 6269 6270 static inline uint32_t ATTRIBUTE_PURE 6271 _3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits(const struct gen_device_info *devinfo) 6272 { 6273 switch (devinfo->gen) { 6274 case 10: return 0; 6275 case 9: return 0; 6276 case 8: return 0; 6277 case 7: 6278 if (devinfo->is_haswell) { 6279 return 0; 6280 } else { 6281 return 0; 6282 } 6283 case 6: return 27; 6284 case 5: return 27; 6285 case 4: 6286 if (devinfo->is_g4x) { 6287 return 27; 6288 } else { 6289 return 27; 6290 } 6291 default: 6292 unreachable("Invalid hardware generation"); 6293 } 6294 } 6295 6296 6297 6298 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 6299 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 6300 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 6301 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 6302 6303 static inline uint32_t ATTRIBUTE_PURE 6304 _3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start(const struct gen_device_info *devinfo) 6305 { 6306 switch (devinfo->gen) { 6307 case 10: return 0; 6308 case 9: return 0; 6309 case 8: return 0; 6310 case 7: 6311 if (devinfo->is_haswell) { 6312 return 0; 6313 } else { 6314 return 0; 6315 } 6316 case 6: return 37; 6317 case 5: return 37; 6318 case 4: 6319 if (devinfo->is_g4x) { 6320 return 37; 6321 } else { 6322 return 37; 6323 } 6324 default: 6325 unreachable("Invalid hardware generation"); 6326 } 6327 } 6328 6329 6330 6331 /* 3DSTATE_BINDING_TABLE_POINTERS::VS Binding Table Change */ 6332 6333 6334 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_bits 1 6335 6336 static inline uint32_t ATTRIBUTE_PURE 6337 _3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_bits(const struct gen_device_info *devinfo) 6338 { 6339 switch (devinfo->gen) { 6340 case 10: return 0; 6341 case 9: return 0; 6342 case 8: return 0; 6343 case 7: 6344 if (devinfo->is_haswell) { 6345 return 0; 6346 } else { 6347 return 0; 6348 } 6349 case 6: return 1; 6350 case 5: return 0; 6351 case 4: 6352 if (devinfo->is_g4x) { 6353 return 0; 6354 } else { 6355 return 0; 6356 } 6357 default: 6358 unreachable("Invalid hardware generation"); 6359 } 6360 } 6361 6362 6363 6364 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_start 8 6365 6366 static inline uint32_t ATTRIBUTE_PURE 6367 _3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_start(const struct gen_device_info *devinfo) 6368 { 6369 switch (devinfo->gen) { 6370 case 10: return 0; 6371 case 9: return 0; 6372 case 8: return 0; 6373 case 7: 6374 if (devinfo->is_haswell) { 6375 return 0; 6376 } else { 6377 return 0; 6378 } 6379 case 6: return 8; 6380 case 5: return 0; 6381 case 4: 6382 if (devinfo->is_g4x) { 6383 return 0; 6384 } else { 6385 return 0; 6386 } 6387 default: 6388 unreachable("Invalid hardware generation"); 6389 } 6390 } 6391 6392 6393 6394 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */ 6395 6396 6397 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 6398 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 6399 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 6400 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 6401 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 6402 6403 static inline uint32_t ATTRIBUTE_PURE 6404 _3DSTATE_BINDING_TABLE_POINTERS_DS_length(const struct gen_device_info *devinfo) 6405 { 6406 switch (devinfo->gen) { 6407 case 10: return 2; 6408 case 9: return 2; 6409 case 8: return 2; 6410 case 7: 6411 if (devinfo->is_haswell) { 6412 return 2; 6413 } else { 6414 return 2; 6415 } 6416 case 6: return 0; 6417 case 5: return 0; 6418 case 4: 6419 if (devinfo->is_g4x) { 6420 return 0; 6421 } else { 6422 return 0; 6423 } 6424 default: 6425 unreachable("Invalid hardware generation"); 6426 } 6427 } 6428 6429 6430 6431 /* 3DSTATE_BINDING_TABLE_POINTERS_DS::3D Command Opcode */ 6432 6433 6434 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 6435 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 6436 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 6437 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 6438 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 6439 6440 static inline uint32_t ATTRIBUTE_PURE 6441 _3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 6442 { 6443 switch (devinfo->gen) { 6444 case 10: return 3; 6445 case 9: return 3; 6446 case 8: return 3; 6447 case 7: 6448 if (devinfo->is_haswell) { 6449 return 3; 6450 } else { 6451 return 3; 6452 } 6453 case 6: return 0; 6454 case 5: return 0; 6455 case 4: 6456 if (devinfo->is_g4x) { 6457 return 0; 6458 } else { 6459 return 0; 6460 } 6461 default: 6462 unreachable("Invalid hardware generation"); 6463 } 6464 } 6465 6466 6467 6468 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 6469 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 6470 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 6471 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 6472 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 6473 6474 static inline uint32_t ATTRIBUTE_PURE 6475 _3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 6476 { 6477 switch (devinfo->gen) { 6478 case 10: return 24; 6479 case 9: return 24; 6480 case 8: return 24; 6481 case 7: 6482 if (devinfo->is_haswell) { 6483 return 24; 6484 } else { 6485 return 24; 6486 } 6487 case 6: return 0; 6488 case 5: return 0; 6489 case 4: 6490 if (devinfo->is_g4x) { 6491 return 0; 6492 } else { 6493 return 0; 6494 } 6495 default: 6496 unreachable("Invalid hardware generation"); 6497 } 6498 } 6499 6500 6501 6502 /* 3DSTATE_BINDING_TABLE_POINTERS_DS::3D Command Sub Opcode */ 6503 6504 6505 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 6506 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 6507 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 6508 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 6509 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 6510 6511 static inline uint32_t ATTRIBUTE_PURE 6512 _3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 6513 { 6514 switch (devinfo->gen) { 6515 case 10: return 8; 6516 case 9: return 8; 6517 case 8: return 8; 6518 case 7: 6519 if (devinfo->is_haswell) { 6520 return 8; 6521 } else { 6522 return 8; 6523 } 6524 case 6: return 0; 6525 case 5: return 0; 6526 case 4: 6527 if (devinfo->is_g4x) { 6528 return 0; 6529 } else { 6530 return 0; 6531 } 6532 default: 6533 unreachable("Invalid hardware generation"); 6534 } 6535 } 6536 6537 6538 6539 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 6540 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 6541 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 6542 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 6543 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 6544 6545 static inline uint32_t ATTRIBUTE_PURE 6546 _3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 6547 { 6548 switch (devinfo->gen) { 6549 case 10: return 16; 6550 case 9: return 16; 6551 case 8: return 16; 6552 case 7: 6553 if (devinfo->is_haswell) { 6554 return 16; 6555 } else { 6556 return 16; 6557 } 6558 case 6: return 0; 6559 case 5: return 0; 6560 case 4: 6561 if (devinfo->is_g4x) { 6562 return 0; 6563 } else { 6564 return 0; 6565 } 6566 default: 6567 unreachable("Invalid hardware generation"); 6568 } 6569 } 6570 6571 6572 6573 /* 3DSTATE_BINDING_TABLE_POINTERS_DS::Command SubType */ 6574 6575 6576 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 6577 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 6578 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 6579 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 6580 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 6581 6582 static inline uint32_t ATTRIBUTE_PURE 6583 _3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits(const struct gen_device_info *devinfo) 6584 { 6585 switch (devinfo->gen) { 6586 case 10: return 2; 6587 case 9: return 2; 6588 case 8: return 2; 6589 case 7: 6590 if (devinfo->is_haswell) { 6591 return 2; 6592 } else { 6593 return 2; 6594 } 6595 case 6: return 0; 6596 case 5: return 0; 6597 case 4: 6598 if (devinfo->is_g4x) { 6599 return 0; 6600 } else { 6601 return 0; 6602 } 6603 default: 6604 unreachable("Invalid hardware generation"); 6605 } 6606 } 6607 6608 6609 6610 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 6611 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 6612 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 6613 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 6614 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 6615 6616 static inline uint32_t ATTRIBUTE_PURE 6617 _3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start(const struct gen_device_info *devinfo) 6618 { 6619 switch (devinfo->gen) { 6620 case 10: return 27; 6621 case 9: return 27; 6622 case 8: return 27; 6623 case 7: 6624 if (devinfo->is_haswell) { 6625 return 27; 6626 } else { 6627 return 27; 6628 } 6629 case 6: return 0; 6630 case 5: return 0; 6631 case 4: 6632 if (devinfo->is_g4x) { 6633 return 0; 6634 } else { 6635 return 0; 6636 } 6637 default: 6638 unreachable("Invalid hardware generation"); 6639 } 6640 } 6641 6642 6643 6644 /* 3DSTATE_BINDING_TABLE_POINTERS_DS::Command Type */ 6645 6646 6647 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 6648 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 6649 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 6650 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 6651 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 6652 6653 static inline uint32_t ATTRIBUTE_PURE 6654 _3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits(const struct gen_device_info *devinfo) 6655 { 6656 switch (devinfo->gen) { 6657 case 10: return 3; 6658 case 9: return 3; 6659 case 8: return 3; 6660 case 7: 6661 if (devinfo->is_haswell) { 6662 return 3; 6663 } else { 6664 return 3; 6665 } 6666 case 6: return 0; 6667 case 5: return 0; 6668 case 4: 6669 if (devinfo->is_g4x) { 6670 return 0; 6671 } else { 6672 return 0; 6673 } 6674 default: 6675 unreachable("Invalid hardware generation"); 6676 } 6677 } 6678 6679 6680 6681 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 6682 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 6683 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 6684 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 6685 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 6686 6687 static inline uint32_t ATTRIBUTE_PURE 6688 _3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start(const struct gen_device_info *devinfo) 6689 { 6690 switch (devinfo->gen) { 6691 case 10: return 29; 6692 case 9: return 29; 6693 case 8: return 29; 6694 case 7: 6695 if (devinfo->is_haswell) { 6696 return 29; 6697 } else { 6698 return 29; 6699 } 6700 case 6: return 0; 6701 case 5: return 0; 6702 case 4: 6703 if (devinfo->is_g4x) { 6704 return 0; 6705 } else { 6706 return 0; 6707 } 6708 default: 6709 unreachable("Invalid hardware generation"); 6710 } 6711 } 6712 6713 6714 6715 /* 3DSTATE_BINDING_TABLE_POINTERS_DS::DWord Length */ 6716 6717 6718 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 6719 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 6720 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 6721 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 6722 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 6723 6724 static inline uint32_t ATTRIBUTE_PURE 6725 _3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits(const struct gen_device_info *devinfo) 6726 { 6727 switch (devinfo->gen) { 6728 case 10: return 8; 6729 case 9: return 8; 6730 case 8: return 8; 6731 case 7: 6732 if (devinfo->is_haswell) { 6733 return 8; 6734 } else { 6735 return 8; 6736 } 6737 case 6: return 0; 6738 case 5: return 0; 6739 case 4: 6740 if (devinfo->is_g4x) { 6741 return 0; 6742 } else { 6743 return 0; 6744 } 6745 default: 6746 unreachable("Invalid hardware generation"); 6747 } 6748 } 6749 6750 6751 6752 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 6753 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 6754 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 6755 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 6756 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 6757 6758 static inline uint32_t ATTRIBUTE_PURE 6759 _3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start(const struct gen_device_info *devinfo) 6760 { 6761 switch (devinfo->gen) { 6762 case 10: return 0; 6763 case 9: return 0; 6764 case 8: return 0; 6765 case 7: 6766 if (devinfo->is_haswell) { 6767 return 0; 6768 } else { 6769 return 0; 6770 } 6771 case 6: return 0; 6772 case 5: return 0; 6773 case 4: 6774 if (devinfo->is_g4x) { 6775 return 0; 6776 } else { 6777 return 0; 6778 } 6779 default: 6780 unreachable("Invalid hardware generation"); 6781 } 6782 } 6783 6784 6785 6786 /* 3DSTATE_BINDING_TABLE_POINTERS_DS::Pointer to DS Binding Table */ 6787 6788 6789 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 6790 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 6791 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 6792 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 6793 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 6794 6795 static inline uint32_t ATTRIBUTE_PURE 6796 _3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits(const struct gen_device_info *devinfo) 6797 { 6798 switch (devinfo->gen) { 6799 case 10: return 11; 6800 case 9: return 11; 6801 case 8: return 11; 6802 case 7: 6803 if (devinfo->is_haswell) { 6804 return 11; 6805 } else { 6806 return 11; 6807 } 6808 case 6: return 0; 6809 case 5: return 0; 6810 case 4: 6811 if (devinfo->is_g4x) { 6812 return 0; 6813 } else { 6814 return 0; 6815 } 6816 default: 6817 unreachable("Invalid hardware generation"); 6818 } 6819 } 6820 6821 6822 6823 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 6824 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 6825 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 6826 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 6827 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 6828 6829 static inline uint32_t ATTRIBUTE_PURE 6830 _3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start(const struct gen_device_info *devinfo) 6831 { 6832 switch (devinfo->gen) { 6833 case 10: return 37; 6834 case 9: return 37; 6835 case 8: return 37; 6836 case 7: 6837 if (devinfo->is_haswell) { 6838 return 37; 6839 } else { 6840 return 37; 6841 } 6842 case 6: return 0; 6843 case 5: return 0; 6844 case 4: 6845 if (devinfo->is_g4x) { 6846 return 0; 6847 } else { 6848 return 0; 6849 } 6850 default: 6851 unreachable("Invalid hardware generation"); 6852 } 6853 } 6854 6855 6856 6857 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */ 6858 6859 6860 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 6861 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 6862 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 6863 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 6864 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 6865 6866 static inline uint32_t ATTRIBUTE_PURE 6867 _3DSTATE_BINDING_TABLE_POINTERS_GS_length(const struct gen_device_info *devinfo) 6868 { 6869 switch (devinfo->gen) { 6870 case 10: return 2; 6871 case 9: return 2; 6872 case 8: return 2; 6873 case 7: 6874 if (devinfo->is_haswell) { 6875 return 2; 6876 } else { 6877 return 2; 6878 } 6879 case 6: return 0; 6880 case 5: return 0; 6881 case 4: 6882 if (devinfo->is_g4x) { 6883 return 0; 6884 } else { 6885 return 0; 6886 } 6887 default: 6888 unreachable("Invalid hardware generation"); 6889 } 6890 } 6891 6892 6893 6894 /* 3DSTATE_BINDING_TABLE_POINTERS_GS::3D Command Opcode */ 6895 6896 6897 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 6898 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 6899 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 6900 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 6901 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 6902 6903 static inline uint32_t ATTRIBUTE_PURE 6904 _3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 6905 { 6906 switch (devinfo->gen) { 6907 case 10: return 3; 6908 case 9: return 3; 6909 case 8: return 3; 6910 case 7: 6911 if (devinfo->is_haswell) { 6912 return 3; 6913 } else { 6914 return 3; 6915 } 6916 case 6: return 0; 6917 case 5: return 0; 6918 case 4: 6919 if (devinfo->is_g4x) { 6920 return 0; 6921 } else { 6922 return 0; 6923 } 6924 default: 6925 unreachable("Invalid hardware generation"); 6926 } 6927 } 6928 6929 6930 6931 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 6932 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 6933 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 6934 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 6935 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 6936 6937 static inline uint32_t ATTRIBUTE_PURE 6938 _3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 6939 { 6940 switch (devinfo->gen) { 6941 case 10: return 24; 6942 case 9: return 24; 6943 case 8: return 24; 6944 case 7: 6945 if (devinfo->is_haswell) { 6946 return 24; 6947 } else { 6948 return 24; 6949 } 6950 case 6: return 0; 6951 case 5: return 0; 6952 case 4: 6953 if (devinfo->is_g4x) { 6954 return 0; 6955 } else { 6956 return 0; 6957 } 6958 default: 6959 unreachable("Invalid hardware generation"); 6960 } 6961 } 6962 6963 6964 6965 /* 3DSTATE_BINDING_TABLE_POINTERS_GS::3D Command Sub Opcode */ 6966 6967 6968 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 6969 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 6970 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 6971 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 6972 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 6973 6974 static inline uint32_t ATTRIBUTE_PURE 6975 _3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 6976 { 6977 switch (devinfo->gen) { 6978 case 10: return 8; 6979 case 9: return 8; 6980 case 8: return 8; 6981 case 7: 6982 if (devinfo->is_haswell) { 6983 return 8; 6984 } else { 6985 return 8; 6986 } 6987 case 6: return 0; 6988 case 5: return 0; 6989 case 4: 6990 if (devinfo->is_g4x) { 6991 return 0; 6992 } else { 6993 return 0; 6994 } 6995 default: 6996 unreachable("Invalid hardware generation"); 6997 } 6998 } 6999 7000 7001 7002 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 7003 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 7004 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 7005 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 7006 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 7007 7008 static inline uint32_t ATTRIBUTE_PURE 7009 _3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 7010 { 7011 switch (devinfo->gen) { 7012 case 10: return 16; 7013 case 9: return 16; 7014 case 8: return 16; 7015 case 7: 7016 if (devinfo->is_haswell) { 7017 return 16; 7018 } else { 7019 return 16; 7020 } 7021 case 6: return 0; 7022 case 5: return 0; 7023 case 4: 7024 if (devinfo->is_g4x) { 7025 return 0; 7026 } else { 7027 return 0; 7028 } 7029 default: 7030 unreachable("Invalid hardware generation"); 7031 } 7032 } 7033 7034 7035 7036 /* 3DSTATE_BINDING_TABLE_POINTERS_GS::Command SubType */ 7037 7038 7039 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 7040 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 7041 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 7042 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 7043 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 7044 7045 static inline uint32_t ATTRIBUTE_PURE 7046 _3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits(const struct gen_device_info *devinfo) 7047 { 7048 switch (devinfo->gen) { 7049 case 10: return 2; 7050 case 9: return 2; 7051 case 8: return 2; 7052 case 7: 7053 if (devinfo->is_haswell) { 7054 return 2; 7055 } else { 7056 return 2; 7057 } 7058 case 6: return 0; 7059 case 5: return 0; 7060 case 4: 7061 if (devinfo->is_g4x) { 7062 return 0; 7063 } else { 7064 return 0; 7065 } 7066 default: 7067 unreachable("Invalid hardware generation"); 7068 } 7069 } 7070 7071 7072 7073 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 7074 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 7075 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 7076 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 7077 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 7078 7079 static inline uint32_t ATTRIBUTE_PURE 7080 _3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start(const struct gen_device_info *devinfo) 7081 { 7082 switch (devinfo->gen) { 7083 case 10: return 27; 7084 case 9: return 27; 7085 case 8: return 27; 7086 case 7: 7087 if (devinfo->is_haswell) { 7088 return 27; 7089 } else { 7090 return 27; 7091 } 7092 case 6: return 0; 7093 case 5: return 0; 7094 case 4: 7095 if (devinfo->is_g4x) { 7096 return 0; 7097 } else { 7098 return 0; 7099 } 7100 default: 7101 unreachable("Invalid hardware generation"); 7102 } 7103 } 7104 7105 7106 7107 /* 3DSTATE_BINDING_TABLE_POINTERS_GS::Command Type */ 7108 7109 7110 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 7111 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 7112 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 7113 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 7114 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 7115 7116 static inline uint32_t ATTRIBUTE_PURE 7117 _3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits(const struct gen_device_info *devinfo) 7118 { 7119 switch (devinfo->gen) { 7120 case 10: return 3; 7121 case 9: return 3; 7122 case 8: return 3; 7123 case 7: 7124 if (devinfo->is_haswell) { 7125 return 3; 7126 } else { 7127 return 3; 7128 } 7129 case 6: return 0; 7130 case 5: return 0; 7131 case 4: 7132 if (devinfo->is_g4x) { 7133 return 0; 7134 } else { 7135 return 0; 7136 } 7137 default: 7138 unreachable("Invalid hardware generation"); 7139 } 7140 } 7141 7142 7143 7144 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 7145 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 7146 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 7147 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 7148 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 7149 7150 static inline uint32_t ATTRIBUTE_PURE 7151 _3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start(const struct gen_device_info *devinfo) 7152 { 7153 switch (devinfo->gen) { 7154 case 10: return 29; 7155 case 9: return 29; 7156 case 8: return 29; 7157 case 7: 7158 if (devinfo->is_haswell) { 7159 return 29; 7160 } else { 7161 return 29; 7162 } 7163 case 6: return 0; 7164 case 5: return 0; 7165 case 4: 7166 if (devinfo->is_g4x) { 7167 return 0; 7168 } else { 7169 return 0; 7170 } 7171 default: 7172 unreachable("Invalid hardware generation"); 7173 } 7174 } 7175 7176 7177 7178 /* 3DSTATE_BINDING_TABLE_POINTERS_GS::DWord Length */ 7179 7180 7181 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 7182 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 7183 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 7184 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 7185 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 7186 7187 static inline uint32_t ATTRIBUTE_PURE 7188 _3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits(const struct gen_device_info *devinfo) 7189 { 7190 switch (devinfo->gen) { 7191 case 10: return 8; 7192 case 9: return 8; 7193 case 8: return 8; 7194 case 7: 7195 if (devinfo->is_haswell) { 7196 return 8; 7197 } else { 7198 return 8; 7199 } 7200 case 6: return 0; 7201 case 5: return 0; 7202 case 4: 7203 if (devinfo->is_g4x) { 7204 return 0; 7205 } else { 7206 return 0; 7207 } 7208 default: 7209 unreachable("Invalid hardware generation"); 7210 } 7211 } 7212 7213 7214 7215 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 7216 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 7217 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 7218 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 7219 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 7220 7221 static inline uint32_t ATTRIBUTE_PURE 7222 _3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start(const struct gen_device_info *devinfo) 7223 { 7224 switch (devinfo->gen) { 7225 case 10: return 0; 7226 case 9: return 0; 7227 case 8: return 0; 7228 case 7: 7229 if (devinfo->is_haswell) { 7230 return 0; 7231 } else { 7232 return 0; 7233 } 7234 case 6: return 0; 7235 case 5: return 0; 7236 case 4: 7237 if (devinfo->is_g4x) { 7238 return 0; 7239 } else { 7240 return 0; 7241 } 7242 default: 7243 unreachable("Invalid hardware generation"); 7244 } 7245 } 7246 7247 7248 7249 /* 3DSTATE_BINDING_TABLE_POINTERS_GS::Pointer to GS Binding Table */ 7250 7251 7252 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 7253 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 7254 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 7255 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 7256 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 7257 7258 static inline uint32_t ATTRIBUTE_PURE 7259 _3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits(const struct gen_device_info *devinfo) 7260 { 7261 switch (devinfo->gen) { 7262 case 10: return 11; 7263 case 9: return 11; 7264 case 8: return 11; 7265 case 7: 7266 if (devinfo->is_haswell) { 7267 return 11; 7268 } else { 7269 return 11; 7270 } 7271 case 6: return 0; 7272 case 5: return 0; 7273 case 4: 7274 if (devinfo->is_g4x) { 7275 return 0; 7276 } else { 7277 return 0; 7278 } 7279 default: 7280 unreachable("Invalid hardware generation"); 7281 } 7282 } 7283 7284 7285 7286 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 7287 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 7288 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 7289 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 7290 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 7291 7292 static inline uint32_t ATTRIBUTE_PURE 7293 _3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start(const struct gen_device_info *devinfo) 7294 { 7295 switch (devinfo->gen) { 7296 case 10: return 37; 7297 case 9: return 37; 7298 case 8: return 37; 7299 case 7: 7300 if (devinfo->is_haswell) { 7301 return 37; 7302 } else { 7303 return 37; 7304 } 7305 case 6: return 0; 7306 case 5: return 0; 7307 case 4: 7308 if (devinfo->is_g4x) { 7309 return 0; 7310 } else { 7311 return 0; 7312 } 7313 default: 7314 unreachable("Invalid hardware generation"); 7315 } 7316 } 7317 7318 7319 7320 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */ 7321 7322 7323 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 7324 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 7325 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 7326 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 7327 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 7328 7329 static inline uint32_t ATTRIBUTE_PURE 7330 _3DSTATE_BINDING_TABLE_POINTERS_HS_length(const struct gen_device_info *devinfo) 7331 { 7332 switch (devinfo->gen) { 7333 case 10: return 2; 7334 case 9: return 2; 7335 case 8: return 2; 7336 case 7: 7337 if (devinfo->is_haswell) { 7338 return 2; 7339 } else { 7340 return 2; 7341 } 7342 case 6: return 0; 7343 case 5: return 0; 7344 case 4: 7345 if (devinfo->is_g4x) { 7346 return 0; 7347 } else { 7348 return 0; 7349 } 7350 default: 7351 unreachable("Invalid hardware generation"); 7352 } 7353 } 7354 7355 7356 7357 /* 3DSTATE_BINDING_TABLE_POINTERS_HS::3D Command Opcode */ 7358 7359 7360 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 7361 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 7362 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 7363 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 7364 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 7365 7366 static inline uint32_t ATTRIBUTE_PURE 7367 _3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 7368 { 7369 switch (devinfo->gen) { 7370 case 10: return 3; 7371 case 9: return 3; 7372 case 8: return 3; 7373 case 7: 7374 if (devinfo->is_haswell) { 7375 return 3; 7376 } else { 7377 return 3; 7378 } 7379 case 6: return 0; 7380 case 5: return 0; 7381 case 4: 7382 if (devinfo->is_g4x) { 7383 return 0; 7384 } else { 7385 return 0; 7386 } 7387 default: 7388 unreachable("Invalid hardware generation"); 7389 } 7390 } 7391 7392 7393 7394 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 7395 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 7396 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 7397 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 7398 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 7399 7400 static inline uint32_t ATTRIBUTE_PURE 7401 _3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 7402 { 7403 switch (devinfo->gen) { 7404 case 10: return 24; 7405 case 9: return 24; 7406 case 8: return 24; 7407 case 7: 7408 if (devinfo->is_haswell) { 7409 return 24; 7410 } else { 7411 return 24; 7412 } 7413 case 6: return 0; 7414 case 5: return 0; 7415 case 4: 7416 if (devinfo->is_g4x) { 7417 return 0; 7418 } else { 7419 return 0; 7420 } 7421 default: 7422 unreachable("Invalid hardware generation"); 7423 } 7424 } 7425 7426 7427 7428 /* 3DSTATE_BINDING_TABLE_POINTERS_HS::3D Command Sub Opcode */ 7429 7430 7431 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 7432 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 7433 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 7434 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 7435 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 7436 7437 static inline uint32_t ATTRIBUTE_PURE 7438 _3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 7439 { 7440 switch (devinfo->gen) { 7441 case 10: return 8; 7442 case 9: return 8; 7443 case 8: return 8; 7444 case 7: 7445 if (devinfo->is_haswell) { 7446 return 8; 7447 } else { 7448 return 8; 7449 } 7450 case 6: return 0; 7451 case 5: return 0; 7452 case 4: 7453 if (devinfo->is_g4x) { 7454 return 0; 7455 } else { 7456 return 0; 7457 } 7458 default: 7459 unreachable("Invalid hardware generation"); 7460 } 7461 } 7462 7463 7464 7465 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 7466 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 7467 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 7468 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 7469 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 7470 7471 static inline uint32_t ATTRIBUTE_PURE 7472 _3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 7473 { 7474 switch (devinfo->gen) { 7475 case 10: return 16; 7476 case 9: return 16; 7477 case 8: return 16; 7478 case 7: 7479 if (devinfo->is_haswell) { 7480 return 16; 7481 } else { 7482 return 16; 7483 } 7484 case 6: return 0; 7485 case 5: return 0; 7486 case 4: 7487 if (devinfo->is_g4x) { 7488 return 0; 7489 } else { 7490 return 0; 7491 } 7492 default: 7493 unreachable("Invalid hardware generation"); 7494 } 7495 } 7496 7497 7498 7499 /* 3DSTATE_BINDING_TABLE_POINTERS_HS::Command SubType */ 7500 7501 7502 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 7503 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 7504 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 7505 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 7506 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 7507 7508 static inline uint32_t ATTRIBUTE_PURE 7509 _3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits(const struct gen_device_info *devinfo) 7510 { 7511 switch (devinfo->gen) { 7512 case 10: return 2; 7513 case 9: return 2; 7514 case 8: return 2; 7515 case 7: 7516 if (devinfo->is_haswell) { 7517 return 2; 7518 } else { 7519 return 2; 7520 } 7521 case 6: return 0; 7522 case 5: return 0; 7523 case 4: 7524 if (devinfo->is_g4x) { 7525 return 0; 7526 } else { 7527 return 0; 7528 } 7529 default: 7530 unreachable("Invalid hardware generation"); 7531 } 7532 } 7533 7534 7535 7536 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 7537 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 7538 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 7539 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 7540 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 7541 7542 static inline uint32_t ATTRIBUTE_PURE 7543 _3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start(const struct gen_device_info *devinfo) 7544 { 7545 switch (devinfo->gen) { 7546 case 10: return 27; 7547 case 9: return 27; 7548 case 8: return 27; 7549 case 7: 7550 if (devinfo->is_haswell) { 7551 return 27; 7552 } else { 7553 return 27; 7554 } 7555 case 6: return 0; 7556 case 5: return 0; 7557 case 4: 7558 if (devinfo->is_g4x) { 7559 return 0; 7560 } else { 7561 return 0; 7562 } 7563 default: 7564 unreachable("Invalid hardware generation"); 7565 } 7566 } 7567 7568 7569 7570 /* 3DSTATE_BINDING_TABLE_POINTERS_HS::Command Type */ 7571 7572 7573 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 7574 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 7575 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 7576 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 7577 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 7578 7579 static inline uint32_t ATTRIBUTE_PURE 7580 _3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits(const struct gen_device_info *devinfo) 7581 { 7582 switch (devinfo->gen) { 7583 case 10: return 3; 7584 case 9: return 3; 7585 case 8: return 3; 7586 case 7: 7587 if (devinfo->is_haswell) { 7588 return 3; 7589 } else { 7590 return 3; 7591 } 7592 case 6: return 0; 7593 case 5: return 0; 7594 case 4: 7595 if (devinfo->is_g4x) { 7596 return 0; 7597 } else { 7598 return 0; 7599 } 7600 default: 7601 unreachable("Invalid hardware generation"); 7602 } 7603 } 7604 7605 7606 7607 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 7608 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 7609 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 7610 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 7611 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 7612 7613 static inline uint32_t ATTRIBUTE_PURE 7614 _3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start(const struct gen_device_info *devinfo) 7615 { 7616 switch (devinfo->gen) { 7617 case 10: return 29; 7618 case 9: return 29; 7619 case 8: return 29; 7620 case 7: 7621 if (devinfo->is_haswell) { 7622 return 29; 7623 } else { 7624 return 29; 7625 } 7626 case 6: return 0; 7627 case 5: return 0; 7628 case 4: 7629 if (devinfo->is_g4x) { 7630 return 0; 7631 } else { 7632 return 0; 7633 } 7634 default: 7635 unreachable("Invalid hardware generation"); 7636 } 7637 } 7638 7639 7640 7641 /* 3DSTATE_BINDING_TABLE_POINTERS_HS::DWord Length */ 7642 7643 7644 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 7645 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 7646 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 7647 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 7648 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 7649 7650 static inline uint32_t ATTRIBUTE_PURE 7651 _3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits(const struct gen_device_info *devinfo) 7652 { 7653 switch (devinfo->gen) { 7654 case 10: return 8; 7655 case 9: return 8; 7656 case 8: return 8; 7657 case 7: 7658 if (devinfo->is_haswell) { 7659 return 8; 7660 } else { 7661 return 8; 7662 } 7663 case 6: return 0; 7664 case 5: return 0; 7665 case 4: 7666 if (devinfo->is_g4x) { 7667 return 0; 7668 } else { 7669 return 0; 7670 } 7671 default: 7672 unreachable("Invalid hardware generation"); 7673 } 7674 } 7675 7676 7677 7678 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 7679 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 7680 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 7681 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 7682 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 7683 7684 static inline uint32_t ATTRIBUTE_PURE 7685 _3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start(const struct gen_device_info *devinfo) 7686 { 7687 switch (devinfo->gen) { 7688 case 10: return 0; 7689 case 9: return 0; 7690 case 8: return 0; 7691 case 7: 7692 if (devinfo->is_haswell) { 7693 return 0; 7694 } else { 7695 return 0; 7696 } 7697 case 6: return 0; 7698 case 5: return 0; 7699 case 4: 7700 if (devinfo->is_g4x) { 7701 return 0; 7702 } else { 7703 return 0; 7704 } 7705 default: 7706 unreachable("Invalid hardware generation"); 7707 } 7708 } 7709 7710 7711 7712 /* 3DSTATE_BINDING_TABLE_POINTERS_HS::Pointer to HS Binding Table */ 7713 7714 7715 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 7716 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 7717 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 7718 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 7719 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 7720 7721 static inline uint32_t ATTRIBUTE_PURE 7722 _3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits(const struct gen_device_info *devinfo) 7723 { 7724 switch (devinfo->gen) { 7725 case 10: return 11; 7726 case 9: return 11; 7727 case 8: return 11; 7728 case 7: 7729 if (devinfo->is_haswell) { 7730 return 11; 7731 } else { 7732 return 11; 7733 } 7734 case 6: return 0; 7735 case 5: return 0; 7736 case 4: 7737 if (devinfo->is_g4x) { 7738 return 0; 7739 } else { 7740 return 0; 7741 } 7742 default: 7743 unreachable("Invalid hardware generation"); 7744 } 7745 } 7746 7747 7748 7749 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 7750 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 7751 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 7752 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 7753 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 7754 7755 static inline uint32_t ATTRIBUTE_PURE 7756 _3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start(const struct gen_device_info *devinfo) 7757 { 7758 switch (devinfo->gen) { 7759 case 10: return 37; 7760 case 9: return 37; 7761 case 8: return 37; 7762 case 7: 7763 if (devinfo->is_haswell) { 7764 return 37; 7765 } else { 7766 return 37; 7767 } 7768 case 6: return 0; 7769 case 5: return 0; 7770 case 4: 7771 if (devinfo->is_g4x) { 7772 return 0; 7773 } else { 7774 return 0; 7775 } 7776 default: 7777 unreachable("Invalid hardware generation"); 7778 } 7779 } 7780 7781 7782 7783 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */ 7784 7785 7786 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 7787 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 7788 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 7789 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 7790 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 7791 7792 static inline uint32_t ATTRIBUTE_PURE 7793 _3DSTATE_BINDING_TABLE_POINTERS_PS_length(const struct gen_device_info *devinfo) 7794 { 7795 switch (devinfo->gen) { 7796 case 10: return 2; 7797 case 9: return 2; 7798 case 8: return 2; 7799 case 7: 7800 if (devinfo->is_haswell) { 7801 return 2; 7802 } else { 7803 return 2; 7804 } 7805 case 6: return 0; 7806 case 5: return 0; 7807 case 4: 7808 if (devinfo->is_g4x) { 7809 return 0; 7810 } else { 7811 return 0; 7812 } 7813 default: 7814 unreachable("Invalid hardware generation"); 7815 } 7816 } 7817 7818 7819 7820 /* 3DSTATE_BINDING_TABLE_POINTERS_PS::3D Command Opcode */ 7821 7822 7823 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 7824 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 7825 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 7826 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 7827 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 7828 7829 static inline uint32_t ATTRIBUTE_PURE 7830 _3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 7831 { 7832 switch (devinfo->gen) { 7833 case 10: return 3; 7834 case 9: return 3; 7835 case 8: return 3; 7836 case 7: 7837 if (devinfo->is_haswell) { 7838 return 3; 7839 } else { 7840 return 3; 7841 } 7842 case 6: return 0; 7843 case 5: return 0; 7844 case 4: 7845 if (devinfo->is_g4x) { 7846 return 0; 7847 } else { 7848 return 0; 7849 } 7850 default: 7851 unreachable("Invalid hardware generation"); 7852 } 7853 } 7854 7855 7856 7857 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 7858 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 7859 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 7860 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 7861 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 7862 7863 static inline uint32_t ATTRIBUTE_PURE 7864 _3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 7865 { 7866 switch (devinfo->gen) { 7867 case 10: return 24; 7868 case 9: return 24; 7869 case 8: return 24; 7870 case 7: 7871 if (devinfo->is_haswell) { 7872 return 24; 7873 } else { 7874 return 24; 7875 } 7876 case 6: return 0; 7877 case 5: return 0; 7878 case 4: 7879 if (devinfo->is_g4x) { 7880 return 0; 7881 } else { 7882 return 0; 7883 } 7884 default: 7885 unreachable("Invalid hardware generation"); 7886 } 7887 } 7888 7889 7890 7891 /* 3DSTATE_BINDING_TABLE_POINTERS_PS::3D Command Sub Opcode */ 7892 7893 7894 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 7895 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 7896 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 7897 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 7898 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 7899 7900 static inline uint32_t ATTRIBUTE_PURE 7901 _3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 7902 { 7903 switch (devinfo->gen) { 7904 case 10: return 8; 7905 case 9: return 8; 7906 case 8: return 8; 7907 case 7: 7908 if (devinfo->is_haswell) { 7909 return 8; 7910 } else { 7911 return 8; 7912 } 7913 case 6: return 0; 7914 case 5: return 0; 7915 case 4: 7916 if (devinfo->is_g4x) { 7917 return 0; 7918 } else { 7919 return 0; 7920 } 7921 default: 7922 unreachable("Invalid hardware generation"); 7923 } 7924 } 7925 7926 7927 7928 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 7929 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 7930 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 7931 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 7932 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 7933 7934 static inline uint32_t ATTRIBUTE_PURE 7935 _3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 7936 { 7937 switch (devinfo->gen) { 7938 case 10: return 16; 7939 case 9: return 16; 7940 case 8: return 16; 7941 case 7: 7942 if (devinfo->is_haswell) { 7943 return 16; 7944 } else { 7945 return 16; 7946 } 7947 case 6: return 0; 7948 case 5: return 0; 7949 case 4: 7950 if (devinfo->is_g4x) { 7951 return 0; 7952 } else { 7953 return 0; 7954 } 7955 default: 7956 unreachable("Invalid hardware generation"); 7957 } 7958 } 7959 7960 7961 7962 /* 3DSTATE_BINDING_TABLE_POINTERS_PS::Command SubType */ 7963 7964 7965 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 7966 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 7967 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 7968 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 7969 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 7970 7971 static inline uint32_t ATTRIBUTE_PURE 7972 _3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits(const struct gen_device_info *devinfo) 7973 { 7974 switch (devinfo->gen) { 7975 case 10: return 2; 7976 case 9: return 2; 7977 case 8: return 2; 7978 case 7: 7979 if (devinfo->is_haswell) { 7980 return 2; 7981 } else { 7982 return 2; 7983 } 7984 case 6: return 0; 7985 case 5: return 0; 7986 case 4: 7987 if (devinfo->is_g4x) { 7988 return 0; 7989 } else { 7990 return 0; 7991 } 7992 default: 7993 unreachable("Invalid hardware generation"); 7994 } 7995 } 7996 7997 7998 7999 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 8000 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 8001 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 8002 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 8003 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 8004 8005 static inline uint32_t ATTRIBUTE_PURE 8006 _3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start(const struct gen_device_info *devinfo) 8007 { 8008 switch (devinfo->gen) { 8009 case 10: return 27; 8010 case 9: return 27; 8011 case 8: return 27; 8012 case 7: 8013 if (devinfo->is_haswell) { 8014 return 27; 8015 } else { 8016 return 27; 8017 } 8018 case 6: return 0; 8019 case 5: return 0; 8020 case 4: 8021 if (devinfo->is_g4x) { 8022 return 0; 8023 } else { 8024 return 0; 8025 } 8026 default: 8027 unreachable("Invalid hardware generation"); 8028 } 8029 } 8030 8031 8032 8033 /* 3DSTATE_BINDING_TABLE_POINTERS_PS::Command Type */ 8034 8035 8036 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 8037 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 8038 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 8039 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 8040 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 8041 8042 static inline uint32_t ATTRIBUTE_PURE 8043 _3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits(const struct gen_device_info *devinfo) 8044 { 8045 switch (devinfo->gen) { 8046 case 10: return 3; 8047 case 9: return 3; 8048 case 8: return 3; 8049 case 7: 8050 if (devinfo->is_haswell) { 8051 return 3; 8052 } else { 8053 return 3; 8054 } 8055 case 6: return 0; 8056 case 5: return 0; 8057 case 4: 8058 if (devinfo->is_g4x) { 8059 return 0; 8060 } else { 8061 return 0; 8062 } 8063 default: 8064 unreachable("Invalid hardware generation"); 8065 } 8066 } 8067 8068 8069 8070 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 8071 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 8072 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 8073 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 8074 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 8075 8076 static inline uint32_t ATTRIBUTE_PURE 8077 _3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start(const struct gen_device_info *devinfo) 8078 { 8079 switch (devinfo->gen) { 8080 case 10: return 29; 8081 case 9: return 29; 8082 case 8: return 29; 8083 case 7: 8084 if (devinfo->is_haswell) { 8085 return 29; 8086 } else { 8087 return 29; 8088 } 8089 case 6: return 0; 8090 case 5: return 0; 8091 case 4: 8092 if (devinfo->is_g4x) { 8093 return 0; 8094 } else { 8095 return 0; 8096 } 8097 default: 8098 unreachable("Invalid hardware generation"); 8099 } 8100 } 8101 8102 8103 8104 /* 3DSTATE_BINDING_TABLE_POINTERS_PS::DWord Length */ 8105 8106 8107 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 8108 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 8109 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 8110 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 8111 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 8112 8113 static inline uint32_t ATTRIBUTE_PURE 8114 _3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits(const struct gen_device_info *devinfo) 8115 { 8116 switch (devinfo->gen) { 8117 case 10: return 8; 8118 case 9: return 8; 8119 case 8: return 8; 8120 case 7: 8121 if (devinfo->is_haswell) { 8122 return 8; 8123 } else { 8124 return 8; 8125 } 8126 case 6: return 0; 8127 case 5: return 0; 8128 case 4: 8129 if (devinfo->is_g4x) { 8130 return 0; 8131 } else { 8132 return 0; 8133 } 8134 default: 8135 unreachable("Invalid hardware generation"); 8136 } 8137 } 8138 8139 8140 8141 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 8142 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 8143 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 8144 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 8145 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 8146 8147 static inline uint32_t ATTRIBUTE_PURE 8148 _3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start(const struct gen_device_info *devinfo) 8149 { 8150 switch (devinfo->gen) { 8151 case 10: return 0; 8152 case 9: return 0; 8153 case 8: return 0; 8154 case 7: 8155 if (devinfo->is_haswell) { 8156 return 0; 8157 } else { 8158 return 0; 8159 } 8160 case 6: return 0; 8161 case 5: return 0; 8162 case 4: 8163 if (devinfo->is_g4x) { 8164 return 0; 8165 } else { 8166 return 0; 8167 } 8168 default: 8169 unreachable("Invalid hardware generation"); 8170 } 8171 } 8172 8173 8174 8175 /* 3DSTATE_BINDING_TABLE_POINTERS_PS::Pointer to PS Binding Table */ 8176 8177 8178 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 8179 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 8180 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 8181 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 8182 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 8183 8184 static inline uint32_t ATTRIBUTE_PURE 8185 _3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits(const struct gen_device_info *devinfo) 8186 { 8187 switch (devinfo->gen) { 8188 case 10: return 11; 8189 case 9: return 11; 8190 case 8: return 11; 8191 case 7: 8192 if (devinfo->is_haswell) { 8193 return 11; 8194 } else { 8195 return 11; 8196 } 8197 case 6: return 0; 8198 case 5: return 0; 8199 case 4: 8200 if (devinfo->is_g4x) { 8201 return 0; 8202 } else { 8203 return 0; 8204 } 8205 default: 8206 unreachable("Invalid hardware generation"); 8207 } 8208 } 8209 8210 8211 8212 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 8213 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 8214 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 8215 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 8216 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 8217 8218 static inline uint32_t ATTRIBUTE_PURE 8219 _3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start(const struct gen_device_info *devinfo) 8220 { 8221 switch (devinfo->gen) { 8222 case 10: return 37; 8223 case 9: return 37; 8224 case 8: return 37; 8225 case 7: 8226 if (devinfo->is_haswell) { 8227 return 37; 8228 } else { 8229 return 37; 8230 } 8231 case 6: return 0; 8232 case 5: return 0; 8233 case 4: 8234 if (devinfo->is_g4x) { 8235 return 0; 8236 } else { 8237 return 0; 8238 } 8239 default: 8240 unreachable("Invalid hardware generation"); 8241 } 8242 } 8243 8244 8245 8246 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */ 8247 8248 8249 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 8250 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 8251 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 8252 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 8253 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 8254 8255 static inline uint32_t ATTRIBUTE_PURE 8256 _3DSTATE_BINDING_TABLE_POINTERS_VS_length(const struct gen_device_info *devinfo) 8257 { 8258 switch (devinfo->gen) { 8259 case 10: return 2; 8260 case 9: return 2; 8261 case 8: return 2; 8262 case 7: 8263 if (devinfo->is_haswell) { 8264 return 2; 8265 } else { 8266 return 2; 8267 } 8268 case 6: return 0; 8269 case 5: return 0; 8270 case 4: 8271 if (devinfo->is_g4x) { 8272 return 0; 8273 } else { 8274 return 0; 8275 } 8276 default: 8277 unreachable("Invalid hardware generation"); 8278 } 8279 } 8280 8281 8282 8283 /* 3DSTATE_BINDING_TABLE_POINTERS_VS::3D Command Opcode */ 8284 8285 8286 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 8287 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 8288 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 8289 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 8290 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 8291 8292 static inline uint32_t ATTRIBUTE_PURE 8293 _3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 8294 { 8295 switch (devinfo->gen) { 8296 case 10: return 3; 8297 case 9: return 3; 8298 case 8: return 3; 8299 case 7: 8300 if (devinfo->is_haswell) { 8301 return 3; 8302 } else { 8303 return 3; 8304 } 8305 case 6: return 0; 8306 case 5: return 0; 8307 case 4: 8308 if (devinfo->is_g4x) { 8309 return 0; 8310 } else { 8311 return 0; 8312 } 8313 default: 8314 unreachable("Invalid hardware generation"); 8315 } 8316 } 8317 8318 8319 8320 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 8321 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 8322 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 8323 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 8324 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 8325 8326 static inline uint32_t ATTRIBUTE_PURE 8327 _3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 8328 { 8329 switch (devinfo->gen) { 8330 case 10: return 24; 8331 case 9: return 24; 8332 case 8: return 24; 8333 case 7: 8334 if (devinfo->is_haswell) { 8335 return 24; 8336 } else { 8337 return 24; 8338 } 8339 case 6: return 0; 8340 case 5: return 0; 8341 case 4: 8342 if (devinfo->is_g4x) { 8343 return 0; 8344 } else { 8345 return 0; 8346 } 8347 default: 8348 unreachable("Invalid hardware generation"); 8349 } 8350 } 8351 8352 8353 8354 /* 3DSTATE_BINDING_TABLE_POINTERS_VS::3D Command Sub Opcode */ 8355 8356 8357 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 8358 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 8359 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 8360 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 8361 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 8362 8363 static inline uint32_t ATTRIBUTE_PURE 8364 _3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 8365 { 8366 switch (devinfo->gen) { 8367 case 10: return 8; 8368 case 9: return 8; 8369 case 8: return 8; 8370 case 7: 8371 if (devinfo->is_haswell) { 8372 return 8; 8373 } else { 8374 return 8; 8375 } 8376 case 6: return 0; 8377 case 5: return 0; 8378 case 4: 8379 if (devinfo->is_g4x) { 8380 return 0; 8381 } else { 8382 return 0; 8383 } 8384 default: 8385 unreachable("Invalid hardware generation"); 8386 } 8387 } 8388 8389 8390 8391 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 8392 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 8393 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 8394 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 8395 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 8396 8397 static inline uint32_t ATTRIBUTE_PURE 8398 _3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 8399 { 8400 switch (devinfo->gen) { 8401 case 10: return 16; 8402 case 9: return 16; 8403 case 8: return 16; 8404 case 7: 8405 if (devinfo->is_haswell) { 8406 return 16; 8407 } else { 8408 return 16; 8409 } 8410 case 6: return 0; 8411 case 5: return 0; 8412 case 4: 8413 if (devinfo->is_g4x) { 8414 return 0; 8415 } else { 8416 return 0; 8417 } 8418 default: 8419 unreachable("Invalid hardware generation"); 8420 } 8421 } 8422 8423 8424 8425 /* 3DSTATE_BINDING_TABLE_POINTERS_VS::Command SubType */ 8426 8427 8428 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 8429 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 8430 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 8431 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 8432 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 8433 8434 static inline uint32_t ATTRIBUTE_PURE 8435 _3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits(const struct gen_device_info *devinfo) 8436 { 8437 switch (devinfo->gen) { 8438 case 10: return 2; 8439 case 9: return 2; 8440 case 8: return 2; 8441 case 7: 8442 if (devinfo->is_haswell) { 8443 return 2; 8444 } else { 8445 return 2; 8446 } 8447 case 6: return 0; 8448 case 5: return 0; 8449 case 4: 8450 if (devinfo->is_g4x) { 8451 return 0; 8452 } else { 8453 return 0; 8454 } 8455 default: 8456 unreachable("Invalid hardware generation"); 8457 } 8458 } 8459 8460 8461 8462 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 8463 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 8464 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 8465 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 8466 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 8467 8468 static inline uint32_t ATTRIBUTE_PURE 8469 _3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start(const struct gen_device_info *devinfo) 8470 { 8471 switch (devinfo->gen) { 8472 case 10: return 27; 8473 case 9: return 27; 8474 case 8: return 27; 8475 case 7: 8476 if (devinfo->is_haswell) { 8477 return 27; 8478 } else { 8479 return 27; 8480 } 8481 case 6: return 0; 8482 case 5: return 0; 8483 case 4: 8484 if (devinfo->is_g4x) { 8485 return 0; 8486 } else { 8487 return 0; 8488 } 8489 default: 8490 unreachable("Invalid hardware generation"); 8491 } 8492 } 8493 8494 8495 8496 /* 3DSTATE_BINDING_TABLE_POINTERS_VS::Command Type */ 8497 8498 8499 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 8500 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 8501 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 8502 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 8503 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 8504 8505 static inline uint32_t ATTRIBUTE_PURE 8506 _3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits(const struct gen_device_info *devinfo) 8507 { 8508 switch (devinfo->gen) { 8509 case 10: return 3; 8510 case 9: return 3; 8511 case 8: return 3; 8512 case 7: 8513 if (devinfo->is_haswell) { 8514 return 3; 8515 } else { 8516 return 3; 8517 } 8518 case 6: return 0; 8519 case 5: return 0; 8520 case 4: 8521 if (devinfo->is_g4x) { 8522 return 0; 8523 } else { 8524 return 0; 8525 } 8526 default: 8527 unreachable("Invalid hardware generation"); 8528 } 8529 } 8530 8531 8532 8533 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 8534 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 8535 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 8536 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 8537 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 8538 8539 static inline uint32_t ATTRIBUTE_PURE 8540 _3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start(const struct gen_device_info *devinfo) 8541 { 8542 switch (devinfo->gen) { 8543 case 10: return 29; 8544 case 9: return 29; 8545 case 8: return 29; 8546 case 7: 8547 if (devinfo->is_haswell) { 8548 return 29; 8549 } else { 8550 return 29; 8551 } 8552 case 6: return 0; 8553 case 5: return 0; 8554 case 4: 8555 if (devinfo->is_g4x) { 8556 return 0; 8557 } else { 8558 return 0; 8559 } 8560 default: 8561 unreachable("Invalid hardware generation"); 8562 } 8563 } 8564 8565 8566 8567 /* 3DSTATE_BINDING_TABLE_POINTERS_VS::DWord Length */ 8568 8569 8570 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 8571 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 8572 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 8573 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 8574 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 8575 8576 static inline uint32_t ATTRIBUTE_PURE 8577 _3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits(const struct gen_device_info *devinfo) 8578 { 8579 switch (devinfo->gen) { 8580 case 10: return 8; 8581 case 9: return 8; 8582 case 8: return 8; 8583 case 7: 8584 if (devinfo->is_haswell) { 8585 return 8; 8586 } else { 8587 return 8; 8588 } 8589 case 6: return 0; 8590 case 5: return 0; 8591 case 4: 8592 if (devinfo->is_g4x) { 8593 return 0; 8594 } else { 8595 return 0; 8596 } 8597 default: 8598 unreachable("Invalid hardware generation"); 8599 } 8600 } 8601 8602 8603 8604 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 8605 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 8606 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 8607 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 8608 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 8609 8610 static inline uint32_t ATTRIBUTE_PURE 8611 _3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start(const struct gen_device_info *devinfo) 8612 { 8613 switch (devinfo->gen) { 8614 case 10: return 0; 8615 case 9: return 0; 8616 case 8: return 0; 8617 case 7: 8618 if (devinfo->is_haswell) { 8619 return 0; 8620 } else { 8621 return 0; 8622 } 8623 case 6: return 0; 8624 case 5: return 0; 8625 case 4: 8626 if (devinfo->is_g4x) { 8627 return 0; 8628 } else { 8629 return 0; 8630 } 8631 default: 8632 unreachable("Invalid hardware generation"); 8633 } 8634 } 8635 8636 8637 8638 /* 3DSTATE_BINDING_TABLE_POINTERS_VS::Pointer to VS Binding Table */ 8639 8640 8641 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 8642 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 8643 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 8644 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 8645 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 8646 8647 static inline uint32_t ATTRIBUTE_PURE 8648 _3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits(const struct gen_device_info *devinfo) 8649 { 8650 switch (devinfo->gen) { 8651 case 10: return 11; 8652 case 9: return 11; 8653 case 8: return 11; 8654 case 7: 8655 if (devinfo->is_haswell) { 8656 return 11; 8657 } else { 8658 return 11; 8659 } 8660 case 6: return 0; 8661 case 5: return 0; 8662 case 4: 8663 if (devinfo->is_g4x) { 8664 return 0; 8665 } else { 8666 return 0; 8667 } 8668 default: 8669 unreachable("Invalid hardware generation"); 8670 } 8671 } 8672 8673 8674 8675 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 8676 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 8677 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 8678 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 8679 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 8680 8681 static inline uint32_t ATTRIBUTE_PURE 8682 _3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start(const struct gen_device_info *devinfo) 8683 { 8684 switch (devinfo->gen) { 8685 case 10: return 37; 8686 case 9: return 37; 8687 case 8: return 37; 8688 case 7: 8689 if (devinfo->is_haswell) { 8690 return 37; 8691 } else { 8692 return 37; 8693 } 8694 case 6: return 0; 8695 case 5: return 0; 8696 case 4: 8697 if (devinfo->is_g4x) { 8698 return 0; 8699 } else { 8700 return 0; 8701 } 8702 default: 8703 unreachable("Invalid hardware generation"); 8704 } 8705 } 8706 8707 8708 8709 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC */ 8710 8711 8712 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 8713 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 8714 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 8715 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 3 8716 8717 static inline uint32_t ATTRIBUTE_PURE 8718 _3DSTATE_BINDING_TABLE_POOL_ALLOC_length(const struct gen_device_info *devinfo) 8719 { 8720 switch (devinfo->gen) { 8721 case 10: return 4; 8722 case 9: return 4; 8723 case 8: return 4; 8724 case 7: 8725 if (devinfo->is_haswell) { 8726 return 3; 8727 } else { 8728 return 0; 8729 } 8730 case 6: return 0; 8731 case 5: return 0; 8732 case 4: 8733 if (devinfo->is_g4x) { 8734 return 0; 8735 } else { 8736 return 0; 8737 } 8738 default: 8739 unreachable("Invalid hardware generation"); 8740 } 8741 } 8742 8743 8744 8745 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::3D Command Opcode */ 8746 8747 8748 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 8749 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 8750 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 8751 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 8752 8753 static inline uint32_t ATTRIBUTE_PURE 8754 _3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 8755 { 8756 switch (devinfo->gen) { 8757 case 10: return 3; 8758 case 9: return 3; 8759 case 8: return 3; 8760 case 7: 8761 if (devinfo->is_haswell) { 8762 return 3; 8763 } else { 8764 return 0; 8765 } 8766 case 6: return 0; 8767 case 5: return 0; 8768 case 4: 8769 if (devinfo->is_g4x) { 8770 return 0; 8771 } else { 8772 return 0; 8773 } 8774 default: 8775 unreachable("Invalid hardware generation"); 8776 } 8777 } 8778 8779 8780 8781 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 8782 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 8783 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 8784 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 8785 8786 static inline uint32_t ATTRIBUTE_PURE 8787 _3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start(const struct gen_device_info *devinfo) 8788 { 8789 switch (devinfo->gen) { 8790 case 10: return 24; 8791 case 9: return 24; 8792 case 8: return 24; 8793 case 7: 8794 if (devinfo->is_haswell) { 8795 return 24; 8796 } else { 8797 return 0; 8798 } 8799 case 6: return 0; 8800 case 5: return 0; 8801 case 4: 8802 if (devinfo->is_g4x) { 8803 return 0; 8804 } else { 8805 return 0; 8806 } 8807 default: 8808 unreachable("Invalid hardware generation"); 8809 } 8810 } 8811 8812 8813 8814 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::3D Command Sub Opcode */ 8815 8816 8817 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 8818 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 8819 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 8820 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 8821 8822 static inline uint32_t ATTRIBUTE_PURE 8823 _3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 8824 { 8825 switch (devinfo->gen) { 8826 case 10: return 8; 8827 case 9: return 8; 8828 case 8: return 8; 8829 case 7: 8830 if (devinfo->is_haswell) { 8831 return 8; 8832 } else { 8833 return 0; 8834 } 8835 case 6: return 0; 8836 case 5: return 0; 8837 case 4: 8838 if (devinfo->is_g4x) { 8839 return 0; 8840 } else { 8841 return 0; 8842 } 8843 default: 8844 unreachable("Invalid hardware generation"); 8845 } 8846 } 8847 8848 8849 8850 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 8851 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 8852 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 8853 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 8854 8855 static inline uint32_t ATTRIBUTE_PURE 8856 _3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 8857 { 8858 switch (devinfo->gen) { 8859 case 10: return 16; 8860 case 9: return 16; 8861 case 8: return 16; 8862 case 7: 8863 if (devinfo->is_haswell) { 8864 return 16; 8865 } else { 8866 return 0; 8867 } 8868 case 6: return 0; 8869 case 5: return 0; 8870 case 4: 8871 if (devinfo->is_g4x) { 8872 return 0; 8873 } else { 8874 return 0; 8875 } 8876 default: 8877 unreachable("Invalid hardware generation"); 8878 } 8879 } 8880 8881 8882 8883 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Base Address */ 8884 8885 8886 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 8887 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 8888 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 8889 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 20 8890 8891 static inline uint32_t ATTRIBUTE_PURE 8892 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits(const struct gen_device_info *devinfo) 8893 { 8894 switch (devinfo->gen) { 8895 case 10: return 52; 8896 case 9: return 52; 8897 case 8: return 52; 8898 case 7: 8899 if (devinfo->is_haswell) { 8900 return 20; 8901 } else { 8902 return 0; 8903 } 8904 case 6: return 0; 8905 case 5: return 0; 8906 case 4: 8907 if (devinfo->is_g4x) { 8908 return 0; 8909 } else { 8910 return 0; 8911 } 8912 default: 8913 unreachable("Invalid hardware generation"); 8914 } 8915 } 8916 8917 8918 8919 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 8920 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 8921 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 8922 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 8923 8924 static inline uint32_t ATTRIBUTE_PURE 8925 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start(const struct gen_device_info *devinfo) 8926 { 8927 switch (devinfo->gen) { 8928 case 10: return 44; 8929 case 9: return 44; 8930 case 8: return 44; 8931 case 7: 8932 if (devinfo->is_haswell) { 8933 return 44; 8934 } else { 8935 return 0; 8936 } 8937 case 6: return 0; 8938 case 5: return 0; 8939 case 4: 8940 if (devinfo->is_g4x) { 8941 return 0; 8942 } else { 8943 return 0; 8944 } 8945 default: 8946 unreachable("Invalid hardware generation"); 8947 } 8948 } 8949 8950 8951 8952 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Buffer Size */ 8953 8954 8955 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 8956 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 8957 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 8958 8959 static inline uint32_t ATTRIBUTE_PURE 8960 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits(const struct gen_device_info *devinfo) 8961 { 8962 switch (devinfo->gen) { 8963 case 10: return 20; 8964 case 9: return 20; 8965 case 8: return 20; 8966 case 7: 8967 if (devinfo->is_haswell) { 8968 return 0; 8969 } else { 8970 return 0; 8971 } 8972 case 6: return 0; 8973 case 5: return 0; 8974 case 4: 8975 if (devinfo->is_g4x) { 8976 return 0; 8977 } else { 8978 return 0; 8979 } 8980 default: 8981 unreachable("Invalid hardware generation"); 8982 } 8983 } 8984 8985 8986 8987 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 8988 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 8989 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 8990 8991 static inline uint32_t ATTRIBUTE_PURE 8992 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start(const struct gen_device_info *devinfo) 8993 { 8994 switch (devinfo->gen) { 8995 case 10: return 108; 8996 case 9: return 108; 8997 case 8: return 108; 8998 case 7: 8999 if (devinfo->is_haswell) { 9000 return 0; 9001 } else { 9002 return 0; 9003 } 9004 case 6: return 0; 9005 case 5: return 0; 9006 case 4: 9007 if (devinfo->is_g4x) { 9008 return 0; 9009 } else { 9010 return 0; 9011 } 9012 default: 9013 unreachable("Invalid hardware generation"); 9014 } 9015 } 9016 9017 9018 9019 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Enable */ 9020 9021 9022 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 9023 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 9024 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 9025 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 9026 9027 static inline uint32_t ATTRIBUTE_PURE 9028 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits(const struct gen_device_info *devinfo) 9029 { 9030 switch (devinfo->gen) { 9031 case 10: return 1; 9032 case 9: return 1; 9033 case 8: return 1; 9034 case 7: 9035 if (devinfo->is_haswell) { 9036 return 1; 9037 } else { 9038 return 0; 9039 } 9040 case 6: return 0; 9041 case 5: return 0; 9042 case 4: 9043 if (devinfo->is_g4x) { 9044 return 0; 9045 } else { 9046 return 0; 9047 } 9048 default: 9049 unreachable("Invalid hardware generation"); 9050 } 9051 } 9052 9053 9054 9055 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 9056 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 9057 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 9058 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 9059 9060 static inline uint32_t ATTRIBUTE_PURE 9061 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start(const struct gen_device_info *devinfo) 9062 { 9063 switch (devinfo->gen) { 9064 case 10: return 43; 9065 case 9: return 43; 9066 case 8: return 43; 9067 case 7: 9068 if (devinfo->is_haswell) { 9069 return 43; 9070 } else { 9071 return 0; 9072 } 9073 case 6: return 0; 9074 case 5: return 0; 9075 case 4: 9076 if (devinfo->is_g4x) { 9077 return 0; 9078 } else { 9079 return 0; 9080 } 9081 default: 9082 unreachable("Invalid hardware generation"); 9083 } 9084 } 9085 9086 9087 9088 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Upper Bound */ 9089 9090 9091 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_bits 20 9092 9093 static inline uint32_t ATTRIBUTE_PURE 9094 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_bits(const struct gen_device_info *devinfo) 9095 { 9096 switch (devinfo->gen) { 9097 case 10: return 0; 9098 case 9: return 0; 9099 case 8: return 0; 9100 case 7: 9101 if (devinfo->is_haswell) { 9102 return 20; 9103 } else { 9104 return 0; 9105 } 9106 case 6: return 0; 9107 case 5: return 0; 9108 case 4: 9109 if (devinfo->is_g4x) { 9110 return 0; 9111 } else { 9112 return 0; 9113 } 9114 default: 9115 unreachable("Invalid hardware generation"); 9116 } 9117 } 9118 9119 9120 9121 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_start 76 9122 9123 static inline uint32_t ATTRIBUTE_PURE 9124 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_start(const struct gen_device_info *devinfo) 9125 { 9126 switch (devinfo->gen) { 9127 case 10: return 0; 9128 case 9: return 0; 9129 case 8: return 0; 9130 case 7: 9131 if (devinfo->is_haswell) { 9132 return 76; 9133 } else { 9134 return 0; 9135 } 9136 case 6: return 0; 9137 case 5: return 0; 9138 case 4: 9139 if (devinfo->is_g4x) { 9140 return 0; 9141 } else { 9142 return 0; 9143 } 9144 default: 9145 unreachable("Invalid hardware generation"); 9146 } 9147 } 9148 9149 9150 9151 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Command SubType */ 9152 9153 9154 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 9155 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 9156 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 9157 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 9158 9159 static inline uint32_t ATTRIBUTE_PURE 9160 _3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits(const struct gen_device_info *devinfo) 9161 { 9162 switch (devinfo->gen) { 9163 case 10: return 2; 9164 case 9: return 2; 9165 case 8: return 2; 9166 case 7: 9167 if (devinfo->is_haswell) { 9168 return 2; 9169 } else { 9170 return 0; 9171 } 9172 case 6: return 0; 9173 case 5: return 0; 9174 case 4: 9175 if (devinfo->is_g4x) { 9176 return 0; 9177 } else { 9178 return 0; 9179 } 9180 default: 9181 unreachable("Invalid hardware generation"); 9182 } 9183 } 9184 9185 9186 9187 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 9188 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 9189 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 9190 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 9191 9192 static inline uint32_t ATTRIBUTE_PURE 9193 _3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start(const struct gen_device_info *devinfo) 9194 { 9195 switch (devinfo->gen) { 9196 case 10: return 27; 9197 case 9: return 27; 9198 case 8: return 27; 9199 case 7: 9200 if (devinfo->is_haswell) { 9201 return 27; 9202 } else { 9203 return 0; 9204 } 9205 case 6: return 0; 9206 case 5: return 0; 9207 case 4: 9208 if (devinfo->is_g4x) { 9209 return 0; 9210 } else { 9211 return 0; 9212 } 9213 default: 9214 unreachable("Invalid hardware generation"); 9215 } 9216 } 9217 9218 9219 9220 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Command Type */ 9221 9222 9223 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 9224 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 9225 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 9226 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 9227 9228 static inline uint32_t ATTRIBUTE_PURE 9229 _3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits(const struct gen_device_info *devinfo) 9230 { 9231 switch (devinfo->gen) { 9232 case 10: return 3; 9233 case 9: return 3; 9234 case 8: return 3; 9235 case 7: 9236 if (devinfo->is_haswell) { 9237 return 3; 9238 } else { 9239 return 0; 9240 } 9241 case 6: return 0; 9242 case 5: return 0; 9243 case 4: 9244 if (devinfo->is_g4x) { 9245 return 0; 9246 } else { 9247 return 0; 9248 } 9249 default: 9250 unreachable("Invalid hardware generation"); 9251 } 9252 } 9253 9254 9255 9256 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 9257 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 9258 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 9259 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 9260 9261 static inline uint32_t ATTRIBUTE_PURE 9262 _3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start(const struct gen_device_info *devinfo) 9263 { 9264 switch (devinfo->gen) { 9265 case 10: return 29; 9266 case 9: return 29; 9267 case 8: return 29; 9268 case 7: 9269 if (devinfo->is_haswell) { 9270 return 29; 9271 } else { 9272 return 0; 9273 } 9274 case 6: return 0; 9275 case 5: return 0; 9276 case 4: 9277 if (devinfo->is_g4x) { 9278 return 0; 9279 } else { 9280 return 0; 9281 } 9282 default: 9283 unreachable("Invalid hardware generation"); 9284 } 9285 } 9286 9287 9288 9289 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::DWord Length */ 9290 9291 9292 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 9293 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 9294 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 9295 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 9296 9297 static inline uint32_t ATTRIBUTE_PURE 9298 _3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits(const struct gen_device_info *devinfo) 9299 { 9300 switch (devinfo->gen) { 9301 case 10: return 8; 9302 case 9: return 8; 9303 case 8: return 8; 9304 case 7: 9305 if (devinfo->is_haswell) { 9306 return 8; 9307 } else { 9308 return 0; 9309 } 9310 case 6: return 0; 9311 case 5: return 0; 9312 case 4: 9313 if (devinfo->is_g4x) { 9314 return 0; 9315 } else { 9316 return 0; 9317 } 9318 default: 9319 unreachable("Invalid hardware generation"); 9320 } 9321 } 9322 9323 9324 9325 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 9326 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 9327 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 9328 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 9329 9330 static inline uint32_t ATTRIBUTE_PURE 9331 _3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start(const struct gen_device_info *devinfo) 9332 { 9333 switch (devinfo->gen) { 9334 case 10: return 0; 9335 case 9: return 0; 9336 case 8: return 0; 9337 case 7: 9338 if (devinfo->is_haswell) { 9339 return 0; 9340 } else { 9341 return 0; 9342 } 9343 case 6: return 0; 9344 case 5: return 0; 9345 case 4: 9346 if (devinfo->is_g4x) { 9347 return 0; 9348 } else { 9349 return 0; 9350 } 9351 default: 9352 unreachable("Invalid hardware generation"); 9353 } 9354 } 9355 9356 9357 9358 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Surface Object Control State */ 9359 9360 9361 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 7 9362 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 7 9363 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 7 9364 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 4 9365 9366 static inline uint32_t ATTRIBUTE_PURE 9367 _3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits(const struct gen_device_info *devinfo) 9368 { 9369 switch (devinfo->gen) { 9370 case 10: return 7; 9371 case 9: return 7; 9372 case 8: return 7; 9373 case 7: 9374 if (devinfo->is_haswell) { 9375 return 4; 9376 } else { 9377 return 0; 9378 } 9379 case 6: return 0; 9380 case 5: return 0; 9381 case 4: 9382 if (devinfo->is_g4x) { 9383 return 0; 9384 } else { 9385 return 0; 9386 } 9387 default: 9388 unreachable("Invalid hardware generation"); 9389 } 9390 } 9391 9392 9393 9394 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 32 9395 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 32 9396 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 32 9397 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 39 9398 9399 static inline uint32_t ATTRIBUTE_PURE 9400 _3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start(const struct gen_device_info *devinfo) 9401 { 9402 switch (devinfo->gen) { 9403 case 10: return 32; 9404 case 9: return 32; 9405 case 8: return 32; 9406 case 7: 9407 if (devinfo->is_haswell) { 9408 return 39; 9409 } else { 9410 return 0; 9411 } 9412 case 6: return 0; 9413 case 5: return 0; 9414 case 4: 9415 if (devinfo->is_g4x) { 9416 return 0; 9417 } else { 9418 return 0; 9419 } 9420 default: 9421 unreachable("Invalid hardware generation"); 9422 } 9423 } 9424 9425 9426 9427 /* 3DSTATE_BLEND_STATE_POINTERS */ 9428 9429 9430 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_length 2 9431 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_length 2 9432 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_length 2 9433 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_length 2 9434 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_length 2 9435 9436 static inline uint32_t ATTRIBUTE_PURE 9437 _3DSTATE_BLEND_STATE_POINTERS_length(const struct gen_device_info *devinfo) 9438 { 9439 switch (devinfo->gen) { 9440 case 10: return 2; 9441 case 9: return 2; 9442 case 8: return 2; 9443 case 7: 9444 if (devinfo->is_haswell) { 9445 return 2; 9446 } else { 9447 return 2; 9448 } 9449 case 6: return 0; 9450 case 5: return 0; 9451 case 4: 9452 if (devinfo->is_g4x) { 9453 return 0; 9454 } else { 9455 return 0; 9456 } 9457 default: 9458 unreachable("Invalid hardware generation"); 9459 } 9460 } 9461 9462 9463 9464 /* 3DSTATE_BLEND_STATE_POINTERS::3D Command Opcode */ 9465 9466 9467 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 9468 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 9469 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 9470 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 9471 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 9472 9473 static inline uint32_t ATTRIBUTE_PURE 9474 _3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 9475 { 9476 switch (devinfo->gen) { 9477 case 10: return 3; 9478 case 9: return 3; 9479 case 8: return 3; 9480 case 7: 9481 if (devinfo->is_haswell) { 9482 return 3; 9483 } else { 9484 return 3; 9485 } 9486 case 6: return 0; 9487 case 5: return 0; 9488 case 4: 9489 if (devinfo->is_g4x) { 9490 return 0; 9491 } else { 9492 return 0; 9493 } 9494 default: 9495 unreachable("Invalid hardware generation"); 9496 } 9497 } 9498 9499 9500 9501 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 9502 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 9503 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 9504 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 9505 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 9506 9507 static inline uint32_t ATTRIBUTE_PURE 9508 _3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 9509 { 9510 switch (devinfo->gen) { 9511 case 10: return 24; 9512 case 9: return 24; 9513 case 8: return 24; 9514 case 7: 9515 if (devinfo->is_haswell) { 9516 return 24; 9517 } else { 9518 return 24; 9519 } 9520 case 6: return 0; 9521 case 5: return 0; 9522 case 4: 9523 if (devinfo->is_g4x) { 9524 return 0; 9525 } else { 9526 return 0; 9527 } 9528 default: 9529 unreachable("Invalid hardware generation"); 9530 } 9531 } 9532 9533 9534 9535 /* 3DSTATE_BLEND_STATE_POINTERS::3D Command Sub Opcode */ 9536 9537 9538 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 9539 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 9540 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 9541 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 9542 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 9543 9544 static inline uint32_t ATTRIBUTE_PURE 9545 _3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 9546 { 9547 switch (devinfo->gen) { 9548 case 10: return 8; 9549 case 9: return 8; 9550 case 8: return 8; 9551 case 7: 9552 if (devinfo->is_haswell) { 9553 return 8; 9554 } else { 9555 return 8; 9556 } 9557 case 6: return 0; 9558 case 5: return 0; 9559 case 4: 9560 if (devinfo->is_g4x) { 9561 return 0; 9562 } else { 9563 return 0; 9564 } 9565 default: 9566 unreachable("Invalid hardware generation"); 9567 } 9568 } 9569 9570 9571 9572 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 9573 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 9574 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 9575 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 9576 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 9577 9578 static inline uint32_t ATTRIBUTE_PURE 9579 _3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 9580 { 9581 switch (devinfo->gen) { 9582 case 10: return 16; 9583 case 9: return 16; 9584 case 8: return 16; 9585 case 7: 9586 if (devinfo->is_haswell) { 9587 return 16; 9588 } else { 9589 return 16; 9590 } 9591 case 6: return 0; 9592 case 5: return 0; 9593 case 4: 9594 if (devinfo->is_g4x) { 9595 return 0; 9596 } else { 9597 return 0; 9598 } 9599 default: 9600 unreachable("Invalid hardware generation"); 9601 } 9602 } 9603 9604 9605 9606 /* 3DSTATE_BLEND_STATE_POINTERS::Blend State Pointer */ 9607 9608 9609 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 9610 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 9611 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 9612 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 9613 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 9614 9615 static inline uint32_t ATTRIBUTE_PURE 9616 _3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits(const struct gen_device_info *devinfo) 9617 { 9618 switch (devinfo->gen) { 9619 case 10: return 26; 9620 case 9: return 26; 9621 case 8: return 26; 9622 case 7: 9623 if (devinfo->is_haswell) { 9624 return 26; 9625 } else { 9626 return 26; 9627 } 9628 case 6: return 0; 9629 case 5: return 0; 9630 case 4: 9631 if (devinfo->is_g4x) { 9632 return 0; 9633 } else { 9634 return 0; 9635 } 9636 default: 9637 unreachable("Invalid hardware generation"); 9638 } 9639 } 9640 9641 9642 9643 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 9644 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 9645 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 9646 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 9647 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 9648 9649 static inline uint32_t ATTRIBUTE_PURE 9650 _3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start(const struct gen_device_info *devinfo) 9651 { 9652 switch (devinfo->gen) { 9653 case 10: return 38; 9654 case 9: return 38; 9655 case 8: return 38; 9656 case 7: 9657 if (devinfo->is_haswell) { 9658 return 38; 9659 } else { 9660 return 38; 9661 } 9662 case 6: return 0; 9663 case 5: return 0; 9664 case 4: 9665 if (devinfo->is_g4x) { 9666 return 0; 9667 } else { 9668 return 0; 9669 } 9670 default: 9671 unreachable("Invalid hardware generation"); 9672 } 9673 } 9674 9675 9676 9677 /* 3DSTATE_BLEND_STATE_POINTERS::Blend State Pointer Valid */ 9678 9679 9680 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 9681 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 9682 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 9683 9684 static inline uint32_t ATTRIBUTE_PURE 9685 _3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits(const struct gen_device_info *devinfo) 9686 { 9687 switch (devinfo->gen) { 9688 case 10: return 1; 9689 case 9: return 1; 9690 case 8: return 1; 9691 case 7: 9692 if (devinfo->is_haswell) { 9693 return 0; 9694 } else { 9695 return 0; 9696 } 9697 case 6: return 0; 9698 case 5: return 0; 9699 case 4: 9700 if (devinfo->is_g4x) { 9701 return 0; 9702 } else { 9703 return 0; 9704 } 9705 default: 9706 unreachable("Invalid hardware generation"); 9707 } 9708 } 9709 9710 9711 9712 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 9713 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 9714 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 9715 9716 static inline uint32_t ATTRIBUTE_PURE 9717 _3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start(const struct gen_device_info *devinfo) 9718 { 9719 switch (devinfo->gen) { 9720 case 10: return 32; 9721 case 9: return 32; 9722 case 8: return 32; 9723 case 7: 9724 if (devinfo->is_haswell) { 9725 return 0; 9726 } else { 9727 return 0; 9728 } 9729 case 6: return 0; 9730 case 5: return 0; 9731 case 4: 9732 if (devinfo->is_g4x) { 9733 return 0; 9734 } else { 9735 return 0; 9736 } 9737 default: 9738 unreachable("Invalid hardware generation"); 9739 } 9740 } 9741 9742 9743 9744 /* 3DSTATE_BLEND_STATE_POINTERS::Command SubType */ 9745 9746 9747 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 9748 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 9749 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 9750 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 9751 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 9752 9753 static inline uint32_t ATTRIBUTE_PURE 9754 _3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) 9755 { 9756 switch (devinfo->gen) { 9757 case 10: return 2; 9758 case 9: return 2; 9759 case 8: return 2; 9760 case 7: 9761 if (devinfo->is_haswell) { 9762 return 2; 9763 } else { 9764 return 2; 9765 } 9766 case 6: return 0; 9767 case 5: return 0; 9768 case 4: 9769 if (devinfo->is_g4x) { 9770 return 0; 9771 } else { 9772 return 0; 9773 } 9774 default: 9775 unreachable("Invalid hardware generation"); 9776 } 9777 } 9778 9779 9780 9781 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 9782 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 9783 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 9784 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 9785 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 9786 9787 static inline uint32_t ATTRIBUTE_PURE 9788 _3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) 9789 { 9790 switch (devinfo->gen) { 9791 case 10: return 27; 9792 case 9: return 27; 9793 case 8: return 27; 9794 case 7: 9795 if (devinfo->is_haswell) { 9796 return 27; 9797 } else { 9798 return 27; 9799 } 9800 case 6: return 0; 9801 case 5: return 0; 9802 case 4: 9803 if (devinfo->is_g4x) { 9804 return 0; 9805 } else { 9806 return 0; 9807 } 9808 default: 9809 unreachable("Invalid hardware generation"); 9810 } 9811 } 9812 9813 9814 9815 /* 3DSTATE_BLEND_STATE_POINTERS::Command Type */ 9816 9817 9818 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 9819 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 9820 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 9821 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 9822 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 9823 9824 static inline uint32_t ATTRIBUTE_PURE 9825 _3DSTATE_BLEND_STATE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) 9826 { 9827 switch (devinfo->gen) { 9828 case 10: return 3; 9829 case 9: return 3; 9830 case 8: return 3; 9831 case 7: 9832 if (devinfo->is_haswell) { 9833 return 3; 9834 } else { 9835 return 3; 9836 } 9837 case 6: return 0; 9838 case 5: return 0; 9839 case 4: 9840 if (devinfo->is_g4x) { 9841 return 0; 9842 } else { 9843 return 0; 9844 } 9845 default: 9846 unreachable("Invalid hardware generation"); 9847 } 9848 } 9849 9850 9851 9852 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 9853 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 9854 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 9855 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 9856 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 9857 9858 static inline uint32_t ATTRIBUTE_PURE 9859 _3DSTATE_BLEND_STATE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) 9860 { 9861 switch (devinfo->gen) { 9862 case 10: return 29; 9863 case 9: return 29; 9864 case 8: return 29; 9865 case 7: 9866 if (devinfo->is_haswell) { 9867 return 29; 9868 } else { 9869 return 29; 9870 } 9871 case 6: return 0; 9872 case 5: return 0; 9873 case 4: 9874 if (devinfo->is_g4x) { 9875 return 0; 9876 } else { 9877 return 0; 9878 } 9879 default: 9880 unreachable("Invalid hardware generation"); 9881 } 9882 } 9883 9884 9885 9886 /* 3DSTATE_BLEND_STATE_POINTERS::DWord Length */ 9887 9888 9889 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 9890 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 9891 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 9892 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 9893 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 9894 9895 static inline uint32_t ATTRIBUTE_PURE 9896 _3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) 9897 { 9898 switch (devinfo->gen) { 9899 case 10: return 8; 9900 case 9: return 8; 9901 case 8: return 8; 9902 case 7: 9903 if (devinfo->is_haswell) { 9904 return 8; 9905 } else { 9906 return 8; 9907 } 9908 case 6: return 0; 9909 case 5: return 0; 9910 case 4: 9911 if (devinfo->is_g4x) { 9912 return 0; 9913 } else { 9914 return 0; 9915 } 9916 default: 9917 unreachable("Invalid hardware generation"); 9918 } 9919 } 9920 9921 9922 9923 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 9924 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 9925 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 9926 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 9927 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 9928 9929 static inline uint32_t ATTRIBUTE_PURE 9930 _3DSTATE_BLEND_STATE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) 9931 { 9932 switch (devinfo->gen) { 9933 case 10: return 0; 9934 case 9: return 0; 9935 case 8: return 0; 9936 case 7: 9937 if (devinfo->is_haswell) { 9938 return 0; 9939 } else { 9940 return 0; 9941 } 9942 case 6: return 0; 9943 case 5: return 0; 9944 case 4: 9945 if (devinfo->is_g4x) { 9946 return 0; 9947 } else { 9948 return 0; 9949 } 9950 default: 9951 unreachable("Invalid hardware generation"); 9952 } 9953 } 9954 9955 9956 9957 /* 3DSTATE_CC_STATE_POINTERS */ 9958 9959 9960 #define GEN10_3DSTATE_CC_STATE_POINTERS_length 2 9961 #define GEN9_3DSTATE_CC_STATE_POINTERS_length 2 9962 #define GEN8_3DSTATE_CC_STATE_POINTERS_length 2 9963 #define GEN75_3DSTATE_CC_STATE_POINTERS_length 2 9964 #define GEN7_3DSTATE_CC_STATE_POINTERS_length 2 9965 #define GEN6_3DSTATE_CC_STATE_POINTERS_length 4 9966 9967 static inline uint32_t ATTRIBUTE_PURE 9968 _3DSTATE_CC_STATE_POINTERS_length(const struct gen_device_info *devinfo) 9969 { 9970 switch (devinfo->gen) { 9971 case 10: return 2; 9972 case 9: return 2; 9973 case 8: return 2; 9974 case 7: 9975 if (devinfo->is_haswell) { 9976 return 2; 9977 } else { 9978 return 2; 9979 } 9980 case 6: return 4; 9981 case 5: return 0; 9982 case 4: 9983 if (devinfo->is_g4x) { 9984 return 0; 9985 } else { 9986 return 0; 9987 } 9988 default: 9989 unreachable("Invalid hardware generation"); 9990 } 9991 } 9992 9993 9994 9995 /* 3DSTATE_CC_STATE_POINTERS::3D Command Opcode */ 9996 9997 9998 #define GEN10_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 9999 #define GEN9_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 10000 #define GEN8_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 10001 #define GEN75_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 10002 #define GEN7_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 10003 #define GEN6_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 10004 10005 static inline uint32_t ATTRIBUTE_PURE 10006 _3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 10007 { 10008 switch (devinfo->gen) { 10009 case 10: return 3; 10010 case 9: return 3; 10011 case 8: return 3; 10012 case 7: 10013 if (devinfo->is_haswell) { 10014 return 3; 10015 } else { 10016 return 3; 10017 } 10018 case 6: return 3; 10019 case 5: return 0; 10020 case 4: 10021 if (devinfo->is_g4x) { 10022 return 0; 10023 } else { 10024 return 0; 10025 } 10026 default: 10027 unreachable("Invalid hardware generation"); 10028 } 10029 } 10030 10031 10032 10033 #define GEN10_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 10034 #define GEN9_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 10035 #define GEN8_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 10036 #define GEN75_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 10037 #define GEN7_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 10038 #define GEN6_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 10039 10040 static inline uint32_t ATTRIBUTE_PURE 10041 _3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 10042 { 10043 switch (devinfo->gen) { 10044 case 10: return 24; 10045 case 9: return 24; 10046 case 8: return 24; 10047 case 7: 10048 if (devinfo->is_haswell) { 10049 return 24; 10050 } else { 10051 return 24; 10052 } 10053 case 6: return 24; 10054 case 5: return 0; 10055 case 4: 10056 if (devinfo->is_g4x) { 10057 return 0; 10058 } else { 10059 return 0; 10060 } 10061 default: 10062 unreachable("Invalid hardware generation"); 10063 } 10064 } 10065 10066 10067 10068 /* 3DSTATE_CC_STATE_POINTERS::3D Command Sub Opcode */ 10069 10070 10071 #define GEN10_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 10072 #define GEN9_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 10073 #define GEN8_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 10074 #define GEN75_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 10075 #define GEN7_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 10076 #define GEN6_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 10077 10078 static inline uint32_t ATTRIBUTE_PURE 10079 _3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 10080 { 10081 switch (devinfo->gen) { 10082 case 10: return 8; 10083 case 9: return 8; 10084 case 8: return 8; 10085 case 7: 10086 if (devinfo->is_haswell) { 10087 return 8; 10088 } else { 10089 return 8; 10090 } 10091 case 6: return 8; 10092 case 5: return 0; 10093 case 4: 10094 if (devinfo->is_g4x) { 10095 return 0; 10096 } else { 10097 return 0; 10098 } 10099 default: 10100 unreachable("Invalid hardware generation"); 10101 } 10102 } 10103 10104 10105 10106 #define GEN10_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 10107 #define GEN9_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 10108 #define GEN8_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 10109 #define GEN75_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 10110 #define GEN7_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 10111 #define GEN6_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 10112 10113 static inline uint32_t ATTRIBUTE_PURE 10114 _3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 10115 { 10116 switch (devinfo->gen) { 10117 case 10: return 16; 10118 case 9: return 16; 10119 case 8: return 16; 10120 case 7: 10121 if (devinfo->is_haswell) { 10122 return 16; 10123 } else { 10124 return 16; 10125 } 10126 case 6: return 16; 10127 case 5: return 0; 10128 case 4: 10129 if (devinfo->is_g4x) { 10130 return 0; 10131 } else { 10132 return 0; 10133 } 10134 default: 10135 unreachable("Invalid hardware generation"); 10136 } 10137 } 10138 10139 10140 10141 /* 3DSTATE_CC_STATE_POINTERS::BLEND_STATE Change */ 10142 10143 10144 #define GEN6_3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_bits 1 10145 10146 static inline uint32_t ATTRIBUTE_PURE 10147 _3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_bits(const struct gen_device_info *devinfo) 10148 { 10149 switch (devinfo->gen) { 10150 case 10: return 0; 10151 case 9: return 0; 10152 case 8: return 0; 10153 case 7: 10154 if (devinfo->is_haswell) { 10155 return 0; 10156 } else { 10157 return 0; 10158 } 10159 case 6: return 1; 10160 case 5: return 0; 10161 case 4: 10162 if (devinfo->is_g4x) { 10163 return 0; 10164 } else { 10165 return 0; 10166 } 10167 default: 10168 unreachable("Invalid hardware generation"); 10169 } 10170 } 10171 10172 10173 10174 #define GEN6_3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_start 32 10175 10176 static inline uint32_t ATTRIBUTE_PURE 10177 _3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_start(const struct gen_device_info *devinfo) 10178 { 10179 switch (devinfo->gen) { 10180 case 10: return 0; 10181 case 9: return 0; 10182 case 8: return 0; 10183 case 7: 10184 if (devinfo->is_haswell) { 10185 return 0; 10186 } else { 10187 return 0; 10188 } 10189 case 6: return 32; 10190 case 5: return 0; 10191 case 4: 10192 if (devinfo->is_g4x) { 10193 return 0; 10194 } else { 10195 return 0; 10196 } 10197 default: 10198 unreachable("Invalid hardware generation"); 10199 } 10200 } 10201 10202 10203 10204 /* 3DSTATE_CC_STATE_POINTERS::Color Calc State Pointer */ 10205 10206 10207 #define GEN10_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 10208 #define GEN9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 10209 #define GEN8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 10210 #define GEN75_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 10211 #define GEN7_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 10212 #define GEN6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 10213 10214 static inline uint32_t ATTRIBUTE_PURE 10215 _3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits(const struct gen_device_info *devinfo) 10216 { 10217 switch (devinfo->gen) { 10218 case 10: return 26; 10219 case 9: return 26; 10220 case 8: return 26; 10221 case 7: 10222 if (devinfo->is_haswell) { 10223 return 26; 10224 } else { 10225 return 26; 10226 } 10227 case 6: return 26; 10228 case 5: return 0; 10229 case 4: 10230 if (devinfo->is_g4x) { 10231 return 0; 10232 } else { 10233 return 0; 10234 } 10235 default: 10236 unreachable("Invalid hardware generation"); 10237 } 10238 } 10239 10240 10241 10242 #define GEN10_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 10243 #define GEN9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 10244 #define GEN8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 10245 #define GEN75_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 10246 #define GEN7_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 10247 #define GEN6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 102 10248 10249 static inline uint32_t ATTRIBUTE_PURE 10250 _3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start(const struct gen_device_info *devinfo) 10251 { 10252 switch (devinfo->gen) { 10253 case 10: return 38; 10254 case 9: return 38; 10255 case 8: return 38; 10256 case 7: 10257 if (devinfo->is_haswell) { 10258 return 38; 10259 } else { 10260 return 38; 10261 } 10262 case 6: return 102; 10263 case 5: return 0; 10264 case 4: 10265 if (devinfo->is_g4x) { 10266 return 0; 10267 } else { 10268 return 0; 10269 } 10270 default: 10271 unreachable("Invalid hardware generation"); 10272 } 10273 } 10274 10275 10276 10277 /* 3DSTATE_CC_STATE_POINTERS::Color Calc State Pointer Valid */ 10278 10279 10280 #define GEN10_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 10281 #define GEN9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 10282 #define GEN8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 10283 #define GEN6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 10284 10285 static inline uint32_t ATTRIBUTE_PURE 10286 _3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits(const struct gen_device_info *devinfo) 10287 { 10288 switch (devinfo->gen) { 10289 case 10: return 1; 10290 case 9: return 1; 10291 case 8: return 1; 10292 case 7: 10293 if (devinfo->is_haswell) { 10294 return 0; 10295 } else { 10296 return 0; 10297 } 10298 case 6: return 1; 10299 case 5: return 0; 10300 case 4: 10301 if (devinfo->is_g4x) { 10302 return 0; 10303 } else { 10304 return 0; 10305 } 10306 default: 10307 unreachable("Invalid hardware generation"); 10308 } 10309 } 10310 10311 10312 10313 #define GEN10_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 10314 #define GEN9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 10315 #define GEN8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 10316 #define GEN6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 96 10317 10318 static inline uint32_t ATTRIBUTE_PURE 10319 _3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start(const struct gen_device_info *devinfo) 10320 { 10321 switch (devinfo->gen) { 10322 case 10: return 32; 10323 case 9: return 32; 10324 case 8: return 32; 10325 case 7: 10326 if (devinfo->is_haswell) { 10327 return 0; 10328 } else { 10329 return 0; 10330 } 10331 case 6: return 96; 10332 case 5: return 0; 10333 case 4: 10334 if (devinfo->is_g4x) { 10335 return 0; 10336 } else { 10337 return 0; 10338 } 10339 default: 10340 unreachable("Invalid hardware generation"); 10341 } 10342 } 10343 10344 10345 10346 /* 3DSTATE_CC_STATE_POINTERS::Command SubType */ 10347 10348 10349 #define GEN10_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 10350 #define GEN9_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 10351 #define GEN8_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 10352 #define GEN75_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 10353 #define GEN7_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 10354 #define GEN6_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 10355 10356 static inline uint32_t ATTRIBUTE_PURE 10357 _3DSTATE_CC_STATE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) 10358 { 10359 switch (devinfo->gen) { 10360 case 10: return 2; 10361 case 9: return 2; 10362 case 8: return 2; 10363 case 7: 10364 if (devinfo->is_haswell) { 10365 return 2; 10366 } else { 10367 return 2; 10368 } 10369 case 6: return 2; 10370 case 5: return 0; 10371 case 4: 10372 if (devinfo->is_g4x) { 10373 return 0; 10374 } else { 10375 return 0; 10376 } 10377 default: 10378 unreachable("Invalid hardware generation"); 10379 } 10380 } 10381 10382 10383 10384 #define GEN10_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 10385 #define GEN9_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 10386 #define GEN8_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 10387 #define GEN75_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 10388 #define GEN7_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 10389 #define GEN6_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 10390 10391 static inline uint32_t ATTRIBUTE_PURE 10392 _3DSTATE_CC_STATE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) 10393 { 10394 switch (devinfo->gen) { 10395 case 10: return 27; 10396 case 9: return 27; 10397 case 8: return 27; 10398 case 7: 10399 if (devinfo->is_haswell) { 10400 return 27; 10401 } else { 10402 return 27; 10403 } 10404 case 6: return 27; 10405 case 5: return 0; 10406 case 4: 10407 if (devinfo->is_g4x) { 10408 return 0; 10409 } else { 10410 return 0; 10411 } 10412 default: 10413 unreachable("Invalid hardware generation"); 10414 } 10415 } 10416 10417 10418 10419 /* 3DSTATE_CC_STATE_POINTERS::Command Type */ 10420 10421 10422 #define GEN10_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 10423 #define GEN9_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 10424 #define GEN8_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 10425 #define GEN75_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 10426 #define GEN7_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 10427 #define GEN6_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 10428 10429 static inline uint32_t ATTRIBUTE_PURE 10430 _3DSTATE_CC_STATE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) 10431 { 10432 switch (devinfo->gen) { 10433 case 10: return 3; 10434 case 9: return 3; 10435 case 8: return 3; 10436 case 7: 10437 if (devinfo->is_haswell) { 10438 return 3; 10439 } else { 10440 return 3; 10441 } 10442 case 6: return 3; 10443 case 5: return 0; 10444 case 4: 10445 if (devinfo->is_g4x) { 10446 return 0; 10447 } else { 10448 return 0; 10449 } 10450 default: 10451 unreachable("Invalid hardware generation"); 10452 } 10453 } 10454 10455 10456 10457 #define GEN10_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 10458 #define GEN9_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 10459 #define GEN8_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 10460 #define GEN75_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 10461 #define GEN7_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 10462 #define GEN6_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 10463 10464 static inline uint32_t ATTRIBUTE_PURE 10465 _3DSTATE_CC_STATE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) 10466 { 10467 switch (devinfo->gen) { 10468 case 10: return 29; 10469 case 9: return 29; 10470 case 8: return 29; 10471 case 7: 10472 if (devinfo->is_haswell) { 10473 return 29; 10474 } else { 10475 return 29; 10476 } 10477 case 6: return 29; 10478 case 5: return 0; 10479 case 4: 10480 if (devinfo->is_g4x) { 10481 return 0; 10482 } else { 10483 return 0; 10484 } 10485 default: 10486 unreachable("Invalid hardware generation"); 10487 } 10488 } 10489 10490 10491 10492 /* 3DSTATE_CC_STATE_POINTERS::DEPTH_STENCIL_STATE Change */ 10493 10494 10495 #define GEN6_3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_bits 1 10496 10497 static inline uint32_t ATTRIBUTE_PURE 10498 _3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_bits(const struct gen_device_info *devinfo) 10499 { 10500 switch (devinfo->gen) { 10501 case 10: return 0; 10502 case 9: return 0; 10503 case 8: return 0; 10504 case 7: 10505 if (devinfo->is_haswell) { 10506 return 0; 10507 } else { 10508 return 0; 10509 } 10510 case 6: return 1; 10511 case 5: return 0; 10512 case 4: 10513 if (devinfo->is_g4x) { 10514 return 0; 10515 } else { 10516 return 0; 10517 } 10518 default: 10519 unreachable("Invalid hardware generation"); 10520 } 10521 } 10522 10523 10524 10525 #define GEN6_3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_start 64 10526 10527 static inline uint32_t ATTRIBUTE_PURE 10528 _3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_start(const struct gen_device_info *devinfo) 10529 { 10530 switch (devinfo->gen) { 10531 case 10: return 0; 10532 case 9: return 0; 10533 case 8: return 0; 10534 case 7: 10535 if (devinfo->is_haswell) { 10536 return 0; 10537 } else { 10538 return 0; 10539 } 10540 case 6: return 64; 10541 case 5: return 0; 10542 case 4: 10543 if (devinfo->is_g4x) { 10544 return 0; 10545 } else { 10546 return 0; 10547 } 10548 default: 10549 unreachable("Invalid hardware generation"); 10550 } 10551 } 10552 10553 10554 10555 /* 3DSTATE_CC_STATE_POINTERS::DWord Length */ 10556 10557 10558 #define GEN10_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 10559 #define GEN9_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 10560 #define GEN8_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 10561 #define GEN75_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 10562 #define GEN7_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 10563 #define GEN6_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 10564 10565 static inline uint32_t ATTRIBUTE_PURE 10566 _3DSTATE_CC_STATE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) 10567 { 10568 switch (devinfo->gen) { 10569 case 10: return 8; 10570 case 9: return 8; 10571 case 8: return 8; 10572 case 7: 10573 if (devinfo->is_haswell) { 10574 return 8; 10575 } else { 10576 return 8; 10577 } 10578 case 6: return 8; 10579 case 5: return 0; 10580 case 4: 10581 if (devinfo->is_g4x) { 10582 return 0; 10583 } else { 10584 return 0; 10585 } 10586 default: 10587 unreachable("Invalid hardware generation"); 10588 } 10589 } 10590 10591 10592 10593 #define GEN10_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 10594 #define GEN9_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 10595 #define GEN8_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 10596 #define GEN75_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 10597 #define GEN7_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 10598 #define GEN6_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 10599 10600 static inline uint32_t ATTRIBUTE_PURE 10601 _3DSTATE_CC_STATE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) 10602 { 10603 switch (devinfo->gen) { 10604 case 10: return 0; 10605 case 9: return 0; 10606 case 8: return 0; 10607 case 7: 10608 if (devinfo->is_haswell) { 10609 return 0; 10610 } else { 10611 return 0; 10612 } 10613 case 6: return 0; 10614 case 5: return 0; 10615 case 4: 10616 if (devinfo->is_g4x) { 10617 return 0; 10618 } else { 10619 return 0; 10620 } 10621 default: 10622 unreachable("Invalid hardware generation"); 10623 } 10624 } 10625 10626 10627 10628 /* 3DSTATE_CC_STATE_POINTERS::Pointer to BLEND_STATE */ 10629 10630 10631 #define GEN6_3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_bits 26 10632 10633 static inline uint32_t ATTRIBUTE_PURE 10634 _3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_bits(const struct gen_device_info *devinfo) 10635 { 10636 switch (devinfo->gen) { 10637 case 10: return 0; 10638 case 9: return 0; 10639 case 8: return 0; 10640 case 7: 10641 if (devinfo->is_haswell) { 10642 return 0; 10643 } else { 10644 return 0; 10645 } 10646 case 6: return 26; 10647 case 5: return 0; 10648 case 4: 10649 if (devinfo->is_g4x) { 10650 return 0; 10651 } else { 10652 return 0; 10653 } 10654 default: 10655 unreachable("Invalid hardware generation"); 10656 } 10657 } 10658 10659 10660 10661 #define GEN6_3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_start 38 10662 10663 static inline uint32_t ATTRIBUTE_PURE 10664 _3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_start(const struct gen_device_info *devinfo) 10665 { 10666 switch (devinfo->gen) { 10667 case 10: return 0; 10668 case 9: return 0; 10669 case 8: return 0; 10670 case 7: 10671 if (devinfo->is_haswell) { 10672 return 0; 10673 } else { 10674 return 0; 10675 } 10676 case 6: return 38; 10677 case 5: return 0; 10678 case 4: 10679 if (devinfo->is_g4x) { 10680 return 0; 10681 } else { 10682 return 0; 10683 } 10684 default: 10685 unreachable("Invalid hardware generation"); 10686 } 10687 } 10688 10689 10690 10691 /* 3DSTATE_CC_STATE_POINTERS::Pointer to DEPTH_STENCIL_STATE */ 10692 10693 10694 #define GEN6_3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits 26 10695 10696 static inline uint32_t ATTRIBUTE_PURE 10697 _3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits(const struct gen_device_info *devinfo) 10698 { 10699 switch (devinfo->gen) { 10700 case 10: return 0; 10701 case 9: return 0; 10702 case 8: return 0; 10703 case 7: 10704 if (devinfo->is_haswell) { 10705 return 0; 10706 } else { 10707 return 0; 10708 } 10709 case 6: return 26; 10710 case 5: return 0; 10711 case 4: 10712 if (devinfo->is_g4x) { 10713 return 0; 10714 } else { 10715 return 0; 10716 } 10717 default: 10718 unreachable("Invalid hardware generation"); 10719 } 10720 } 10721 10722 10723 10724 #define GEN6_3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start 70 10725 10726 static inline uint32_t ATTRIBUTE_PURE 10727 _3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start(const struct gen_device_info *devinfo) 10728 { 10729 switch (devinfo->gen) { 10730 case 10: return 0; 10731 case 9: return 0; 10732 case 8: return 0; 10733 case 7: 10734 if (devinfo->is_haswell) { 10735 return 0; 10736 } else { 10737 return 0; 10738 } 10739 case 6: return 70; 10740 case 5: return 0; 10741 case 4: 10742 if (devinfo->is_g4x) { 10743 return 0; 10744 } else { 10745 return 0; 10746 } 10747 default: 10748 unreachable("Invalid hardware generation"); 10749 } 10750 } 10751 10752 10753 10754 /* 3DSTATE_CHROMA_KEY */ 10755 10756 10757 #define GEN10_3DSTATE_CHROMA_KEY_length 4 10758 #define GEN9_3DSTATE_CHROMA_KEY_length 4 10759 #define GEN8_3DSTATE_CHROMA_KEY_length 4 10760 #define GEN75_3DSTATE_CHROMA_KEY_length 4 10761 #define GEN7_3DSTATE_CHROMA_KEY_length 4 10762 #define GEN6_3DSTATE_CHROMA_KEY_length 4 10763 10764 static inline uint32_t ATTRIBUTE_PURE 10765 _3DSTATE_CHROMA_KEY_length(const struct gen_device_info *devinfo) 10766 { 10767 switch (devinfo->gen) { 10768 case 10: return 4; 10769 case 9: return 4; 10770 case 8: return 4; 10771 case 7: 10772 if (devinfo->is_haswell) { 10773 return 4; 10774 } else { 10775 return 4; 10776 } 10777 case 6: return 4; 10778 case 5: return 0; 10779 case 4: 10780 if (devinfo->is_g4x) { 10781 return 0; 10782 } else { 10783 return 0; 10784 } 10785 default: 10786 unreachable("Invalid hardware generation"); 10787 } 10788 } 10789 10790 10791 10792 /* 3DSTATE_CHROMA_KEY::3D Command Opcode */ 10793 10794 10795 #define GEN10_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 10796 #define GEN9_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 10797 #define GEN8_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 10798 #define GEN75_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 10799 #define GEN7_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 10800 #define GEN6_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 10801 10802 static inline uint32_t ATTRIBUTE_PURE 10803 _3DSTATE_CHROMA_KEY_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 10804 { 10805 switch (devinfo->gen) { 10806 case 10: return 3; 10807 case 9: return 3; 10808 case 8: return 3; 10809 case 7: 10810 if (devinfo->is_haswell) { 10811 return 3; 10812 } else { 10813 return 3; 10814 } 10815 case 6: return 3; 10816 case 5: return 0; 10817 case 4: 10818 if (devinfo->is_g4x) { 10819 return 0; 10820 } else { 10821 return 0; 10822 } 10823 default: 10824 unreachable("Invalid hardware generation"); 10825 } 10826 } 10827 10828 10829 10830 #define GEN10_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 10831 #define GEN9_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 10832 #define GEN8_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 10833 #define GEN75_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 10834 #define GEN7_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 10835 #define GEN6_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 10836 10837 static inline uint32_t ATTRIBUTE_PURE 10838 _3DSTATE_CHROMA_KEY_3DCommandOpcode_start(const struct gen_device_info *devinfo) 10839 { 10840 switch (devinfo->gen) { 10841 case 10: return 24; 10842 case 9: return 24; 10843 case 8: return 24; 10844 case 7: 10845 if (devinfo->is_haswell) { 10846 return 24; 10847 } else { 10848 return 24; 10849 } 10850 case 6: return 24; 10851 case 5: return 0; 10852 case 4: 10853 if (devinfo->is_g4x) { 10854 return 0; 10855 } else { 10856 return 0; 10857 } 10858 default: 10859 unreachable("Invalid hardware generation"); 10860 } 10861 } 10862 10863 10864 10865 /* 3DSTATE_CHROMA_KEY::3D Command Sub Opcode */ 10866 10867 10868 #define GEN10_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 10869 #define GEN9_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 10870 #define GEN8_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 10871 #define GEN75_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 10872 #define GEN7_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 10873 #define GEN6_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 10874 10875 static inline uint32_t ATTRIBUTE_PURE 10876 _3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 10877 { 10878 switch (devinfo->gen) { 10879 case 10: return 8; 10880 case 9: return 8; 10881 case 8: return 8; 10882 case 7: 10883 if (devinfo->is_haswell) { 10884 return 8; 10885 } else { 10886 return 8; 10887 } 10888 case 6: return 8; 10889 case 5: return 0; 10890 case 4: 10891 if (devinfo->is_g4x) { 10892 return 0; 10893 } else { 10894 return 0; 10895 } 10896 default: 10897 unreachable("Invalid hardware generation"); 10898 } 10899 } 10900 10901 10902 10903 #define GEN10_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 10904 #define GEN9_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 10905 #define GEN8_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 10906 #define GEN75_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 10907 #define GEN7_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 10908 #define GEN6_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 10909 10910 static inline uint32_t ATTRIBUTE_PURE 10911 _3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 10912 { 10913 switch (devinfo->gen) { 10914 case 10: return 16; 10915 case 9: return 16; 10916 case 8: return 16; 10917 case 7: 10918 if (devinfo->is_haswell) { 10919 return 16; 10920 } else { 10921 return 16; 10922 } 10923 case 6: return 16; 10924 case 5: return 0; 10925 case 4: 10926 if (devinfo->is_g4x) { 10927 return 0; 10928 } else { 10929 return 0; 10930 } 10931 default: 10932 unreachable("Invalid hardware generation"); 10933 } 10934 } 10935 10936 10937 10938 /* 3DSTATE_CHROMA_KEY::ChromaKey High Value */ 10939 10940 10941 #define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 10942 #define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 10943 #define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 10944 #define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 10945 #define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 10946 #define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 10947 10948 static inline uint32_t ATTRIBUTE_PURE 10949 _3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits(const struct gen_device_info *devinfo) 10950 { 10951 switch (devinfo->gen) { 10952 case 10: return 32; 10953 case 9: return 32; 10954 case 8: return 32; 10955 case 7: 10956 if (devinfo->is_haswell) { 10957 return 32; 10958 } else { 10959 return 32; 10960 } 10961 case 6: return 32; 10962 case 5: return 0; 10963 case 4: 10964 if (devinfo->is_g4x) { 10965 return 0; 10966 } else { 10967 return 0; 10968 } 10969 default: 10970 unreachable("Invalid hardware generation"); 10971 } 10972 } 10973 10974 10975 10976 #define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 10977 #define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 10978 #define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 10979 #define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 10980 #define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 10981 #define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 10982 10983 static inline uint32_t ATTRIBUTE_PURE 10984 _3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start(const struct gen_device_info *devinfo) 10985 { 10986 switch (devinfo->gen) { 10987 case 10: return 96; 10988 case 9: return 96; 10989 case 8: return 96; 10990 case 7: 10991 if (devinfo->is_haswell) { 10992 return 96; 10993 } else { 10994 return 96; 10995 } 10996 case 6: return 96; 10997 case 5: return 0; 10998 case 4: 10999 if (devinfo->is_g4x) { 11000 return 0; 11001 } else { 11002 return 0; 11003 } 11004 default: 11005 unreachable("Invalid hardware generation"); 11006 } 11007 } 11008 11009 11010 11011 /* 3DSTATE_CHROMA_KEY::ChromaKey Low Value */ 11012 11013 11014 #define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 11015 #define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 11016 #define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 11017 #define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 11018 #define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 11019 #define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 11020 11021 static inline uint32_t ATTRIBUTE_PURE 11022 _3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits(const struct gen_device_info *devinfo) 11023 { 11024 switch (devinfo->gen) { 11025 case 10: return 32; 11026 case 9: return 32; 11027 case 8: return 32; 11028 case 7: 11029 if (devinfo->is_haswell) { 11030 return 32; 11031 } else { 11032 return 32; 11033 } 11034 case 6: return 32; 11035 case 5: return 0; 11036 case 4: 11037 if (devinfo->is_g4x) { 11038 return 0; 11039 } else { 11040 return 0; 11041 } 11042 default: 11043 unreachable("Invalid hardware generation"); 11044 } 11045 } 11046 11047 11048 11049 #define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 11050 #define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 11051 #define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 11052 #define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 11053 #define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 11054 #define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 11055 11056 static inline uint32_t ATTRIBUTE_PURE 11057 _3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start(const struct gen_device_info *devinfo) 11058 { 11059 switch (devinfo->gen) { 11060 case 10: return 64; 11061 case 9: return 64; 11062 case 8: return 64; 11063 case 7: 11064 if (devinfo->is_haswell) { 11065 return 64; 11066 } else { 11067 return 64; 11068 } 11069 case 6: return 64; 11070 case 5: return 0; 11071 case 4: 11072 if (devinfo->is_g4x) { 11073 return 0; 11074 } else { 11075 return 0; 11076 } 11077 default: 11078 unreachable("Invalid hardware generation"); 11079 } 11080 } 11081 11082 11083 11084 /* 3DSTATE_CHROMA_KEY::ChromaKey Table Index */ 11085 11086 11087 #define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 11088 #define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 11089 #define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 11090 #define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 11091 #define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 11092 #define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 11093 11094 static inline uint32_t ATTRIBUTE_PURE 11095 _3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits(const struct gen_device_info *devinfo) 11096 { 11097 switch (devinfo->gen) { 11098 case 10: return 2; 11099 case 9: return 2; 11100 case 8: return 2; 11101 case 7: 11102 if (devinfo->is_haswell) { 11103 return 2; 11104 } else { 11105 return 2; 11106 } 11107 case 6: return 2; 11108 case 5: return 0; 11109 case 4: 11110 if (devinfo->is_g4x) { 11111 return 0; 11112 } else { 11113 return 0; 11114 } 11115 default: 11116 unreachable("Invalid hardware generation"); 11117 } 11118 } 11119 11120 11121 11122 #define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 11123 #define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 11124 #define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 11125 #define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 11126 #define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 11127 #define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 11128 11129 static inline uint32_t ATTRIBUTE_PURE 11130 _3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start(const struct gen_device_info *devinfo) 11131 { 11132 switch (devinfo->gen) { 11133 case 10: return 62; 11134 case 9: return 62; 11135 case 8: return 62; 11136 case 7: 11137 if (devinfo->is_haswell) { 11138 return 62; 11139 } else { 11140 return 62; 11141 } 11142 case 6: return 62; 11143 case 5: return 0; 11144 case 4: 11145 if (devinfo->is_g4x) { 11146 return 0; 11147 } else { 11148 return 0; 11149 } 11150 default: 11151 unreachable("Invalid hardware generation"); 11152 } 11153 } 11154 11155 11156 11157 /* 3DSTATE_CHROMA_KEY::Command SubType */ 11158 11159 11160 #define GEN10_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 11161 #define GEN9_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 11162 #define GEN8_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 11163 #define GEN75_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 11164 #define GEN7_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 11165 #define GEN6_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 11166 11167 static inline uint32_t ATTRIBUTE_PURE 11168 _3DSTATE_CHROMA_KEY_CommandSubType_bits(const struct gen_device_info *devinfo) 11169 { 11170 switch (devinfo->gen) { 11171 case 10: return 2; 11172 case 9: return 2; 11173 case 8: return 2; 11174 case 7: 11175 if (devinfo->is_haswell) { 11176 return 2; 11177 } else { 11178 return 2; 11179 } 11180 case 6: return 2; 11181 case 5: return 0; 11182 case 4: 11183 if (devinfo->is_g4x) { 11184 return 0; 11185 } else { 11186 return 0; 11187 } 11188 default: 11189 unreachable("Invalid hardware generation"); 11190 } 11191 } 11192 11193 11194 11195 #define GEN10_3DSTATE_CHROMA_KEY_CommandSubType_start 27 11196 #define GEN9_3DSTATE_CHROMA_KEY_CommandSubType_start 27 11197 #define GEN8_3DSTATE_CHROMA_KEY_CommandSubType_start 27 11198 #define GEN75_3DSTATE_CHROMA_KEY_CommandSubType_start 27 11199 #define GEN7_3DSTATE_CHROMA_KEY_CommandSubType_start 27 11200 #define GEN6_3DSTATE_CHROMA_KEY_CommandSubType_start 27 11201 11202 static inline uint32_t ATTRIBUTE_PURE 11203 _3DSTATE_CHROMA_KEY_CommandSubType_start(const struct gen_device_info *devinfo) 11204 { 11205 switch (devinfo->gen) { 11206 case 10: return 27; 11207 case 9: return 27; 11208 case 8: return 27; 11209 case 7: 11210 if (devinfo->is_haswell) { 11211 return 27; 11212 } else { 11213 return 27; 11214 } 11215 case 6: return 27; 11216 case 5: return 0; 11217 case 4: 11218 if (devinfo->is_g4x) { 11219 return 0; 11220 } else { 11221 return 0; 11222 } 11223 default: 11224 unreachable("Invalid hardware generation"); 11225 } 11226 } 11227 11228 11229 11230 /* 3DSTATE_CHROMA_KEY::Command Type */ 11231 11232 11233 #define GEN10_3DSTATE_CHROMA_KEY_CommandType_bits 3 11234 #define GEN9_3DSTATE_CHROMA_KEY_CommandType_bits 3 11235 #define GEN8_3DSTATE_CHROMA_KEY_CommandType_bits 3 11236 #define GEN75_3DSTATE_CHROMA_KEY_CommandType_bits 3 11237 #define GEN7_3DSTATE_CHROMA_KEY_CommandType_bits 3 11238 #define GEN6_3DSTATE_CHROMA_KEY_CommandType_bits 3 11239 11240 static inline uint32_t ATTRIBUTE_PURE 11241 _3DSTATE_CHROMA_KEY_CommandType_bits(const struct gen_device_info *devinfo) 11242 { 11243 switch (devinfo->gen) { 11244 case 10: return 3; 11245 case 9: return 3; 11246 case 8: return 3; 11247 case 7: 11248 if (devinfo->is_haswell) { 11249 return 3; 11250 } else { 11251 return 3; 11252 } 11253 case 6: return 3; 11254 case 5: return 0; 11255 case 4: 11256 if (devinfo->is_g4x) { 11257 return 0; 11258 } else { 11259 return 0; 11260 } 11261 default: 11262 unreachable("Invalid hardware generation"); 11263 } 11264 } 11265 11266 11267 11268 #define GEN10_3DSTATE_CHROMA_KEY_CommandType_start 29 11269 #define GEN9_3DSTATE_CHROMA_KEY_CommandType_start 29 11270 #define GEN8_3DSTATE_CHROMA_KEY_CommandType_start 29 11271 #define GEN75_3DSTATE_CHROMA_KEY_CommandType_start 29 11272 #define GEN7_3DSTATE_CHROMA_KEY_CommandType_start 29 11273 #define GEN6_3DSTATE_CHROMA_KEY_CommandType_start 29 11274 11275 static inline uint32_t ATTRIBUTE_PURE 11276 _3DSTATE_CHROMA_KEY_CommandType_start(const struct gen_device_info *devinfo) 11277 { 11278 switch (devinfo->gen) { 11279 case 10: return 29; 11280 case 9: return 29; 11281 case 8: return 29; 11282 case 7: 11283 if (devinfo->is_haswell) { 11284 return 29; 11285 } else { 11286 return 29; 11287 } 11288 case 6: return 29; 11289 case 5: return 0; 11290 case 4: 11291 if (devinfo->is_g4x) { 11292 return 0; 11293 } else { 11294 return 0; 11295 } 11296 default: 11297 unreachable("Invalid hardware generation"); 11298 } 11299 } 11300 11301 11302 11303 /* 3DSTATE_CHROMA_KEY::DWord Length */ 11304 11305 11306 #define GEN10_3DSTATE_CHROMA_KEY_DWordLength_bits 8 11307 #define GEN9_3DSTATE_CHROMA_KEY_DWordLength_bits 8 11308 #define GEN8_3DSTATE_CHROMA_KEY_DWordLength_bits 8 11309 #define GEN75_3DSTATE_CHROMA_KEY_DWordLength_bits 8 11310 #define GEN7_3DSTATE_CHROMA_KEY_DWordLength_bits 8 11311 #define GEN6_3DSTATE_CHROMA_KEY_DWordLength_bits 8 11312 11313 static inline uint32_t ATTRIBUTE_PURE 11314 _3DSTATE_CHROMA_KEY_DWordLength_bits(const struct gen_device_info *devinfo) 11315 { 11316 switch (devinfo->gen) { 11317 case 10: return 8; 11318 case 9: return 8; 11319 case 8: return 8; 11320 case 7: 11321 if (devinfo->is_haswell) { 11322 return 8; 11323 } else { 11324 return 8; 11325 } 11326 case 6: return 8; 11327 case 5: return 0; 11328 case 4: 11329 if (devinfo->is_g4x) { 11330 return 0; 11331 } else { 11332 return 0; 11333 } 11334 default: 11335 unreachable("Invalid hardware generation"); 11336 } 11337 } 11338 11339 11340 11341 #define GEN10_3DSTATE_CHROMA_KEY_DWordLength_start 0 11342 #define GEN9_3DSTATE_CHROMA_KEY_DWordLength_start 0 11343 #define GEN8_3DSTATE_CHROMA_KEY_DWordLength_start 0 11344 #define GEN75_3DSTATE_CHROMA_KEY_DWordLength_start 0 11345 #define GEN7_3DSTATE_CHROMA_KEY_DWordLength_start 0 11346 #define GEN6_3DSTATE_CHROMA_KEY_DWordLength_start 0 11347 11348 static inline uint32_t ATTRIBUTE_PURE 11349 _3DSTATE_CHROMA_KEY_DWordLength_start(const struct gen_device_info *devinfo) 11350 { 11351 switch (devinfo->gen) { 11352 case 10: return 0; 11353 case 9: return 0; 11354 case 8: return 0; 11355 case 7: 11356 if (devinfo->is_haswell) { 11357 return 0; 11358 } else { 11359 return 0; 11360 } 11361 case 6: return 0; 11362 case 5: return 0; 11363 case 4: 11364 if (devinfo->is_g4x) { 11365 return 0; 11366 } else { 11367 return 0; 11368 } 11369 default: 11370 unreachable("Invalid hardware generation"); 11371 } 11372 } 11373 11374 11375 11376 /* 3DSTATE_CLEAR_PARAMS */ 11377 11378 11379 #define GEN10_3DSTATE_CLEAR_PARAMS_length 3 11380 #define GEN9_3DSTATE_CLEAR_PARAMS_length 3 11381 #define GEN8_3DSTATE_CLEAR_PARAMS_length 3 11382 #define GEN75_3DSTATE_CLEAR_PARAMS_length 3 11383 #define GEN7_3DSTATE_CLEAR_PARAMS_length 3 11384 #define GEN6_3DSTATE_CLEAR_PARAMS_length 2 11385 #define GEN5_3DSTATE_CLEAR_PARAMS_length 2 11386 11387 static inline uint32_t ATTRIBUTE_PURE 11388 _3DSTATE_CLEAR_PARAMS_length(const struct gen_device_info *devinfo) 11389 { 11390 switch (devinfo->gen) { 11391 case 10: return 3; 11392 case 9: return 3; 11393 case 8: return 3; 11394 case 7: 11395 if (devinfo->is_haswell) { 11396 return 3; 11397 } else { 11398 return 3; 11399 } 11400 case 6: return 2; 11401 case 5: return 2; 11402 case 4: 11403 if (devinfo->is_g4x) { 11404 return 0; 11405 } else { 11406 return 0; 11407 } 11408 default: 11409 unreachable("Invalid hardware generation"); 11410 } 11411 } 11412 11413 11414 11415 /* 3DSTATE_CLEAR_PARAMS::3D Command Opcode */ 11416 11417 11418 #define GEN10_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11419 #define GEN9_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11420 #define GEN8_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11421 #define GEN75_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11422 #define GEN7_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11423 #define GEN6_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11424 #define GEN5_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11425 11426 static inline uint32_t ATTRIBUTE_PURE 11427 _3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 11428 { 11429 switch (devinfo->gen) { 11430 case 10: return 3; 11431 case 9: return 3; 11432 case 8: return 3; 11433 case 7: 11434 if (devinfo->is_haswell) { 11435 return 3; 11436 } else { 11437 return 3; 11438 } 11439 case 6: return 3; 11440 case 5: return 3; 11441 case 4: 11442 if (devinfo->is_g4x) { 11443 return 0; 11444 } else { 11445 return 0; 11446 } 11447 default: 11448 unreachable("Invalid hardware generation"); 11449 } 11450 } 11451 11452 11453 11454 #define GEN10_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11455 #define GEN9_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11456 #define GEN8_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11457 #define GEN75_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11458 #define GEN7_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11459 #define GEN6_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11460 #define GEN5_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11461 11462 static inline uint32_t ATTRIBUTE_PURE 11463 _3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 11464 { 11465 switch (devinfo->gen) { 11466 case 10: return 24; 11467 case 9: return 24; 11468 case 8: return 24; 11469 case 7: 11470 if (devinfo->is_haswell) { 11471 return 24; 11472 } else { 11473 return 24; 11474 } 11475 case 6: return 24; 11476 case 5: return 24; 11477 case 4: 11478 if (devinfo->is_g4x) { 11479 return 0; 11480 } else { 11481 return 0; 11482 } 11483 default: 11484 unreachable("Invalid hardware generation"); 11485 } 11486 } 11487 11488 11489 11490 /* 3DSTATE_CLEAR_PARAMS::3D Command Sub Opcode */ 11491 11492 11493 #define GEN10_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11494 #define GEN9_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11495 #define GEN8_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11496 #define GEN75_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11497 #define GEN7_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11498 #define GEN6_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11499 #define GEN5_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11500 11501 static inline uint32_t ATTRIBUTE_PURE 11502 _3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 11503 { 11504 switch (devinfo->gen) { 11505 case 10: return 8; 11506 case 9: return 8; 11507 case 8: return 8; 11508 case 7: 11509 if (devinfo->is_haswell) { 11510 return 8; 11511 } else { 11512 return 8; 11513 } 11514 case 6: return 8; 11515 case 5: return 8; 11516 case 4: 11517 if (devinfo->is_g4x) { 11518 return 0; 11519 } else { 11520 return 0; 11521 } 11522 default: 11523 unreachable("Invalid hardware generation"); 11524 } 11525 } 11526 11527 11528 11529 #define GEN10_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11530 #define GEN9_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11531 #define GEN8_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11532 #define GEN75_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11533 #define GEN7_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11534 #define GEN6_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11535 #define GEN5_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11536 11537 static inline uint32_t ATTRIBUTE_PURE 11538 _3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 11539 { 11540 switch (devinfo->gen) { 11541 case 10: return 16; 11542 case 9: return 16; 11543 case 8: return 16; 11544 case 7: 11545 if (devinfo->is_haswell) { 11546 return 16; 11547 } else { 11548 return 16; 11549 } 11550 case 6: return 16; 11551 case 5: return 16; 11552 case 4: 11553 if (devinfo->is_g4x) { 11554 return 0; 11555 } else { 11556 return 0; 11557 } 11558 default: 11559 unreachable("Invalid hardware generation"); 11560 } 11561 } 11562 11563 11564 11565 /* 3DSTATE_CLEAR_PARAMS::Command SubType */ 11566 11567 11568 #define GEN10_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11569 #define GEN9_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11570 #define GEN8_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11571 #define GEN75_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11572 #define GEN7_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11573 #define GEN6_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11574 #define GEN5_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11575 11576 static inline uint32_t ATTRIBUTE_PURE 11577 _3DSTATE_CLEAR_PARAMS_CommandSubType_bits(const struct gen_device_info *devinfo) 11578 { 11579 switch (devinfo->gen) { 11580 case 10: return 2; 11581 case 9: return 2; 11582 case 8: return 2; 11583 case 7: 11584 if (devinfo->is_haswell) { 11585 return 2; 11586 } else { 11587 return 2; 11588 } 11589 case 6: return 2; 11590 case 5: return 2; 11591 case 4: 11592 if (devinfo->is_g4x) { 11593 return 0; 11594 } else { 11595 return 0; 11596 } 11597 default: 11598 unreachable("Invalid hardware generation"); 11599 } 11600 } 11601 11602 11603 11604 #define GEN10_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11605 #define GEN9_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11606 #define GEN8_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11607 #define GEN75_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11608 #define GEN7_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11609 #define GEN6_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11610 #define GEN5_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11611 11612 static inline uint32_t ATTRIBUTE_PURE 11613 _3DSTATE_CLEAR_PARAMS_CommandSubType_start(const struct gen_device_info *devinfo) 11614 { 11615 switch (devinfo->gen) { 11616 case 10: return 27; 11617 case 9: return 27; 11618 case 8: return 27; 11619 case 7: 11620 if (devinfo->is_haswell) { 11621 return 27; 11622 } else { 11623 return 27; 11624 } 11625 case 6: return 27; 11626 case 5: return 27; 11627 case 4: 11628 if (devinfo->is_g4x) { 11629 return 0; 11630 } else { 11631 return 0; 11632 } 11633 default: 11634 unreachable("Invalid hardware generation"); 11635 } 11636 } 11637 11638 11639 11640 /* 3DSTATE_CLEAR_PARAMS::Command Type */ 11641 11642 11643 #define GEN10_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11644 #define GEN9_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11645 #define GEN8_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11646 #define GEN75_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11647 #define GEN7_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11648 #define GEN6_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11649 #define GEN5_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11650 11651 static inline uint32_t ATTRIBUTE_PURE 11652 _3DSTATE_CLEAR_PARAMS_CommandType_bits(const struct gen_device_info *devinfo) 11653 { 11654 switch (devinfo->gen) { 11655 case 10: return 3; 11656 case 9: return 3; 11657 case 8: return 3; 11658 case 7: 11659 if (devinfo->is_haswell) { 11660 return 3; 11661 } else { 11662 return 3; 11663 } 11664 case 6: return 3; 11665 case 5: return 3; 11666 case 4: 11667 if (devinfo->is_g4x) { 11668 return 0; 11669 } else { 11670 return 0; 11671 } 11672 default: 11673 unreachable("Invalid hardware generation"); 11674 } 11675 } 11676 11677 11678 11679 #define GEN10_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11680 #define GEN9_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11681 #define GEN8_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11682 #define GEN75_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11683 #define GEN7_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11684 #define GEN6_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11685 #define GEN5_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11686 11687 static inline uint32_t ATTRIBUTE_PURE 11688 _3DSTATE_CLEAR_PARAMS_CommandType_start(const struct gen_device_info *devinfo) 11689 { 11690 switch (devinfo->gen) { 11691 case 10: return 29; 11692 case 9: return 29; 11693 case 8: return 29; 11694 case 7: 11695 if (devinfo->is_haswell) { 11696 return 29; 11697 } else { 11698 return 29; 11699 } 11700 case 6: return 29; 11701 case 5: return 29; 11702 case 4: 11703 if (devinfo->is_g4x) { 11704 return 0; 11705 } else { 11706 return 0; 11707 } 11708 default: 11709 unreachable("Invalid hardware generation"); 11710 } 11711 } 11712 11713 11714 11715 /* 3DSTATE_CLEAR_PARAMS::DWord Length */ 11716 11717 11718 #define GEN10_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11719 #define GEN9_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11720 #define GEN8_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11721 #define GEN75_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11722 #define GEN7_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11723 #define GEN6_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11724 #define GEN5_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11725 11726 static inline uint32_t ATTRIBUTE_PURE 11727 _3DSTATE_CLEAR_PARAMS_DWordLength_bits(const struct gen_device_info *devinfo) 11728 { 11729 switch (devinfo->gen) { 11730 case 10: return 8; 11731 case 9: return 8; 11732 case 8: return 8; 11733 case 7: 11734 if (devinfo->is_haswell) { 11735 return 8; 11736 } else { 11737 return 8; 11738 } 11739 case 6: return 8; 11740 case 5: return 8; 11741 case 4: 11742 if (devinfo->is_g4x) { 11743 return 0; 11744 } else { 11745 return 0; 11746 } 11747 default: 11748 unreachable("Invalid hardware generation"); 11749 } 11750 } 11751 11752 11753 11754 #define GEN10_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11755 #define GEN9_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11756 #define GEN8_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11757 #define GEN75_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11758 #define GEN7_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11759 #define GEN6_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11760 #define GEN5_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11761 11762 static inline uint32_t ATTRIBUTE_PURE 11763 _3DSTATE_CLEAR_PARAMS_DWordLength_start(const struct gen_device_info *devinfo) 11764 { 11765 switch (devinfo->gen) { 11766 case 10: return 0; 11767 case 9: return 0; 11768 case 8: return 0; 11769 case 7: 11770 if (devinfo->is_haswell) { 11771 return 0; 11772 } else { 11773 return 0; 11774 } 11775 case 6: return 0; 11776 case 5: return 0; 11777 case 4: 11778 if (devinfo->is_g4x) { 11779 return 0; 11780 } else { 11781 return 0; 11782 } 11783 default: 11784 unreachable("Invalid hardware generation"); 11785 } 11786 } 11787 11788 11789 11790 /* 3DSTATE_CLEAR_PARAMS::Depth Clear Value */ 11791 11792 11793 #define GEN10_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11794 #define GEN9_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11795 #define GEN8_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11796 #define GEN75_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11797 #define GEN7_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11798 #define GEN6_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11799 #define GEN5_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11800 11801 static inline uint32_t ATTRIBUTE_PURE 11802 _3DSTATE_CLEAR_PARAMS_DepthClearValue_bits(const struct gen_device_info *devinfo) 11803 { 11804 switch (devinfo->gen) { 11805 case 10: return 32; 11806 case 9: return 32; 11807 case 8: return 32; 11808 case 7: 11809 if (devinfo->is_haswell) { 11810 return 32; 11811 } else { 11812 return 32; 11813 } 11814 case 6: return 32; 11815 case 5: return 32; 11816 case 4: 11817 if (devinfo->is_g4x) { 11818 return 0; 11819 } else { 11820 return 0; 11821 } 11822 default: 11823 unreachable("Invalid hardware generation"); 11824 } 11825 } 11826 11827 11828 11829 #define GEN10_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11830 #define GEN9_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11831 #define GEN8_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11832 #define GEN75_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11833 #define GEN7_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11834 #define GEN6_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11835 #define GEN5_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11836 11837 static inline uint32_t ATTRIBUTE_PURE 11838 _3DSTATE_CLEAR_PARAMS_DepthClearValue_start(const struct gen_device_info *devinfo) 11839 { 11840 switch (devinfo->gen) { 11841 case 10: return 32; 11842 case 9: return 32; 11843 case 8: return 32; 11844 case 7: 11845 if (devinfo->is_haswell) { 11846 return 32; 11847 } else { 11848 return 32; 11849 } 11850 case 6: return 32; 11851 case 5: return 32; 11852 case 4: 11853 if (devinfo->is_g4x) { 11854 return 0; 11855 } else { 11856 return 0; 11857 } 11858 default: 11859 unreachable("Invalid hardware generation"); 11860 } 11861 } 11862 11863 11864 11865 /* 3DSTATE_CLEAR_PARAMS::Depth Clear Value Valid */ 11866 11867 11868 #define GEN10_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11869 #define GEN9_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11870 #define GEN8_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11871 #define GEN75_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11872 #define GEN7_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11873 #define GEN6_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11874 #define GEN5_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11875 11876 static inline uint32_t ATTRIBUTE_PURE 11877 _3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits(const struct gen_device_info *devinfo) 11878 { 11879 switch (devinfo->gen) { 11880 case 10: return 1; 11881 case 9: return 1; 11882 case 8: return 1; 11883 case 7: 11884 if (devinfo->is_haswell) { 11885 return 1; 11886 } else { 11887 return 1; 11888 } 11889 case 6: return 1; 11890 case 5: return 1; 11891 case 4: 11892 if (devinfo->is_g4x) { 11893 return 0; 11894 } else { 11895 return 0; 11896 } 11897 default: 11898 unreachable("Invalid hardware generation"); 11899 } 11900 } 11901 11902 11903 11904 #define GEN10_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 11905 #define GEN9_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 11906 #define GEN8_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 11907 #define GEN75_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 11908 #define GEN7_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 11909 #define GEN6_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 15 11910 #define GEN5_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 15 11911 11912 static inline uint32_t ATTRIBUTE_PURE 11913 _3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start(const struct gen_device_info *devinfo) 11914 { 11915 switch (devinfo->gen) { 11916 case 10: return 64; 11917 case 9: return 64; 11918 case 8: return 64; 11919 case 7: 11920 if (devinfo->is_haswell) { 11921 return 64; 11922 } else { 11923 return 64; 11924 } 11925 case 6: return 15; 11926 case 5: return 15; 11927 case 4: 11928 if (devinfo->is_g4x) { 11929 return 0; 11930 } else { 11931 return 0; 11932 } 11933 default: 11934 unreachable("Invalid hardware generation"); 11935 } 11936 } 11937 11938 11939 11940 /* 3DSTATE_CLIP */ 11941 11942 11943 #define GEN10_3DSTATE_CLIP_length 4 11944 #define GEN9_3DSTATE_CLIP_length 4 11945 #define GEN8_3DSTATE_CLIP_length 4 11946 #define GEN75_3DSTATE_CLIP_length 4 11947 #define GEN7_3DSTATE_CLIP_length 4 11948 #define GEN6_3DSTATE_CLIP_length 4 11949 11950 static inline uint32_t ATTRIBUTE_PURE 11951 _3DSTATE_CLIP_length(const struct gen_device_info *devinfo) 11952 { 11953 switch (devinfo->gen) { 11954 case 10: return 4; 11955 case 9: return 4; 11956 case 8: return 4; 11957 case 7: 11958 if (devinfo->is_haswell) { 11959 return 4; 11960 } else { 11961 return 4; 11962 } 11963 case 6: return 4; 11964 case 5: return 0; 11965 case 4: 11966 if (devinfo->is_g4x) { 11967 return 0; 11968 } else { 11969 return 0; 11970 } 11971 default: 11972 unreachable("Invalid hardware generation"); 11973 } 11974 } 11975 11976 11977 11978 /* 3DSTATE_CLIP::3D Command Opcode */ 11979 11980 11981 #define GEN10_3DSTATE_CLIP_3DCommandOpcode_bits 3 11982 #define GEN9_3DSTATE_CLIP_3DCommandOpcode_bits 3 11983 #define GEN8_3DSTATE_CLIP_3DCommandOpcode_bits 3 11984 #define GEN75_3DSTATE_CLIP_3DCommandOpcode_bits 3 11985 #define GEN7_3DSTATE_CLIP_3DCommandOpcode_bits 3 11986 #define GEN6_3DSTATE_CLIP_3DCommandOpcode_bits 3 11987 11988 static inline uint32_t ATTRIBUTE_PURE 11989 _3DSTATE_CLIP_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 11990 { 11991 switch (devinfo->gen) { 11992 case 10: return 3; 11993 case 9: return 3; 11994 case 8: return 3; 11995 case 7: 11996 if (devinfo->is_haswell) { 11997 return 3; 11998 } else { 11999 return 3; 12000 } 12001 case 6: return 3; 12002 case 5: return 0; 12003 case 4: 12004 if (devinfo->is_g4x) { 12005 return 0; 12006 } else { 12007 return 0; 12008 } 12009 default: 12010 unreachable("Invalid hardware generation"); 12011 } 12012 } 12013 12014 12015 12016 #define GEN10_3DSTATE_CLIP_3DCommandOpcode_start 24 12017 #define GEN9_3DSTATE_CLIP_3DCommandOpcode_start 24 12018 #define GEN8_3DSTATE_CLIP_3DCommandOpcode_start 24 12019 #define GEN75_3DSTATE_CLIP_3DCommandOpcode_start 24 12020 #define GEN7_3DSTATE_CLIP_3DCommandOpcode_start 24 12021 #define GEN6_3DSTATE_CLIP_3DCommandOpcode_start 24 12022 12023 static inline uint32_t ATTRIBUTE_PURE 12024 _3DSTATE_CLIP_3DCommandOpcode_start(const struct gen_device_info *devinfo) 12025 { 12026 switch (devinfo->gen) { 12027 case 10: return 24; 12028 case 9: return 24; 12029 case 8: return 24; 12030 case 7: 12031 if (devinfo->is_haswell) { 12032 return 24; 12033 } else { 12034 return 24; 12035 } 12036 case 6: return 24; 12037 case 5: return 0; 12038 case 4: 12039 if (devinfo->is_g4x) { 12040 return 0; 12041 } else { 12042 return 0; 12043 } 12044 default: 12045 unreachable("Invalid hardware generation"); 12046 } 12047 } 12048 12049 12050 12051 /* 3DSTATE_CLIP::3D Command Sub Opcode */ 12052 12053 12054 #define GEN10_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 12055 #define GEN9_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 12056 #define GEN8_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 12057 #define GEN75_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 12058 #define GEN7_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 12059 #define GEN6_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 12060 12061 static inline uint32_t ATTRIBUTE_PURE 12062 _3DSTATE_CLIP_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 12063 { 12064 switch (devinfo->gen) { 12065 case 10: return 8; 12066 case 9: return 8; 12067 case 8: return 8; 12068 case 7: 12069 if (devinfo->is_haswell) { 12070 return 8; 12071 } else { 12072 return 8; 12073 } 12074 case 6: return 8; 12075 case 5: return 0; 12076 case 4: 12077 if (devinfo->is_g4x) { 12078 return 0; 12079 } else { 12080 return 0; 12081 } 12082 default: 12083 unreachable("Invalid hardware generation"); 12084 } 12085 } 12086 12087 12088 12089 #define GEN10_3DSTATE_CLIP_3DCommandSubOpcode_start 16 12090 #define GEN9_3DSTATE_CLIP_3DCommandSubOpcode_start 16 12091 #define GEN8_3DSTATE_CLIP_3DCommandSubOpcode_start 16 12092 #define GEN75_3DSTATE_CLIP_3DCommandSubOpcode_start 16 12093 #define GEN7_3DSTATE_CLIP_3DCommandSubOpcode_start 16 12094 #define GEN6_3DSTATE_CLIP_3DCommandSubOpcode_start 16 12095 12096 static inline uint32_t ATTRIBUTE_PURE 12097 _3DSTATE_CLIP_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 12098 { 12099 switch (devinfo->gen) { 12100 case 10: return 16; 12101 case 9: return 16; 12102 case 8: return 16; 12103 case 7: 12104 if (devinfo->is_haswell) { 12105 return 16; 12106 } else { 12107 return 16; 12108 } 12109 case 6: return 16; 12110 case 5: return 0; 12111 case 4: 12112 if (devinfo->is_g4x) { 12113 return 0; 12114 } else { 12115 return 0; 12116 } 12117 default: 12118 unreachable("Invalid hardware generation"); 12119 } 12120 } 12121 12122 12123 12124 /* 3DSTATE_CLIP::API Mode */ 12125 12126 12127 #define GEN10_3DSTATE_CLIP_APIMode_bits 1 12128 #define GEN9_3DSTATE_CLIP_APIMode_bits 1 12129 #define GEN8_3DSTATE_CLIP_APIMode_bits 1 12130 #define GEN75_3DSTATE_CLIP_APIMode_bits 1 12131 #define GEN7_3DSTATE_CLIP_APIMode_bits 1 12132 #define GEN6_3DSTATE_CLIP_APIMode_bits 1 12133 12134 static inline uint32_t ATTRIBUTE_PURE 12135 _3DSTATE_CLIP_APIMode_bits(const struct gen_device_info *devinfo) 12136 { 12137 switch (devinfo->gen) { 12138 case 10: return 1; 12139 case 9: return 1; 12140 case 8: return 1; 12141 case 7: 12142 if (devinfo->is_haswell) { 12143 return 1; 12144 } else { 12145 return 1; 12146 } 12147 case 6: return 1; 12148 case 5: return 0; 12149 case 4: 12150 if (devinfo->is_g4x) { 12151 return 0; 12152 } else { 12153 return 0; 12154 } 12155 default: 12156 unreachable("Invalid hardware generation"); 12157 } 12158 } 12159 12160 12161 12162 #define GEN10_3DSTATE_CLIP_APIMode_start 94 12163 #define GEN9_3DSTATE_CLIP_APIMode_start 94 12164 #define GEN8_3DSTATE_CLIP_APIMode_start 94 12165 #define GEN75_3DSTATE_CLIP_APIMode_start 94 12166 #define GEN7_3DSTATE_CLIP_APIMode_start 94 12167 #define GEN6_3DSTATE_CLIP_APIMode_start 94 12168 12169 static inline uint32_t ATTRIBUTE_PURE 12170 _3DSTATE_CLIP_APIMode_start(const struct gen_device_info *devinfo) 12171 { 12172 switch (devinfo->gen) { 12173 case 10: return 94; 12174 case 9: return 94; 12175 case 8: return 94; 12176 case 7: 12177 if (devinfo->is_haswell) { 12178 return 94; 12179 } else { 12180 return 94; 12181 } 12182 case 6: return 94; 12183 case 5: return 0; 12184 case 4: 12185 if (devinfo->is_g4x) { 12186 return 0; 12187 } else { 12188 return 0; 12189 } 12190 default: 12191 unreachable("Invalid hardware generation"); 12192 } 12193 } 12194 12195 12196 12197 /* 3DSTATE_CLIP::Clip Enable */ 12198 12199 12200 #define GEN10_3DSTATE_CLIP_ClipEnable_bits 1 12201 #define GEN9_3DSTATE_CLIP_ClipEnable_bits 1 12202 #define GEN8_3DSTATE_CLIP_ClipEnable_bits 1 12203 #define GEN75_3DSTATE_CLIP_ClipEnable_bits 1 12204 #define GEN7_3DSTATE_CLIP_ClipEnable_bits 1 12205 #define GEN6_3DSTATE_CLIP_ClipEnable_bits 1 12206 12207 static inline uint32_t ATTRIBUTE_PURE 12208 _3DSTATE_CLIP_ClipEnable_bits(const struct gen_device_info *devinfo) 12209 { 12210 switch (devinfo->gen) { 12211 case 10: return 1; 12212 case 9: return 1; 12213 case 8: return 1; 12214 case 7: 12215 if (devinfo->is_haswell) { 12216 return 1; 12217 } else { 12218 return 1; 12219 } 12220 case 6: return 1; 12221 case 5: return 0; 12222 case 4: 12223 if (devinfo->is_g4x) { 12224 return 0; 12225 } else { 12226 return 0; 12227 } 12228 default: 12229 unreachable("Invalid hardware generation"); 12230 } 12231 } 12232 12233 12234 12235 #define GEN10_3DSTATE_CLIP_ClipEnable_start 95 12236 #define GEN9_3DSTATE_CLIP_ClipEnable_start 95 12237 #define GEN8_3DSTATE_CLIP_ClipEnable_start 95 12238 #define GEN75_3DSTATE_CLIP_ClipEnable_start 95 12239 #define GEN7_3DSTATE_CLIP_ClipEnable_start 95 12240 #define GEN6_3DSTATE_CLIP_ClipEnable_start 95 12241 12242 static inline uint32_t ATTRIBUTE_PURE 12243 _3DSTATE_CLIP_ClipEnable_start(const struct gen_device_info *devinfo) 12244 { 12245 switch (devinfo->gen) { 12246 case 10: return 95; 12247 case 9: return 95; 12248 case 8: return 95; 12249 case 7: 12250 if (devinfo->is_haswell) { 12251 return 95; 12252 } else { 12253 return 95; 12254 } 12255 case 6: return 95; 12256 case 5: return 0; 12257 case 4: 12258 if (devinfo->is_g4x) { 12259 return 0; 12260 } else { 12261 return 0; 12262 } 12263 default: 12264 unreachable("Invalid hardware generation"); 12265 } 12266 } 12267 12268 12269 12270 /* 3DSTATE_CLIP::Clip Mode */ 12271 12272 12273 #define GEN10_3DSTATE_CLIP_ClipMode_bits 3 12274 #define GEN9_3DSTATE_CLIP_ClipMode_bits 3 12275 #define GEN8_3DSTATE_CLIP_ClipMode_bits 3 12276 #define GEN75_3DSTATE_CLIP_ClipMode_bits 3 12277 #define GEN7_3DSTATE_CLIP_ClipMode_bits 3 12278 #define GEN6_3DSTATE_CLIP_ClipMode_bits 3 12279 12280 static inline uint32_t ATTRIBUTE_PURE 12281 _3DSTATE_CLIP_ClipMode_bits(const struct gen_device_info *devinfo) 12282 { 12283 switch (devinfo->gen) { 12284 case 10: return 3; 12285 case 9: return 3; 12286 case 8: return 3; 12287 case 7: 12288 if (devinfo->is_haswell) { 12289 return 3; 12290 } else { 12291 return 3; 12292 } 12293 case 6: return 3; 12294 case 5: return 0; 12295 case 4: 12296 if (devinfo->is_g4x) { 12297 return 0; 12298 } else { 12299 return 0; 12300 } 12301 default: 12302 unreachable("Invalid hardware generation"); 12303 } 12304 } 12305 12306 12307 12308 #define GEN10_3DSTATE_CLIP_ClipMode_start 77 12309 #define GEN9_3DSTATE_CLIP_ClipMode_start 77 12310 #define GEN8_3DSTATE_CLIP_ClipMode_start 77 12311 #define GEN75_3DSTATE_CLIP_ClipMode_start 77 12312 #define GEN7_3DSTATE_CLIP_ClipMode_start 77 12313 #define GEN6_3DSTATE_CLIP_ClipMode_start 77 12314 12315 static inline uint32_t ATTRIBUTE_PURE 12316 _3DSTATE_CLIP_ClipMode_start(const struct gen_device_info *devinfo) 12317 { 12318 switch (devinfo->gen) { 12319 case 10: return 77; 12320 case 9: return 77; 12321 case 8: return 77; 12322 case 7: 12323 if (devinfo->is_haswell) { 12324 return 77; 12325 } else { 12326 return 77; 12327 } 12328 case 6: return 77; 12329 case 5: return 0; 12330 case 4: 12331 if (devinfo->is_g4x) { 12332 return 0; 12333 } else { 12334 return 0; 12335 } 12336 default: 12337 unreachable("Invalid hardware generation"); 12338 } 12339 } 12340 12341 12342 12343 /* 3DSTATE_CLIP::Command SubType */ 12344 12345 12346 #define GEN10_3DSTATE_CLIP_CommandSubType_bits 2 12347 #define GEN9_3DSTATE_CLIP_CommandSubType_bits 2 12348 #define GEN8_3DSTATE_CLIP_CommandSubType_bits 2 12349 #define GEN75_3DSTATE_CLIP_CommandSubType_bits 2 12350 #define GEN7_3DSTATE_CLIP_CommandSubType_bits 2 12351 #define GEN6_3DSTATE_CLIP_CommandSubType_bits 2 12352 12353 static inline uint32_t ATTRIBUTE_PURE 12354 _3DSTATE_CLIP_CommandSubType_bits(const struct gen_device_info *devinfo) 12355 { 12356 switch (devinfo->gen) { 12357 case 10: return 2; 12358 case 9: return 2; 12359 case 8: return 2; 12360 case 7: 12361 if (devinfo->is_haswell) { 12362 return 2; 12363 } else { 12364 return 2; 12365 } 12366 case 6: return 2; 12367 case 5: return 0; 12368 case 4: 12369 if (devinfo->is_g4x) { 12370 return 0; 12371 } else { 12372 return 0; 12373 } 12374 default: 12375 unreachable("Invalid hardware generation"); 12376 } 12377 } 12378 12379 12380 12381 #define GEN10_3DSTATE_CLIP_CommandSubType_start 27 12382 #define GEN9_3DSTATE_CLIP_CommandSubType_start 27 12383 #define GEN8_3DSTATE_CLIP_CommandSubType_start 27 12384 #define GEN75_3DSTATE_CLIP_CommandSubType_start 27 12385 #define GEN7_3DSTATE_CLIP_CommandSubType_start 27 12386 #define GEN6_3DSTATE_CLIP_CommandSubType_start 27 12387 12388 static inline uint32_t ATTRIBUTE_PURE 12389 _3DSTATE_CLIP_CommandSubType_start(const struct gen_device_info *devinfo) 12390 { 12391 switch (devinfo->gen) { 12392 case 10: return 27; 12393 case 9: return 27; 12394 case 8: return 27; 12395 case 7: 12396 if (devinfo->is_haswell) { 12397 return 27; 12398 } else { 12399 return 27; 12400 } 12401 case 6: return 27; 12402 case 5: return 0; 12403 case 4: 12404 if (devinfo->is_g4x) { 12405 return 0; 12406 } else { 12407 return 0; 12408 } 12409 default: 12410 unreachable("Invalid hardware generation"); 12411 } 12412 } 12413 12414 12415 12416 /* 3DSTATE_CLIP::Command Type */ 12417 12418 12419 #define GEN10_3DSTATE_CLIP_CommandType_bits 3 12420 #define GEN9_3DSTATE_CLIP_CommandType_bits 3 12421 #define GEN8_3DSTATE_CLIP_CommandType_bits 3 12422 #define GEN75_3DSTATE_CLIP_CommandType_bits 3 12423 #define GEN7_3DSTATE_CLIP_CommandType_bits 3 12424 #define GEN6_3DSTATE_CLIP_CommandType_bits 3 12425 12426 static inline uint32_t ATTRIBUTE_PURE 12427 _3DSTATE_CLIP_CommandType_bits(const struct gen_device_info *devinfo) 12428 { 12429 switch (devinfo->gen) { 12430 case 10: return 3; 12431 case 9: return 3; 12432 case 8: return 3; 12433 case 7: 12434 if (devinfo->is_haswell) { 12435 return 3; 12436 } else { 12437 return 3; 12438 } 12439 case 6: return 3; 12440 case 5: return 0; 12441 case 4: 12442 if (devinfo->is_g4x) { 12443 return 0; 12444 } else { 12445 return 0; 12446 } 12447 default: 12448 unreachable("Invalid hardware generation"); 12449 } 12450 } 12451 12452 12453 12454 #define GEN10_3DSTATE_CLIP_CommandType_start 29 12455 #define GEN9_3DSTATE_CLIP_CommandType_start 29 12456 #define GEN8_3DSTATE_CLIP_CommandType_start 29 12457 #define GEN75_3DSTATE_CLIP_CommandType_start 29 12458 #define GEN7_3DSTATE_CLIP_CommandType_start 29 12459 #define GEN6_3DSTATE_CLIP_CommandType_start 29 12460 12461 static inline uint32_t ATTRIBUTE_PURE 12462 _3DSTATE_CLIP_CommandType_start(const struct gen_device_info *devinfo) 12463 { 12464 switch (devinfo->gen) { 12465 case 10: return 29; 12466 case 9: return 29; 12467 case 8: return 29; 12468 case 7: 12469 if (devinfo->is_haswell) { 12470 return 29; 12471 } else { 12472 return 29; 12473 } 12474 case 6: return 29; 12475 case 5: return 0; 12476 case 4: 12477 if (devinfo->is_g4x) { 12478 return 0; 12479 } else { 12480 return 0; 12481 } 12482 default: 12483 unreachable("Invalid hardware generation"); 12484 } 12485 } 12486 12487 12488 12489 /* 3DSTATE_CLIP::Cull Mode */ 12490 12491 12492 #define GEN75_3DSTATE_CLIP_CullMode_bits 2 12493 #define GEN7_3DSTATE_CLIP_CullMode_bits 2 12494 12495 static inline uint32_t ATTRIBUTE_PURE 12496 _3DSTATE_CLIP_CullMode_bits(const struct gen_device_info *devinfo) 12497 { 12498 switch (devinfo->gen) { 12499 case 10: return 0; 12500 case 9: return 0; 12501 case 8: return 0; 12502 case 7: 12503 if (devinfo->is_haswell) { 12504 return 2; 12505 } else { 12506 return 2; 12507 } 12508 case 6: return 0; 12509 case 5: return 0; 12510 case 4: 12511 if (devinfo->is_g4x) { 12512 return 0; 12513 } else { 12514 return 0; 12515 } 12516 default: 12517 unreachable("Invalid hardware generation"); 12518 } 12519 } 12520 12521 12522 12523 #define GEN75_3DSTATE_CLIP_CullMode_start 48 12524 #define GEN7_3DSTATE_CLIP_CullMode_start 48 12525 12526 static inline uint32_t ATTRIBUTE_PURE 12527 _3DSTATE_CLIP_CullMode_start(const struct gen_device_info *devinfo) 12528 { 12529 switch (devinfo->gen) { 12530 case 10: return 0; 12531 case 9: return 0; 12532 case 8: return 0; 12533 case 7: 12534 if (devinfo->is_haswell) { 12535 return 48; 12536 } else { 12537 return 48; 12538 } 12539 case 6: return 0; 12540 case 5: return 0; 12541 case 4: 12542 if (devinfo->is_g4x) { 12543 return 0; 12544 } else { 12545 return 0; 12546 } 12547 default: 12548 unreachable("Invalid hardware generation"); 12549 } 12550 } 12551 12552 12553 12554 /* 3DSTATE_CLIP::DWord Length */ 12555 12556 12557 #define GEN10_3DSTATE_CLIP_DWordLength_bits 8 12558 #define GEN9_3DSTATE_CLIP_DWordLength_bits 8 12559 #define GEN8_3DSTATE_CLIP_DWordLength_bits 8 12560 #define GEN75_3DSTATE_CLIP_DWordLength_bits 8 12561 #define GEN7_3DSTATE_CLIP_DWordLength_bits 8 12562 #define GEN6_3DSTATE_CLIP_DWordLength_bits 8 12563 12564 static inline uint32_t ATTRIBUTE_PURE 12565 _3DSTATE_CLIP_DWordLength_bits(const struct gen_device_info *devinfo) 12566 { 12567 switch (devinfo->gen) { 12568 case 10: return 8; 12569 case 9: return 8; 12570 case 8: return 8; 12571 case 7: 12572 if (devinfo->is_haswell) { 12573 return 8; 12574 } else { 12575 return 8; 12576 } 12577 case 6: return 8; 12578 case 5: return 0; 12579 case 4: 12580 if (devinfo->is_g4x) { 12581 return 0; 12582 } else { 12583 return 0; 12584 } 12585 default: 12586 unreachable("Invalid hardware generation"); 12587 } 12588 } 12589 12590 12591 12592 #define GEN10_3DSTATE_CLIP_DWordLength_start 0 12593 #define GEN9_3DSTATE_CLIP_DWordLength_start 0 12594 #define GEN8_3DSTATE_CLIP_DWordLength_start 0 12595 #define GEN75_3DSTATE_CLIP_DWordLength_start 0 12596 #define GEN7_3DSTATE_CLIP_DWordLength_start 0 12597 #define GEN6_3DSTATE_CLIP_DWordLength_start 0 12598 12599 static inline uint32_t ATTRIBUTE_PURE 12600 _3DSTATE_CLIP_DWordLength_start(const struct gen_device_info *devinfo) 12601 { 12602 switch (devinfo->gen) { 12603 case 10: return 0; 12604 case 9: return 0; 12605 case 8: return 0; 12606 case 7: 12607 if (devinfo->is_haswell) { 12608 return 0; 12609 } else { 12610 return 0; 12611 } 12612 case 6: return 0; 12613 case 5: return 0; 12614 case 4: 12615 if (devinfo->is_g4x) { 12616 return 0; 12617 } else { 12618 return 0; 12619 } 12620 default: 12621 unreachable("Invalid hardware generation"); 12622 } 12623 } 12624 12625 12626 12627 /* 3DSTATE_CLIP::Early Cull Enable */ 12628 12629 12630 #define GEN10_3DSTATE_CLIP_EarlyCullEnable_bits 1 12631 #define GEN9_3DSTATE_CLIP_EarlyCullEnable_bits 1 12632 #define GEN8_3DSTATE_CLIP_EarlyCullEnable_bits 1 12633 #define GEN75_3DSTATE_CLIP_EarlyCullEnable_bits 1 12634 #define GEN7_3DSTATE_CLIP_EarlyCullEnable_bits 1 12635 12636 static inline uint32_t ATTRIBUTE_PURE 12637 _3DSTATE_CLIP_EarlyCullEnable_bits(const struct gen_device_info *devinfo) 12638 { 12639 switch (devinfo->gen) { 12640 case 10: return 1; 12641 case 9: return 1; 12642 case 8: return 1; 12643 case 7: 12644 if (devinfo->is_haswell) { 12645 return 1; 12646 } else { 12647 return 1; 12648 } 12649 case 6: return 0; 12650 case 5: return 0; 12651 case 4: 12652 if (devinfo->is_g4x) { 12653 return 0; 12654 } else { 12655 return 0; 12656 } 12657 default: 12658 unreachable("Invalid hardware generation"); 12659 } 12660 } 12661 12662 12663 12664 #define GEN10_3DSTATE_CLIP_EarlyCullEnable_start 50 12665 #define GEN9_3DSTATE_CLIP_EarlyCullEnable_start 50 12666 #define GEN8_3DSTATE_CLIP_EarlyCullEnable_start 50 12667 #define GEN75_3DSTATE_CLIP_EarlyCullEnable_start 50 12668 #define GEN7_3DSTATE_CLIP_EarlyCullEnable_start 50 12669 12670 static inline uint32_t ATTRIBUTE_PURE 12671 _3DSTATE_CLIP_EarlyCullEnable_start(const struct gen_device_info *devinfo) 12672 { 12673 switch (devinfo->gen) { 12674 case 10: return 50; 12675 case 9: return 50; 12676 case 8: return 50; 12677 case 7: 12678 if (devinfo->is_haswell) { 12679 return 50; 12680 } else { 12681 return 50; 12682 } 12683 case 6: return 0; 12684 case 5: return 0; 12685 case 4: 12686 if (devinfo->is_g4x) { 12687 return 0; 12688 } else { 12689 return 0; 12690 } 12691 default: 12692 unreachable("Invalid hardware generation"); 12693 } 12694 } 12695 12696 12697 12698 /* 3DSTATE_CLIP::Force Clip Mode */ 12699 12700 12701 #define GEN10_3DSTATE_CLIP_ForceClipMode_bits 1 12702 #define GEN9_3DSTATE_CLIP_ForceClipMode_bits 1 12703 #define GEN8_3DSTATE_CLIP_ForceClipMode_bits 1 12704 12705 static inline uint32_t ATTRIBUTE_PURE 12706 _3DSTATE_CLIP_ForceClipMode_bits(const struct gen_device_info *devinfo) 12707 { 12708 switch (devinfo->gen) { 12709 case 10: return 1; 12710 case 9: return 1; 12711 case 8: return 1; 12712 case 7: 12713 if (devinfo->is_haswell) { 12714 return 0; 12715 } else { 12716 return 0; 12717 } 12718 case 6: return 0; 12719 case 5: return 0; 12720 case 4: 12721 if (devinfo->is_g4x) { 12722 return 0; 12723 } else { 12724 return 0; 12725 } 12726 default: 12727 unreachable("Invalid hardware generation"); 12728 } 12729 } 12730 12731 12732 12733 #define GEN10_3DSTATE_CLIP_ForceClipMode_start 48 12734 #define GEN9_3DSTATE_CLIP_ForceClipMode_start 48 12735 #define GEN8_3DSTATE_CLIP_ForceClipMode_start 48 12736 12737 static inline uint32_t ATTRIBUTE_PURE 12738 _3DSTATE_CLIP_ForceClipMode_start(const struct gen_device_info *devinfo) 12739 { 12740 switch (devinfo->gen) { 12741 case 10: return 48; 12742 case 9: return 48; 12743 case 8: return 48; 12744 case 7: 12745 if (devinfo->is_haswell) { 12746 return 0; 12747 } else { 12748 return 0; 12749 } 12750 case 6: return 0; 12751 case 5: return 0; 12752 case 4: 12753 if (devinfo->is_g4x) { 12754 return 0; 12755 } else { 12756 return 0; 12757 } 12758 default: 12759 unreachable("Invalid hardware generation"); 12760 } 12761 } 12762 12763 12764 12765 /* 3DSTATE_CLIP::Force User Clip Distance Clip Test Enable Bitmask */ 12766 12767 12768 #define GEN10_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 12769 #define GEN9_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 12770 #define GEN8_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 12771 12772 static inline uint32_t ATTRIBUTE_PURE 12773 _3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits(const struct gen_device_info *devinfo) 12774 { 12775 switch (devinfo->gen) { 12776 case 10: return 1; 12777 case 9: return 1; 12778 case 8: return 1; 12779 case 7: 12780 if (devinfo->is_haswell) { 12781 return 0; 12782 } else { 12783 return 0; 12784 } 12785 case 6: return 0; 12786 case 5: return 0; 12787 case 4: 12788 if (devinfo->is_g4x) { 12789 return 0; 12790 } else { 12791 return 0; 12792 } 12793 default: 12794 unreachable("Invalid hardware generation"); 12795 } 12796 } 12797 12798 12799 12800 #define GEN10_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 12801 #define GEN9_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 12802 #define GEN8_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 12803 12804 static inline uint32_t ATTRIBUTE_PURE 12805 _3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start(const struct gen_device_info *devinfo) 12806 { 12807 switch (devinfo->gen) { 12808 case 10: return 49; 12809 case 9: return 49; 12810 case 8: return 49; 12811 case 7: 12812 if (devinfo->is_haswell) { 12813 return 0; 12814 } else { 12815 return 0; 12816 } 12817 case 6: return 0; 12818 case 5: return 0; 12819 case 4: 12820 if (devinfo->is_g4x) { 12821 return 0; 12822 } else { 12823 return 0; 12824 } 12825 default: 12826 unreachable("Invalid hardware generation"); 12827 } 12828 } 12829 12830 12831 12832 /* 3DSTATE_CLIP::Force User Clip Distance Cull Test Enable Bitmask */ 12833 12834 12835 #define GEN10_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 12836 #define GEN9_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 12837 #define GEN8_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 12838 12839 static inline uint32_t ATTRIBUTE_PURE 12840 _3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits(const struct gen_device_info *devinfo) 12841 { 12842 switch (devinfo->gen) { 12843 case 10: return 1; 12844 case 9: return 1; 12845 case 8: return 1; 12846 case 7: 12847 if (devinfo->is_haswell) { 12848 return 0; 12849 } else { 12850 return 0; 12851 } 12852 case 6: return 0; 12853 case 5: return 0; 12854 case 4: 12855 if (devinfo->is_g4x) { 12856 return 0; 12857 } else { 12858 return 0; 12859 } 12860 default: 12861 unreachable("Invalid hardware generation"); 12862 } 12863 } 12864 12865 12866 12867 #define GEN10_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 12868 #define GEN9_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 12869 #define GEN8_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 12870 12871 static inline uint32_t ATTRIBUTE_PURE 12872 _3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start(const struct gen_device_info *devinfo) 12873 { 12874 switch (devinfo->gen) { 12875 case 10: return 52; 12876 case 9: return 52; 12877 case 8: return 52; 12878 case 7: 12879 if (devinfo->is_haswell) { 12880 return 0; 12881 } else { 12882 return 0; 12883 } 12884 case 6: return 0; 12885 case 5: return 0; 12886 case 4: 12887 if (devinfo->is_g4x) { 12888 return 0; 12889 } else { 12890 return 0; 12891 } 12892 default: 12893 unreachable("Invalid hardware generation"); 12894 } 12895 } 12896 12897 12898 12899 /* 3DSTATE_CLIP::Force Zero RTA Index Enable */ 12900 12901 12902 #define GEN10_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 12903 #define GEN9_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 12904 #define GEN8_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 12905 #define GEN75_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 12906 #define GEN7_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 12907 #define GEN6_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 12908 12909 static inline uint32_t ATTRIBUTE_PURE 12910 _3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits(const struct gen_device_info *devinfo) 12911 { 12912 switch (devinfo->gen) { 12913 case 10: return 1; 12914 case 9: return 1; 12915 case 8: return 1; 12916 case 7: 12917 if (devinfo->is_haswell) { 12918 return 1; 12919 } else { 12920 return 1; 12921 } 12922 case 6: return 1; 12923 case 5: return 0; 12924 case 4: 12925 if (devinfo->is_g4x) { 12926 return 0; 12927 } else { 12928 return 0; 12929 } 12930 default: 12931 unreachable("Invalid hardware generation"); 12932 } 12933 } 12934 12935 12936 12937 #define GEN10_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 12938 #define GEN9_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 12939 #define GEN8_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 12940 #define GEN75_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 12941 #define GEN7_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 12942 #define GEN6_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 12943 12944 static inline uint32_t ATTRIBUTE_PURE 12945 _3DSTATE_CLIP_ForceZeroRTAIndexEnable_start(const struct gen_device_info *devinfo) 12946 { 12947 switch (devinfo->gen) { 12948 case 10: return 101; 12949 case 9: return 101; 12950 case 8: return 101; 12951 case 7: 12952 if (devinfo->is_haswell) { 12953 return 101; 12954 } else { 12955 return 101; 12956 } 12957 case 6: return 101; 12958 case 5: return 0; 12959 case 4: 12960 if (devinfo->is_g4x) { 12961 return 0; 12962 } else { 12963 return 0; 12964 } 12965 default: 12966 unreachable("Invalid hardware generation"); 12967 } 12968 } 12969 12970 12971 12972 /* 3DSTATE_CLIP::Front Winding */ 12973 12974 12975 #define GEN75_3DSTATE_CLIP_FrontWinding_bits 1 12976 #define GEN7_3DSTATE_CLIP_FrontWinding_bits 1 12977 12978 static inline uint32_t ATTRIBUTE_PURE 12979 _3DSTATE_CLIP_FrontWinding_bits(const struct gen_device_info *devinfo) 12980 { 12981 switch (devinfo->gen) { 12982 case 10: return 0; 12983 case 9: return 0; 12984 case 8: return 0; 12985 case 7: 12986 if (devinfo->is_haswell) { 12987 return 1; 12988 } else { 12989 return 1; 12990 } 12991 case 6: return 0; 12992 case 5: return 0; 12993 case 4: 12994 if (devinfo->is_g4x) { 12995 return 0; 12996 } else { 12997 return 0; 12998 } 12999 default: 13000 unreachable("Invalid hardware generation"); 13001 } 13002 } 13003 13004 13005 13006 #define GEN75_3DSTATE_CLIP_FrontWinding_start 52 13007 #define GEN7_3DSTATE_CLIP_FrontWinding_start 52 13008 13009 static inline uint32_t ATTRIBUTE_PURE 13010 _3DSTATE_CLIP_FrontWinding_start(const struct gen_device_info *devinfo) 13011 { 13012 switch (devinfo->gen) { 13013 case 10: return 0; 13014 case 9: return 0; 13015 case 8: return 0; 13016 case 7: 13017 if (devinfo->is_haswell) { 13018 return 52; 13019 } else { 13020 return 52; 13021 } 13022 case 6: return 0; 13023 case 5: return 0; 13024 case 4: 13025 if (devinfo->is_g4x) { 13026 return 0; 13027 } else { 13028 return 0; 13029 } 13030 default: 13031 unreachable("Invalid hardware generation"); 13032 } 13033 } 13034 13035 13036 13037 /* 3DSTATE_CLIP::Guardband Clip Test Enable */ 13038 13039 13040 #define GEN10_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 13041 #define GEN9_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 13042 #define GEN8_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 13043 #define GEN75_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 13044 #define GEN7_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 13045 #define GEN6_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 13046 13047 static inline uint32_t ATTRIBUTE_PURE 13048 _3DSTATE_CLIP_GuardbandClipTestEnable_bits(const struct gen_device_info *devinfo) 13049 { 13050 switch (devinfo->gen) { 13051 case 10: return 1; 13052 case 9: return 1; 13053 case 8: return 1; 13054 case 7: 13055 if (devinfo->is_haswell) { 13056 return 1; 13057 } else { 13058 return 1; 13059 } 13060 case 6: return 1; 13061 case 5: return 0; 13062 case 4: 13063 if (devinfo->is_g4x) { 13064 return 0; 13065 } else { 13066 return 0; 13067 } 13068 default: 13069 unreachable("Invalid hardware generation"); 13070 } 13071 } 13072 13073 13074 13075 #define GEN10_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 13076 #define GEN9_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 13077 #define GEN8_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 13078 #define GEN75_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 13079 #define GEN7_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 13080 #define GEN6_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 13081 13082 static inline uint32_t ATTRIBUTE_PURE 13083 _3DSTATE_CLIP_GuardbandClipTestEnable_start(const struct gen_device_info *devinfo) 13084 { 13085 switch (devinfo->gen) { 13086 case 10: return 90; 13087 case 9: return 90; 13088 case 8: return 90; 13089 case 7: 13090 if (devinfo->is_haswell) { 13091 return 90; 13092 } else { 13093 return 90; 13094 } 13095 case 6: return 90; 13096 case 5: return 0; 13097 case 4: 13098 if (devinfo->is_g4x) { 13099 return 0; 13100 } else { 13101 return 0; 13102 } 13103 default: 13104 unreachable("Invalid hardware generation"); 13105 } 13106 } 13107 13108 13109 13110 /* 3DSTATE_CLIP::Line Strip/List Provoking Vertex Select */ 13111 13112 13113 #define GEN10_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 13114 #define GEN9_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 13115 #define GEN8_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 13116 #define GEN75_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 13117 #define GEN7_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 13118 #define GEN6_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 13119 13120 static inline uint32_t ATTRIBUTE_PURE 13121 _3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits(const struct gen_device_info *devinfo) 13122 { 13123 switch (devinfo->gen) { 13124 case 10: return 2; 13125 case 9: return 2; 13126 case 8: return 2; 13127 case 7: 13128 if (devinfo->is_haswell) { 13129 return 2; 13130 } else { 13131 return 2; 13132 } 13133 case 6: return 2; 13134 case 5: return 0; 13135 case 4: 13136 if (devinfo->is_g4x) { 13137 return 0; 13138 } else { 13139 return 0; 13140 } 13141 default: 13142 unreachable("Invalid hardware generation"); 13143 } 13144 } 13145 13146 13147 13148 #define GEN10_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 13149 #define GEN9_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 13150 #define GEN8_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 13151 #define GEN75_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 13152 #define GEN7_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 13153 #define GEN6_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 13154 13155 static inline uint32_t ATTRIBUTE_PURE 13156 _3DSTATE_CLIP_LineStripListProvokingVertexSelect_start(const struct gen_device_info *devinfo) 13157 { 13158 switch (devinfo->gen) { 13159 case 10: return 66; 13160 case 9: return 66; 13161 case 8: return 66; 13162 case 7: 13163 if (devinfo->is_haswell) { 13164 return 66; 13165 } else { 13166 return 66; 13167 } 13168 case 6: return 66; 13169 case 5: return 0; 13170 case 4: 13171 if (devinfo->is_g4x) { 13172 return 0; 13173 } else { 13174 return 0; 13175 } 13176 default: 13177 unreachable("Invalid hardware generation"); 13178 } 13179 } 13180 13181 13182 13183 /* 3DSTATE_CLIP::Maximum Point Width */ 13184 13185 13186 #define GEN10_3DSTATE_CLIP_MaximumPointWidth_bits 11 13187 #define GEN9_3DSTATE_CLIP_MaximumPointWidth_bits 11 13188 #define GEN8_3DSTATE_CLIP_MaximumPointWidth_bits 11 13189 #define GEN75_3DSTATE_CLIP_MaximumPointWidth_bits 11 13190 #define GEN7_3DSTATE_CLIP_MaximumPointWidth_bits 11 13191 #define GEN6_3DSTATE_CLIP_MaximumPointWidth_bits 11 13192 13193 static inline uint32_t ATTRIBUTE_PURE 13194 _3DSTATE_CLIP_MaximumPointWidth_bits(const struct gen_device_info *devinfo) 13195 { 13196 switch (devinfo->gen) { 13197 case 10: return 11; 13198 case 9: return 11; 13199 case 8: return 11; 13200 case 7: 13201 if (devinfo->is_haswell) { 13202 return 11; 13203 } else { 13204 return 11; 13205 } 13206 case 6: return 11; 13207 case 5: return 0; 13208 case 4: 13209 if (devinfo->is_g4x) { 13210 return 0; 13211 } else { 13212 return 0; 13213 } 13214 default: 13215 unreachable("Invalid hardware generation"); 13216 } 13217 } 13218 13219 13220 13221 #define GEN10_3DSTATE_CLIP_MaximumPointWidth_start 102 13222 #define GEN9_3DSTATE_CLIP_MaximumPointWidth_start 102 13223 #define GEN8_3DSTATE_CLIP_MaximumPointWidth_start 102 13224 #define GEN75_3DSTATE_CLIP_MaximumPointWidth_start 102 13225 #define GEN7_3DSTATE_CLIP_MaximumPointWidth_start 102 13226 #define GEN6_3DSTATE_CLIP_MaximumPointWidth_start 102 13227 13228 static inline uint32_t ATTRIBUTE_PURE 13229 _3DSTATE_CLIP_MaximumPointWidth_start(const struct gen_device_info *devinfo) 13230 { 13231 switch (devinfo->gen) { 13232 case 10: return 102; 13233 case 9: return 102; 13234 case 8: return 102; 13235 case 7: 13236 if (devinfo->is_haswell) { 13237 return 102; 13238 } else { 13239 return 102; 13240 } 13241 case 6: return 102; 13242 case 5: return 0; 13243 case 4: 13244 if (devinfo->is_g4x) { 13245 return 0; 13246 } else { 13247 return 0; 13248 } 13249 default: 13250 unreachable("Invalid hardware generation"); 13251 } 13252 } 13253 13254 13255 13256 /* 3DSTATE_CLIP::Maximum VP Index */ 13257 13258 13259 #define GEN10_3DSTATE_CLIP_MaximumVPIndex_bits 4 13260 #define GEN9_3DSTATE_CLIP_MaximumVPIndex_bits 4 13261 #define GEN8_3DSTATE_CLIP_MaximumVPIndex_bits 4 13262 #define GEN75_3DSTATE_CLIP_MaximumVPIndex_bits 4 13263 #define GEN7_3DSTATE_CLIP_MaximumVPIndex_bits 4 13264 #define GEN6_3DSTATE_CLIP_MaximumVPIndex_bits 4 13265 13266 static inline uint32_t ATTRIBUTE_PURE 13267 _3DSTATE_CLIP_MaximumVPIndex_bits(const struct gen_device_info *devinfo) 13268 { 13269 switch (devinfo->gen) { 13270 case 10: return 4; 13271 case 9: return 4; 13272 case 8: return 4; 13273 case 7: 13274 if (devinfo->is_haswell) { 13275 return 4; 13276 } else { 13277 return 4; 13278 } 13279 case 6: return 4; 13280 case 5: return 0; 13281 case 4: 13282 if (devinfo->is_g4x) { 13283 return 0; 13284 } else { 13285 return 0; 13286 } 13287 default: 13288 unreachable("Invalid hardware generation"); 13289 } 13290 } 13291 13292 13293 13294 #define GEN10_3DSTATE_CLIP_MaximumVPIndex_start 96 13295 #define GEN9_3DSTATE_CLIP_MaximumVPIndex_start 96 13296 #define GEN8_3DSTATE_CLIP_MaximumVPIndex_start 96 13297 #define GEN75_3DSTATE_CLIP_MaximumVPIndex_start 96 13298 #define GEN7_3DSTATE_CLIP_MaximumVPIndex_start 96 13299 #define GEN6_3DSTATE_CLIP_MaximumVPIndex_start 96 13300 13301 static inline uint32_t ATTRIBUTE_PURE 13302 _3DSTATE_CLIP_MaximumVPIndex_start(const struct gen_device_info *devinfo) 13303 { 13304 switch (devinfo->gen) { 13305 case 10: return 96; 13306 case 9: return 96; 13307 case 8: return 96; 13308 case 7: 13309 if (devinfo->is_haswell) { 13310 return 96; 13311 } else { 13312 return 96; 13313 } 13314 case 6: return 96; 13315 case 5: return 0; 13316 case 4: 13317 if (devinfo->is_g4x) { 13318 return 0; 13319 } else { 13320 return 0; 13321 } 13322 default: 13323 unreachable("Invalid hardware generation"); 13324 } 13325 } 13326 13327 13328 13329 /* 3DSTATE_CLIP::Minimum Point Width */ 13330 13331 13332 #define GEN10_3DSTATE_CLIP_MinimumPointWidth_bits 11 13333 #define GEN9_3DSTATE_CLIP_MinimumPointWidth_bits 11 13334 #define GEN8_3DSTATE_CLIP_MinimumPointWidth_bits 11 13335 #define GEN75_3DSTATE_CLIP_MinimumPointWidth_bits 11 13336 #define GEN7_3DSTATE_CLIP_MinimumPointWidth_bits 11 13337 #define GEN6_3DSTATE_CLIP_MinimumPointWidth_bits 11 13338 13339 static inline uint32_t ATTRIBUTE_PURE 13340 _3DSTATE_CLIP_MinimumPointWidth_bits(const struct gen_device_info *devinfo) 13341 { 13342 switch (devinfo->gen) { 13343 case 10: return 11; 13344 case 9: return 11; 13345 case 8: return 11; 13346 case 7: 13347 if (devinfo->is_haswell) { 13348 return 11; 13349 } else { 13350 return 11; 13351 } 13352 case 6: return 11; 13353 case 5: return 0; 13354 case 4: 13355 if (devinfo->is_g4x) { 13356 return 0; 13357 } else { 13358 return 0; 13359 } 13360 default: 13361 unreachable("Invalid hardware generation"); 13362 } 13363 } 13364 13365 13366 13367 #define GEN10_3DSTATE_CLIP_MinimumPointWidth_start 113 13368 #define GEN9_3DSTATE_CLIP_MinimumPointWidth_start 113 13369 #define GEN8_3DSTATE_CLIP_MinimumPointWidth_start 113 13370 #define GEN75_3DSTATE_CLIP_MinimumPointWidth_start 113 13371 #define GEN7_3DSTATE_CLIP_MinimumPointWidth_start 113 13372 #define GEN6_3DSTATE_CLIP_MinimumPointWidth_start 113 13373 13374 static inline uint32_t ATTRIBUTE_PURE 13375 _3DSTATE_CLIP_MinimumPointWidth_start(const struct gen_device_info *devinfo) 13376 { 13377 switch (devinfo->gen) { 13378 case 10: return 113; 13379 case 9: return 113; 13380 case 8: return 113; 13381 case 7: 13382 if (devinfo->is_haswell) { 13383 return 113; 13384 } else { 13385 return 113; 13386 } 13387 case 6: return 113; 13388 case 5: return 0; 13389 case 4: 13390 if (devinfo->is_g4x) { 13391 return 0; 13392 } else { 13393 return 0; 13394 } 13395 default: 13396 unreachable("Invalid hardware generation"); 13397 } 13398 } 13399 13400 13401 13402 /* 3DSTATE_CLIP::Non-Perspective Barycentric Enable */ 13403 13404 13405 #define GEN10_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 13406 #define GEN9_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 13407 #define GEN8_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 13408 #define GEN75_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 13409 #define GEN7_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 13410 #define GEN6_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 13411 13412 static inline uint32_t ATTRIBUTE_PURE 13413 _3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits(const struct gen_device_info *devinfo) 13414 { 13415 switch (devinfo->gen) { 13416 case 10: return 1; 13417 case 9: return 1; 13418 case 8: return 1; 13419 case 7: 13420 if (devinfo->is_haswell) { 13421 return 1; 13422 } else { 13423 return 1; 13424 } 13425 case 6: return 1; 13426 case 5: return 0; 13427 case 4: 13428 if (devinfo->is_g4x) { 13429 return 0; 13430 } else { 13431 return 0; 13432 } 13433 default: 13434 unreachable("Invalid hardware generation"); 13435 } 13436 } 13437 13438 13439 13440 #define GEN10_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 13441 #define GEN9_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 13442 #define GEN8_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 13443 #define GEN75_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 13444 #define GEN7_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 13445 #define GEN6_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 13446 13447 static inline uint32_t ATTRIBUTE_PURE 13448 _3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start(const struct gen_device_info *devinfo) 13449 { 13450 switch (devinfo->gen) { 13451 case 10: return 72; 13452 case 9: return 72; 13453 case 8: return 72; 13454 case 7: 13455 if (devinfo->is_haswell) { 13456 return 72; 13457 } else { 13458 return 72; 13459 } 13460 case 6: return 72; 13461 case 5: return 0; 13462 case 4: 13463 if (devinfo->is_g4x) { 13464 return 0; 13465 } else { 13466 return 0; 13467 } 13468 default: 13469 unreachable("Invalid hardware generation"); 13470 } 13471 } 13472 13473 13474 13475 /* 3DSTATE_CLIP::Perspective Divide Disable */ 13476 13477 13478 #define GEN10_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 13479 #define GEN9_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 13480 #define GEN8_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 13481 #define GEN75_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 13482 #define GEN7_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 13483 #define GEN6_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 13484 13485 static inline uint32_t ATTRIBUTE_PURE 13486 _3DSTATE_CLIP_PerspectiveDivideDisable_bits(const struct gen_device_info *devinfo) 13487 { 13488 switch (devinfo->gen) { 13489 case 10: return 1; 13490 case 9: return 1; 13491 case 8: return 1; 13492 case 7: 13493 if (devinfo->is_haswell) { 13494 return 1; 13495 } else { 13496 return 1; 13497 } 13498 case 6: return 1; 13499 case 5: return 0; 13500 case 4: 13501 if (devinfo->is_g4x) { 13502 return 0; 13503 } else { 13504 return 0; 13505 } 13506 default: 13507 unreachable("Invalid hardware generation"); 13508 } 13509 } 13510 13511 13512 13513 #define GEN10_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 13514 #define GEN9_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 13515 #define GEN8_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 13516 #define GEN75_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 13517 #define GEN7_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 13518 #define GEN6_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 13519 13520 static inline uint32_t ATTRIBUTE_PURE 13521 _3DSTATE_CLIP_PerspectiveDivideDisable_start(const struct gen_device_info *devinfo) 13522 { 13523 switch (devinfo->gen) { 13524 case 10: return 73; 13525 case 9: return 73; 13526 case 8: return 73; 13527 case 7: 13528 if (devinfo->is_haswell) { 13529 return 73; 13530 } else { 13531 return 73; 13532 } 13533 case 6: return 73; 13534 case 5: return 0; 13535 case 4: 13536 if (devinfo->is_g4x) { 13537 return 0; 13538 } else { 13539 return 0; 13540 } 13541 default: 13542 unreachable("Invalid hardware generation"); 13543 } 13544 } 13545 13546 13547 13548 /* 3DSTATE_CLIP::Statistics Enable */ 13549 13550 13551 #define GEN10_3DSTATE_CLIP_StatisticsEnable_bits 1 13552 #define GEN9_3DSTATE_CLIP_StatisticsEnable_bits 1 13553 #define GEN8_3DSTATE_CLIP_StatisticsEnable_bits 1 13554 #define GEN75_3DSTATE_CLIP_StatisticsEnable_bits 1 13555 #define GEN7_3DSTATE_CLIP_StatisticsEnable_bits 1 13556 #define GEN6_3DSTATE_CLIP_StatisticsEnable_bits 1 13557 13558 static inline uint32_t ATTRIBUTE_PURE 13559 _3DSTATE_CLIP_StatisticsEnable_bits(const struct gen_device_info *devinfo) 13560 { 13561 switch (devinfo->gen) { 13562 case 10: return 1; 13563 case 9: return 1; 13564 case 8: return 1; 13565 case 7: 13566 if (devinfo->is_haswell) { 13567 return 1; 13568 } else { 13569 return 1; 13570 } 13571 case 6: return 1; 13572 case 5: return 0; 13573 case 4: 13574 if (devinfo->is_g4x) { 13575 return 0; 13576 } else { 13577 return 0; 13578 } 13579 default: 13580 unreachable("Invalid hardware generation"); 13581 } 13582 } 13583 13584 13585 13586 #define GEN10_3DSTATE_CLIP_StatisticsEnable_start 42 13587 #define GEN9_3DSTATE_CLIP_StatisticsEnable_start 42 13588 #define GEN8_3DSTATE_CLIP_StatisticsEnable_start 42 13589 #define GEN75_3DSTATE_CLIP_StatisticsEnable_start 42 13590 #define GEN7_3DSTATE_CLIP_StatisticsEnable_start 42 13591 #define GEN6_3DSTATE_CLIP_StatisticsEnable_start 42 13592 13593 static inline uint32_t ATTRIBUTE_PURE 13594 _3DSTATE_CLIP_StatisticsEnable_start(const struct gen_device_info *devinfo) 13595 { 13596 switch (devinfo->gen) { 13597 case 10: return 42; 13598 case 9: return 42; 13599 case 8: return 42; 13600 case 7: 13601 if (devinfo->is_haswell) { 13602 return 42; 13603 } else { 13604 return 42; 13605 } 13606 case 6: return 42; 13607 case 5: return 0; 13608 case 4: 13609 if (devinfo->is_g4x) { 13610 return 0; 13611 } else { 13612 return 0; 13613 } 13614 default: 13615 unreachable("Invalid hardware generation"); 13616 } 13617 } 13618 13619 13620 13621 /* 3DSTATE_CLIP::Triangle Fan Provoking Vertex Select */ 13622 13623 13624 #define GEN10_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 13625 #define GEN9_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 13626 #define GEN8_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 13627 #define GEN75_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 13628 #define GEN7_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 13629 #define GEN6_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 13630 13631 static inline uint32_t ATTRIBUTE_PURE 13632 _3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits(const struct gen_device_info *devinfo) 13633 { 13634 switch (devinfo->gen) { 13635 case 10: return 2; 13636 case 9: return 2; 13637 case 8: return 2; 13638 case 7: 13639 if (devinfo->is_haswell) { 13640 return 2; 13641 } else { 13642 return 2; 13643 } 13644 case 6: return 2; 13645 case 5: return 0; 13646 case 4: 13647 if (devinfo->is_g4x) { 13648 return 0; 13649 } else { 13650 return 0; 13651 } 13652 default: 13653 unreachable("Invalid hardware generation"); 13654 } 13655 } 13656 13657 13658 13659 #define GEN10_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 13660 #define GEN9_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 13661 #define GEN8_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 13662 #define GEN75_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 13663 #define GEN7_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 13664 #define GEN6_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 13665 13666 static inline uint32_t ATTRIBUTE_PURE 13667 _3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start(const struct gen_device_info *devinfo) 13668 { 13669 switch (devinfo->gen) { 13670 case 10: return 64; 13671 case 9: return 64; 13672 case 8: return 64; 13673 case 7: 13674 if (devinfo->is_haswell) { 13675 return 64; 13676 } else { 13677 return 64; 13678 } 13679 case 6: return 64; 13680 case 5: return 0; 13681 case 4: 13682 if (devinfo->is_g4x) { 13683 return 0; 13684 } else { 13685 return 0; 13686 } 13687 default: 13688 unreachable("Invalid hardware generation"); 13689 } 13690 } 13691 13692 13693 13694 /* 3DSTATE_CLIP::Triangle Strip/List Provoking Vertex Select */ 13695 13696 13697 #define GEN10_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 13698 #define GEN9_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 13699 #define GEN8_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 13700 #define GEN75_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 13701 #define GEN7_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 13702 #define GEN6_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 13703 13704 static inline uint32_t ATTRIBUTE_PURE 13705 _3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits(const struct gen_device_info *devinfo) 13706 { 13707 switch (devinfo->gen) { 13708 case 10: return 2; 13709 case 9: return 2; 13710 case 8: return 2; 13711 case 7: 13712 if (devinfo->is_haswell) { 13713 return 2; 13714 } else { 13715 return 2; 13716 } 13717 case 6: return 2; 13718 case 5: return 0; 13719 case 4: 13720 if (devinfo->is_g4x) { 13721 return 0; 13722 } else { 13723 return 0; 13724 } 13725 default: 13726 unreachable("Invalid hardware generation"); 13727 } 13728 } 13729 13730 13731 13732 #define GEN10_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 13733 #define GEN9_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 13734 #define GEN8_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 13735 #define GEN75_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 13736 #define GEN7_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 13737 #define GEN6_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 13738 13739 static inline uint32_t ATTRIBUTE_PURE 13740 _3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start(const struct gen_device_info *devinfo) 13741 { 13742 switch (devinfo->gen) { 13743 case 10: return 68; 13744 case 9: return 68; 13745 case 8: return 68; 13746 case 7: 13747 if (devinfo->is_haswell) { 13748 return 68; 13749 } else { 13750 return 68; 13751 } 13752 case 6: return 68; 13753 case 5: return 0; 13754 case 4: 13755 if (devinfo->is_g4x) { 13756 return 0; 13757 } else { 13758 return 0; 13759 } 13760 default: 13761 unreachable("Invalid hardware generation"); 13762 } 13763 } 13764 13765 13766 13767 /* 3DSTATE_CLIP::User Clip Distance Clip Test Enable Bitmask */ 13768 13769 13770 #define GEN10_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 13771 #define GEN9_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 13772 #define GEN8_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 13773 #define GEN75_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 13774 #define GEN7_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 13775 #define GEN6_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 13776 13777 static inline uint32_t ATTRIBUTE_PURE 13778 _3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits(const struct gen_device_info *devinfo) 13779 { 13780 switch (devinfo->gen) { 13781 case 10: return 8; 13782 case 9: return 8; 13783 case 8: return 8; 13784 case 7: 13785 if (devinfo->is_haswell) { 13786 return 8; 13787 } else { 13788 return 8; 13789 } 13790 case 6: return 8; 13791 case 5: return 0; 13792 case 4: 13793 if (devinfo->is_g4x) { 13794 return 0; 13795 } else { 13796 return 0; 13797 } 13798 default: 13799 unreachable("Invalid hardware generation"); 13800 } 13801 } 13802 13803 13804 13805 #define GEN10_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 13806 #define GEN9_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 13807 #define GEN8_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 13808 #define GEN75_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 13809 #define GEN7_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 13810 #define GEN6_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 13811 13812 static inline uint32_t ATTRIBUTE_PURE 13813 _3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start(const struct gen_device_info *devinfo) 13814 { 13815 switch (devinfo->gen) { 13816 case 10: return 80; 13817 case 9: return 80; 13818 case 8: return 80; 13819 case 7: 13820 if (devinfo->is_haswell) { 13821 return 80; 13822 } else { 13823 return 80; 13824 } 13825 case 6: return 80; 13826 case 5: return 0; 13827 case 4: 13828 if (devinfo->is_g4x) { 13829 return 0; 13830 } else { 13831 return 0; 13832 } 13833 default: 13834 unreachable("Invalid hardware generation"); 13835 } 13836 } 13837 13838 13839 13840 /* 3DSTATE_CLIP::User Clip Distance Cull Test Enable Bitmask */ 13841 13842 13843 #define GEN10_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 13844 #define GEN9_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 13845 #define GEN8_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 13846 #define GEN75_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 13847 #define GEN7_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 13848 #define GEN6_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 13849 13850 static inline uint32_t ATTRIBUTE_PURE 13851 _3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits(const struct gen_device_info *devinfo) 13852 { 13853 switch (devinfo->gen) { 13854 case 10: return 8; 13855 case 9: return 8; 13856 case 8: return 8; 13857 case 7: 13858 if (devinfo->is_haswell) { 13859 return 8; 13860 } else { 13861 return 8; 13862 } 13863 case 6: return 8; 13864 case 5: return 0; 13865 case 4: 13866 if (devinfo->is_g4x) { 13867 return 0; 13868 } else { 13869 return 0; 13870 } 13871 default: 13872 unreachable("Invalid hardware generation"); 13873 } 13874 } 13875 13876 13877 13878 #define GEN10_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 13879 #define GEN9_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 13880 #define GEN8_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 13881 #define GEN75_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 13882 #define GEN7_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 13883 #define GEN6_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 13884 13885 static inline uint32_t ATTRIBUTE_PURE 13886 _3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start(const struct gen_device_info *devinfo) 13887 { 13888 switch (devinfo->gen) { 13889 case 10: return 32; 13890 case 9: return 32; 13891 case 8: return 32; 13892 case 7: 13893 if (devinfo->is_haswell) { 13894 return 32; 13895 } else { 13896 return 32; 13897 } 13898 case 6: return 32; 13899 case 5: return 0; 13900 case 4: 13901 if (devinfo->is_g4x) { 13902 return 0; 13903 } else { 13904 return 0; 13905 } 13906 default: 13907 unreachable("Invalid hardware generation"); 13908 } 13909 } 13910 13911 13912 13913 /* 3DSTATE_CLIP::Vertex Sub Pixel Precision Select */ 13914 13915 13916 #define GEN10_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 13917 #define GEN9_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 13918 #define GEN8_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 13919 #define GEN75_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 13920 #define GEN7_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 13921 13922 static inline uint32_t ATTRIBUTE_PURE 13923 _3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits(const struct gen_device_info *devinfo) 13924 { 13925 switch (devinfo->gen) { 13926 case 10: return 1; 13927 case 9: return 1; 13928 case 8: return 1; 13929 case 7: 13930 if (devinfo->is_haswell) { 13931 return 1; 13932 } else { 13933 return 1; 13934 } 13935 case 6: return 0; 13936 case 5: return 0; 13937 case 4: 13938 if (devinfo->is_g4x) { 13939 return 0; 13940 } else { 13941 return 0; 13942 } 13943 default: 13944 unreachable("Invalid hardware generation"); 13945 } 13946 } 13947 13948 13949 13950 #define GEN10_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 13951 #define GEN9_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 13952 #define GEN8_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 13953 #define GEN75_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 13954 #define GEN7_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 13955 13956 static inline uint32_t ATTRIBUTE_PURE 13957 _3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start(const struct gen_device_info *devinfo) 13958 { 13959 switch (devinfo->gen) { 13960 case 10: return 51; 13961 case 9: return 51; 13962 case 8: return 51; 13963 case 7: 13964 if (devinfo->is_haswell) { 13965 return 51; 13966 } else { 13967 return 51; 13968 } 13969 case 6: return 0; 13970 case 5: return 0; 13971 case 4: 13972 if (devinfo->is_g4x) { 13973 return 0; 13974 } else { 13975 return 0; 13976 } 13977 default: 13978 unreachable("Invalid hardware generation"); 13979 } 13980 } 13981 13982 13983 13984 /* 3DSTATE_CLIP::Viewport XY Clip Test Enable */ 13985 13986 13987 #define GEN10_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 13988 #define GEN9_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 13989 #define GEN8_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 13990 #define GEN75_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 13991 #define GEN7_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 13992 #define GEN6_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 13993 13994 static inline uint32_t ATTRIBUTE_PURE 13995 _3DSTATE_CLIP_ViewportXYClipTestEnable_bits(const struct gen_device_info *devinfo) 13996 { 13997 switch (devinfo->gen) { 13998 case 10: return 1; 13999 case 9: return 1; 14000 case 8: return 1; 14001 case 7: 14002 if (devinfo->is_haswell) { 14003 return 1; 14004 } else { 14005 return 1; 14006 } 14007 case 6: return 1; 14008 case 5: return 0; 14009 case 4: 14010 if (devinfo->is_g4x) { 14011 return 0; 14012 } else { 14013 return 0; 14014 } 14015 default: 14016 unreachable("Invalid hardware generation"); 14017 } 14018 } 14019 14020 14021 14022 #define GEN10_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 14023 #define GEN9_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 14024 #define GEN8_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 14025 #define GEN75_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 14026 #define GEN7_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 14027 #define GEN6_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 14028 14029 static inline uint32_t ATTRIBUTE_PURE 14030 _3DSTATE_CLIP_ViewportXYClipTestEnable_start(const struct gen_device_info *devinfo) 14031 { 14032 switch (devinfo->gen) { 14033 case 10: return 92; 14034 case 9: return 92; 14035 case 8: return 92; 14036 case 7: 14037 if (devinfo->is_haswell) { 14038 return 92; 14039 } else { 14040 return 92; 14041 } 14042 case 6: return 92; 14043 case 5: return 0; 14044 case 4: 14045 if (devinfo->is_g4x) { 14046 return 0; 14047 } else { 14048 return 0; 14049 } 14050 default: 14051 unreachable("Invalid hardware generation"); 14052 } 14053 } 14054 14055 14056 14057 /* 3DSTATE_CLIP::Viewport Z Clip Test Enable */ 14058 14059 14060 #define GEN75_3DSTATE_CLIP_ViewportZClipTestEnable_bits 1 14061 #define GEN7_3DSTATE_CLIP_ViewportZClipTestEnable_bits 1 14062 #define GEN6_3DSTATE_CLIP_ViewportZClipTestEnable_bits 1 14063 14064 static inline uint32_t ATTRIBUTE_PURE 14065 _3DSTATE_CLIP_ViewportZClipTestEnable_bits(const struct gen_device_info *devinfo) 14066 { 14067 switch (devinfo->gen) { 14068 case 10: return 0; 14069 case 9: return 0; 14070 case 8: return 0; 14071 case 7: 14072 if (devinfo->is_haswell) { 14073 return 1; 14074 } else { 14075 return 1; 14076 } 14077 case 6: return 1; 14078 case 5: return 0; 14079 case 4: 14080 if (devinfo->is_g4x) { 14081 return 0; 14082 } else { 14083 return 0; 14084 } 14085 default: 14086 unreachable("Invalid hardware generation"); 14087 } 14088 } 14089 14090 14091 14092 #define GEN75_3DSTATE_CLIP_ViewportZClipTestEnable_start 91 14093 #define GEN7_3DSTATE_CLIP_ViewportZClipTestEnable_start 91 14094 #define GEN6_3DSTATE_CLIP_ViewportZClipTestEnable_start 91 14095 14096 static inline uint32_t ATTRIBUTE_PURE 14097 _3DSTATE_CLIP_ViewportZClipTestEnable_start(const struct gen_device_info *devinfo) 14098 { 14099 switch (devinfo->gen) { 14100 case 10: return 0; 14101 case 9: return 0; 14102 case 8: return 0; 14103 case 7: 14104 if (devinfo->is_haswell) { 14105 return 91; 14106 } else { 14107 return 91; 14108 } 14109 case 6: return 91; 14110 case 5: return 0; 14111 case 4: 14112 if (devinfo->is_g4x) { 14113 return 0; 14114 } else { 14115 return 0; 14116 } 14117 default: 14118 unreachable("Invalid hardware generation"); 14119 } 14120 } 14121 14122 14123 14124 /* 3DSTATE_CONSTANT_BODY */ 14125 14126 14127 #define GEN10_3DSTATE_CONSTANT_BODY_length 10 14128 #define GEN9_3DSTATE_CONSTANT_BODY_length 10 14129 #define GEN8_3DSTATE_CONSTANT_BODY_length 10 14130 #define GEN75_3DSTATE_CONSTANT_BODY_length 6 14131 #define GEN7_3DSTATE_CONSTANT_BODY_length 6 14132 14133 static inline uint32_t ATTRIBUTE_PURE 14134 _3DSTATE_CONSTANT_BODY_length(const struct gen_device_info *devinfo) 14135 { 14136 switch (devinfo->gen) { 14137 case 10: return 10; 14138 case 9: return 10; 14139 case 8: return 10; 14140 case 7: 14141 if (devinfo->is_haswell) { 14142 return 6; 14143 } else { 14144 return 6; 14145 } 14146 case 6: return 0; 14147 case 5: return 0; 14148 case 4: 14149 if (devinfo->is_g4x) { 14150 return 0; 14151 } else { 14152 return 0; 14153 } 14154 default: 14155 unreachable("Invalid hardware generation"); 14156 } 14157 } 14158 14159 14160 14161 /* 3DSTATE_CONSTANT_BODY::Buffer */ 14162 14163 14164 #define GEN10_3DSTATE_CONSTANT_BODY_Buffer_bits 59 14165 #define GEN9_3DSTATE_CONSTANT_BODY_Buffer_bits 59 14166 #define GEN8_3DSTATE_CONSTANT_BODY_Buffer_bits 59 14167 #define GEN75_3DSTATE_CONSTANT_BODY_Buffer_bits 27 14168 #define GEN7_3DSTATE_CONSTANT_BODY_Buffer_bits 27 14169 14170 static inline uint32_t ATTRIBUTE_PURE 14171 _3DSTATE_CONSTANT_BODY_Buffer_bits(const struct gen_device_info *devinfo) 14172 { 14173 switch (devinfo->gen) { 14174 case 10: return 59; 14175 case 9: return 59; 14176 case 8: return 59; 14177 case 7: 14178 if (devinfo->is_haswell) { 14179 return 27; 14180 } else { 14181 return 27; 14182 } 14183 case 6: return 0; 14184 case 5: return 0; 14185 case 4: 14186 if (devinfo->is_g4x) { 14187 return 0; 14188 } else { 14189 return 0; 14190 } 14191 default: 14192 unreachable("Invalid hardware generation"); 14193 } 14194 } 14195 14196 14197 14198 #define GEN10_3DSTATE_CONSTANT_BODY_Buffer_start 5 14199 #define GEN9_3DSTATE_CONSTANT_BODY_Buffer_start 5 14200 #define GEN8_3DSTATE_CONSTANT_BODY_Buffer_start 5 14201 #define GEN75_3DSTATE_CONSTANT_BODY_Buffer_start 5 14202 #define GEN7_3DSTATE_CONSTANT_BODY_Buffer_start 5 14203 14204 static inline uint32_t ATTRIBUTE_PURE 14205 _3DSTATE_CONSTANT_BODY_Buffer_start(const struct gen_device_info *devinfo) 14206 { 14207 switch (devinfo->gen) { 14208 case 10: return 5; 14209 case 9: return 5; 14210 case 8: return 5; 14211 case 7: 14212 if (devinfo->is_haswell) { 14213 return 5; 14214 } else { 14215 return 5; 14216 } 14217 case 6: return 0; 14218 case 5: return 0; 14219 case 4: 14220 if (devinfo->is_g4x) { 14221 return 0; 14222 } else { 14223 return 0; 14224 } 14225 default: 14226 unreachable("Invalid hardware generation"); 14227 } 14228 } 14229 14230 14231 14232 /* 3DSTATE_CONSTANT_BODY::Constant Buffer Object Control State */ 14233 14234 14235 #define GEN75_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_bits 5 14236 #define GEN7_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_bits 5 14237 14238 static inline uint32_t ATTRIBUTE_PURE 14239 _3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) 14240 { 14241 switch (devinfo->gen) { 14242 case 10: return 0; 14243 case 9: return 0; 14244 case 8: return 0; 14245 case 7: 14246 if (devinfo->is_haswell) { 14247 return 5; 14248 } else { 14249 return 5; 14250 } 14251 case 6: return 0; 14252 case 5: return 0; 14253 case 4: 14254 if (devinfo->is_g4x) { 14255 return 0; 14256 } else { 14257 return 0; 14258 } 14259 default: 14260 unreachable("Invalid hardware generation"); 14261 } 14262 } 14263 14264 14265 14266 #define GEN75_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_start 64 14267 #define GEN7_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_start 64 14268 14269 static inline uint32_t ATTRIBUTE_PURE 14270 _3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) 14271 { 14272 switch (devinfo->gen) { 14273 case 10: return 0; 14274 case 9: return 0; 14275 case 8: return 0; 14276 case 7: 14277 if (devinfo->is_haswell) { 14278 return 64; 14279 } else { 14280 return 64; 14281 } 14282 case 6: return 0; 14283 case 5: return 0; 14284 case 4: 14285 if (devinfo->is_g4x) { 14286 return 0; 14287 } else { 14288 return 0; 14289 } 14290 default: 14291 unreachable("Invalid hardware generation"); 14292 } 14293 } 14294 14295 14296 14297 /* 3DSTATE_CONSTANT_BODY::Read Length */ 14298 14299 14300 #define GEN10_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 14301 #define GEN9_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 14302 #define GEN8_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 14303 #define GEN75_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 14304 #define GEN7_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 14305 14306 static inline uint32_t ATTRIBUTE_PURE 14307 _3DSTATE_CONSTANT_BODY_ReadLength_bits(const struct gen_device_info *devinfo) 14308 { 14309 switch (devinfo->gen) { 14310 case 10: return 16; 14311 case 9: return 16; 14312 case 8: return 16; 14313 case 7: 14314 if (devinfo->is_haswell) { 14315 return 16; 14316 } else { 14317 return 16; 14318 } 14319 case 6: return 0; 14320 case 5: return 0; 14321 case 4: 14322 if (devinfo->is_g4x) { 14323 return 0; 14324 } else { 14325 return 0; 14326 } 14327 default: 14328 unreachable("Invalid hardware generation"); 14329 } 14330 } 14331 14332 14333 14334 #define GEN10_3DSTATE_CONSTANT_BODY_ReadLength_start 0 14335 #define GEN9_3DSTATE_CONSTANT_BODY_ReadLength_start 0 14336 #define GEN8_3DSTATE_CONSTANT_BODY_ReadLength_start 0 14337 #define GEN75_3DSTATE_CONSTANT_BODY_ReadLength_start 0 14338 #define GEN7_3DSTATE_CONSTANT_BODY_ReadLength_start 0 14339 14340 static inline uint32_t ATTRIBUTE_PURE 14341 _3DSTATE_CONSTANT_BODY_ReadLength_start(const struct gen_device_info *devinfo) 14342 { 14343 switch (devinfo->gen) { 14344 case 10: return 0; 14345 case 9: return 0; 14346 case 8: return 0; 14347 case 7: 14348 if (devinfo->is_haswell) { 14349 return 0; 14350 } else { 14351 return 0; 14352 } 14353 case 6: return 0; 14354 case 5: return 0; 14355 case 4: 14356 if (devinfo->is_g4x) { 14357 return 0; 14358 } else { 14359 return 0; 14360 } 14361 default: 14362 unreachable("Invalid hardware generation"); 14363 } 14364 } 14365 14366 14367 14368 /* 3DSTATE_CONSTANT_COLOR */ 14369 14370 14371 #define GEN5_3DSTATE_CONSTANT_COLOR_length 5 14372 #define GEN45_3DSTATE_CONSTANT_COLOR_length 5 14373 #define GEN4_3DSTATE_CONSTANT_COLOR_length 5 14374 14375 static inline uint32_t ATTRIBUTE_PURE 14376 _3DSTATE_CONSTANT_COLOR_length(const struct gen_device_info *devinfo) 14377 { 14378 switch (devinfo->gen) { 14379 case 10: return 0; 14380 case 9: return 0; 14381 case 8: return 0; 14382 case 7: 14383 if (devinfo->is_haswell) { 14384 return 0; 14385 } else { 14386 return 0; 14387 } 14388 case 6: return 0; 14389 case 5: return 5; 14390 case 4: 14391 if (devinfo->is_g4x) { 14392 return 5; 14393 } else { 14394 return 5; 14395 } 14396 default: 14397 unreachable("Invalid hardware generation"); 14398 } 14399 } 14400 14401 14402 14403 /* 3DSTATE_CONSTANT_COLOR::3D Command Opcode */ 14404 14405 14406 #define GEN5_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits 3 14407 #define GEN45_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits 3 14408 #define GEN4_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits 3 14409 14410 static inline uint32_t ATTRIBUTE_PURE 14411 _3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 14412 { 14413 switch (devinfo->gen) { 14414 case 10: return 0; 14415 case 9: return 0; 14416 case 8: return 0; 14417 case 7: 14418 if (devinfo->is_haswell) { 14419 return 0; 14420 } else { 14421 return 0; 14422 } 14423 case 6: return 0; 14424 case 5: return 3; 14425 case 4: 14426 if (devinfo->is_g4x) { 14427 return 3; 14428 } else { 14429 return 3; 14430 } 14431 default: 14432 unreachable("Invalid hardware generation"); 14433 } 14434 } 14435 14436 14437 14438 #define GEN5_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start 24 14439 #define GEN45_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start 24 14440 #define GEN4_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start 24 14441 14442 static inline uint32_t ATTRIBUTE_PURE 14443 _3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start(const struct gen_device_info *devinfo) 14444 { 14445 switch (devinfo->gen) { 14446 case 10: return 0; 14447 case 9: return 0; 14448 case 8: return 0; 14449 case 7: 14450 if (devinfo->is_haswell) { 14451 return 0; 14452 } else { 14453 return 0; 14454 } 14455 case 6: return 0; 14456 case 5: return 24; 14457 case 4: 14458 if (devinfo->is_g4x) { 14459 return 24; 14460 } else { 14461 return 24; 14462 } 14463 default: 14464 unreachable("Invalid hardware generation"); 14465 } 14466 } 14467 14468 14469 14470 /* 3DSTATE_CONSTANT_COLOR::3D Command Sub Opcode */ 14471 14472 14473 #define GEN5_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits 8 14474 #define GEN45_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits 8 14475 #define GEN4_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits 8 14476 14477 static inline uint32_t ATTRIBUTE_PURE 14478 _3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 14479 { 14480 switch (devinfo->gen) { 14481 case 10: return 0; 14482 case 9: return 0; 14483 case 8: return 0; 14484 case 7: 14485 if (devinfo->is_haswell) { 14486 return 0; 14487 } else { 14488 return 0; 14489 } 14490 case 6: return 0; 14491 case 5: return 8; 14492 case 4: 14493 if (devinfo->is_g4x) { 14494 return 8; 14495 } else { 14496 return 8; 14497 } 14498 default: 14499 unreachable("Invalid hardware generation"); 14500 } 14501 } 14502 14503 14504 14505 #define GEN5_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start 16 14506 #define GEN45_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start 16 14507 #define GEN4_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start 16 14508 14509 static inline uint32_t ATTRIBUTE_PURE 14510 _3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 14511 { 14512 switch (devinfo->gen) { 14513 case 10: return 0; 14514 case 9: return 0; 14515 case 8: return 0; 14516 case 7: 14517 if (devinfo->is_haswell) { 14518 return 0; 14519 } else { 14520 return 0; 14521 } 14522 case 6: return 0; 14523 case 5: return 16; 14524 case 4: 14525 if (devinfo->is_g4x) { 14526 return 16; 14527 } else { 14528 return 16; 14529 } 14530 default: 14531 unreachable("Invalid hardware generation"); 14532 } 14533 } 14534 14535 14536 14537 /* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Alpha */ 14538 14539 14540 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits 32 14541 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits 32 14542 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits 32 14543 14544 static inline uint32_t ATTRIBUTE_PURE 14545 _3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits(const struct gen_device_info *devinfo) 14546 { 14547 switch (devinfo->gen) { 14548 case 10: return 0; 14549 case 9: return 0; 14550 case 8: return 0; 14551 case 7: 14552 if (devinfo->is_haswell) { 14553 return 0; 14554 } else { 14555 return 0; 14556 } 14557 case 6: return 0; 14558 case 5: return 32; 14559 case 4: 14560 if (devinfo->is_g4x) { 14561 return 32; 14562 } else { 14563 return 32; 14564 } 14565 default: 14566 unreachable("Invalid hardware generation"); 14567 } 14568 } 14569 14570 14571 14572 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start 128 14573 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start 128 14574 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start 128 14575 14576 static inline uint32_t ATTRIBUTE_PURE 14577 _3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start(const struct gen_device_info *devinfo) 14578 { 14579 switch (devinfo->gen) { 14580 case 10: return 0; 14581 case 9: return 0; 14582 case 8: return 0; 14583 case 7: 14584 if (devinfo->is_haswell) { 14585 return 0; 14586 } else { 14587 return 0; 14588 } 14589 case 6: return 0; 14590 case 5: return 128; 14591 case 4: 14592 if (devinfo->is_g4x) { 14593 return 128; 14594 } else { 14595 return 128; 14596 } 14597 default: 14598 unreachable("Invalid hardware generation"); 14599 } 14600 } 14601 14602 14603 14604 /* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Blue */ 14605 14606 14607 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits 32 14608 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits 32 14609 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits 32 14610 14611 static inline uint32_t ATTRIBUTE_PURE 14612 _3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits(const struct gen_device_info *devinfo) 14613 { 14614 switch (devinfo->gen) { 14615 case 10: return 0; 14616 case 9: return 0; 14617 case 8: return 0; 14618 case 7: 14619 if (devinfo->is_haswell) { 14620 return 0; 14621 } else { 14622 return 0; 14623 } 14624 case 6: return 0; 14625 case 5: return 32; 14626 case 4: 14627 if (devinfo->is_g4x) { 14628 return 32; 14629 } else { 14630 return 32; 14631 } 14632 default: 14633 unreachable("Invalid hardware generation"); 14634 } 14635 } 14636 14637 14638 14639 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start 96 14640 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start 96 14641 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start 96 14642 14643 static inline uint32_t ATTRIBUTE_PURE 14644 _3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start(const struct gen_device_info *devinfo) 14645 { 14646 switch (devinfo->gen) { 14647 case 10: return 0; 14648 case 9: return 0; 14649 case 8: return 0; 14650 case 7: 14651 if (devinfo->is_haswell) { 14652 return 0; 14653 } else { 14654 return 0; 14655 } 14656 case 6: return 0; 14657 case 5: return 96; 14658 case 4: 14659 if (devinfo->is_g4x) { 14660 return 96; 14661 } else { 14662 return 96; 14663 } 14664 default: 14665 unreachable("Invalid hardware generation"); 14666 } 14667 } 14668 14669 14670 14671 /* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Green */ 14672 14673 14674 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits 32 14675 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits 32 14676 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits 32 14677 14678 static inline uint32_t ATTRIBUTE_PURE 14679 _3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits(const struct gen_device_info *devinfo) 14680 { 14681 switch (devinfo->gen) { 14682 case 10: return 0; 14683 case 9: return 0; 14684 case 8: return 0; 14685 case 7: 14686 if (devinfo->is_haswell) { 14687 return 0; 14688 } else { 14689 return 0; 14690 } 14691 case 6: return 0; 14692 case 5: return 32; 14693 case 4: 14694 if (devinfo->is_g4x) { 14695 return 32; 14696 } else { 14697 return 32; 14698 } 14699 default: 14700 unreachable("Invalid hardware generation"); 14701 } 14702 } 14703 14704 14705 14706 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start 64 14707 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start 64 14708 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start 64 14709 14710 static inline uint32_t ATTRIBUTE_PURE 14711 _3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start(const struct gen_device_info *devinfo) 14712 { 14713 switch (devinfo->gen) { 14714 case 10: return 0; 14715 case 9: return 0; 14716 case 8: return 0; 14717 case 7: 14718 if (devinfo->is_haswell) { 14719 return 0; 14720 } else { 14721 return 0; 14722 } 14723 case 6: return 0; 14724 case 5: return 64; 14725 case 4: 14726 if (devinfo->is_g4x) { 14727 return 64; 14728 } else { 14729 return 64; 14730 } 14731 default: 14732 unreachable("Invalid hardware generation"); 14733 } 14734 } 14735 14736 14737 14738 /* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Red */ 14739 14740 14741 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits 32 14742 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits 32 14743 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits 32 14744 14745 static inline uint32_t ATTRIBUTE_PURE 14746 _3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits(const struct gen_device_info *devinfo) 14747 { 14748 switch (devinfo->gen) { 14749 case 10: return 0; 14750 case 9: return 0; 14751 case 8: return 0; 14752 case 7: 14753 if (devinfo->is_haswell) { 14754 return 0; 14755 } else { 14756 return 0; 14757 } 14758 case 6: return 0; 14759 case 5: return 32; 14760 case 4: 14761 if (devinfo->is_g4x) { 14762 return 32; 14763 } else { 14764 return 32; 14765 } 14766 default: 14767 unreachable("Invalid hardware generation"); 14768 } 14769 } 14770 14771 14772 14773 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start 32 14774 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start 32 14775 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start 32 14776 14777 static inline uint32_t ATTRIBUTE_PURE 14778 _3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start(const struct gen_device_info *devinfo) 14779 { 14780 switch (devinfo->gen) { 14781 case 10: return 0; 14782 case 9: return 0; 14783 case 8: return 0; 14784 case 7: 14785 if (devinfo->is_haswell) { 14786 return 0; 14787 } else { 14788 return 0; 14789 } 14790 case 6: return 0; 14791 case 5: return 32; 14792 case 4: 14793 if (devinfo->is_g4x) { 14794 return 32; 14795 } else { 14796 return 32; 14797 } 14798 default: 14799 unreachable("Invalid hardware generation"); 14800 } 14801 } 14802 14803 14804 14805 /* 3DSTATE_CONSTANT_COLOR::Command SubType */ 14806 14807 14808 #define GEN5_3DSTATE_CONSTANT_COLOR_CommandSubType_bits 2 14809 #define GEN45_3DSTATE_CONSTANT_COLOR_CommandSubType_bits 2 14810 #define GEN4_3DSTATE_CONSTANT_COLOR_CommandSubType_bits 2 14811 14812 static inline uint32_t ATTRIBUTE_PURE 14813 _3DSTATE_CONSTANT_COLOR_CommandSubType_bits(const struct gen_device_info *devinfo) 14814 { 14815 switch (devinfo->gen) { 14816 case 10: return 0; 14817 case 9: return 0; 14818 case 8: return 0; 14819 case 7: 14820 if (devinfo->is_haswell) { 14821 return 0; 14822 } else { 14823 return 0; 14824 } 14825 case 6: return 0; 14826 case 5: return 2; 14827 case 4: 14828 if (devinfo->is_g4x) { 14829 return 2; 14830 } else { 14831 return 2; 14832 } 14833 default: 14834 unreachable("Invalid hardware generation"); 14835 } 14836 } 14837 14838 14839 14840 #define GEN5_3DSTATE_CONSTANT_COLOR_CommandSubType_start 27 14841 #define GEN45_3DSTATE_CONSTANT_COLOR_CommandSubType_start 27 14842 #define GEN4_3DSTATE_CONSTANT_COLOR_CommandSubType_start 27 14843 14844 static inline uint32_t ATTRIBUTE_PURE 14845 _3DSTATE_CONSTANT_COLOR_CommandSubType_start(const struct gen_device_info *devinfo) 14846 { 14847 switch (devinfo->gen) { 14848 case 10: return 0; 14849 case 9: return 0; 14850 case 8: return 0; 14851 case 7: 14852 if (devinfo->is_haswell) { 14853 return 0; 14854 } else { 14855 return 0; 14856 } 14857 case 6: return 0; 14858 case 5: return 27; 14859 case 4: 14860 if (devinfo->is_g4x) { 14861 return 27; 14862 } else { 14863 return 27; 14864 } 14865 default: 14866 unreachable("Invalid hardware generation"); 14867 } 14868 } 14869 14870 14871 14872 /* 3DSTATE_CONSTANT_COLOR::Command Type */ 14873 14874 14875 #define GEN5_3DSTATE_CONSTANT_COLOR_CommandType_bits 3 14876 #define GEN45_3DSTATE_CONSTANT_COLOR_CommandType_bits 3 14877 #define GEN4_3DSTATE_CONSTANT_COLOR_CommandType_bits 3 14878 14879 static inline uint32_t ATTRIBUTE_PURE 14880 _3DSTATE_CONSTANT_COLOR_CommandType_bits(const struct gen_device_info *devinfo) 14881 { 14882 switch (devinfo->gen) { 14883 case 10: return 0; 14884 case 9: return 0; 14885 case 8: return 0; 14886 case 7: 14887 if (devinfo->is_haswell) { 14888 return 0; 14889 } else { 14890 return 0; 14891 } 14892 case 6: return 0; 14893 case 5: return 3; 14894 case 4: 14895 if (devinfo->is_g4x) { 14896 return 3; 14897 } else { 14898 return 3; 14899 } 14900 default: 14901 unreachable("Invalid hardware generation"); 14902 } 14903 } 14904 14905 14906 14907 #define GEN5_3DSTATE_CONSTANT_COLOR_CommandType_start 29 14908 #define GEN45_3DSTATE_CONSTANT_COLOR_CommandType_start 29 14909 #define GEN4_3DSTATE_CONSTANT_COLOR_CommandType_start 29 14910 14911 static inline uint32_t ATTRIBUTE_PURE 14912 _3DSTATE_CONSTANT_COLOR_CommandType_start(const struct gen_device_info *devinfo) 14913 { 14914 switch (devinfo->gen) { 14915 case 10: return 0; 14916 case 9: return 0; 14917 case 8: return 0; 14918 case 7: 14919 if (devinfo->is_haswell) { 14920 return 0; 14921 } else { 14922 return 0; 14923 } 14924 case 6: return 0; 14925 case 5: return 29; 14926 case 4: 14927 if (devinfo->is_g4x) { 14928 return 29; 14929 } else { 14930 return 29; 14931 } 14932 default: 14933 unreachable("Invalid hardware generation"); 14934 } 14935 } 14936 14937 14938 14939 /* 3DSTATE_CONSTANT_COLOR::DWord Length */ 14940 14941 14942 #define GEN5_3DSTATE_CONSTANT_COLOR_DWordLength_bits 8 14943 #define GEN45_3DSTATE_CONSTANT_COLOR_DWordLength_bits 8 14944 #define GEN4_3DSTATE_CONSTANT_COLOR_DWordLength_bits 8 14945 14946 static inline uint32_t ATTRIBUTE_PURE 14947 _3DSTATE_CONSTANT_COLOR_DWordLength_bits(const struct gen_device_info *devinfo) 14948 { 14949 switch (devinfo->gen) { 14950 case 10: return 0; 14951 case 9: return 0; 14952 case 8: return 0; 14953 case 7: 14954 if (devinfo->is_haswell) { 14955 return 0; 14956 } else { 14957 return 0; 14958 } 14959 case 6: return 0; 14960 case 5: return 8; 14961 case 4: 14962 if (devinfo->is_g4x) { 14963 return 8; 14964 } else { 14965 return 8; 14966 } 14967 default: 14968 unreachable("Invalid hardware generation"); 14969 } 14970 } 14971 14972 14973 14974 #define GEN5_3DSTATE_CONSTANT_COLOR_DWordLength_start 0 14975 #define GEN45_3DSTATE_CONSTANT_COLOR_DWordLength_start 0 14976 #define GEN4_3DSTATE_CONSTANT_COLOR_DWordLength_start 0 14977 14978 static inline uint32_t ATTRIBUTE_PURE 14979 _3DSTATE_CONSTANT_COLOR_DWordLength_start(const struct gen_device_info *devinfo) 14980 { 14981 switch (devinfo->gen) { 14982 case 10: return 0; 14983 case 9: return 0; 14984 case 8: return 0; 14985 case 7: 14986 if (devinfo->is_haswell) { 14987 return 0; 14988 } else { 14989 return 0; 14990 } 14991 case 6: return 0; 14992 case 5: return 0; 14993 case 4: 14994 if (devinfo->is_g4x) { 14995 return 0; 14996 } else { 14997 return 0; 14998 } 14999 default: 15000 unreachable("Invalid hardware generation"); 15001 } 15002 } 15003 15004 15005 15006 /* 3DSTATE_CONSTANT_DS */ 15007 15008 15009 #define GEN10_3DSTATE_CONSTANT_DS_length 11 15010 #define GEN9_3DSTATE_CONSTANT_DS_length 11 15011 #define GEN8_3DSTATE_CONSTANT_DS_length 11 15012 #define GEN75_3DSTATE_CONSTANT_DS_length 7 15013 #define GEN7_3DSTATE_CONSTANT_DS_length 7 15014 15015 static inline uint32_t ATTRIBUTE_PURE 15016 _3DSTATE_CONSTANT_DS_length(const struct gen_device_info *devinfo) 15017 { 15018 switch (devinfo->gen) { 15019 case 10: return 11; 15020 case 9: return 11; 15021 case 8: return 11; 15022 case 7: 15023 if (devinfo->is_haswell) { 15024 return 7; 15025 } else { 15026 return 7; 15027 } 15028 case 6: return 0; 15029 case 5: return 0; 15030 case 4: 15031 if (devinfo->is_g4x) { 15032 return 0; 15033 } else { 15034 return 0; 15035 } 15036 default: 15037 unreachable("Invalid hardware generation"); 15038 } 15039 } 15040 15041 15042 15043 /* 3DSTATE_CONSTANT_DS::3D Command Opcode */ 15044 15045 15046 #define GEN10_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 15047 #define GEN9_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 15048 #define GEN8_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 15049 #define GEN75_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 15050 #define GEN7_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 15051 15052 static inline uint32_t ATTRIBUTE_PURE 15053 _3DSTATE_CONSTANT_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 15054 { 15055 switch (devinfo->gen) { 15056 case 10: return 3; 15057 case 9: return 3; 15058 case 8: return 3; 15059 case 7: 15060 if (devinfo->is_haswell) { 15061 return 3; 15062 } else { 15063 return 3; 15064 } 15065 case 6: return 0; 15066 case 5: return 0; 15067 case 4: 15068 if (devinfo->is_g4x) { 15069 return 0; 15070 } else { 15071 return 0; 15072 } 15073 default: 15074 unreachable("Invalid hardware generation"); 15075 } 15076 } 15077 15078 15079 15080 #define GEN10_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 15081 #define GEN9_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 15082 #define GEN8_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 15083 #define GEN75_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 15084 #define GEN7_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 15085 15086 static inline uint32_t ATTRIBUTE_PURE 15087 _3DSTATE_CONSTANT_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 15088 { 15089 switch (devinfo->gen) { 15090 case 10: return 24; 15091 case 9: return 24; 15092 case 8: return 24; 15093 case 7: 15094 if (devinfo->is_haswell) { 15095 return 24; 15096 } else { 15097 return 24; 15098 } 15099 case 6: return 0; 15100 case 5: return 0; 15101 case 4: 15102 if (devinfo->is_g4x) { 15103 return 0; 15104 } else { 15105 return 0; 15106 } 15107 default: 15108 unreachable("Invalid hardware generation"); 15109 } 15110 } 15111 15112 15113 15114 /* 3DSTATE_CONSTANT_DS::3D Command Sub Opcode */ 15115 15116 15117 #define GEN10_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 15118 #define GEN9_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 15119 #define GEN8_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 15120 #define GEN75_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 15121 #define GEN7_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 15122 15123 static inline uint32_t ATTRIBUTE_PURE 15124 _3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 15125 { 15126 switch (devinfo->gen) { 15127 case 10: return 8; 15128 case 9: return 8; 15129 case 8: return 8; 15130 case 7: 15131 if (devinfo->is_haswell) { 15132 return 8; 15133 } else { 15134 return 8; 15135 } 15136 case 6: return 0; 15137 case 5: return 0; 15138 case 4: 15139 if (devinfo->is_g4x) { 15140 return 0; 15141 } else { 15142 return 0; 15143 } 15144 default: 15145 unreachable("Invalid hardware generation"); 15146 } 15147 } 15148 15149 15150 15151 #define GEN10_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 15152 #define GEN9_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 15153 #define GEN8_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 15154 #define GEN75_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 15155 #define GEN7_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 15156 15157 static inline uint32_t ATTRIBUTE_PURE 15158 _3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 15159 { 15160 switch (devinfo->gen) { 15161 case 10: return 16; 15162 case 9: return 16; 15163 case 8: return 16; 15164 case 7: 15165 if (devinfo->is_haswell) { 15166 return 16; 15167 } else { 15168 return 16; 15169 } 15170 case 6: return 0; 15171 case 5: return 0; 15172 case 4: 15173 if (devinfo->is_g4x) { 15174 return 0; 15175 } else { 15176 return 0; 15177 } 15178 default: 15179 unreachable("Invalid hardware generation"); 15180 } 15181 } 15182 15183 15184 15185 /* 3DSTATE_CONSTANT_DS::Command SubType */ 15186 15187 15188 #define GEN10_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 15189 #define GEN9_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 15190 #define GEN8_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 15191 #define GEN75_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 15192 #define GEN7_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 15193 15194 static inline uint32_t ATTRIBUTE_PURE 15195 _3DSTATE_CONSTANT_DS_CommandSubType_bits(const struct gen_device_info *devinfo) 15196 { 15197 switch (devinfo->gen) { 15198 case 10: return 2; 15199 case 9: return 2; 15200 case 8: return 2; 15201 case 7: 15202 if (devinfo->is_haswell) { 15203 return 2; 15204 } else { 15205 return 2; 15206 } 15207 case 6: return 0; 15208 case 5: return 0; 15209 case 4: 15210 if (devinfo->is_g4x) { 15211 return 0; 15212 } else { 15213 return 0; 15214 } 15215 default: 15216 unreachable("Invalid hardware generation"); 15217 } 15218 } 15219 15220 15221 15222 #define GEN10_3DSTATE_CONSTANT_DS_CommandSubType_start 27 15223 #define GEN9_3DSTATE_CONSTANT_DS_CommandSubType_start 27 15224 #define GEN8_3DSTATE_CONSTANT_DS_CommandSubType_start 27 15225 #define GEN75_3DSTATE_CONSTANT_DS_CommandSubType_start 27 15226 #define GEN7_3DSTATE_CONSTANT_DS_CommandSubType_start 27 15227 15228 static inline uint32_t ATTRIBUTE_PURE 15229 _3DSTATE_CONSTANT_DS_CommandSubType_start(const struct gen_device_info *devinfo) 15230 { 15231 switch (devinfo->gen) { 15232 case 10: return 27; 15233 case 9: return 27; 15234 case 8: return 27; 15235 case 7: 15236 if (devinfo->is_haswell) { 15237 return 27; 15238 } else { 15239 return 27; 15240 } 15241 case 6: return 0; 15242 case 5: return 0; 15243 case 4: 15244 if (devinfo->is_g4x) { 15245 return 0; 15246 } else { 15247 return 0; 15248 } 15249 default: 15250 unreachable("Invalid hardware generation"); 15251 } 15252 } 15253 15254 15255 15256 /* 3DSTATE_CONSTANT_DS::Command Type */ 15257 15258 15259 #define GEN10_3DSTATE_CONSTANT_DS_CommandType_bits 3 15260 #define GEN9_3DSTATE_CONSTANT_DS_CommandType_bits 3 15261 #define GEN8_3DSTATE_CONSTANT_DS_CommandType_bits 3 15262 #define GEN75_3DSTATE_CONSTANT_DS_CommandType_bits 3 15263 #define GEN7_3DSTATE_CONSTANT_DS_CommandType_bits 3 15264 15265 static inline uint32_t ATTRIBUTE_PURE 15266 _3DSTATE_CONSTANT_DS_CommandType_bits(const struct gen_device_info *devinfo) 15267 { 15268 switch (devinfo->gen) { 15269 case 10: return 3; 15270 case 9: return 3; 15271 case 8: return 3; 15272 case 7: 15273 if (devinfo->is_haswell) { 15274 return 3; 15275 } else { 15276 return 3; 15277 } 15278 case 6: return 0; 15279 case 5: return 0; 15280 case 4: 15281 if (devinfo->is_g4x) { 15282 return 0; 15283 } else { 15284 return 0; 15285 } 15286 default: 15287 unreachable("Invalid hardware generation"); 15288 } 15289 } 15290 15291 15292 15293 #define GEN10_3DSTATE_CONSTANT_DS_CommandType_start 29 15294 #define GEN9_3DSTATE_CONSTANT_DS_CommandType_start 29 15295 #define GEN8_3DSTATE_CONSTANT_DS_CommandType_start 29 15296 #define GEN75_3DSTATE_CONSTANT_DS_CommandType_start 29 15297 #define GEN7_3DSTATE_CONSTANT_DS_CommandType_start 29 15298 15299 static inline uint32_t ATTRIBUTE_PURE 15300 _3DSTATE_CONSTANT_DS_CommandType_start(const struct gen_device_info *devinfo) 15301 { 15302 switch (devinfo->gen) { 15303 case 10: return 29; 15304 case 9: return 29; 15305 case 8: return 29; 15306 case 7: 15307 if (devinfo->is_haswell) { 15308 return 29; 15309 } else { 15310 return 29; 15311 } 15312 case 6: return 0; 15313 case 5: return 0; 15314 case 4: 15315 if (devinfo->is_g4x) { 15316 return 0; 15317 } else { 15318 return 0; 15319 } 15320 default: 15321 unreachable("Invalid hardware generation"); 15322 } 15323 } 15324 15325 15326 15327 /* 3DSTATE_CONSTANT_DS::Constant Body */ 15328 15329 15330 #define GEN10_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 15331 #define GEN9_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 15332 #define GEN8_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 15333 #define GEN75_3DSTATE_CONSTANT_DS_ConstantBody_bits 192 15334 #define GEN7_3DSTATE_CONSTANT_DS_ConstantBody_bits 192 15335 15336 static inline uint32_t ATTRIBUTE_PURE 15337 _3DSTATE_CONSTANT_DS_ConstantBody_bits(const struct gen_device_info *devinfo) 15338 { 15339 switch (devinfo->gen) { 15340 case 10: return 320; 15341 case 9: return 320; 15342 case 8: return 320; 15343 case 7: 15344 if (devinfo->is_haswell) { 15345 return 192; 15346 } else { 15347 return 192; 15348 } 15349 case 6: return 0; 15350 case 5: return 0; 15351 case 4: 15352 if (devinfo->is_g4x) { 15353 return 0; 15354 } else { 15355 return 0; 15356 } 15357 default: 15358 unreachable("Invalid hardware generation"); 15359 } 15360 } 15361 15362 15363 15364 #define GEN10_3DSTATE_CONSTANT_DS_ConstantBody_start 32 15365 #define GEN9_3DSTATE_CONSTANT_DS_ConstantBody_start 32 15366 #define GEN8_3DSTATE_CONSTANT_DS_ConstantBody_start 32 15367 #define GEN75_3DSTATE_CONSTANT_DS_ConstantBody_start 32 15368 #define GEN7_3DSTATE_CONSTANT_DS_ConstantBody_start 32 15369 15370 static inline uint32_t ATTRIBUTE_PURE 15371 _3DSTATE_CONSTANT_DS_ConstantBody_start(const struct gen_device_info *devinfo) 15372 { 15373 switch (devinfo->gen) { 15374 case 10: return 32; 15375 case 9: return 32; 15376 case 8: return 32; 15377 case 7: 15378 if (devinfo->is_haswell) { 15379 return 32; 15380 } else { 15381 return 32; 15382 } 15383 case 6: return 0; 15384 case 5: return 0; 15385 case 4: 15386 if (devinfo->is_g4x) { 15387 return 0; 15388 } else { 15389 return 0; 15390 } 15391 default: 15392 unreachable("Invalid hardware generation"); 15393 } 15394 } 15395 15396 15397 15398 /* 3DSTATE_CONSTANT_DS::Constant Buffer Object Control State */ 15399 15400 15401 #define GEN10_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits 7 15402 #define GEN9_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits 7 15403 #define GEN8_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits 7 15404 15405 static inline uint32_t ATTRIBUTE_PURE 15406 _3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) 15407 { 15408 switch (devinfo->gen) { 15409 case 10: return 7; 15410 case 9: return 7; 15411 case 8: return 7; 15412 case 7: 15413 if (devinfo->is_haswell) { 15414 return 0; 15415 } else { 15416 return 0; 15417 } 15418 case 6: return 0; 15419 case 5: return 0; 15420 case 4: 15421 if (devinfo->is_g4x) { 15422 return 0; 15423 } else { 15424 return 0; 15425 } 15426 default: 15427 unreachable("Invalid hardware generation"); 15428 } 15429 } 15430 15431 15432 15433 #define GEN10_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start 8 15434 #define GEN9_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start 8 15435 #define GEN8_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start 8 15436 15437 static inline uint32_t ATTRIBUTE_PURE 15438 _3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) 15439 { 15440 switch (devinfo->gen) { 15441 case 10: return 8; 15442 case 9: return 8; 15443 case 8: return 8; 15444 case 7: 15445 if (devinfo->is_haswell) { 15446 return 0; 15447 } else { 15448 return 0; 15449 } 15450 case 6: return 0; 15451 case 5: return 0; 15452 case 4: 15453 if (devinfo->is_g4x) { 15454 return 0; 15455 } else { 15456 return 0; 15457 } 15458 default: 15459 unreachable("Invalid hardware generation"); 15460 } 15461 } 15462 15463 15464 15465 /* 3DSTATE_CONSTANT_DS::DWord Length */ 15466 15467 15468 #define GEN10_3DSTATE_CONSTANT_DS_DWordLength_bits 8 15469 #define GEN9_3DSTATE_CONSTANT_DS_DWordLength_bits 8 15470 #define GEN8_3DSTATE_CONSTANT_DS_DWordLength_bits 8 15471 #define GEN75_3DSTATE_CONSTANT_DS_DWordLength_bits 8 15472 #define GEN7_3DSTATE_CONSTANT_DS_DWordLength_bits 8 15473 15474 static inline uint32_t ATTRIBUTE_PURE 15475 _3DSTATE_CONSTANT_DS_DWordLength_bits(const struct gen_device_info *devinfo) 15476 { 15477 switch (devinfo->gen) { 15478 case 10: return 8; 15479 case 9: return 8; 15480 case 8: return 8; 15481 case 7: 15482 if (devinfo->is_haswell) { 15483 return 8; 15484 } else { 15485 return 8; 15486 } 15487 case 6: return 0; 15488 case 5: return 0; 15489 case 4: 15490 if (devinfo->is_g4x) { 15491 return 0; 15492 } else { 15493 return 0; 15494 } 15495 default: 15496 unreachable("Invalid hardware generation"); 15497 } 15498 } 15499 15500 15501 15502 #define GEN10_3DSTATE_CONSTANT_DS_DWordLength_start 0 15503 #define GEN9_3DSTATE_CONSTANT_DS_DWordLength_start 0 15504 #define GEN8_3DSTATE_CONSTANT_DS_DWordLength_start 0 15505 #define GEN75_3DSTATE_CONSTANT_DS_DWordLength_start 0 15506 #define GEN7_3DSTATE_CONSTANT_DS_DWordLength_start 0 15507 15508 static inline uint32_t ATTRIBUTE_PURE 15509 _3DSTATE_CONSTANT_DS_DWordLength_start(const struct gen_device_info *devinfo) 15510 { 15511 switch (devinfo->gen) { 15512 case 10: return 0; 15513 case 9: return 0; 15514 case 8: return 0; 15515 case 7: 15516 if (devinfo->is_haswell) { 15517 return 0; 15518 } else { 15519 return 0; 15520 } 15521 case 6: return 0; 15522 case 5: return 0; 15523 case 4: 15524 if (devinfo->is_g4x) { 15525 return 0; 15526 } else { 15527 return 0; 15528 } 15529 default: 15530 unreachable("Invalid hardware generation"); 15531 } 15532 } 15533 15534 15535 15536 /* 3DSTATE_CONSTANT_GS */ 15537 15538 15539 #define GEN10_3DSTATE_CONSTANT_GS_length 11 15540 #define GEN9_3DSTATE_CONSTANT_GS_length 11 15541 #define GEN8_3DSTATE_CONSTANT_GS_length 11 15542 #define GEN75_3DSTATE_CONSTANT_GS_length 7 15543 #define GEN7_3DSTATE_CONSTANT_GS_length 7 15544 #define GEN6_3DSTATE_CONSTANT_GS_length 5 15545 15546 static inline uint32_t ATTRIBUTE_PURE 15547 _3DSTATE_CONSTANT_GS_length(const struct gen_device_info *devinfo) 15548 { 15549 switch (devinfo->gen) { 15550 case 10: return 11; 15551 case 9: return 11; 15552 case 8: return 11; 15553 case 7: 15554 if (devinfo->is_haswell) { 15555 return 7; 15556 } else { 15557 return 7; 15558 } 15559 case 6: return 5; 15560 case 5: return 0; 15561 case 4: 15562 if (devinfo->is_g4x) { 15563 return 0; 15564 } else { 15565 return 0; 15566 } 15567 default: 15568 unreachable("Invalid hardware generation"); 15569 } 15570 } 15571 15572 15573 15574 /* 3DSTATE_CONSTANT_GS::3D Command Opcode */ 15575 15576 15577 #define GEN10_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 15578 #define GEN9_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 15579 #define GEN8_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 15580 #define GEN75_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 15581 #define GEN7_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 15582 #define GEN6_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 15583 15584 static inline uint32_t ATTRIBUTE_PURE 15585 _3DSTATE_CONSTANT_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 15586 { 15587 switch (devinfo->gen) { 15588 case 10: return 3; 15589 case 9: return 3; 15590 case 8: return 3; 15591 case 7: 15592 if (devinfo->is_haswell) { 15593 return 3; 15594 } else { 15595 return 3; 15596 } 15597 case 6: return 3; 15598 case 5: return 0; 15599 case 4: 15600 if (devinfo->is_g4x) { 15601 return 0; 15602 } else { 15603 return 0; 15604 } 15605 default: 15606 unreachable("Invalid hardware generation"); 15607 } 15608 } 15609 15610 15611 15612 #define GEN10_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 15613 #define GEN9_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 15614 #define GEN8_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 15615 #define GEN75_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 15616 #define GEN7_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 15617 #define GEN6_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 15618 15619 static inline uint32_t ATTRIBUTE_PURE 15620 _3DSTATE_CONSTANT_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 15621 { 15622 switch (devinfo->gen) { 15623 case 10: return 24; 15624 case 9: return 24; 15625 case 8: return 24; 15626 case 7: 15627 if (devinfo->is_haswell) { 15628 return 24; 15629 } else { 15630 return 24; 15631 } 15632 case 6: return 24; 15633 case 5: return 0; 15634 case 4: 15635 if (devinfo->is_g4x) { 15636 return 0; 15637 } else { 15638 return 0; 15639 } 15640 default: 15641 unreachable("Invalid hardware generation"); 15642 } 15643 } 15644 15645 15646 15647 /* 3DSTATE_CONSTANT_GS::3D Command Sub Opcode */ 15648 15649 15650 #define GEN10_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 15651 #define GEN9_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 15652 #define GEN8_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 15653 #define GEN75_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 15654 #define GEN7_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 15655 #define GEN6_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 15656 15657 static inline uint32_t ATTRIBUTE_PURE 15658 _3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 15659 { 15660 switch (devinfo->gen) { 15661 case 10: return 8; 15662 case 9: return 8; 15663 case 8: return 8; 15664 case 7: 15665 if (devinfo->is_haswell) { 15666 return 8; 15667 } else { 15668 return 8; 15669 } 15670 case 6: return 8; 15671 case 5: return 0; 15672 case 4: 15673 if (devinfo->is_g4x) { 15674 return 0; 15675 } else { 15676 return 0; 15677 } 15678 default: 15679 unreachable("Invalid hardware generation"); 15680 } 15681 } 15682 15683 15684 15685 #define GEN10_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 15686 #define GEN9_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 15687 #define GEN8_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 15688 #define GEN75_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 15689 #define GEN7_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 15690 #define GEN6_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 15691 15692 static inline uint32_t ATTRIBUTE_PURE 15693 _3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 15694 { 15695 switch (devinfo->gen) { 15696 case 10: return 16; 15697 case 9: return 16; 15698 case 8: return 16; 15699 case 7: 15700 if (devinfo->is_haswell) { 15701 return 16; 15702 } else { 15703 return 16; 15704 } 15705 case 6: return 16; 15706 case 5: return 0; 15707 case 4: 15708 if (devinfo->is_g4x) { 15709 return 0; 15710 } else { 15711 return 0; 15712 } 15713 default: 15714 unreachable("Invalid hardware generation"); 15715 } 15716 } 15717 15718 15719 15720 /* 3DSTATE_CONSTANT_GS::Buffer 0 Valid */ 15721 15722 15723 #define GEN6_3DSTATE_CONSTANT_GS_Buffer0Valid_bits 1 15724 15725 static inline uint32_t ATTRIBUTE_PURE 15726 _3DSTATE_CONSTANT_GS_Buffer0Valid_bits(const struct gen_device_info *devinfo) 15727 { 15728 switch (devinfo->gen) { 15729 case 10: return 0; 15730 case 9: return 0; 15731 case 8: return 0; 15732 case 7: 15733 if (devinfo->is_haswell) { 15734 return 0; 15735 } else { 15736 return 0; 15737 } 15738 case 6: return 1; 15739 case 5: return 0; 15740 case 4: 15741 if (devinfo->is_g4x) { 15742 return 0; 15743 } else { 15744 return 0; 15745 } 15746 default: 15747 unreachable("Invalid hardware generation"); 15748 } 15749 } 15750 15751 15752 15753 #define GEN6_3DSTATE_CONSTANT_GS_Buffer0Valid_start 12 15754 15755 static inline uint32_t ATTRIBUTE_PURE 15756 _3DSTATE_CONSTANT_GS_Buffer0Valid_start(const struct gen_device_info *devinfo) 15757 { 15758 switch (devinfo->gen) { 15759 case 10: return 0; 15760 case 9: return 0; 15761 case 8: return 0; 15762 case 7: 15763 if (devinfo->is_haswell) { 15764 return 0; 15765 } else { 15766 return 0; 15767 } 15768 case 6: return 12; 15769 case 5: return 0; 15770 case 4: 15771 if (devinfo->is_g4x) { 15772 return 0; 15773 } else { 15774 return 0; 15775 } 15776 default: 15777 unreachable("Invalid hardware generation"); 15778 } 15779 } 15780 15781 15782 15783 /* 3DSTATE_CONSTANT_GS::Buffer 1 Valid */ 15784 15785 15786 #define GEN6_3DSTATE_CONSTANT_GS_Buffer1Valid_bits 1 15787 15788 static inline uint32_t ATTRIBUTE_PURE 15789 _3DSTATE_CONSTANT_GS_Buffer1Valid_bits(const struct gen_device_info *devinfo) 15790 { 15791 switch (devinfo->gen) { 15792 case 10: return 0; 15793 case 9: return 0; 15794 case 8: return 0; 15795 case 7: 15796 if (devinfo->is_haswell) { 15797 return 0; 15798 } else { 15799 return 0; 15800 } 15801 case 6: return 1; 15802 case 5: return 0; 15803 case 4: 15804 if (devinfo->is_g4x) { 15805 return 0; 15806 } else { 15807 return 0; 15808 } 15809 default: 15810 unreachable("Invalid hardware generation"); 15811 } 15812 } 15813 15814 15815 15816 #define GEN6_3DSTATE_CONSTANT_GS_Buffer1Valid_start 13 15817 15818 static inline uint32_t ATTRIBUTE_PURE 15819 _3DSTATE_CONSTANT_GS_Buffer1Valid_start(const struct gen_device_info *devinfo) 15820 { 15821 switch (devinfo->gen) { 15822 case 10: return 0; 15823 case 9: return 0; 15824 case 8: return 0; 15825 case 7: 15826 if (devinfo->is_haswell) { 15827 return 0; 15828 } else { 15829 return 0; 15830 } 15831 case 6: return 13; 15832 case 5: return 0; 15833 case 4: 15834 if (devinfo->is_g4x) { 15835 return 0; 15836 } else { 15837 return 0; 15838 } 15839 default: 15840 unreachable("Invalid hardware generation"); 15841 } 15842 } 15843 15844 15845 15846 /* 3DSTATE_CONSTANT_GS::Buffer 2 Valid */ 15847 15848 15849 #define GEN6_3DSTATE_CONSTANT_GS_Buffer2Valid_bits 1 15850 15851 static inline uint32_t ATTRIBUTE_PURE 15852 _3DSTATE_CONSTANT_GS_Buffer2Valid_bits(const struct gen_device_info *devinfo) 15853 { 15854 switch (devinfo->gen) { 15855 case 10: return 0; 15856 case 9: return 0; 15857 case 8: return 0; 15858 case 7: 15859 if (devinfo->is_haswell) { 15860 return 0; 15861 } else { 15862 return 0; 15863 } 15864 case 6: return 1; 15865 case 5: return 0; 15866 case 4: 15867 if (devinfo->is_g4x) { 15868 return 0; 15869 } else { 15870 return 0; 15871 } 15872 default: 15873 unreachable("Invalid hardware generation"); 15874 } 15875 } 15876 15877 15878 15879 #define GEN6_3DSTATE_CONSTANT_GS_Buffer2Valid_start 14 15880 15881 static inline uint32_t ATTRIBUTE_PURE 15882 _3DSTATE_CONSTANT_GS_Buffer2Valid_start(const struct gen_device_info *devinfo) 15883 { 15884 switch (devinfo->gen) { 15885 case 10: return 0; 15886 case 9: return 0; 15887 case 8: return 0; 15888 case 7: 15889 if (devinfo->is_haswell) { 15890 return 0; 15891 } else { 15892 return 0; 15893 } 15894 case 6: return 14; 15895 case 5: return 0; 15896 case 4: 15897 if (devinfo->is_g4x) { 15898 return 0; 15899 } else { 15900 return 0; 15901 } 15902 default: 15903 unreachable("Invalid hardware generation"); 15904 } 15905 } 15906 15907 15908 15909 /* 3DSTATE_CONSTANT_GS::Buffer 3 Valid */ 15910 15911 15912 #define GEN6_3DSTATE_CONSTANT_GS_Buffer3Valid_bits 1 15913 15914 static inline uint32_t ATTRIBUTE_PURE 15915 _3DSTATE_CONSTANT_GS_Buffer3Valid_bits(const struct gen_device_info *devinfo) 15916 { 15917 switch (devinfo->gen) { 15918 case 10: return 0; 15919 case 9: return 0; 15920 case 8: return 0; 15921 case 7: 15922 if (devinfo->is_haswell) { 15923 return 0; 15924 } else { 15925 return 0; 15926 } 15927 case 6: return 1; 15928 case 5: return 0; 15929 case 4: 15930 if (devinfo->is_g4x) { 15931 return 0; 15932 } else { 15933 return 0; 15934 } 15935 default: 15936 unreachable("Invalid hardware generation"); 15937 } 15938 } 15939 15940 15941 15942 #define GEN6_3DSTATE_CONSTANT_GS_Buffer3Valid_start 15 15943 15944 static inline uint32_t ATTRIBUTE_PURE 15945 _3DSTATE_CONSTANT_GS_Buffer3Valid_start(const struct gen_device_info *devinfo) 15946 { 15947 switch (devinfo->gen) { 15948 case 10: return 0; 15949 case 9: return 0; 15950 case 8: return 0; 15951 case 7: 15952 if (devinfo->is_haswell) { 15953 return 0; 15954 } else { 15955 return 0; 15956 } 15957 case 6: return 15; 15958 case 5: return 0; 15959 case 4: 15960 if (devinfo->is_g4x) { 15961 return 0; 15962 } else { 15963 return 0; 15964 } 15965 default: 15966 unreachable("Invalid hardware generation"); 15967 } 15968 } 15969 15970 15971 15972 /* 3DSTATE_CONSTANT_GS::Command SubType */ 15973 15974 15975 #define GEN10_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 15976 #define GEN9_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 15977 #define GEN8_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 15978 #define GEN75_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 15979 #define GEN7_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 15980 #define GEN6_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 15981 15982 static inline uint32_t ATTRIBUTE_PURE 15983 _3DSTATE_CONSTANT_GS_CommandSubType_bits(const struct gen_device_info *devinfo) 15984 { 15985 switch (devinfo->gen) { 15986 case 10: return 2; 15987 case 9: return 2; 15988 case 8: return 2; 15989 case 7: 15990 if (devinfo->is_haswell) { 15991 return 2; 15992 } else { 15993 return 2; 15994 } 15995 case 6: return 2; 15996 case 5: return 0; 15997 case 4: 15998 if (devinfo->is_g4x) { 15999 return 0; 16000 } else { 16001 return 0; 16002 } 16003 default: 16004 unreachable("Invalid hardware generation"); 16005 } 16006 } 16007 16008 16009 16010 #define GEN10_3DSTATE_CONSTANT_GS_CommandSubType_start 27 16011 #define GEN9_3DSTATE_CONSTANT_GS_CommandSubType_start 27 16012 #define GEN8_3DSTATE_CONSTANT_GS_CommandSubType_start 27 16013 #define GEN75_3DSTATE_CONSTANT_GS_CommandSubType_start 27 16014 #define GEN7_3DSTATE_CONSTANT_GS_CommandSubType_start 27 16015 #define GEN6_3DSTATE_CONSTANT_GS_CommandSubType_start 27 16016 16017 static inline uint32_t ATTRIBUTE_PURE 16018 _3DSTATE_CONSTANT_GS_CommandSubType_start(const struct gen_device_info *devinfo) 16019 { 16020 switch (devinfo->gen) { 16021 case 10: return 27; 16022 case 9: return 27; 16023 case 8: return 27; 16024 case 7: 16025 if (devinfo->is_haswell) { 16026 return 27; 16027 } else { 16028 return 27; 16029 } 16030 case 6: return 27; 16031 case 5: return 0; 16032 case 4: 16033 if (devinfo->is_g4x) { 16034 return 0; 16035 } else { 16036 return 0; 16037 } 16038 default: 16039 unreachable("Invalid hardware generation"); 16040 } 16041 } 16042 16043 16044 16045 /* 3DSTATE_CONSTANT_GS::Command Type */ 16046 16047 16048 #define GEN10_3DSTATE_CONSTANT_GS_CommandType_bits 3 16049 #define GEN9_3DSTATE_CONSTANT_GS_CommandType_bits 3 16050 #define GEN8_3DSTATE_CONSTANT_GS_CommandType_bits 3 16051 #define GEN75_3DSTATE_CONSTANT_GS_CommandType_bits 3 16052 #define GEN7_3DSTATE_CONSTANT_GS_CommandType_bits 3 16053 #define GEN6_3DSTATE_CONSTANT_GS_CommandType_bits 3 16054 16055 static inline uint32_t ATTRIBUTE_PURE 16056 _3DSTATE_CONSTANT_GS_CommandType_bits(const struct gen_device_info *devinfo) 16057 { 16058 switch (devinfo->gen) { 16059 case 10: return 3; 16060 case 9: return 3; 16061 case 8: return 3; 16062 case 7: 16063 if (devinfo->is_haswell) { 16064 return 3; 16065 } else { 16066 return 3; 16067 } 16068 case 6: return 3; 16069 case 5: return 0; 16070 case 4: 16071 if (devinfo->is_g4x) { 16072 return 0; 16073 } else { 16074 return 0; 16075 } 16076 default: 16077 unreachable("Invalid hardware generation"); 16078 } 16079 } 16080 16081 16082 16083 #define GEN10_3DSTATE_CONSTANT_GS_CommandType_start 29 16084 #define GEN9_3DSTATE_CONSTANT_GS_CommandType_start 29 16085 #define GEN8_3DSTATE_CONSTANT_GS_CommandType_start 29 16086 #define GEN75_3DSTATE_CONSTANT_GS_CommandType_start 29 16087 #define GEN7_3DSTATE_CONSTANT_GS_CommandType_start 29 16088 #define GEN6_3DSTATE_CONSTANT_GS_CommandType_start 29 16089 16090 static inline uint32_t ATTRIBUTE_PURE 16091 _3DSTATE_CONSTANT_GS_CommandType_start(const struct gen_device_info *devinfo) 16092 { 16093 switch (devinfo->gen) { 16094 case 10: return 29; 16095 case 9: return 29; 16096 case 8: return 29; 16097 case 7: 16098 if (devinfo->is_haswell) { 16099 return 29; 16100 } else { 16101 return 29; 16102 } 16103 case 6: return 29; 16104 case 5: return 0; 16105 case 4: 16106 if (devinfo->is_g4x) { 16107 return 0; 16108 } else { 16109 return 0; 16110 } 16111 default: 16112 unreachable("Invalid hardware generation"); 16113 } 16114 } 16115 16116 16117 16118 /* 3DSTATE_CONSTANT_GS::Constant Body */ 16119 16120 16121 #define GEN10_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 16122 #define GEN9_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 16123 #define GEN8_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 16124 #define GEN75_3DSTATE_CONSTANT_GS_ConstantBody_bits 192 16125 #define GEN7_3DSTATE_CONSTANT_GS_ConstantBody_bits 192 16126 16127 static inline uint32_t ATTRIBUTE_PURE 16128 _3DSTATE_CONSTANT_GS_ConstantBody_bits(const struct gen_device_info *devinfo) 16129 { 16130 switch (devinfo->gen) { 16131 case 10: return 320; 16132 case 9: return 320; 16133 case 8: return 320; 16134 case 7: 16135 if (devinfo->is_haswell) { 16136 return 192; 16137 } else { 16138 return 192; 16139 } 16140 case 6: return 0; 16141 case 5: return 0; 16142 case 4: 16143 if (devinfo->is_g4x) { 16144 return 0; 16145 } else { 16146 return 0; 16147 } 16148 default: 16149 unreachable("Invalid hardware generation"); 16150 } 16151 } 16152 16153 16154 16155 #define GEN10_3DSTATE_CONSTANT_GS_ConstantBody_start 32 16156 #define GEN9_3DSTATE_CONSTANT_GS_ConstantBody_start 32 16157 #define GEN8_3DSTATE_CONSTANT_GS_ConstantBody_start 32 16158 #define GEN75_3DSTATE_CONSTANT_GS_ConstantBody_start 32 16159 #define GEN7_3DSTATE_CONSTANT_GS_ConstantBody_start 32 16160 16161 static inline uint32_t ATTRIBUTE_PURE 16162 _3DSTATE_CONSTANT_GS_ConstantBody_start(const struct gen_device_info *devinfo) 16163 { 16164 switch (devinfo->gen) { 16165 case 10: return 32; 16166 case 9: return 32; 16167 case 8: return 32; 16168 case 7: 16169 if (devinfo->is_haswell) { 16170 return 32; 16171 } else { 16172 return 32; 16173 } 16174 case 6: return 0; 16175 case 5: return 0; 16176 case 4: 16177 if (devinfo->is_g4x) { 16178 return 0; 16179 } else { 16180 return 0; 16181 } 16182 default: 16183 unreachable("Invalid hardware generation"); 16184 } 16185 } 16186 16187 16188 16189 /* 3DSTATE_CONSTANT_GS::Constant Buffer Object Control State */ 16190 16191 16192 #define GEN10_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 7 16193 #define GEN9_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 7 16194 #define GEN8_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 7 16195 #define GEN6_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 4 16196 16197 static inline uint32_t ATTRIBUTE_PURE 16198 _3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) 16199 { 16200 switch (devinfo->gen) { 16201 case 10: return 7; 16202 case 9: return 7; 16203 case 8: return 7; 16204 case 7: 16205 if (devinfo->is_haswell) { 16206 return 0; 16207 } else { 16208 return 0; 16209 } 16210 case 6: return 4; 16211 case 5: return 0; 16212 case 4: 16213 if (devinfo->is_g4x) { 16214 return 0; 16215 } else { 16216 return 0; 16217 } 16218 default: 16219 unreachable("Invalid hardware generation"); 16220 } 16221 } 16222 16223 16224 16225 #define GEN10_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 16226 #define GEN9_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 16227 #define GEN8_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 16228 #define GEN6_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 16229 16230 static inline uint32_t ATTRIBUTE_PURE 16231 _3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) 16232 { 16233 switch (devinfo->gen) { 16234 case 10: return 8; 16235 case 9: return 8; 16236 case 8: return 8; 16237 case 7: 16238 if (devinfo->is_haswell) { 16239 return 0; 16240 } else { 16241 return 0; 16242 } 16243 case 6: return 8; 16244 case 5: return 0; 16245 case 4: 16246 if (devinfo->is_g4x) { 16247 return 0; 16248 } else { 16249 return 0; 16250 } 16251 default: 16252 unreachable("Invalid hardware generation"); 16253 } 16254 } 16255 16256 16257 16258 /* 3DSTATE_CONSTANT_GS::DWord Length */ 16259 16260 16261 #define GEN10_3DSTATE_CONSTANT_GS_DWordLength_bits 8 16262 #define GEN9_3DSTATE_CONSTANT_GS_DWordLength_bits 8 16263 #define GEN8_3DSTATE_CONSTANT_GS_DWordLength_bits 8 16264 #define GEN75_3DSTATE_CONSTANT_GS_DWordLength_bits 8 16265 #define GEN7_3DSTATE_CONSTANT_GS_DWordLength_bits 8 16266 #define GEN6_3DSTATE_CONSTANT_GS_DWordLength_bits 8 16267 16268 static inline uint32_t ATTRIBUTE_PURE 16269 _3DSTATE_CONSTANT_GS_DWordLength_bits(const struct gen_device_info *devinfo) 16270 { 16271 switch (devinfo->gen) { 16272 case 10: return 8; 16273 case 9: return 8; 16274 case 8: return 8; 16275 case 7: 16276 if (devinfo->is_haswell) { 16277 return 8; 16278 } else { 16279 return 8; 16280 } 16281 case 6: return 8; 16282 case 5: return 0; 16283 case 4: 16284 if (devinfo->is_g4x) { 16285 return 0; 16286 } else { 16287 return 0; 16288 } 16289 default: 16290 unreachable("Invalid hardware generation"); 16291 } 16292 } 16293 16294 16295 16296 #define GEN10_3DSTATE_CONSTANT_GS_DWordLength_start 0 16297 #define GEN9_3DSTATE_CONSTANT_GS_DWordLength_start 0 16298 #define GEN8_3DSTATE_CONSTANT_GS_DWordLength_start 0 16299 #define GEN75_3DSTATE_CONSTANT_GS_DWordLength_start 0 16300 #define GEN7_3DSTATE_CONSTANT_GS_DWordLength_start 0 16301 #define GEN6_3DSTATE_CONSTANT_GS_DWordLength_start 0 16302 16303 static inline uint32_t ATTRIBUTE_PURE 16304 _3DSTATE_CONSTANT_GS_DWordLength_start(const struct gen_device_info *devinfo) 16305 { 16306 switch (devinfo->gen) { 16307 case 10: return 0; 16308 case 9: return 0; 16309 case 8: return 0; 16310 case 7: 16311 if (devinfo->is_haswell) { 16312 return 0; 16313 } else { 16314 return 0; 16315 } 16316 case 6: return 0; 16317 case 5: return 0; 16318 case 4: 16319 if (devinfo->is_g4x) { 16320 return 0; 16321 } else { 16322 return 0; 16323 } 16324 default: 16325 unreachable("Invalid hardware generation"); 16326 } 16327 } 16328 16329 16330 16331 /* 3DSTATE_CONSTANT_GS::GS Constant Buffer 0 Read Length */ 16332 16333 16334 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer0ReadLength_bits 5 16335 16336 static inline uint32_t ATTRIBUTE_PURE 16337 _3DSTATE_CONSTANT_GS_GSConstantBuffer0ReadLength_bits(const struct gen_device_info *devinfo) 16338 { 16339 switch (devinfo->gen) { 16340 case 10: return 0; 16341 case 9: return 0; 16342 case 8: return 0; 16343 case 7: 16344 if (devinfo->is_haswell) { 16345 return 0; 16346 } else { 16347 return 0; 16348 } 16349 case 6: return 5; 16350 case 5: return 0; 16351 case 4: 16352 if (devinfo->is_g4x) { 16353 return 0; 16354 } else { 16355 return 0; 16356 } 16357 default: 16358 unreachable("Invalid hardware generation"); 16359 } 16360 } 16361 16362 16363 16364 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer0ReadLength_start 32 16365 16366 static inline uint32_t ATTRIBUTE_PURE 16367 _3DSTATE_CONSTANT_GS_GSConstantBuffer0ReadLength_start(const struct gen_device_info *devinfo) 16368 { 16369 switch (devinfo->gen) { 16370 case 10: return 0; 16371 case 9: return 0; 16372 case 8: return 0; 16373 case 7: 16374 if (devinfo->is_haswell) { 16375 return 0; 16376 } else { 16377 return 0; 16378 } 16379 case 6: return 32; 16380 case 5: return 0; 16381 case 4: 16382 if (devinfo->is_g4x) { 16383 return 0; 16384 } else { 16385 return 0; 16386 } 16387 default: 16388 unreachable("Invalid hardware generation"); 16389 } 16390 } 16391 16392 16393 16394 /* 3DSTATE_CONSTANT_GS::GS Constant Buffer 1 Read Length */ 16395 16396 16397 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer1ReadLength_bits 5 16398 16399 static inline uint32_t ATTRIBUTE_PURE 16400 _3DSTATE_CONSTANT_GS_GSConstantBuffer1ReadLength_bits(const struct gen_device_info *devinfo) 16401 { 16402 switch (devinfo->gen) { 16403 case 10: return 0; 16404 case 9: return 0; 16405 case 8: return 0; 16406 case 7: 16407 if (devinfo->is_haswell) { 16408 return 0; 16409 } else { 16410 return 0; 16411 } 16412 case 6: return 5; 16413 case 5: return 0; 16414 case 4: 16415 if (devinfo->is_g4x) { 16416 return 0; 16417 } else { 16418 return 0; 16419 } 16420 default: 16421 unreachable("Invalid hardware generation"); 16422 } 16423 } 16424 16425 16426 16427 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer1ReadLength_start 64 16428 16429 static inline uint32_t ATTRIBUTE_PURE 16430 _3DSTATE_CONSTANT_GS_GSConstantBuffer1ReadLength_start(const struct gen_device_info *devinfo) 16431 { 16432 switch (devinfo->gen) { 16433 case 10: return 0; 16434 case 9: return 0; 16435 case 8: return 0; 16436 case 7: 16437 if (devinfo->is_haswell) { 16438 return 0; 16439 } else { 16440 return 0; 16441 } 16442 case 6: return 64; 16443 case 5: return 0; 16444 case 4: 16445 if (devinfo->is_g4x) { 16446 return 0; 16447 } else { 16448 return 0; 16449 } 16450 default: 16451 unreachable("Invalid hardware generation"); 16452 } 16453 } 16454 16455 16456 16457 /* 3DSTATE_CONSTANT_GS::GS Constant Buffer 2 Read Length */ 16458 16459 16460 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer2ReadLength_bits 5 16461 16462 static inline uint32_t ATTRIBUTE_PURE 16463 _3DSTATE_CONSTANT_GS_GSConstantBuffer2ReadLength_bits(const struct gen_device_info *devinfo) 16464 { 16465 switch (devinfo->gen) { 16466 case 10: return 0; 16467 case 9: return 0; 16468 case 8: return 0; 16469 case 7: 16470 if (devinfo->is_haswell) { 16471 return 0; 16472 } else { 16473 return 0; 16474 } 16475 case 6: return 5; 16476 case 5: return 0; 16477 case 4: 16478 if (devinfo->is_g4x) { 16479 return 0; 16480 } else { 16481 return 0; 16482 } 16483 default: 16484 unreachable("Invalid hardware generation"); 16485 } 16486 } 16487 16488 16489 16490 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer2ReadLength_start 96 16491 16492 static inline uint32_t ATTRIBUTE_PURE 16493 _3DSTATE_CONSTANT_GS_GSConstantBuffer2ReadLength_start(const struct gen_device_info *devinfo) 16494 { 16495 switch (devinfo->gen) { 16496 case 10: return 0; 16497 case 9: return 0; 16498 case 8: return 0; 16499 case 7: 16500 if (devinfo->is_haswell) { 16501 return 0; 16502 } else { 16503 return 0; 16504 } 16505 case 6: return 96; 16506 case 5: return 0; 16507 case 4: 16508 if (devinfo->is_g4x) { 16509 return 0; 16510 } else { 16511 return 0; 16512 } 16513 default: 16514 unreachable("Invalid hardware generation"); 16515 } 16516 } 16517 16518 16519 16520 /* 3DSTATE_CONSTANT_GS::GS Constant Buffer 3 Read Length */ 16521 16522 16523 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer3ReadLength_bits 5 16524 16525 static inline uint32_t ATTRIBUTE_PURE 16526 _3DSTATE_CONSTANT_GS_GSConstantBuffer3ReadLength_bits(const struct gen_device_info *devinfo) 16527 { 16528 switch (devinfo->gen) { 16529 case 10: return 0; 16530 case 9: return 0; 16531 case 8: return 0; 16532 case 7: 16533 if (devinfo->is_haswell) { 16534 return 0; 16535 } else { 16536 return 0; 16537 } 16538 case 6: return 5; 16539 case 5: return 0; 16540 case 4: 16541 if (devinfo->is_g4x) { 16542 return 0; 16543 } else { 16544 return 0; 16545 } 16546 default: 16547 unreachable("Invalid hardware generation"); 16548 } 16549 } 16550 16551 16552 16553 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer3ReadLength_start 128 16554 16555 static inline uint32_t ATTRIBUTE_PURE 16556 _3DSTATE_CONSTANT_GS_GSConstantBuffer3ReadLength_start(const struct gen_device_info *devinfo) 16557 { 16558 switch (devinfo->gen) { 16559 case 10: return 0; 16560 case 9: return 0; 16561 case 8: return 0; 16562 case 7: 16563 if (devinfo->is_haswell) { 16564 return 0; 16565 } else { 16566 return 0; 16567 } 16568 case 6: return 128; 16569 case 5: return 0; 16570 case 4: 16571 if (devinfo->is_g4x) { 16572 return 0; 16573 } else { 16574 return 0; 16575 } 16576 default: 16577 unreachable("Invalid hardware generation"); 16578 } 16579 } 16580 16581 16582 16583 /* 3DSTATE_CONSTANT_GS::Pointer to GS Constant Buffer 0 */ 16584 16585 16586 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer0_bits 27 16587 16588 static inline uint32_t ATTRIBUTE_PURE 16589 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer0_bits(const struct gen_device_info *devinfo) 16590 { 16591 switch (devinfo->gen) { 16592 case 10: return 0; 16593 case 9: return 0; 16594 case 8: return 0; 16595 case 7: 16596 if (devinfo->is_haswell) { 16597 return 0; 16598 } else { 16599 return 0; 16600 } 16601 case 6: return 27; 16602 case 5: return 0; 16603 case 4: 16604 if (devinfo->is_g4x) { 16605 return 0; 16606 } else { 16607 return 0; 16608 } 16609 default: 16610 unreachable("Invalid hardware generation"); 16611 } 16612 } 16613 16614 16615 16616 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer0_start 37 16617 16618 static inline uint32_t ATTRIBUTE_PURE 16619 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer0_start(const struct gen_device_info *devinfo) 16620 { 16621 switch (devinfo->gen) { 16622 case 10: return 0; 16623 case 9: return 0; 16624 case 8: return 0; 16625 case 7: 16626 if (devinfo->is_haswell) { 16627 return 0; 16628 } else { 16629 return 0; 16630 } 16631 case 6: return 37; 16632 case 5: return 0; 16633 case 4: 16634 if (devinfo->is_g4x) { 16635 return 0; 16636 } else { 16637 return 0; 16638 } 16639 default: 16640 unreachable("Invalid hardware generation"); 16641 } 16642 } 16643 16644 16645 16646 /* 3DSTATE_CONSTANT_GS::Pointer to GS Constant Buffer 1 */ 16647 16648 16649 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer1_bits 27 16650 16651 static inline uint32_t ATTRIBUTE_PURE 16652 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer1_bits(const struct gen_device_info *devinfo) 16653 { 16654 switch (devinfo->gen) { 16655 case 10: return 0; 16656 case 9: return 0; 16657 case 8: return 0; 16658 case 7: 16659 if (devinfo->is_haswell) { 16660 return 0; 16661 } else { 16662 return 0; 16663 } 16664 case 6: return 27; 16665 case 5: return 0; 16666 case 4: 16667 if (devinfo->is_g4x) { 16668 return 0; 16669 } else { 16670 return 0; 16671 } 16672 default: 16673 unreachable("Invalid hardware generation"); 16674 } 16675 } 16676 16677 16678 16679 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer1_start 69 16680 16681 static inline uint32_t ATTRIBUTE_PURE 16682 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer1_start(const struct gen_device_info *devinfo) 16683 { 16684 switch (devinfo->gen) { 16685 case 10: return 0; 16686 case 9: return 0; 16687 case 8: return 0; 16688 case 7: 16689 if (devinfo->is_haswell) { 16690 return 0; 16691 } else { 16692 return 0; 16693 } 16694 case 6: return 69; 16695 case 5: return 0; 16696 case 4: 16697 if (devinfo->is_g4x) { 16698 return 0; 16699 } else { 16700 return 0; 16701 } 16702 default: 16703 unreachable("Invalid hardware generation"); 16704 } 16705 } 16706 16707 16708 16709 /* 3DSTATE_CONSTANT_GS::Pointer to GS Constant Buffer 2 */ 16710 16711 16712 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer2_bits 27 16713 16714 static inline uint32_t ATTRIBUTE_PURE 16715 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer2_bits(const struct gen_device_info *devinfo) 16716 { 16717 switch (devinfo->gen) { 16718 case 10: return 0; 16719 case 9: return 0; 16720 case 8: return 0; 16721 case 7: 16722 if (devinfo->is_haswell) { 16723 return 0; 16724 } else { 16725 return 0; 16726 } 16727 case 6: return 27; 16728 case 5: return 0; 16729 case 4: 16730 if (devinfo->is_g4x) { 16731 return 0; 16732 } else { 16733 return 0; 16734 } 16735 default: 16736 unreachable("Invalid hardware generation"); 16737 } 16738 } 16739 16740 16741 16742 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer2_start 101 16743 16744 static inline uint32_t ATTRIBUTE_PURE 16745 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer2_start(const struct gen_device_info *devinfo) 16746 { 16747 switch (devinfo->gen) { 16748 case 10: return 0; 16749 case 9: return 0; 16750 case 8: return 0; 16751 case 7: 16752 if (devinfo->is_haswell) { 16753 return 0; 16754 } else { 16755 return 0; 16756 } 16757 case 6: return 101; 16758 case 5: return 0; 16759 case 4: 16760 if (devinfo->is_g4x) { 16761 return 0; 16762 } else { 16763 return 0; 16764 } 16765 default: 16766 unreachable("Invalid hardware generation"); 16767 } 16768 } 16769 16770 16771 16772 /* 3DSTATE_CONSTANT_GS::Pointer to GS Constant Buffer 3 */ 16773 16774 16775 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer3_bits 27 16776 16777 static inline uint32_t ATTRIBUTE_PURE 16778 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer3_bits(const struct gen_device_info *devinfo) 16779 { 16780 switch (devinfo->gen) { 16781 case 10: return 0; 16782 case 9: return 0; 16783 case 8: return 0; 16784 case 7: 16785 if (devinfo->is_haswell) { 16786 return 0; 16787 } else { 16788 return 0; 16789 } 16790 case 6: return 27; 16791 case 5: return 0; 16792 case 4: 16793 if (devinfo->is_g4x) { 16794 return 0; 16795 } else { 16796 return 0; 16797 } 16798 default: 16799 unreachable("Invalid hardware generation"); 16800 } 16801 } 16802 16803 16804 16805 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer3_start 133 16806 16807 static inline uint32_t ATTRIBUTE_PURE 16808 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer3_start(const struct gen_device_info *devinfo) 16809 { 16810 switch (devinfo->gen) { 16811 case 10: return 0; 16812 case 9: return 0; 16813 case 8: return 0; 16814 case 7: 16815 if (devinfo->is_haswell) { 16816 return 0; 16817 } else { 16818 return 0; 16819 } 16820 case 6: return 133; 16821 case 5: return 0; 16822 case 4: 16823 if (devinfo->is_g4x) { 16824 return 0; 16825 } else { 16826 return 0; 16827 } 16828 default: 16829 unreachable("Invalid hardware generation"); 16830 } 16831 } 16832 16833 16834 16835 /* 3DSTATE_CONSTANT_HS */ 16836 16837 16838 #define GEN10_3DSTATE_CONSTANT_HS_length 11 16839 #define GEN9_3DSTATE_CONSTANT_HS_length 11 16840 #define GEN8_3DSTATE_CONSTANT_HS_length 11 16841 #define GEN75_3DSTATE_CONSTANT_HS_length 7 16842 #define GEN7_3DSTATE_CONSTANT_HS_length 7 16843 16844 static inline uint32_t ATTRIBUTE_PURE 16845 _3DSTATE_CONSTANT_HS_length(const struct gen_device_info *devinfo) 16846 { 16847 switch (devinfo->gen) { 16848 case 10: return 11; 16849 case 9: return 11; 16850 case 8: return 11; 16851 case 7: 16852 if (devinfo->is_haswell) { 16853 return 7; 16854 } else { 16855 return 7; 16856 } 16857 case 6: return 0; 16858 case 5: return 0; 16859 case 4: 16860 if (devinfo->is_g4x) { 16861 return 0; 16862 } else { 16863 return 0; 16864 } 16865 default: 16866 unreachable("Invalid hardware generation"); 16867 } 16868 } 16869 16870 16871 16872 /* 3DSTATE_CONSTANT_HS::3D Command Opcode */ 16873 16874 16875 #define GEN10_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 16876 #define GEN9_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 16877 #define GEN8_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 16878 #define GEN75_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 16879 #define GEN7_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 16880 16881 static inline uint32_t ATTRIBUTE_PURE 16882 _3DSTATE_CONSTANT_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 16883 { 16884 switch (devinfo->gen) { 16885 case 10: return 3; 16886 case 9: return 3; 16887 case 8: return 3; 16888 case 7: 16889 if (devinfo->is_haswell) { 16890 return 3; 16891 } else { 16892 return 3; 16893 } 16894 case 6: return 0; 16895 case 5: return 0; 16896 case 4: 16897 if (devinfo->is_g4x) { 16898 return 0; 16899 } else { 16900 return 0; 16901 } 16902 default: 16903 unreachable("Invalid hardware generation"); 16904 } 16905 } 16906 16907 16908 16909 #define GEN10_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 16910 #define GEN9_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 16911 #define GEN8_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 16912 #define GEN75_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 16913 #define GEN7_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 16914 16915 static inline uint32_t ATTRIBUTE_PURE 16916 _3DSTATE_CONSTANT_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 16917 { 16918 switch (devinfo->gen) { 16919 case 10: return 24; 16920 case 9: return 24; 16921 case 8: return 24; 16922 case 7: 16923 if (devinfo->is_haswell) { 16924 return 24; 16925 } else { 16926 return 24; 16927 } 16928 case 6: return 0; 16929 case 5: return 0; 16930 case 4: 16931 if (devinfo->is_g4x) { 16932 return 0; 16933 } else { 16934 return 0; 16935 } 16936 default: 16937 unreachable("Invalid hardware generation"); 16938 } 16939 } 16940 16941 16942 16943 /* 3DSTATE_CONSTANT_HS::3D Command Sub Opcode */ 16944 16945 16946 #define GEN10_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 16947 #define GEN9_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 16948 #define GEN8_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 16949 #define GEN75_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 16950 #define GEN7_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 16951 16952 static inline uint32_t ATTRIBUTE_PURE 16953 _3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 16954 { 16955 switch (devinfo->gen) { 16956 case 10: return 8; 16957 case 9: return 8; 16958 case 8: return 8; 16959 case 7: 16960 if (devinfo->is_haswell) { 16961 return 8; 16962 } else { 16963 return 8; 16964 } 16965 case 6: return 0; 16966 case 5: return 0; 16967 case 4: 16968 if (devinfo->is_g4x) { 16969 return 0; 16970 } else { 16971 return 0; 16972 } 16973 default: 16974 unreachable("Invalid hardware generation"); 16975 } 16976 } 16977 16978 16979 16980 #define GEN10_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 16981 #define GEN9_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 16982 #define GEN8_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 16983 #define GEN75_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 16984 #define GEN7_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 16985 16986 static inline uint32_t ATTRIBUTE_PURE 16987 _3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 16988 { 16989 switch (devinfo->gen) { 16990 case 10: return 16; 16991 case 9: return 16; 16992 case 8: return 16; 16993 case 7: 16994 if (devinfo->is_haswell) { 16995 return 16; 16996 } else { 16997 return 16; 16998 } 16999 case 6: return 0; 17000 case 5: return 0; 17001 case 4: 17002 if (devinfo->is_g4x) { 17003 return 0; 17004 } else { 17005 return 0; 17006 } 17007 default: 17008 unreachable("Invalid hardware generation"); 17009 } 17010 } 17011 17012 17013 17014 /* 3DSTATE_CONSTANT_HS::Command SubType */ 17015 17016 17017 #define GEN10_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 17018 #define GEN9_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 17019 #define GEN8_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 17020 #define GEN75_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 17021 #define GEN7_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 17022 17023 static inline uint32_t ATTRIBUTE_PURE 17024 _3DSTATE_CONSTANT_HS_CommandSubType_bits(const struct gen_device_info *devinfo) 17025 { 17026 switch (devinfo->gen) { 17027 case 10: return 2; 17028 case 9: return 2; 17029 case 8: return 2; 17030 case 7: 17031 if (devinfo->is_haswell) { 17032 return 2; 17033 } else { 17034 return 2; 17035 } 17036 case 6: return 0; 17037 case 5: return 0; 17038 case 4: 17039 if (devinfo->is_g4x) { 17040 return 0; 17041 } else { 17042 return 0; 17043 } 17044 default: 17045 unreachable("Invalid hardware generation"); 17046 } 17047 } 17048 17049 17050 17051 #define GEN10_3DSTATE_CONSTANT_HS_CommandSubType_start 27 17052 #define GEN9_3DSTATE_CONSTANT_HS_CommandSubType_start 27 17053 #define GEN8_3DSTATE_CONSTANT_HS_CommandSubType_start 27 17054 #define GEN75_3DSTATE_CONSTANT_HS_CommandSubType_start 27 17055 #define GEN7_3DSTATE_CONSTANT_HS_CommandSubType_start 27 17056 17057 static inline uint32_t ATTRIBUTE_PURE 17058 _3DSTATE_CONSTANT_HS_CommandSubType_start(const struct gen_device_info *devinfo) 17059 { 17060 switch (devinfo->gen) { 17061 case 10: return 27; 17062 case 9: return 27; 17063 case 8: return 27; 17064 case 7: 17065 if (devinfo->is_haswell) { 17066 return 27; 17067 } else { 17068 return 27; 17069 } 17070 case 6: return 0; 17071 case 5: return 0; 17072 case 4: 17073 if (devinfo->is_g4x) { 17074 return 0; 17075 } else { 17076 return 0; 17077 } 17078 default: 17079 unreachable("Invalid hardware generation"); 17080 } 17081 } 17082 17083 17084 17085 /* 3DSTATE_CONSTANT_HS::Command Type */ 17086 17087 17088 #define GEN10_3DSTATE_CONSTANT_HS_CommandType_bits 3 17089 #define GEN9_3DSTATE_CONSTANT_HS_CommandType_bits 3 17090 #define GEN8_3DSTATE_CONSTANT_HS_CommandType_bits 3 17091 #define GEN75_3DSTATE_CONSTANT_HS_CommandType_bits 3 17092 #define GEN7_3DSTATE_CONSTANT_HS_CommandType_bits 3 17093 17094 static inline uint32_t ATTRIBUTE_PURE 17095 _3DSTATE_CONSTANT_HS_CommandType_bits(const struct gen_device_info *devinfo) 17096 { 17097 switch (devinfo->gen) { 17098 case 10: return 3; 17099 case 9: return 3; 17100 case 8: return 3; 17101 case 7: 17102 if (devinfo->is_haswell) { 17103 return 3; 17104 } else { 17105 return 3; 17106 } 17107 case 6: return 0; 17108 case 5: return 0; 17109 case 4: 17110 if (devinfo->is_g4x) { 17111 return 0; 17112 } else { 17113 return 0; 17114 } 17115 default: 17116 unreachable("Invalid hardware generation"); 17117 } 17118 } 17119 17120 17121 17122 #define GEN10_3DSTATE_CONSTANT_HS_CommandType_start 29 17123 #define GEN9_3DSTATE_CONSTANT_HS_CommandType_start 29 17124 #define GEN8_3DSTATE_CONSTANT_HS_CommandType_start 29 17125 #define GEN75_3DSTATE_CONSTANT_HS_CommandType_start 29 17126 #define GEN7_3DSTATE_CONSTANT_HS_CommandType_start 29 17127 17128 static inline uint32_t ATTRIBUTE_PURE 17129 _3DSTATE_CONSTANT_HS_CommandType_start(const struct gen_device_info *devinfo) 17130 { 17131 switch (devinfo->gen) { 17132 case 10: return 29; 17133 case 9: return 29; 17134 case 8: return 29; 17135 case 7: 17136 if (devinfo->is_haswell) { 17137 return 29; 17138 } else { 17139 return 29; 17140 } 17141 case 6: return 0; 17142 case 5: return 0; 17143 case 4: 17144 if (devinfo->is_g4x) { 17145 return 0; 17146 } else { 17147 return 0; 17148 } 17149 default: 17150 unreachable("Invalid hardware generation"); 17151 } 17152 } 17153 17154 17155 17156 /* 3DSTATE_CONSTANT_HS::Constant Body */ 17157 17158 17159 #define GEN10_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 17160 #define GEN9_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 17161 #define GEN8_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 17162 #define GEN75_3DSTATE_CONSTANT_HS_ConstantBody_bits 192 17163 #define GEN7_3DSTATE_CONSTANT_HS_ConstantBody_bits 192 17164 17165 static inline uint32_t ATTRIBUTE_PURE 17166 _3DSTATE_CONSTANT_HS_ConstantBody_bits(const struct gen_device_info *devinfo) 17167 { 17168 switch (devinfo->gen) { 17169 case 10: return 320; 17170 case 9: return 320; 17171 case 8: return 320; 17172 case 7: 17173 if (devinfo->is_haswell) { 17174 return 192; 17175 } else { 17176 return 192; 17177 } 17178 case 6: return 0; 17179 case 5: return 0; 17180 case 4: 17181 if (devinfo->is_g4x) { 17182 return 0; 17183 } else { 17184 return 0; 17185 } 17186 default: 17187 unreachable("Invalid hardware generation"); 17188 } 17189 } 17190 17191 17192 17193 #define GEN10_3DSTATE_CONSTANT_HS_ConstantBody_start 32 17194 #define GEN9_3DSTATE_CONSTANT_HS_ConstantBody_start 32 17195 #define GEN8_3DSTATE_CONSTANT_HS_ConstantBody_start 32 17196 #define GEN75_3DSTATE_CONSTANT_HS_ConstantBody_start 32 17197 #define GEN7_3DSTATE_CONSTANT_HS_ConstantBody_start 32 17198 17199 static inline uint32_t ATTRIBUTE_PURE 17200 _3DSTATE_CONSTANT_HS_ConstantBody_start(const struct gen_device_info *devinfo) 17201 { 17202 switch (devinfo->gen) { 17203 case 10: return 32; 17204 case 9: return 32; 17205 case 8: return 32; 17206 case 7: 17207 if (devinfo->is_haswell) { 17208 return 32; 17209 } else { 17210 return 32; 17211 } 17212 case 6: return 0; 17213 case 5: return 0; 17214 case 4: 17215 if (devinfo->is_g4x) { 17216 return 0; 17217 } else { 17218 return 0; 17219 } 17220 default: 17221 unreachable("Invalid hardware generation"); 17222 } 17223 } 17224 17225 17226 17227 /* 3DSTATE_CONSTANT_HS::Constant Buffer Object Control State */ 17228 17229 17230 #define GEN10_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits 7 17231 #define GEN9_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits 7 17232 #define GEN8_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits 7 17233 17234 static inline uint32_t ATTRIBUTE_PURE 17235 _3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) 17236 { 17237 switch (devinfo->gen) { 17238 case 10: return 7; 17239 case 9: return 7; 17240 case 8: return 7; 17241 case 7: 17242 if (devinfo->is_haswell) { 17243 return 0; 17244 } else { 17245 return 0; 17246 } 17247 case 6: return 0; 17248 case 5: return 0; 17249 case 4: 17250 if (devinfo->is_g4x) { 17251 return 0; 17252 } else { 17253 return 0; 17254 } 17255 default: 17256 unreachable("Invalid hardware generation"); 17257 } 17258 } 17259 17260 17261 17262 #define GEN10_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start 8 17263 #define GEN9_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start 8 17264 #define GEN8_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start 8 17265 17266 static inline uint32_t ATTRIBUTE_PURE 17267 _3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) 17268 { 17269 switch (devinfo->gen) { 17270 case 10: return 8; 17271 case 9: return 8; 17272 case 8: return 8; 17273 case 7: 17274 if (devinfo->is_haswell) { 17275 return 0; 17276 } else { 17277 return 0; 17278 } 17279 case 6: return 0; 17280 case 5: return 0; 17281 case 4: 17282 if (devinfo->is_g4x) { 17283 return 0; 17284 } else { 17285 return 0; 17286 } 17287 default: 17288 unreachable("Invalid hardware generation"); 17289 } 17290 } 17291 17292 17293 17294 /* 3DSTATE_CONSTANT_HS::DWord Length */ 17295 17296 17297 #define GEN10_3DSTATE_CONSTANT_HS_DWordLength_bits 8 17298 #define GEN9_3DSTATE_CONSTANT_HS_DWordLength_bits 8 17299 #define GEN8_3DSTATE_CONSTANT_HS_DWordLength_bits 8 17300 #define GEN75_3DSTATE_CONSTANT_HS_DWordLength_bits 8 17301 #define GEN7_3DSTATE_CONSTANT_HS_DWordLength_bits 8 17302 17303 static inline uint32_t ATTRIBUTE_PURE 17304 _3DSTATE_CONSTANT_HS_DWordLength_bits(const struct gen_device_info *devinfo) 17305 { 17306 switch (devinfo->gen) { 17307 case 10: return 8; 17308 case 9: return 8; 17309 case 8: return 8; 17310 case 7: 17311 if (devinfo->is_haswell) { 17312 return 8; 17313 } else { 17314 return 8; 17315 } 17316 case 6: return 0; 17317 case 5: return 0; 17318 case 4: 17319 if (devinfo->is_g4x) { 17320 return 0; 17321 } else { 17322 return 0; 17323 } 17324 default: 17325 unreachable("Invalid hardware generation"); 17326 } 17327 } 17328 17329 17330 17331 #define GEN10_3DSTATE_CONSTANT_HS_DWordLength_start 0 17332 #define GEN9_3DSTATE_CONSTANT_HS_DWordLength_start 0 17333 #define GEN8_3DSTATE_CONSTANT_HS_DWordLength_start 0 17334 #define GEN75_3DSTATE_CONSTANT_HS_DWordLength_start 0 17335 #define GEN7_3DSTATE_CONSTANT_HS_DWordLength_start 0 17336 17337 static inline uint32_t ATTRIBUTE_PURE 17338 _3DSTATE_CONSTANT_HS_DWordLength_start(const struct gen_device_info *devinfo) 17339 { 17340 switch (devinfo->gen) { 17341 case 10: return 0; 17342 case 9: return 0; 17343 case 8: return 0; 17344 case 7: 17345 if (devinfo->is_haswell) { 17346 return 0; 17347 } else { 17348 return 0; 17349 } 17350 case 6: return 0; 17351 case 5: return 0; 17352 case 4: 17353 if (devinfo->is_g4x) { 17354 return 0; 17355 } else { 17356 return 0; 17357 } 17358 default: 17359 unreachable("Invalid hardware generation"); 17360 } 17361 } 17362 17363 17364 17365 /* 3DSTATE_CONSTANT_PS */ 17366 17367 17368 #define GEN10_3DSTATE_CONSTANT_PS_length 11 17369 #define GEN9_3DSTATE_CONSTANT_PS_length 11 17370 #define GEN8_3DSTATE_CONSTANT_PS_length 11 17371 #define GEN75_3DSTATE_CONSTANT_PS_length 7 17372 #define GEN7_3DSTATE_CONSTANT_PS_length 7 17373 #define GEN6_3DSTATE_CONSTANT_PS_length 5 17374 17375 static inline uint32_t ATTRIBUTE_PURE 17376 _3DSTATE_CONSTANT_PS_length(const struct gen_device_info *devinfo) 17377 { 17378 switch (devinfo->gen) { 17379 case 10: return 11; 17380 case 9: return 11; 17381 case 8: return 11; 17382 case 7: 17383 if (devinfo->is_haswell) { 17384 return 7; 17385 } else { 17386 return 7; 17387 } 17388 case 6: return 5; 17389 case 5: return 0; 17390 case 4: 17391 if (devinfo->is_g4x) { 17392 return 0; 17393 } else { 17394 return 0; 17395 } 17396 default: 17397 unreachable("Invalid hardware generation"); 17398 } 17399 } 17400 17401 17402 17403 /* 3DSTATE_CONSTANT_PS::3D Command Opcode */ 17404 17405 17406 #define GEN10_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 17407 #define GEN9_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 17408 #define GEN8_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 17409 #define GEN75_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 17410 #define GEN7_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 17411 #define GEN6_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 17412 17413 static inline uint32_t ATTRIBUTE_PURE 17414 _3DSTATE_CONSTANT_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 17415 { 17416 switch (devinfo->gen) { 17417 case 10: return 3; 17418 case 9: return 3; 17419 case 8: return 3; 17420 case 7: 17421 if (devinfo->is_haswell) { 17422 return 3; 17423 } else { 17424 return 3; 17425 } 17426 case 6: return 3; 17427 case 5: return 0; 17428 case 4: 17429 if (devinfo->is_g4x) { 17430 return 0; 17431 } else { 17432 return 0; 17433 } 17434 default: 17435 unreachable("Invalid hardware generation"); 17436 } 17437 } 17438 17439 17440 17441 #define GEN10_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 17442 #define GEN9_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 17443 #define GEN8_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 17444 #define GEN75_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 17445 #define GEN7_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 17446 #define GEN6_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 17447 17448 static inline uint32_t ATTRIBUTE_PURE 17449 _3DSTATE_CONSTANT_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 17450 { 17451 switch (devinfo->gen) { 17452 case 10: return 24; 17453 case 9: return 24; 17454 case 8: return 24; 17455 case 7: 17456 if (devinfo->is_haswell) { 17457 return 24; 17458 } else { 17459 return 24; 17460 } 17461 case 6: return 24; 17462 case 5: return 0; 17463 case 4: 17464 if (devinfo->is_g4x) { 17465 return 0; 17466 } else { 17467 return 0; 17468 } 17469 default: 17470 unreachable("Invalid hardware generation"); 17471 } 17472 } 17473 17474 17475 17476 /* 3DSTATE_CONSTANT_PS::3D Command Sub Opcode */ 17477 17478 17479 #define GEN10_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 17480 #define GEN9_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 17481 #define GEN8_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 17482 #define GEN75_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 17483 #define GEN7_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 17484 #define GEN6_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 17485 17486 static inline uint32_t ATTRIBUTE_PURE 17487 _3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 17488 { 17489 switch (devinfo->gen) { 17490 case 10: return 8; 17491 case 9: return 8; 17492 case 8: return 8; 17493 case 7: 17494 if (devinfo->is_haswell) { 17495 return 8; 17496 } else { 17497 return 8; 17498 } 17499 case 6: return 8; 17500 case 5: return 0; 17501 case 4: 17502 if (devinfo->is_g4x) { 17503 return 0; 17504 } else { 17505 return 0; 17506 } 17507 default: 17508 unreachable("Invalid hardware generation"); 17509 } 17510 } 17511 17512 17513 17514 #define GEN10_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 17515 #define GEN9_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 17516 #define GEN8_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 17517 #define GEN75_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 17518 #define GEN7_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 17519 #define GEN6_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 17520 17521 static inline uint32_t ATTRIBUTE_PURE 17522 _3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 17523 { 17524 switch (devinfo->gen) { 17525 case 10: return 16; 17526 case 9: return 16; 17527 case 8: return 16; 17528 case 7: 17529 if (devinfo->is_haswell) { 17530 return 16; 17531 } else { 17532 return 16; 17533 } 17534 case 6: return 16; 17535 case 5: return 0; 17536 case 4: 17537 if (devinfo->is_g4x) { 17538 return 0; 17539 } else { 17540 return 0; 17541 } 17542 default: 17543 unreachable("Invalid hardware generation"); 17544 } 17545 } 17546 17547 17548 17549 /* 3DSTATE_CONSTANT_PS::Buffer 0 Valid */ 17550 17551 17552 #define GEN6_3DSTATE_CONSTANT_PS_Buffer0Valid_bits 1 17553 17554 static inline uint32_t ATTRIBUTE_PURE 17555 _3DSTATE_CONSTANT_PS_Buffer0Valid_bits(const struct gen_device_info *devinfo) 17556 { 17557 switch (devinfo->gen) { 17558 case 10: return 0; 17559 case 9: return 0; 17560 case 8: return 0; 17561 case 7: 17562 if (devinfo->is_haswell) { 17563 return 0; 17564 } else { 17565 return 0; 17566 } 17567 case 6: return 1; 17568 case 5: return 0; 17569 case 4: 17570 if (devinfo->is_g4x) { 17571 return 0; 17572 } else { 17573 return 0; 17574 } 17575 default: 17576 unreachable("Invalid hardware generation"); 17577 } 17578 } 17579 17580 17581 17582 #define GEN6_3DSTATE_CONSTANT_PS_Buffer0Valid_start 12 17583 17584 static inline uint32_t ATTRIBUTE_PURE 17585 _3DSTATE_CONSTANT_PS_Buffer0Valid_start(const struct gen_device_info *devinfo) 17586 { 17587 switch (devinfo->gen) { 17588 case 10: return 0; 17589 case 9: return 0; 17590 case 8: return 0; 17591 case 7: 17592 if (devinfo->is_haswell) { 17593 return 0; 17594 } else { 17595 return 0; 17596 } 17597 case 6: return 12; 17598 case 5: return 0; 17599 case 4: 17600 if (devinfo->is_g4x) { 17601 return 0; 17602 } else { 17603 return 0; 17604 } 17605 default: 17606 unreachable("Invalid hardware generation"); 17607 } 17608 } 17609 17610 17611 17612 /* 3DSTATE_CONSTANT_PS::Buffer 1 Valid */ 17613 17614 17615 #define GEN6_3DSTATE_CONSTANT_PS_Buffer1Valid_bits 1 17616 17617 static inline uint32_t ATTRIBUTE_PURE 17618 _3DSTATE_CONSTANT_PS_Buffer1Valid_bits(const struct gen_device_info *devinfo) 17619 { 17620 switch (devinfo->gen) { 17621 case 10: return 0; 17622 case 9: return 0; 17623 case 8: return 0; 17624 case 7: 17625 if (devinfo->is_haswell) { 17626 return 0; 17627 } else { 17628 return 0; 17629 } 17630 case 6: return 1; 17631 case 5: return 0; 17632 case 4: 17633 if (devinfo->is_g4x) { 17634 return 0; 17635 } else { 17636 return 0; 17637 } 17638 default: 17639 unreachable("Invalid hardware generation"); 17640 } 17641 } 17642 17643 17644 17645 #define GEN6_3DSTATE_CONSTANT_PS_Buffer1Valid_start 13 17646 17647 static inline uint32_t ATTRIBUTE_PURE 17648 _3DSTATE_CONSTANT_PS_Buffer1Valid_start(const struct gen_device_info *devinfo) 17649 { 17650 switch (devinfo->gen) { 17651 case 10: return 0; 17652 case 9: return 0; 17653 case 8: return 0; 17654 case 7: 17655 if (devinfo->is_haswell) { 17656 return 0; 17657 } else { 17658 return 0; 17659 } 17660 case 6: return 13; 17661 case 5: return 0; 17662 case 4: 17663 if (devinfo->is_g4x) { 17664 return 0; 17665 } else { 17666 return 0; 17667 } 17668 default: 17669 unreachable("Invalid hardware generation"); 17670 } 17671 } 17672 17673 17674 17675 /* 3DSTATE_CONSTANT_PS::Buffer 2 Valid */ 17676 17677 17678 #define GEN6_3DSTATE_CONSTANT_PS_Buffer2Valid_bits 1 17679 17680 static inline uint32_t ATTRIBUTE_PURE 17681 _3DSTATE_CONSTANT_PS_Buffer2Valid_bits(const struct gen_device_info *devinfo) 17682 { 17683 switch (devinfo->gen) { 17684 case 10: return 0; 17685 case 9: return 0; 17686 case 8: return 0; 17687 case 7: 17688 if (devinfo->is_haswell) { 17689 return 0; 17690 } else { 17691 return 0; 17692 } 17693 case 6: return 1; 17694 case 5: return 0; 17695 case 4: 17696 if (devinfo->is_g4x) { 17697 return 0; 17698 } else { 17699 return 0; 17700 } 17701 default: 17702 unreachable("Invalid hardware generation"); 17703 } 17704 } 17705 17706 17707 17708 #define GEN6_3DSTATE_CONSTANT_PS_Buffer2Valid_start 14 17709 17710 static inline uint32_t ATTRIBUTE_PURE 17711 _3DSTATE_CONSTANT_PS_Buffer2Valid_start(const struct gen_device_info *devinfo) 17712 { 17713 switch (devinfo->gen) { 17714 case 10: return 0; 17715 case 9: return 0; 17716 case 8: return 0; 17717 case 7: 17718 if (devinfo->is_haswell) { 17719 return 0; 17720 } else { 17721 return 0; 17722 } 17723 case 6: return 14; 17724 case 5: return 0; 17725 case 4: 17726 if (devinfo->is_g4x) { 17727 return 0; 17728 } else { 17729 return 0; 17730 } 17731 default: 17732 unreachable("Invalid hardware generation"); 17733 } 17734 } 17735 17736 17737 17738 /* 3DSTATE_CONSTANT_PS::Buffer 3 Valid */ 17739 17740 17741 #define GEN6_3DSTATE_CONSTANT_PS_Buffer3Valid_bits 1 17742 17743 static inline uint32_t ATTRIBUTE_PURE 17744 _3DSTATE_CONSTANT_PS_Buffer3Valid_bits(const struct gen_device_info *devinfo) 17745 { 17746 switch (devinfo->gen) { 17747 case 10: return 0; 17748 case 9: return 0; 17749 case 8: return 0; 17750 case 7: 17751 if (devinfo->is_haswell) { 17752 return 0; 17753 } else { 17754 return 0; 17755 } 17756 case 6: return 1; 17757 case 5: return 0; 17758 case 4: 17759 if (devinfo->is_g4x) { 17760 return 0; 17761 } else { 17762 return 0; 17763 } 17764 default: 17765 unreachable("Invalid hardware generation"); 17766 } 17767 } 17768 17769 17770 17771 #define GEN6_3DSTATE_CONSTANT_PS_Buffer3Valid_start 15 17772 17773 static inline uint32_t ATTRIBUTE_PURE 17774 _3DSTATE_CONSTANT_PS_Buffer3Valid_start(const struct gen_device_info *devinfo) 17775 { 17776 switch (devinfo->gen) { 17777 case 10: return 0; 17778 case 9: return 0; 17779 case 8: return 0; 17780 case 7: 17781 if (devinfo->is_haswell) { 17782 return 0; 17783 } else { 17784 return 0; 17785 } 17786 case 6: return 15; 17787 case 5: return 0; 17788 case 4: 17789 if (devinfo->is_g4x) { 17790 return 0; 17791 } else { 17792 return 0; 17793 } 17794 default: 17795 unreachable("Invalid hardware generation"); 17796 } 17797 } 17798 17799 17800 17801 /* 3DSTATE_CONSTANT_PS::Command SubType */ 17802 17803 17804 #define GEN10_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 17805 #define GEN9_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 17806 #define GEN8_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 17807 #define GEN75_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 17808 #define GEN7_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 17809 #define GEN6_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 17810 17811 static inline uint32_t ATTRIBUTE_PURE 17812 _3DSTATE_CONSTANT_PS_CommandSubType_bits(const struct gen_device_info *devinfo) 17813 { 17814 switch (devinfo->gen) { 17815 case 10: return 2; 17816 case 9: return 2; 17817 case 8: return 2; 17818 case 7: 17819 if (devinfo->is_haswell) { 17820 return 2; 17821 } else { 17822 return 2; 17823 } 17824 case 6: return 2; 17825 case 5: return 0; 17826 case 4: 17827 if (devinfo->is_g4x) { 17828 return 0; 17829 } else { 17830 return 0; 17831 } 17832 default: 17833 unreachable("Invalid hardware generation"); 17834 } 17835 } 17836 17837 17838 17839 #define GEN10_3DSTATE_CONSTANT_PS_CommandSubType_start 27 17840 #define GEN9_3DSTATE_CONSTANT_PS_CommandSubType_start 27 17841 #define GEN8_3DSTATE_CONSTANT_PS_CommandSubType_start 27 17842 #define GEN75_3DSTATE_CONSTANT_PS_CommandSubType_start 27 17843 #define GEN7_3DSTATE_CONSTANT_PS_CommandSubType_start 27 17844 #define GEN6_3DSTATE_CONSTANT_PS_CommandSubType_start 27 17845 17846 static inline uint32_t ATTRIBUTE_PURE 17847 _3DSTATE_CONSTANT_PS_CommandSubType_start(const struct gen_device_info *devinfo) 17848 { 17849 switch (devinfo->gen) { 17850 case 10: return 27; 17851 case 9: return 27; 17852 case 8: return 27; 17853 case 7: 17854 if (devinfo->is_haswell) { 17855 return 27; 17856 } else { 17857 return 27; 17858 } 17859 case 6: return 27; 17860 case 5: return 0; 17861 case 4: 17862 if (devinfo->is_g4x) { 17863 return 0; 17864 } else { 17865 return 0; 17866 } 17867 default: 17868 unreachable("Invalid hardware generation"); 17869 } 17870 } 17871 17872 17873 17874 /* 3DSTATE_CONSTANT_PS::Command Type */ 17875 17876 17877 #define GEN10_3DSTATE_CONSTANT_PS_CommandType_bits 3 17878 #define GEN9_3DSTATE_CONSTANT_PS_CommandType_bits 3 17879 #define GEN8_3DSTATE_CONSTANT_PS_CommandType_bits 3 17880 #define GEN75_3DSTATE_CONSTANT_PS_CommandType_bits 3 17881 #define GEN7_3DSTATE_CONSTANT_PS_CommandType_bits 3 17882 #define GEN6_3DSTATE_CONSTANT_PS_CommandType_bits 3 17883 17884 static inline uint32_t ATTRIBUTE_PURE 17885 _3DSTATE_CONSTANT_PS_CommandType_bits(const struct gen_device_info *devinfo) 17886 { 17887 switch (devinfo->gen) { 17888 case 10: return 3; 17889 case 9: return 3; 17890 case 8: return 3; 17891 case 7: 17892 if (devinfo->is_haswell) { 17893 return 3; 17894 } else { 17895 return 3; 17896 } 17897 case 6: return 3; 17898 case 5: return 0; 17899 case 4: 17900 if (devinfo->is_g4x) { 17901 return 0; 17902 } else { 17903 return 0; 17904 } 17905 default: 17906 unreachable("Invalid hardware generation"); 17907 } 17908 } 17909 17910 17911 17912 #define GEN10_3DSTATE_CONSTANT_PS_CommandType_start 29 17913 #define GEN9_3DSTATE_CONSTANT_PS_CommandType_start 29 17914 #define GEN8_3DSTATE_CONSTANT_PS_CommandType_start 29 17915 #define GEN75_3DSTATE_CONSTANT_PS_CommandType_start 29 17916 #define GEN7_3DSTATE_CONSTANT_PS_CommandType_start 29 17917 #define GEN6_3DSTATE_CONSTANT_PS_CommandType_start 29 17918 17919 static inline uint32_t ATTRIBUTE_PURE 17920 _3DSTATE_CONSTANT_PS_CommandType_start(const struct gen_device_info *devinfo) 17921 { 17922 switch (devinfo->gen) { 17923 case 10: return 29; 17924 case 9: return 29; 17925 case 8: return 29; 17926 case 7: 17927 if (devinfo->is_haswell) { 17928 return 29; 17929 } else { 17930 return 29; 17931 } 17932 case 6: return 29; 17933 case 5: return 0; 17934 case 4: 17935 if (devinfo->is_g4x) { 17936 return 0; 17937 } else { 17938 return 0; 17939 } 17940 default: 17941 unreachable("Invalid hardware generation"); 17942 } 17943 } 17944 17945 17946 17947 /* 3DSTATE_CONSTANT_PS::Constant Body */ 17948 17949 17950 #define GEN10_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 17951 #define GEN9_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 17952 #define GEN8_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 17953 #define GEN75_3DSTATE_CONSTANT_PS_ConstantBody_bits 192 17954 #define GEN7_3DSTATE_CONSTANT_PS_ConstantBody_bits 192 17955 17956 static inline uint32_t ATTRIBUTE_PURE 17957 _3DSTATE_CONSTANT_PS_ConstantBody_bits(const struct gen_device_info *devinfo) 17958 { 17959 switch (devinfo->gen) { 17960 case 10: return 320; 17961 case 9: return 320; 17962 case 8: return 320; 17963 case 7: 17964 if (devinfo->is_haswell) { 17965 return 192; 17966 } else { 17967 return 192; 17968 } 17969 case 6: return 0; 17970 case 5: return 0; 17971 case 4: 17972 if (devinfo->is_g4x) { 17973 return 0; 17974 } else { 17975 return 0; 17976 } 17977 default: 17978 unreachable("Invalid hardware generation"); 17979 } 17980 } 17981 17982 17983 17984 #define GEN10_3DSTATE_CONSTANT_PS_ConstantBody_start 32 17985 #define GEN9_3DSTATE_CONSTANT_PS_ConstantBody_start 32 17986 #define GEN8_3DSTATE_CONSTANT_PS_ConstantBody_start 32 17987 #define GEN75_3DSTATE_CONSTANT_PS_ConstantBody_start 32 17988 #define GEN7_3DSTATE_CONSTANT_PS_ConstantBody_start 32 17989 17990 static inline uint32_t ATTRIBUTE_PURE 17991 _3DSTATE_CONSTANT_PS_ConstantBody_start(const struct gen_device_info *devinfo) 17992 { 17993 switch (devinfo->gen) { 17994 case 10: return 32; 17995 case 9: return 32; 17996 case 8: return 32; 17997 case 7: 17998 if (devinfo->is_haswell) { 17999 return 32; 18000 } else { 18001 return 32; 18002 } 18003 case 6: return 0; 18004 case 5: return 0; 18005 case 4: 18006 if (devinfo->is_g4x) { 18007 return 0; 18008 } else { 18009 return 0; 18010 } 18011 default: 18012 unreachable("Invalid hardware generation"); 18013 } 18014 } 18015 18016 18017 18018 /* 3DSTATE_CONSTANT_PS::Constant Buffer Object Control State */ 18019 18020 18021 #define GEN10_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 7 18022 #define GEN9_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 7 18023 #define GEN8_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 7 18024 #define GEN6_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 4 18025 18026 static inline uint32_t ATTRIBUTE_PURE 18027 _3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) 18028 { 18029 switch (devinfo->gen) { 18030 case 10: return 7; 18031 case 9: return 7; 18032 case 8: return 7; 18033 case 7: 18034 if (devinfo->is_haswell) { 18035 return 0; 18036 } else { 18037 return 0; 18038 } 18039 case 6: return 4; 18040 case 5: return 0; 18041 case 4: 18042 if (devinfo->is_g4x) { 18043 return 0; 18044 } else { 18045 return 0; 18046 } 18047 default: 18048 unreachable("Invalid hardware generation"); 18049 } 18050 } 18051 18052 18053 18054 #define GEN10_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 18055 #define GEN9_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 18056 #define GEN8_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 18057 #define GEN6_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 18058 18059 static inline uint32_t ATTRIBUTE_PURE 18060 _3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) 18061 { 18062 switch (devinfo->gen) { 18063 case 10: return 8; 18064 case 9: return 8; 18065 case 8: return 8; 18066 case 7: 18067 if (devinfo->is_haswell) { 18068 return 0; 18069 } else { 18070 return 0; 18071 } 18072 case 6: return 8; 18073 case 5: return 0; 18074 case 4: 18075 if (devinfo->is_g4x) { 18076 return 0; 18077 } else { 18078 return 0; 18079 } 18080 default: 18081 unreachable("Invalid hardware generation"); 18082 } 18083 } 18084 18085 18086 18087 /* 3DSTATE_CONSTANT_PS::DWord Length */ 18088 18089 18090 #define GEN10_3DSTATE_CONSTANT_PS_DWordLength_bits 8 18091 #define GEN9_3DSTATE_CONSTANT_PS_DWordLength_bits 8 18092 #define GEN8_3DSTATE_CONSTANT_PS_DWordLength_bits 8 18093 #define GEN75_3DSTATE_CONSTANT_PS_DWordLength_bits 8 18094 #define GEN7_3DSTATE_CONSTANT_PS_DWordLength_bits 8 18095 #define GEN6_3DSTATE_CONSTANT_PS_DWordLength_bits 8 18096 18097 static inline uint32_t ATTRIBUTE_PURE 18098 _3DSTATE_CONSTANT_PS_DWordLength_bits(const struct gen_device_info *devinfo) 18099 { 18100 switch (devinfo->gen) { 18101 case 10: return 8; 18102 case 9: return 8; 18103 case 8: return 8; 18104 case 7: 18105 if (devinfo->is_haswell) { 18106 return 8; 18107 } else { 18108 return 8; 18109 } 18110 case 6: return 8; 18111 case 5: return 0; 18112 case 4: 18113 if (devinfo->is_g4x) { 18114 return 0; 18115 } else { 18116 return 0; 18117 } 18118 default: 18119 unreachable("Invalid hardware generation"); 18120 } 18121 } 18122 18123 18124 18125 #define GEN10_3DSTATE_CONSTANT_PS_DWordLength_start 0 18126 #define GEN9_3DSTATE_CONSTANT_PS_DWordLength_start 0 18127 #define GEN8_3DSTATE_CONSTANT_PS_DWordLength_start 0 18128 #define GEN75_3DSTATE_CONSTANT_PS_DWordLength_start 0 18129 #define GEN7_3DSTATE_CONSTANT_PS_DWordLength_start 0 18130 #define GEN6_3DSTATE_CONSTANT_PS_DWordLength_start 0 18131 18132 static inline uint32_t ATTRIBUTE_PURE 18133 _3DSTATE_CONSTANT_PS_DWordLength_start(const struct gen_device_info *devinfo) 18134 { 18135 switch (devinfo->gen) { 18136 case 10: return 0; 18137 case 9: return 0; 18138 case 8: return 0; 18139 case 7: 18140 if (devinfo->is_haswell) { 18141 return 0; 18142 } else { 18143 return 0; 18144 } 18145 case 6: return 0; 18146 case 5: return 0; 18147 case 4: 18148 if (devinfo->is_g4x) { 18149 return 0; 18150 } else { 18151 return 0; 18152 } 18153 default: 18154 unreachable("Invalid hardware generation"); 18155 } 18156 } 18157 18158 18159 18160 /* 3DSTATE_CONSTANT_PS::Disable Gather at Set Shader Hint */ 18161 18162 18163 #define GEN10_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits 1 18164 18165 static inline uint32_t ATTRIBUTE_PURE 18166 _3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits(const struct gen_device_info *devinfo) 18167 { 18168 switch (devinfo->gen) { 18169 case 10: return 1; 18170 case 9: return 0; 18171 case 8: return 0; 18172 case 7: 18173 if (devinfo->is_haswell) { 18174 return 0; 18175 } else { 18176 return 0; 18177 } 18178 case 6: return 0; 18179 case 5: return 0; 18180 case 4: 18181 if (devinfo->is_g4x) { 18182 return 0; 18183 } else { 18184 return 0; 18185 } 18186 default: 18187 unreachable("Invalid hardware generation"); 18188 } 18189 } 18190 18191 18192 18193 #define GEN10_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start 15 18194 18195 static inline uint32_t ATTRIBUTE_PURE 18196 _3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start(const struct gen_device_info *devinfo) 18197 { 18198 switch (devinfo->gen) { 18199 case 10: return 15; 18200 case 9: return 0; 18201 case 8: return 0; 18202 case 7: 18203 if (devinfo->is_haswell) { 18204 return 0; 18205 } else { 18206 return 0; 18207 } 18208 case 6: return 0; 18209 case 5: return 0; 18210 case 4: 18211 if (devinfo->is_g4x) { 18212 return 0; 18213 } else { 18214 return 0; 18215 } 18216 default: 18217 unreachable("Invalid hardware generation"); 18218 } 18219 } 18220 18221 18222 18223 /* 3DSTATE_CONSTANT_PS::PS Constant Buffer 0 Read Length */ 18224 18225 18226 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer0ReadLength_bits 5 18227 18228 static inline uint32_t ATTRIBUTE_PURE 18229 _3DSTATE_CONSTANT_PS_PSConstantBuffer0ReadLength_bits(const struct gen_device_info *devinfo) 18230 { 18231 switch (devinfo->gen) { 18232 case 10: return 0; 18233 case 9: return 0; 18234 case 8: return 0; 18235 case 7: 18236 if (devinfo->is_haswell) { 18237 return 0; 18238 } else { 18239 return 0; 18240 } 18241 case 6: return 5; 18242 case 5: return 0; 18243 case 4: 18244 if (devinfo->is_g4x) { 18245 return 0; 18246 } else { 18247 return 0; 18248 } 18249 default: 18250 unreachable("Invalid hardware generation"); 18251 } 18252 } 18253 18254 18255 18256 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer0ReadLength_start 32 18257 18258 static inline uint32_t ATTRIBUTE_PURE 18259 _3DSTATE_CONSTANT_PS_PSConstantBuffer0ReadLength_start(const struct gen_device_info *devinfo) 18260 { 18261 switch (devinfo->gen) { 18262 case 10: return 0; 18263 case 9: return 0; 18264 case 8: return 0; 18265 case 7: 18266 if (devinfo->is_haswell) { 18267 return 0; 18268 } else { 18269 return 0; 18270 } 18271 case 6: return 32; 18272 case 5: return 0; 18273 case 4: 18274 if (devinfo->is_g4x) { 18275 return 0; 18276 } else { 18277 return 0; 18278 } 18279 default: 18280 unreachable("Invalid hardware generation"); 18281 } 18282 } 18283 18284 18285 18286 /* 3DSTATE_CONSTANT_PS::PS Constant Buffer 1 Read Length */ 18287 18288 18289 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer1ReadLength_bits 5 18290 18291 static inline uint32_t ATTRIBUTE_PURE 18292 _3DSTATE_CONSTANT_PS_PSConstantBuffer1ReadLength_bits(const struct gen_device_info *devinfo) 18293 { 18294 switch (devinfo->gen) { 18295 case 10: return 0; 18296 case 9: return 0; 18297 case 8: return 0; 18298 case 7: 18299 if (devinfo->is_haswell) { 18300 return 0; 18301 } else { 18302 return 0; 18303 } 18304 case 6: return 5; 18305 case 5: return 0; 18306 case 4: 18307 if (devinfo->is_g4x) { 18308 return 0; 18309 } else { 18310 return 0; 18311 } 18312 default: 18313 unreachable("Invalid hardware generation"); 18314 } 18315 } 18316 18317 18318 18319 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer1ReadLength_start 64 18320 18321 static inline uint32_t ATTRIBUTE_PURE 18322 _3DSTATE_CONSTANT_PS_PSConstantBuffer1ReadLength_start(const struct gen_device_info *devinfo) 18323 { 18324 switch (devinfo->gen) { 18325 case 10: return 0; 18326 case 9: return 0; 18327 case 8: return 0; 18328 case 7: 18329 if (devinfo->is_haswell) { 18330 return 0; 18331 } else { 18332 return 0; 18333 } 18334 case 6: return 64; 18335 case 5: return 0; 18336 case 4: 18337 if (devinfo->is_g4x) { 18338 return 0; 18339 } else { 18340 return 0; 18341 } 18342 default: 18343 unreachable("Invalid hardware generation"); 18344 } 18345 } 18346 18347 18348 18349 /* 3DSTATE_CONSTANT_PS::PS Constant Buffer 2 Read Length */ 18350 18351 18352 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer2ReadLength_bits 5 18353 18354 static inline uint32_t ATTRIBUTE_PURE 18355 _3DSTATE_CONSTANT_PS_PSConstantBuffer2ReadLength_bits(const struct gen_device_info *devinfo) 18356 { 18357 switch (devinfo->gen) { 18358 case 10: return 0; 18359 case 9: return 0; 18360 case 8: return 0; 18361 case 7: 18362 if (devinfo->is_haswell) { 18363 return 0; 18364 } else { 18365 return 0; 18366 } 18367 case 6: return 5; 18368 case 5: return 0; 18369 case 4: 18370 if (devinfo->is_g4x) { 18371 return 0; 18372 } else { 18373 return 0; 18374 } 18375 default: 18376 unreachable("Invalid hardware generation"); 18377 } 18378 } 18379 18380 18381 18382 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer2ReadLength_start 96 18383 18384 static inline uint32_t ATTRIBUTE_PURE 18385 _3DSTATE_CONSTANT_PS_PSConstantBuffer2ReadLength_start(const struct gen_device_info *devinfo) 18386 { 18387 switch (devinfo->gen) { 18388 case 10: return 0; 18389 case 9: return 0; 18390 case 8: return 0; 18391 case 7: 18392 if (devinfo->is_haswell) { 18393 return 0; 18394 } else { 18395 return 0; 18396 } 18397 case 6: return 96; 18398 case 5: return 0; 18399 case 4: 18400 if (devinfo->is_g4x) { 18401 return 0; 18402 } else { 18403 return 0; 18404 } 18405 default: 18406 unreachable("Invalid hardware generation"); 18407 } 18408 } 18409 18410 18411 18412 /* 3DSTATE_CONSTANT_PS::PS Constant Buffer 3 Read Length */ 18413 18414 18415 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer3ReadLength_bits 5 18416 18417 static inline uint32_t ATTRIBUTE_PURE 18418 _3DSTATE_CONSTANT_PS_PSConstantBuffer3ReadLength_bits(const struct gen_device_info *devinfo) 18419 { 18420 switch (devinfo->gen) { 18421 case 10: return 0; 18422 case 9: return 0; 18423 case 8: return 0; 18424 case 7: 18425 if (devinfo->is_haswell) { 18426 return 0; 18427 } else { 18428 return 0; 18429 } 18430 case 6: return 5; 18431 case 5: return 0; 18432 case 4: 18433 if (devinfo->is_g4x) { 18434 return 0; 18435 } else { 18436 return 0; 18437 } 18438 default: 18439 unreachable("Invalid hardware generation"); 18440 } 18441 } 18442 18443 18444 18445 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer3ReadLength_start 128 18446 18447 static inline uint32_t ATTRIBUTE_PURE 18448 _3DSTATE_CONSTANT_PS_PSConstantBuffer3ReadLength_start(const struct gen_device_info *devinfo) 18449 { 18450 switch (devinfo->gen) { 18451 case 10: return 0; 18452 case 9: return 0; 18453 case 8: return 0; 18454 case 7: 18455 if (devinfo->is_haswell) { 18456 return 0; 18457 } else { 18458 return 0; 18459 } 18460 case 6: return 128; 18461 case 5: return 0; 18462 case 4: 18463 if (devinfo->is_g4x) { 18464 return 0; 18465 } else { 18466 return 0; 18467 } 18468 default: 18469 unreachable("Invalid hardware generation"); 18470 } 18471 } 18472 18473 18474 18475 /* 3DSTATE_CONSTANT_PS::Pointer to PS Constant Buffer 0 */ 18476 18477 18478 #define GEN6_3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer0_bits 27 18479 18480 static inline uint32_t ATTRIBUTE_PURE 18481 _3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer0_bits(const struct gen_device_info *devinfo) 18482 { 18483 switch (devinfo->gen) { 18484 case 10: return 0; 18485 case 9: return 0; 18486 case 8: return 0; 18487 case 7: 18488 if (devinfo->is_haswell) { 18489 return 0; 18490 } else { 18491 return 0; 18492 } 18493 case 6: return 27; 18494 case 5: return 0; 18495 case 4: 18496 if (devinfo->is_g4x) { 18497 return 0; 18498 } else { 18499 return 0; 18500 } 18501 default: 18502 unreachable("Invalid hardware generation"); 18503 } 18504 } 18505 18506 18507 18508 #define GEN6_3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer0_start 37 18509 18510 static inline uint32_t ATTRIBUTE_PURE 18511 _3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer0_start(const struct gen_device_info *devinfo) 18512 { 18513 switch (devinfo->gen) { 18514 case 10: return 0; 18515 case 9: return 0; 18516 case 8: return 0; 18517 case 7: 18518 if (devinfo->is_haswell) { 18519 return 0; 18520 } else { 18521 return 0; 18522 } 18523 case 6: return 37; 18524 case 5: return 0; 18