1 /* 2 * Copyright 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 /* THIS FILE HAS BEEN GENERATED, DO NOT HAND EDIT. 25 * 26 * Sizes of bitfields in genxml instructions, structures, and registers. 27 */ 28 29 #ifndef GENX_BITS_H 30 #define GENX_BITS_H 31 32 #include <stdint.h> 33 34 #include "common/gen_device_info.h" 35 #include "util/macros.h" 36 37 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /* 3DPRIMITIVE */ 44 45 46 #define GEN10_3DPRIMITIVE_length 7 47 #define GEN9_3DPRIMITIVE_length 7 48 #define GEN8_3DPRIMITIVE_length 7 49 #define GEN75_3DPRIMITIVE_length 7 50 #define GEN7_3DPRIMITIVE_length 7 51 #define GEN6_3DPRIMITIVE_length 6 52 #define GEN5_3DPRIMITIVE_length 6 53 #define GEN45_3DPRIMITIVE_length 6 54 #define GEN4_3DPRIMITIVE_length 6 55 56 static inline uint32_t ATTRIBUTE_PURE 57 _3DPRIMITIVE_length(const struct gen_device_info *devinfo) 58 { 59 switch (devinfo->gen) { 60 case 10: return 7; 61 case 9: return 7; 62 case 8: return 7; 63 case 7: 64 if (devinfo->is_haswell) { 65 return 7; 66 } else { 67 return 7; 68 } 69 case 6: return 6; 70 case 5: return 6; 71 case 4: 72 if (devinfo->is_g4x) { 73 return 6; 74 } else { 75 return 6; 76 } 77 default: 78 unreachable("Invalid hardware generation"); 79 } 80 } 81 82 83 84 /* 3DPRIMITIVE::3D Command Opcode */ 85 86 87 #define GEN10_3DPRIMITIVE_3DCommandOpcode_bits 3 88 #define GEN9_3DPRIMITIVE_3DCommandOpcode_bits 3 89 #define GEN8_3DPRIMITIVE_3DCommandOpcode_bits 3 90 #define GEN75_3DPRIMITIVE_3DCommandOpcode_bits 3 91 #define GEN7_3DPRIMITIVE_3DCommandOpcode_bits 3 92 #define GEN6_3DPRIMITIVE_3DCommandOpcode_bits 3 93 #define GEN5_3DPRIMITIVE_3DCommandOpcode_bits 3 94 #define GEN45_3DPRIMITIVE_3DCommandOpcode_bits 3 95 #define GEN4_3DPRIMITIVE_3DCommandOpcode_bits 3 96 97 static inline uint32_t ATTRIBUTE_PURE 98 _3DPRIMITIVE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 99 { 100 switch (devinfo->gen) { 101 case 10: return 3; 102 case 9: return 3; 103 case 8: return 3; 104 case 7: 105 if (devinfo->is_haswell) { 106 return 3; 107 } else { 108 return 3; 109 } 110 case 6: return 3; 111 case 5: return 3; 112 case 4: 113 if (devinfo->is_g4x) { 114 return 3; 115 } else { 116 return 3; 117 } 118 default: 119 unreachable("Invalid hardware generation"); 120 } 121 } 122 123 124 125 #define GEN10_3DPRIMITIVE_3DCommandOpcode_start 24 126 #define GEN9_3DPRIMITIVE_3DCommandOpcode_start 24 127 #define GEN8_3DPRIMITIVE_3DCommandOpcode_start 24 128 #define GEN75_3DPRIMITIVE_3DCommandOpcode_start 24 129 #define GEN7_3DPRIMITIVE_3DCommandOpcode_start 24 130 #define GEN6_3DPRIMITIVE_3DCommandOpcode_start 24 131 #define GEN5_3DPRIMITIVE_3DCommandOpcode_start 24 132 #define GEN45_3DPRIMITIVE_3DCommandOpcode_start 24 133 #define GEN4_3DPRIMITIVE_3DCommandOpcode_start 24 134 135 static inline uint32_t ATTRIBUTE_PURE 136 _3DPRIMITIVE_3DCommandOpcode_start(const struct gen_device_info *devinfo) 137 { 138 switch (devinfo->gen) { 139 case 10: return 24; 140 case 9: return 24; 141 case 8: return 24; 142 case 7: 143 if (devinfo->is_haswell) { 144 return 24; 145 } else { 146 return 24; 147 } 148 case 6: return 24; 149 case 5: return 24; 150 case 4: 151 if (devinfo->is_g4x) { 152 return 24; 153 } else { 154 return 24; 155 } 156 default: 157 unreachable("Invalid hardware generation"); 158 } 159 } 160 161 162 163 /* 3DPRIMITIVE::3D Command Sub Opcode */ 164 165 166 #define GEN10_3DPRIMITIVE_3DCommandSubOpcode_bits 8 167 #define GEN9_3DPRIMITIVE_3DCommandSubOpcode_bits 8 168 #define GEN8_3DPRIMITIVE_3DCommandSubOpcode_bits 8 169 #define GEN75_3DPRIMITIVE_3DCommandSubOpcode_bits 8 170 #define GEN7_3DPRIMITIVE_3DCommandSubOpcode_bits 8 171 #define GEN6_3DPRIMITIVE_3DCommandSubOpcode_bits 8 172 #define GEN5_3DPRIMITIVE_3DCommandSubOpcode_bits 8 173 #define GEN45_3DPRIMITIVE_3DCommandSubOpcode_bits 8 174 #define GEN4_3DPRIMITIVE_3DCommandSubOpcode_bits 8 175 176 static inline uint32_t ATTRIBUTE_PURE 177 _3DPRIMITIVE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 178 { 179 switch (devinfo->gen) { 180 case 10: return 8; 181 case 9: return 8; 182 case 8: return 8; 183 case 7: 184 if (devinfo->is_haswell) { 185 return 8; 186 } else { 187 return 8; 188 } 189 case 6: return 8; 190 case 5: return 8; 191 case 4: 192 if (devinfo->is_g4x) { 193 return 8; 194 } else { 195 return 8; 196 } 197 default: 198 unreachable("Invalid hardware generation"); 199 } 200 } 201 202 203 204 #define GEN10_3DPRIMITIVE_3DCommandSubOpcode_start 16 205 #define GEN9_3DPRIMITIVE_3DCommandSubOpcode_start 16 206 #define GEN8_3DPRIMITIVE_3DCommandSubOpcode_start 16 207 #define GEN75_3DPRIMITIVE_3DCommandSubOpcode_start 16 208 #define GEN7_3DPRIMITIVE_3DCommandSubOpcode_start 16 209 #define GEN6_3DPRIMITIVE_3DCommandSubOpcode_start 16 210 #define GEN5_3DPRIMITIVE_3DCommandSubOpcode_start 16 211 #define GEN45_3DPRIMITIVE_3DCommandSubOpcode_start 16 212 #define GEN4_3DPRIMITIVE_3DCommandSubOpcode_start 16 213 214 static inline uint32_t ATTRIBUTE_PURE 215 _3DPRIMITIVE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 216 { 217 switch (devinfo->gen) { 218 case 10: return 16; 219 case 9: return 16; 220 case 8: return 16; 221 case 7: 222 if (devinfo->is_haswell) { 223 return 16; 224 } else { 225 return 16; 226 } 227 case 6: return 16; 228 case 5: return 16; 229 case 4: 230 if (devinfo->is_g4x) { 231 return 16; 232 } else { 233 return 16; 234 } 235 default: 236 unreachable("Invalid hardware generation"); 237 } 238 } 239 240 241 242 /* 3DPRIMITIVE::Base Vertex Location */ 243 244 245 #define GEN10_3DPRIMITIVE_BaseVertexLocation_bits 32 246 #define GEN9_3DPRIMITIVE_BaseVertexLocation_bits 32 247 #define GEN8_3DPRIMITIVE_BaseVertexLocation_bits 32 248 #define GEN75_3DPRIMITIVE_BaseVertexLocation_bits 32 249 #define GEN7_3DPRIMITIVE_BaseVertexLocation_bits 32 250 #define GEN6_3DPRIMITIVE_BaseVertexLocation_bits 32 251 #define GEN5_3DPRIMITIVE_BaseVertexLocation_bits 32 252 #define GEN45_3DPRIMITIVE_BaseVertexLocation_bits 32 253 #define GEN4_3DPRIMITIVE_BaseVertexLocation_bits 32 254 255 static inline uint32_t ATTRIBUTE_PURE 256 _3DPRIMITIVE_BaseVertexLocation_bits(const struct gen_device_info *devinfo) 257 { 258 switch (devinfo->gen) { 259 case 10: return 32; 260 case 9: return 32; 261 case 8: return 32; 262 case 7: 263 if (devinfo->is_haswell) { 264 return 32; 265 } else { 266 return 32; 267 } 268 case 6: return 32; 269 case 5: return 32; 270 case 4: 271 if (devinfo->is_g4x) { 272 return 32; 273 } else { 274 return 32; 275 } 276 default: 277 unreachable("Invalid hardware generation"); 278 } 279 } 280 281 282 283 #define GEN10_3DPRIMITIVE_BaseVertexLocation_start 192 284 #define GEN9_3DPRIMITIVE_BaseVertexLocation_start 192 285 #define GEN8_3DPRIMITIVE_BaseVertexLocation_start 192 286 #define GEN75_3DPRIMITIVE_BaseVertexLocation_start 192 287 #define GEN7_3DPRIMITIVE_BaseVertexLocation_start 192 288 #define GEN6_3DPRIMITIVE_BaseVertexLocation_start 160 289 #define GEN5_3DPRIMITIVE_BaseVertexLocation_start 160 290 #define GEN45_3DPRIMITIVE_BaseVertexLocation_start 160 291 #define GEN4_3DPRIMITIVE_BaseVertexLocation_start 160 292 293 static inline uint32_t ATTRIBUTE_PURE 294 _3DPRIMITIVE_BaseVertexLocation_start(const struct gen_device_info *devinfo) 295 { 296 switch (devinfo->gen) { 297 case 10: return 192; 298 case 9: return 192; 299 case 8: return 192; 300 case 7: 301 if (devinfo->is_haswell) { 302 return 192; 303 } else { 304 return 192; 305 } 306 case 6: return 160; 307 case 5: return 160; 308 case 4: 309 if (devinfo->is_g4x) { 310 return 160; 311 } else { 312 return 160; 313 } 314 default: 315 unreachable("Invalid hardware generation"); 316 } 317 } 318 319 320 321 /* 3DPRIMITIVE::Command SubType */ 322 323 324 #define GEN10_3DPRIMITIVE_CommandSubType_bits 2 325 #define GEN9_3DPRIMITIVE_CommandSubType_bits 2 326 #define GEN8_3DPRIMITIVE_CommandSubType_bits 2 327 #define GEN75_3DPRIMITIVE_CommandSubType_bits 2 328 #define GEN7_3DPRIMITIVE_CommandSubType_bits 2 329 #define GEN6_3DPRIMITIVE_CommandSubType_bits 2 330 #define GEN5_3DPRIMITIVE_CommandSubType_bits 2 331 #define GEN45_3DPRIMITIVE_CommandSubType_bits 2 332 #define GEN4_3DPRIMITIVE_CommandSubType_bits 2 333 334 static inline uint32_t ATTRIBUTE_PURE 335 _3DPRIMITIVE_CommandSubType_bits(const struct gen_device_info *devinfo) 336 { 337 switch (devinfo->gen) { 338 case 10: return 2; 339 case 9: return 2; 340 case 8: return 2; 341 case 7: 342 if (devinfo->is_haswell) { 343 return 2; 344 } else { 345 return 2; 346 } 347 case 6: return 2; 348 case 5: return 2; 349 case 4: 350 if (devinfo->is_g4x) { 351 return 2; 352 } else { 353 return 2; 354 } 355 default: 356 unreachable("Invalid hardware generation"); 357 } 358 } 359 360 361 362 #define GEN10_3DPRIMITIVE_CommandSubType_start 27 363 #define GEN9_3DPRIMITIVE_CommandSubType_start 27 364 #define GEN8_3DPRIMITIVE_CommandSubType_start 27 365 #define GEN75_3DPRIMITIVE_CommandSubType_start 27 366 #define GEN7_3DPRIMITIVE_CommandSubType_start 27 367 #define GEN6_3DPRIMITIVE_CommandSubType_start 27 368 #define GEN5_3DPRIMITIVE_CommandSubType_start 27 369 #define GEN45_3DPRIMITIVE_CommandSubType_start 27 370 #define GEN4_3DPRIMITIVE_CommandSubType_start 27 371 372 static inline uint32_t ATTRIBUTE_PURE 373 _3DPRIMITIVE_CommandSubType_start(const struct gen_device_info *devinfo) 374 { 375 switch (devinfo->gen) { 376 case 10: return 27; 377 case 9: return 27; 378 case 8: return 27; 379 case 7: 380 if (devinfo->is_haswell) { 381 return 27; 382 } else { 383 return 27; 384 } 385 case 6: return 27; 386 case 5: return 27; 387 case 4: 388 if (devinfo->is_g4x) { 389 return 27; 390 } else { 391 return 27; 392 } 393 default: 394 unreachable("Invalid hardware generation"); 395 } 396 } 397 398 399 400 /* 3DPRIMITIVE::Command Type */ 401 402 403 #define GEN10_3DPRIMITIVE_CommandType_bits 3 404 #define GEN9_3DPRIMITIVE_CommandType_bits 3 405 #define GEN8_3DPRIMITIVE_CommandType_bits 3 406 #define GEN75_3DPRIMITIVE_CommandType_bits 3 407 #define GEN7_3DPRIMITIVE_CommandType_bits 3 408 #define GEN6_3DPRIMITIVE_CommandType_bits 3 409 #define GEN5_3DPRIMITIVE_CommandType_bits 3 410 #define GEN45_3DPRIMITIVE_CommandType_bits 3 411 #define GEN4_3DPRIMITIVE_CommandType_bits 3 412 413 static inline uint32_t ATTRIBUTE_PURE 414 _3DPRIMITIVE_CommandType_bits(const struct gen_device_info *devinfo) 415 { 416 switch (devinfo->gen) { 417 case 10: return 3; 418 case 9: return 3; 419 case 8: return 3; 420 case 7: 421 if (devinfo->is_haswell) { 422 return 3; 423 } else { 424 return 3; 425 } 426 case 6: return 3; 427 case 5: return 3; 428 case 4: 429 if (devinfo->is_g4x) { 430 return 3; 431 } else { 432 return 3; 433 } 434 default: 435 unreachable("Invalid hardware generation"); 436 } 437 } 438 439 440 441 #define GEN10_3DPRIMITIVE_CommandType_start 29 442 #define GEN9_3DPRIMITIVE_CommandType_start 29 443 #define GEN8_3DPRIMITIVE_CommandType_start 29 444 #define GEN75_3DPRIMITIVE_CommandType_start 29 445 #define GEN7_3DPRIMITIVE_CommandType_start 29 446 #define GEN6_3DPRIMITIVE_CommandType_start 29 447 #define GEN5_3DPRIMITIVE_CommandType_start 29 448 #define GEN45_3DPRIMITIVE_CommandType_start 29 449 #define GEN4_3DPRIMITIVE_CommandType_start 29 450 451 static inline uint32_t ATTRIBUTE_PURE 452 _3DPRIMITIVE_CommandType_start(const struct gen_device_info *devinfo) 453 { 454 switch (devinfo->gen) { 455 case 10: return 29; 456 case 9: return 29; 457 case 8: return 29; 458 case 7: 459 if (devinfo->is_haswell) { 460 return 29; 461 } else { 462 return 29; 463 } 464 case 6: return 29; 465 case 5: return 29; 466 case 4: 467 if (devinfo->is_g4x) { 468 return 29; 469 } else { 470 return 29; 471 } 472 default: 473 unreachable("Invalid hardware generation"); 474 } 475 } 476 477 478 479 /* 3DPRIMITIVE::DWord Length */ 480 481 482 #define GEN10_3DPRIMITIVE_DWordLength_bits 8 483 #define GEN9_3DPRIMITIVE_DWordLength_bits 8 484 #define GEN8_3DPRIMITIVE_DWordLength_bits 8 485 #define GEN75_3DPRIMITIVE_DWordLength_bits 8 486 #define GEN7_3DPRIMITIVE_DWordLength_bits 8 487 #define GEN6_3DPRIMITIVE_DWordLength_bits 8 488 #define GEN5_3DPRIMITIVE_DWordLength_bits 8 489 #define GEN45_3DPRIMITIVE_DWordLength_bits 8 490 #define GEN4_3DPRIMITIVE_DWordLength_bits 8 491 492 static inline uint32_t ATTRIBUTE_PURE 493 _3DPRIMITIVE_DWordLength_bits(const struct gen_device_info *devinfo) 494 { 495 switch (devinfo->gen) { 496 case 10: return 8; 497 case 9: return 8; 498 case 8: return 8; 499 case 7: 500 if (devinfo->is_haswell) { 501 return 8; 502 } else { 503 return 8; 504 } 505 case 6: return 8; 506 case 5: return 8; 507 case 4: 508 if (devinfo->is_g4x) { 509 return 8; 510 } else { 511 return 8; 512 } 513 default: 514 unreachable("Invalid hardware generation"); 515 } 516 } 517 518 519 520 #define GEN10_3DPRIMITIVE_DWordLength_start 0 521 #define GEN9_3DPRIMITIVE_DWordLength_start 0 522 #define GEN8_3DPRIMITIVE_DWordLength_start 0 523 #define GEN75_3DPRIMITIVE_DWordLength_start 0 524 #define GEN7_3DPRIMITIVE_DWordLength_start 0 525 #define GEN6_3DPRIMITIVE_DWordLength_start 0 526 #define GEN5_3DPRIMITIVE_DWordLength_start 0 527 #define GEN45_3DPRIMITIVE_DWordLength_start 0 528 #define GEN4_3DPRIMITIVE_DWordLength_start 0 529 530 static inline uint32_t ATTRIBUTE_PURE 531 _3DPRIMITIVE_DWordLength_start(const struct gen_device_info *devinfo) 532 { 533 switch (devinfo->gen) { 534 case 10: return 0; 535 case 9: return 0; 536 case 8: return 0; 537 case 7: 538 if (devinfo->is_haswell) { 539 return 0; 540 } else { 541 return 0; 542 } 543 case 6: return 0; 544 case 5: return 0; 545 case 4: 546 if (devinfo->is_g4x) { 547 return 0; 548 } else { 549 return 0; 550 } 551 default: 552 unreachable("Invalid hardware generation"); 553 } 554 } 555 556 557 558 /* 3DPRIMITIVE::End Offset Enable */ 559 560 561 #define GEN10_3DPRIMITIVE_EndOffsetEnable_bits 1 562 #define GEN9_3DPRIMITIVE_EndOffsetEnable_bits 1 563 #define GEN8_3DPRIMITIVE_EndOffsetEnable_bits 1 564 #define GEN75_3DPRIMITIVE_EndOffsetEnable_bits 1 565 #define GEN7_3DPRIMITIVE_EndOffsetEnable_bits 1 566 567 static inline uint32_t ATTRIBUTE_PURE 568 _3DPRIMITIVE_EndOffsetEnable_bits(const struct gen_device_info *devinfo) 569 { 570 switch (devinfo->gen) { 571 case 10: return 1; 572 case 9: return 1; 573 case 8: return 1; 574 case 7: 575 if (devinfo->is_haswell) { 576 return 1; 577 } else { 578 return 1; 579 } 580 case 6: return 0; 581 case 5: return 0; 582 case 4: 583 if (devinfo->is_g4x) { 584 return 0; 585 } else { 586 return 0; 587 } 588 default: 589 unreachable("Invalid hardware generation"); 590 } 591 } 592 593 594 595 #define GEN10_3DPRIMITIVE_EndOffsetEnable_start 41 596 #define GEN9_3DPRIMITIVE_EndOffsetEnable_start 41 597 #define GEN8_3DPRIMITIVE_EndOffsetEnable_start 41 598 #define GEN75_3DPRIMITIVE_EndOffsetEnable_start 41 599 #define GEN7_3DPRIMITIVE_EndOffsetEnable_start 41 600 601 static inline uint32_t ATTRIBUTE_PURE 602 _3DPRIMITIVE_EndOffsetEnable_start(const struct gen_device_info *devinfo) 603 { 604 switch (devinfo->gen) { 605 case 10: return 41; 606 case 9: return 41; 607 case 8: return 41; 608 case 7: 609 if (devinfo->is_haswell) { 610 return 41; 611 } else { 612 return 41; 613 } 614 case 6: return 0; 615 case 5: return 0; 616 case 4: 617 if (devinfo->is_g4x) { 618 return 0; 619 } else { 620 return 0; 621 } 622 default: 623 unreachable("Invalid hardware generation"); 624 } 625 } 626 627 628 629 /* 3DPRIMITIVE::Extended Parameter 0 */ 630 631 632 #define GEN10_3DPRIMITIVE_ExtendedParameter0_bits 32 633 634 static inline uint32_t ATTRIBUTE_PURE 635 _3DPRIMITIVE_ExtendedParameter0_bits(const struct gen_device_info *devinfo) 636 { 637 switch (devinfo->gen) { 638 case 10: return 32; 639 case 9: return 0; 640 case 8: return 0; 641 case 7: 642 if (devinfo->is_haswell) { 643 return 0; 644 } else { 645 return 0; 646 } 647 case 6: return 0; 648 case 5: return 0; 649 case 4: 650 if (devinfo->is_g4x) { 651 return 0; 652 } else { 653 return 0; 654 } 655 default: 656 unreachable("Invalid hardware generation"); 657 } 658 } 659 660 661 662 #define GEN10_3DPRIMITIVE_ExtendedParameter0_start 224 663 664 static inline uint32_t ATTRIBUTE_PURE 665 _3DPRIMITIVE_ExtendedParameter0_start(const struct gen_device_info *devinfo) 666 { 667 switch (devinfo->gen) { 668 case 10: return 224; 669 case 9: return 0; 670 case 8: return 0; 671 case 7: 672 if (devinfo->is_haswell) { 673 return 0; 674 } else { 675 return 0; 676 } 677 case 6: return 0; 678 case 5: return 0; 679 case 4: 680 if (devinfo->is_g4x) { 681 return 0; 682 } else { 683 return 0; 684 } 685 default: 686 unreachable("Invalid hardware generation"); 687 } 688 } 689 690 691 692 /* 3DPRIMITIVE::Extended Parameter 1 */ 693 694 695 #define GEN10_3DPRIMITIVE_ExtendedParameter1_bits 32 696 697 static inline uint32_t ATTRIBUTE_PURE 698 _3DPRIMITIVE_ExtendedParameter1_bits(const struct gen_device_info *devinfo) 699 { 700 switch (devinfo->gen) { 701 case 10: return 32; 702 case 9: return 0; 703 case 8: return 0; 704 case 7: 705 if (devinfo->is_haswell) { 706 return 0; 707 } else { 708 return 0; 709 } 710 case 6: return 0; 711 case 5: return 0; 712 case 4: 713 if (devinfo->is_g4x) { 714 return 0; 715 } else { 716 return 0; 717 } 718 default: 719 unreachable("Invalid hardware generation"); 720 } 721 } 722 723 724 725 #define GEN10_3DPRIMITIVE_ExtendedParameter1_start 256 726 727 static inline uint32_t ATTRIBUTE_PURE 728 _3DPRIMITIVE_ExtendedParameter1_start(const struct gen_device_info *devinfo) 729 { 730 switch (devinfo->gen) { 731 case 10: return 256; 732 case 9: return 0; 733 case 8: return 0; 734 case 7: 735 if (devinfo->is_haswell) { 736 return 0; 737 } else { 738 return 0; 739 } 740 case 6: return 0; 741 case 5: return 0; 742 case 4: 743 if (devinfo->is_g4x) { 744 return 0; 745 } else { 746 return 0; 747 } 748 default: 749 unreachable("Invalid hardware generation"); 750 } 751 } 752 753 754 755 /* 3DPRIMITIVE::Extended Parameter 2 */ 756 757 758 #define GEN10_3DPRIMITIVE_ExtendedParameter2_bits 32 759 760 static inline uint32_t ATTRIBUTE_PURE 761 _3DPRIMITIVE_ExtendedParameter2_bits(const struct gen_device_info *devinfo) 762 { 763 switch (devinfo->gen) { 764 case 10: return 32; 765 case 9: return 0; 766 case 8: return 0; 767 case 7: 768 if (devinfo->is_haswell) { 769 return 0; 770 } else { 771 return 0; 772 } 773 case 6: return 0; 774 case 5: return 0; 775 case 4: 776 if (devinfo->is_g4x) { 777 return 0; 778 } else { 779 return 0; 780 } 781 default: 782 unreachable("Invalid hardware generation"); 783 } 784 } 785 786 787 788 #define GEN10_3DPRIMITIVE_ExtendedParameter2_start 288 789 790 static inline uint32_t ATTRIBUTE_PURE 791 _3DPRIMITIVE_ExtendedParameter2_start(const struct gen_device_info *devinfo) 792 { 793 switch (devinfo->gen) { 794 case 10: return 288; 795 case 9: return 0; 796 case 8: return 0; 797 case 7: 798 if (devinfo->is_haswell) { 799 return 0; 800 } else { 801 return 0; 802 } 803 case 6: return 0; 804 case 5: return 0; 805 case 4: 806 if (devinfo->is_g4x) { 807 return 0; 808 } else { 809 return 0; 810 } 811 default: 812 unreachable("Invalid hardware generation"); 813 } 814 } 815 816 817 818 /* 3DPRIMITIVE::Extended Parameters Present */ 819 820 821 #define GEN10_3DPRIMITIVE_ExtendedParametersPresent_bits 1 822 823 static inline uint32_t ATTRIBUTE_PURE 824 _3DPRIMITIVE_ExtendedParametersPresent_bits(const struct gen_device_info *devinfo) 825 { 826 switch (devinfo->gen) { 827 case 10: return 1; 828 case 9: return 0; 829 case 8: return 0; 830 case 7: 831 if (devinfo->is_haswell) { 832 return 0; 833 } else { 834 return 0; 835 } 836 case 6: return 0; 837 case 5: return 0; 838 case 4: 839 if (devinfo->is_g4x) { 840 return 0; 841 } else { 842 return 0; 843 } 844 default: 845 unreachable("Invalid hardware generation"); 846 } 847 } 848 849 850 851 #define GEN10_3DPRIMITIVE_ExtendedParametersPresent_start 11 852 853 static inline uint32_t ATTRIBUTE_PURE 854 _3DPRIMITIVE_ExtendedParametersPresent_start(const struct gen_device_info *devinfo) 855 { 856 switch (devinfo->gen) { 857 case 10: return 11; 858 case 9: return 0; 859 case 8: return 0; 860 case 7: 861 if (devinfo->is_haswell) { 862 return 0; 863 } else { 864 return 0; 865 } 866 case 6: return 0; 867 case 5: return 0; 868 case 4: 869 if (devinfo->is_g4x) { 870 return 0; 871 } else { 872 return 0; 873 } 874 default: 875 unreachable("Invalid hardware generation"); 876 } 877 } 878 879 880 881 /* 3DPRIMITIVE::Indirect Parameter Enable */ 882 883 884 #define GEN10_3DPRIMITIVE_IndirectParameterEnable_bits 1 885 #define GEN9_3DPRIMITIVE_IndirectParameterEnable_bits 1 886 #define GEN8_3DPRIMITIVE_IndirectParameterEnable_bits 1 887 #define GEN75_3DPRIMITIVE_IndirectParameterEnable_bits 1 888 #define GEN7_3DPRIMITIVE_IndirectParameterEnable_bits 1 889 890 static inline uint32_t ATTRIBUTE_PURE 891 _3DPRIMITIVE_IndirectParameterEnable_bits(const struct gen_device_info *devinfo) 892 { 893 switch (devinfo->gen) { 894 case 10: return 1; 895 case 9: return 1; 896 case 8: return 1; 897 case 7: 898 if (devinfo->is_haswell) { 899 return 1; 900 } else { 901 return 1; 902 } 903 case 6: return 0; 904 case 5: return 0; 905 case 4: 906 if (devinfo->is_g4x) { 907 return 0; 908 } else { 909 return 0; 910 } 911 default: 912 unreachable("Invalid hardware generation"); 913 } 914 } 915 916 917 918 #define GEN10_3DPRIMITIVE_IndirectParameterEnable_start 10 919 #define GEN9_3DPRIMITIVE_IndirectParameterEnable_start 10 920 #define GEN8_3DPRIMITIVE_IndirectParameterEnable_start 10 921 #define GEN75_3DPRIMITIVE_IndirectParameterEnable_start 10 922 #define GEN7_3DPRIMITIVE_IndirectParameterEnable_start 10 923 924 static inline uint32_t ATTRIBUTE_PURE 925 _3DPRIMITIVE_IndirectParameterEnable_start(const struct gen_device_info *devinfo) 926 { 927 switch (devinfo->gen) { 928 case 10: return 10; 929 case 9: return 10; 930 case 8: return 10; 931 case 7: 932 if (devinfo->is_haswell) { 933 return 10; 934 } else { 935 return 10; 936 } 937 case 6: return 0; 938 case 5: return 0; 939 case 4: 940 if (devinfo->is_g4x) { 941 return 0; 942 } else { 943 return 0; 944 } 945 default: 946 unreachable("Invalid hardware generation"); 947 } 948 } 949 950 951 952 /* 3DPRIMITIVE::Indirect Vertex Count */ 953 954 955 #define GEN5_3DPRIMITIVE_IndirectVertexCount_bits 1 956 #define GEN45_3DPRIMITIVE_IndirectVertexCount_bits 1 957 958 static inline uint32_t ATTRIBUTE_PURE 959 _3DPRIMITIVE_IndirectVertexCount_bits(const struct gen_device_info *devinfo) 960 { 961 switch (devinfo->gen) { 962 case 10: return 0; 963 case 9: return 0; 964 case 8: return 0; 965 case 7: 966 if (devinfo->is_haswell) { 967 return 0; 968 } else { 969 return 0; 970 } 971 case 6: return 0; 972 case 5: return 1; 973 case 4: 974 if (devinfo->is_g4x) { 975 return 1; 976 } else { 977 return 0; 978 } 979 default: 980 unreachable("Invalid hardware generation"); 981 } 982 } 983 984 985 986 #define GEN5_3DPRIMITIVE_IndirectVertexCount_start 9 987 #define GEN45_3DPRIMITIVE_IndirectVertexCount_start 9 988 989 static inline uint32_t ATTRIBUTE_PURE 990 _3DPRIMITIVE_IndirectVertexCount_start(const struct gen_device_info *devinfo) 991 { 992 switch (devinfo->gen) { 993 case 10: return 0; 994 case 9: return 0; 995 case 8: return 0; 996 case 7: 997 if (devinfo->is_haswell) { 998 return 0; 999 } else { 1000 return 0; 1001 } 1002 case 6: return 0; 1003 case 5: return 9; 1004 case 4: 1005 if (devinfo->is_g4x) { 1006 return 9; 1007 } else { 1008 return 0; 1009 } 1010 default: 1011 unreachable("Invalid hardware generation"); 1012 } 1013 } 1014 1015 1016 1017 /* 3DPRIMITIVE::Instance Count */ 1018 1019 1020 #define GEN10_3DPRIMITIVE_InstanceCount_bits 32 1021 #define GEN9_3DPRIMITIVE_InstanceCount_bits 32 1022 #define GEN8_3DPRIMITIVE_InstanceCount_bits 32 1023 #define GEN75_3DPRIMITIVE_InstanceCount_bits 32 1024 #define GEN7_3DPRIMITIVE_InstanceCount_bits 32 1025 #define GEN6_3DPRIMITIVE_InstanceCount_bits 32 1026 #define GEN5_3DPRIMITIVE_InstanceCount_bits 32 1027 #define GEN45_3DPRIMITIVE_InstanceCount_bits 32 1028 #define GEN4_3DPRIMITIVE_InstanceCount_bits 32 1029 1030 static inline uint32_t ATTRIBUTE_PURE 1031 _3DPRIMITIVE_InstanceCount_bits(const struct gen_device_info *devinfo) 1032 { 1033 switch (devinfo->gen) { 1034 case 10: return 32; 1035 case 9: return 32; 1036 case 8: return 32; 1037 case 7: 1038 if (devinfo->is_haswell) { 1039 return 32; 1040 } else { 1041 return 32; 1042 } 1043 case 6: return 32; 1044 case 5: return 32; 1045 case 4: 1046 if (devinfo->is_g4x) { 1047 return 32; 1048 } else { 1049 return 32; 1050 } 1051 default: 1052 unreachable("Invalid hardware generation"); 1053 } 1054 } 1055 1056 1057 1058 #define GEN10_3DPRIMITIVE_InstanceCount_start 128 1059 #define GEN9_3DPRIMITIVE_InstanceCount_start 128 1060 #define GEN8_3DPRIMITIVE_InstanceCount_start 128 1061 #define GEN75_3DPRIMITIVE_InstanceCount_start 128 1062 #define GEN7_3DPRIMITIVE_InstanceCount_start 128 1063 #define GEN6_3DPRIMITIVE_InstanceCount_start 96 1064 #define GEN5_3DPRIMITIVE_InstanceCount_start 96 1065 #define GEN45_3DPRIMITIVE_InstanceCount_start 96 1066 #define GEN4_3DPRIMITIVE_InstanceCount_start 96 1067 1068 static inline uint32_t ATTRIBUTE_PURE 1069 _3DPRIMITIVE_InstanceCount_start(const struct gen_device_info *devinfo) 1070 { 1071 switch (devinfo->gen) { 1072 case 10: return 128; 1073 case 9: return 128; 1074 case 8: return 128; 1075 case 7: 1076 if (devinfo->is_haswell) { 1077 return 128; 1078 } else { 1079 return 128; 1080 } 1081 case 6: return 96; 1082 case 5: return 96; 1083 case 4: 1084 if (devinfo->is_g4x) { 1085 return 96; 1086 } else { 1087 return 96; 1088 } 1089 default: 1090 unreachable("Invalid hardware generation"); 1091 } 1092 } 1093 1094 1095 1096 /* 3DPRIMITIVE::Internal Vertex Count */ 1097 1098 1099 #define GEN6_3DPRIMITIVE_InternalVertexCount_bits 1 1100 1101 static inline uint32_t ATTRIBUTE_PURE 1102 _3DPRIMITIVE_InternalVertexCount_bits(const struct gen_device_info *devinfo) 1103 { 1104 switch (devinfo->gen) { 1105 case 10: return 0; 1106 case 9: return 0; 1107 case 8: return 0; 1108 case 7: 1109 if (devinfo->is_haswell) { 1110 return 0; 1111 } else { 1112 return 0; 1113 } 1114 case 6: return 1; 1115 case 5: return 0; 1116 case 4: 1117 if (devinfo->is_g4x) { 1118 return 0; 1119 } else { 1120 return 0; 1121 } 1122 default: 1123 unreachable("Invalid hardware generation"); 1124 } 1125 } 1126 1127 1128 1129 #define GEN6_3DPRIMITIVE_InternalVertexCount_start 9 1130 1131 static inline uint32_t ATTRIBUTE_PURE 1132 _3DPRIMITIVE_InternalVertexCount_start(const struct gen_device_info *devinfo) 1133 { 1134 switch (devinfo->gen) { 1135 case 10: return 0; 1136 case 9: return 0; 1137 case 8: return 0; 1138 case 7: 1139 if (devinfo->is_haswell) { 1140 return 0; 1141 } else { 1142 return 0; 1143 } 1144 case 6: return 9; 1145 case 5: return 0; 1146 case 4: 1147 if (devinfo->is_g4x) { 1148 return 0; 1149 } else { 1150 return 0; 1151 } 1152 default: 1153 unreachable("Invalid hardware generation"); 1154 } 1155 } 1156 1157 1158 1159 /* 3DPRIMITIVE::Predicate Enable */ 1160 1161 1162 #define GEN10_3DPRIMITIVE_PredicateEnable_bits 1 1163 #define GEN9_3DPRIMITIVE_PredicateEnable_bits 1 1164 #define GEN8_3DPRIMITIVE_PredicateEnable_bits 1 1165 #define GEN75_3DPRIMITIVE_PredicateEnable_bits 1 1166 #define GEN7_3DPRIMITIVE_PredicateEnable_bits 1 1167 1168 static inline uint32_t ATTRIBUTE_PURE 1169 _3DPRIMITIVE_PredicateEnable_bits(const struct gen_device_info *devinfo) 1170 { 1171 switch (devinfo->gen) { 1172 case 10: return 1; 1173 case 9: return 1; 1174 case 8: return 1; 1175 case 7: 1176 if (devinfo->is_haswell) { 1177 return 1; 1178 } else { 1179 return 1; 1180 } 1181 case 6: return 0; 1182 case 5: return 0; 1183 case 4: 1184 if (devinfo->is_g4x) { 1185 return 0; 1186 } else { 1187 return 0; 1188 } 1189 default: 1190 unreachable("Invalid hardware generation"); 1191 } 1192 } 1193 1194 1195 1196 #define GEN10_3DPRIMITIVE_PredicateEnable_start 8 1197 #define GEN9_3DPRIMITIVE_PredicateEnable_start 8 1198 #define GEN8_3DPRIMITIVE_PredicateEnable_start 8 1199 #define GEN75_3DPRIMITIVE_PredicateEnable_start 8 1200 #define GEN7_3DPRIMITIVE_PredicateEnable_start 8 1201 1202 static inline uint32_t ATTRIBUTE_PURE 1203 _3DPRIMITIVE_PredicateEnable_start(const struct gen_device_info *devinfo) 1204 { 1205 switch (devinfo->gen) { 1206 case 10: return 8; 1207 case 9: return 8; 1208 case 8: return 8; 1209 case 7: 1210 if (devinfo->is_haswell) { 1211 return 8; 1212 } else { 1213 return 8; 1214 } 1215 case 6: return 0; 1216 case 5: return 0; 1217 case 4: 1218 if (devinfo->is_g4x) { 1219 return 0; 1220 } else { 1221 return 0; 1222 } 1223 default: 1224 unreachable("Invalid hardware generation"); 1225 } 1226 } 1227 1228 1229 1230 /* 3DPRIMITIVE::Primitive Topology Type */ 1231 1232 1233 #define GEN10_3DPRIMITIVE_PrimitiveTopologyType_bits 6 1234 #define GEN9_3DPRIMITIVE_PrimitiveTopologyType_bits 6 1235 #define GEN8_3DPRIMITIVE_PrimitiveTopologyType_bits 6 1236 #define GEN75_3DPRIMITIVE_PrimitiveTopologyType_bits 6 1237 #define GEN7_3DPRIMITIVE_PrimitiveTopologyType_bits 6 1238 #define GEN6_3DPRIMITIVE_PrimitiveTopologyType_bits 5 1239 #define GEN5_3DPRIMITIVE_PrimitiveTopologyType_bits 5 1240 #define GEN45_3DPRIMITIVE_PrimitiveTopologyType_bits 5 1241 #define GEN4_3DPRIMITIVE_PrimitiveTopologyType_bits 5 1242 1243 static inline uint32_t ATTRIBUTE_PURE 1244 _3DPRIMITIVE_PrimitiveTopologyType_bits(const struct gen_device_info *devinfo) 1245 { 1246 switch (devinfo->gen) { 1247 case 10: return 6; 1248 case 9: return 6; 1249 case 8: return 6; 1250 case 7: 1251 if (devinfo->is_haswell) { 1252 return 6; 1253 } else { 1254 return 6; 1255 } 1256 case 6: return 5; 1257 case 5: return 5; 1258 case 4: 1259 if (devinfo->is_g4x) { 1260 return 5; 1261 } else { 1262 return 5; 1263 } 1264 default: 1265 unreachable("Invalid hardware generation"); 1266 } 1267 } 1268 1269 1270 1271 #define GEN10_3DPRIMITIVE_PrimitiveTopologyType_start 32 1272 #define GEN9_3DPRIMITIVE_PrimitiveTopologyType_start 32 1273 #define GEN8_3DPRIMITIVE_PrimitiveTopologyType_start 32 1274 #define GEN75_3DPRIMITIVE_PrimitiveTopologyType_start 32 1275 #define GEN7_3DPRIMITIVE_PrimitiveTopologyType_start 32 1276 #define GEN6_3DPRIMITIVE_PrimitiveTopologyType_start 10 1277 #define GEN5_3DPRIMITIVE_PrimitiveTopologyType_start 10 1278 #define GEN45_3DPRIMITIVE_PrimitiveTopologyType_start 10 1279 #define GEN4_3DPRIMITIVE_PrimitiveTopologyType_start 10 1280 1281 static inline uint32_t ATTRIBUTE_PURE 1282 _3DPRIMITIVE_PrimitiveTopologyType_start(const struct gen_device_info *devinfo) 1283 { 1284 switch (devinfo->gen) { 1285 case 10: return 32; 1286 case 9: return 32; 1287 case 8: return 32; 1288 case 7: 1289 if (devinfo->is_haswell) { 1290 return 32; 1291 } else { 1292 return 32; 1293 } 1294 case 6: return 10; 1295 case 5: return 10; 1296 case 4: 1297 if (devinfo->is_g4x) { 1298 return 10; 1299 } else { 1300 return 10; 1301 } 1302 default: 1303 unreachable("Invalid hardware generation"); 1304 } 1305 } 1306 1307 1308 1309 /* 3DPRIMITIVE::Start Instance Location */ 1310 1311 1312 #define GEN10_3DPRIMITIVE_StartInstanceLocation_bits 32 1313 #define GEN9_3DPRIMITIVE_StartInstanceLocation_bits 32 1314 #define GEN8_3DPRIMITIVE_StartInstanceLocation_bits 32 1315 #define GEN75_3DPRIMITIVE_StartInstanceLocation_bits 32 1316 #define GEN7_3DPRIMITIVE_StartInstanceLocation_bits 32 1317 #define GEN6_3DPRIMITIVE_StartInstanceLocation_bits 32 1318 #define GEN5_3DPRIMITIVE_StartInstanceLocation_bits 32 1319 #define GEN45_3DPRIMITIVE_StartInstanceLocation_bits 32 1320 1321 static inline uint32_t ATTRIBUTE_PURE 1322 _3DPRIMITIVE_StartInstanceLocation_bits(const struct gen_device_info *devinfo) 1323 { 1324 switch (devinfo->gen) { 1325 case 10: return 32; 1326 case 9: return 32; 1327 case 8: return 32; 1328 case 7: 1329 if (devinfo->is_haswell) { 1330 return 32; 1331 } else { 1332 return 32; 1333 } 1334 case 6: return 32; 1335 case 5: return 32; 1336 case 4: 1337 if (devinfo->is_g4x) { 1338 return 32; 1339 } else { 1340 return 0; 1341 } 1342 default: 1343 unreachable("Invalid hardware generation"); 1344 } 1345 } 1346 1347 1348 1349 #define GEN10_3DPRIMITIVE_StartInstanceLocation_start 160 1350 #define GEN9_3DPRIMITIVE_StartInstanceLocation_start 160 1351 #define GEN8_3DPRIMITIVE_StartInstanceLocation_start 160 1352 #define GEN75_3DPRIMITIVE_StartInstanceLocation_start 160 1353 #define GEN7_3DPRIMITIVE_StartInstanceLocation_start 160 1354 #define GEN6_3DPRIMITIVE_StartInstanceLocation_start 128 1355 #define GEN5_3DPRIMITIVE_StartInstanceLocation_start 128 1356 #define GEN45_3DPRIMITIVE_StartInstanceLocation_start 128 1357 1358 static inline uint32_t ATTRIBUTE_PURE 1359 _3DPRIMITIVE_StartInstanceLocation_start(const struct gen_device_info *devinfo) 1360 { 1361 switch (devinfo->gen) { 1362 case 10: return 160; 1363 case 9: return 160; 1364 case 8: return 160; 1365 case 7: 1366 if (devinfo->is_haswell) { 1367 return 160; 1368 } else { 1369 return 160; 1370 } 1371 case 6: return 128; 1372 case 5: return 128; 1373 case 4: 1374 if (devinfo->is_g4x) { 1375 return 128; 1376 } else { 1377 return 0; 1378 } 1379 default: 1380 unreachable("Invalid hardware generation"); 1381 } 1382 } 1383 1384 1385 1386 /* 3DPRIMITIVE::Start Vertex Location */ 1387 1388 1389 #define GEN10_3DPRIMITIVE_StartVertexLocation_bits 32 1390 #define GEN9_3DPRIMITIVE_StartVertexLocation_bits 32 1391 #define GEN8_3DPRIMITIVE_StartVertexLocation_bits 32 1392 #define GEN75_3DPRIMITIVE_StartVertexLocation_bits 32 1393 #define GEN7_3DPRIMITIVE_StartVertexLocation_bits 32 1394 #define GEN6_3DPRIMITIVE_StartVertexLocation_bits 32 1395 #define GEN5_3DPRIMITIVE_StartVertexLocation_bits 32 1396 #define GEN45_3DPRIMITIVE_StartVertexLocation_bits 32 1397 #define GEN4_3DPRIMITIVE_StartVertexLocation_bits 32 1398 1399 static inline uint32_t ATTRIBUTE_PURE 1400 _3DPRIMITIVE_StartVertexLocation_bits(const struct gen_device_info *devinfo) 1401 { 1402 switch (devinfo->gen) { 1403 case 10: return 32; 1404 case 9: return 32; 1405 case 8: return 32; 1406 case 7: 1407 if (devinfo->is_haswell) { 1408 return 32; 1409 } else { 1410 return 32; 1411 } 1412 case 6: return 32; 1413 case 5: return 32; 1414 case 4: 1415 if (devinfo->is_g4x) { 1416 return 32; 1417 } else { 1418 return 32; 1419 } 1420 default: 1421 unreachable("Invalid hardware generation"); 1422 } 1423 } 1424 1425 1426 1427 #define GEN10_3DPRIMITIVE_StartVertexLocation_start 96 1428 #define GEN9_3DPRIMITIVE_StartVertexLocation_start 96 1429 #define GEN8_3DPRIMITIVE_StartVertexLocation_start 96 1430 #define GEN75_3DPRIMITIVE_StartVertexLocation_start 96 1431 #define GEN7_3DPRIMITIVE_StartVertexLocation_start 96 1432 #define GEN6_3DPRIMITIVE_StartVertexLocation_start 64 1433 #define GEN5_3DPRIMITIVE_StartVertexLocation_start 64 1434 #define GEN45_3DPRIMITIVE_StartVertexLocation_start 64 1435 #define GEN4_3DPRIMITIVE_StartVertexLocation_start 64 1436 1437 static inline uint32_t ATTRIBUTE_PURE 1438 _3DPRIMITIVE_StartVertexLocation_start(const struct gen_device_info *devinfo) 1439 { 1440 switch (devinfo->gen) { 1441 case 10: return 96; 1442 case 9: return 96; 1443 case 8: return 96; 1444 case 7: 1445 if (devinfo->is_haswell) { 1446 return 96; 1447 } else { 1448 return 96; 1449 } 1450 case 6: return 64; 1451 case 5: return 64; 1452 case 4: 1453 if (devinfo->is_g4x) { 1454 return 64; 1455 } else { 1456 return 64; 1457 } 1458 default: 1459 unreachable("Invalid hardware generation"); 1460 } 1461 } 1462 1463 1464 1465 /* 3DPRIMITIVE::UAV Coherency Required */ 1466 1467 1468 #define GEN10_3DPRIMITIVE_UAVCoherencyRequired_bits 1 1469 #define GEN9_3DPRIMITIVE_UAVCoherencyRequired_bits 1 1470 #define GEN8_3DPRIMITIVE_UAVCoherencyRequired_bits 1 1471 #define GEN75_3DPRIMITIVE_UAVCoherencyRequired_bits 1 1472 1473 static inline uint32_t ATTRIBUTE_PURE 1474 _3DPRIMITIVE_UAVCoherencyRequired_bits(const struct gen_device_info *devinfo) 1475 { 1476 switch (devinfo->gen) { 1477 case 10: return 1; 1478 case 9: return 1; 1479 case 8: return 1; 1480 case 7: 1481 if (devinfo->is_haswell) { 1482 return 1; 1483 } else { 1484 return 0; 1485 } 1486 case 6: return 0; 1487 case 5: return 0; 1488 case 4: 1489 if (devinfo->is_g4x) { 1490 return 0; 1491 } else { 1492 return 0; 1493 } 1494 default: 1495 unreachable("Invalid hardware generation"); 1496 } 1497 } 1498 1499 1500 1501 #define GEN10_3DPRIMITIVE_UAVCoherencyRequired_start 9 1502 #define GEN9_3DPRIMITIVE_UAVCoherencyRequired_start 9 1503 #define GEN8_3DPRIMITIVE_UAVCoherencyRequired_start 9 1504 #define GEN75_3DPRIMITIVE_UAVCoherencyRequired_start 9 1505 1506 static inline uint32_t ATTRIBUTE_PURE 1507 _3DPRIMITIVE_UAVCoherencyRequired_start(const struct gen_device_info *devinfo) 1508 { 1509 switch (devinfo->gen) { 1510 case 10: return 9; 1511 case 9: return 9; 1512 case 8: return 9; 1513 case 7: 1514 if (devinfo->is_haswell) { 1515 return 9; 1516 } else { 1517 return 0; 1518 } 1519 case 6: return 0; 1520 case 5: return 0; 1521 case 4: 1522 if (devinfo->is_g4x) { 1523 return 0; 1524 } else { 1525 return 0; 1526 } 1527 default: 1528 unreachable("Invalid hardware generation"); 1529 } 1530 } 1531 1532 1533 1534 /* 3DPRIMITIVE::Vertex Access Type */ 1535 1536 1537 #define GEN10_3DPRIMITIVE_VertexAccessType_bits 1 1538 #define GEN9_3DPRIMITIVE_VertexAccessType_bits 1 1539 #define GEN8_3DPRIMITIVE_VertexAccessType_bits 1 1540 #define GEN75_3DPRIMITIVE_VertexAccessType_bits 1 1541 #define GEN7_3DPRIMITIVE_VertexAccessType_bits 1 1542 #define GEN6_3DPRIMITIVE_VertexAccessType_bits 1 1543 #define GEN5_3DPRIMITIVE_VertexAccessType_bits 1 1544 #define GEN45_3DPRIMITIVE_VertexAccessType_bits 1 1545 #define GEN4_3DPRIMITIVE_VertexAccessType_bits 1 1546 1547 static inline uint32_t ATTRIBUTE_PURE 1548 _3DPRIMITIVE_VertexAccessType_bits(const struct gen_device_info *devinfo) 1549 { 1550 switch (devinfo->gen) { 1551 case 10: return 1; 1552 case 9: return 1; 1553 case 8: return 1; 1554 case 7: 1555 if (devinfo->is_haswell) { 1556 return 1; 1557 } else { 1558 return 1; 1559 } 1560 case 6: return 1; 1561 case 5: return 1; 1562 case 4: 1563 if (devinfo->is_g4x) { 1564 return 1; 1565 } else { 1566 return 1; 1567 } 1568 default: 1569 unreachable("Invalid hardware generation"); 1570 } 1571 } 1572 1573 1574 1575 #define GEN10_3DPRIMITIVE_VertexAccessType_start 40 1576 #define GEN9_3DPRIMITIVE_VertexAccessType_start 40 1577 #define GEN8_3DPRIMITIVE_VertexAccessType_start 40 1578 #define GEN75_3DPRIMITIVE_VertexAccessType_start 40 1579 #define GEN7_3DPRIMITIVE_VertexAccessType_start 40 1580 #define GEN6_3DPRIMITIVE_VertexAccessType_start 15 1581 #define GEN5_3DPRIMITIVE_VertexAccessType_start 15 1582 #define GEN45_3DPRIMITIVE_VertexAccessType_start 15 1583 #define GEN4_3DPRIMITIVE_VertexAccessType_start 15 1584 1585 static inline uint32_t ATTRIBUTE_PURE 1586 _3DPRIMITIVE_VertexAccessType_start(const struct gen_device_info *devinfo) 1587 { 1588 switch (devinfo->gen) { 1589 case 10: return 40; 1590 case 9: return 40; 1591 case 8: return 40; 1592 case 7: 1593 if (devinfo->is_haswell) { 1594 return 40; 1595 } else { 1596 return 40; 1597 } 1598 case 6: return 15; 1599 case 5: return 15; 1600 case 4: 1601 if (devinfo->is_g4x) { 1602 return 15; 1603 } else { 1604 return 15; 1605 } 1606 default: 1607 unreachable("Invalid hardware generation"); 1608 } 1609 } 1610 1611 1612 1613 /* 3DPRIMITIVE::Vertex Count Per Instance */ 1614 1615 1616 #define GEN10_3DPRIMITIVE_VertexCountPerInstance_bits 32 1617 #define GEN9_3DPRIMITIVE_VertexCountPerInstance_bits 32 1618 #define GEN8_3DPRIMITIVE_VertexCountPerInstance_bits 32 1619 #define GEN75_3DPRIMITIVE_VertexCountPerInstance_bits 32 1620 #define GEN7_3DPRIMITIVE_VertexCountPerInstance_bits 32 1621 #define GEN6_3DPRIMITIVE_VertexCountPerInstance_bits 32 1622 #define GEN5_3DPRIMITIVE_VertexCountPerInstance_bits 32 1623 #define GEN45_3DPRIMITIVE_VertexCountPerInstance_bits 32 1624 #define GEN4_3DPRIMITIVE_VertexCountPerInstance_bits 32 1625 1626 static inline uint32_t ATTRIBUTE_PURE 1627 _3DPRIMITIVE_VertexCountPerInstance_bits(const struct gen_device_info *devinfo) 1628 { 1629 switch (devinfo->gen) { 1630 case 10: return 32; 1631 case 9: return 32; 1632 case 8: return 32; 1633 case 7: 1634 if (devinfo->is_haswell) { 1635 return 32; 1636 } else { 1637 return 32; 1638 } 1639 case 6: return 32; 1640 case 5: return 32; 1641 case 4: 1642 if (devinfo->is_g4x) { 1643 return 32; 1644 } else { 1645 return 32; 1646 } 1647 default: 1648 unreachable("Invalid hardware generation"); 1649 } 1650 } 1651 1652 1653 1654 #define GEN10_3DPRIMITIVE_VertexCountPerInstance_start 64 1655 #define GEN9_3DPRIMITIVE_VertexCountPerInstance_start 64 1656 #define GEN8_3DPRIMITIVE_VertexCountPerInstance_start 64 1657 #define GEN75_3DPRIMITIVE_VertexCountPerInstance_start 64 1658 #define GEN7_3DPRIMITIVE_VertexCountPerInstance_start 64 1659 #define GEN6_3DPRIMITIVE_VertexCountPerInstance_start 32 1660 #define GEN5_3DPRIMITIVE_VertexCountPerInstance_start 32 1661 #define GEN45_3DPRIMITIVE_VertexCountPerInstance_start 32 1662 #define GEN4_3DPRIMITIVE_VertexCountPerInstance_start 32 1663 1664 static inline uint32_t ATTRIBUTE_PURE 1665 _3DPRIMITIVE_VertexCountPerInstance_start(const struct gen_device_info *devinfo) 1666 { 1667 switch (devinfo->gen) { 1668 case 10: return 64; 1669 case 9: return 64; 1670 case 8: return 64; 1671 case 7: 1672 if (devinfo->is_haswell) { 1673 return 64; 1674 } else { 1675 return 64; 1676 } 1677 case 6: return 32; 1678 case 5: return 32; 1679 case 4: 1680 if (devinfo->is_g4x) { 1681 return 32; 1682 } else { 1683 return 32; 1684 } 1685 default: 1686 unreachable("Invalid hardware generation"); 1687 } 1688 } 1689 1690 1691 1692 /* 3DSTATE_AA_LINE_PARAMETERS */ 1693 1694 1695 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_length 3 1696 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_length 3 1697 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_length 3 1698 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_length 3 1699 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_length 3 1700 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_length 3 1701 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_length 3 1702 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_length 3 1703 1704 static inline uint32_t ATTRIBUTE_PURE 1705 _3DSTATE_AA_LINE_PARAMETERS_length(const struct gen_device_info *devinfo) 1706 { 1707 switch (devinfo->gen) { 1708 case 10: return 3; 1709 case 9: return 3; 1710 case 8: return 3; 1711 case 7: 1712 if (devinfo->is_haswell) { 1713 return 3; 1714 } else { 1715 return 3; 1716 } 1717 case 6: return 3; 1718 case 5: return 3; 1719 case 4: 1720 if (devinfo->is_g4x) { 1721 return 3; 1722 } else { 1723 return 0; 1724 } 1725 default: 1726 unreachable("Invalid hardware generation"); 1727 } 1728 } 1729 1730 1731 1732 /* 3DSTATE_AA_LINE_PARAMETERS::3D Command Opcode */ 1733 1734 1735 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1736 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1737 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1738 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1739 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1740 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1741 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1742 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 1743 1744 static inline uint32_t ATTRIBUTE_PURE 1745 _3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 1746 { 1747 switch (devinfo->gen) { 1748 case 10: return 3; 1749 case 9: return 3; 1750 case 8: return 3; 1751 case 7: 1752 if (devinfo->is_haswell) { 1753 return 3; 1754 } else { 1755 return 3; 1756 } 1757 case 6: return 3; 1758 case 5: return 3; 1759 case 4: 1760 if (devinfo->is_g4x) { 1761 return 3; 1762 } else { 1763 return 0; 1764 } 1765 default: 1766 unreachable("Invalid hardware generation"); 1767 } 1768 } 1769 1770 1771 1772 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1773 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1774 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1775 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1776 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1777 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1778 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1779 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 1780 1781 static inline uint32_t ATTRIBUTE_PURE 1782 _3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 1783 { 1784 switch (devinfo->gen) { 1785 case 10: return 24; 1786 case 9: return 24; 1787 case 8: return 24; 1788 case 7: 1789 if (devinfo->is_haswell) { 1790 return 24; 1791 } else { 1792 return 24; 1793 } 1794 case 6: return 24; 1795 case 5: return 24; 1796 case 4: 1797 if (devinfo->is_g4x) { 1798 return 24; 1799 } else { 1800 return 0; 1801 } 1802 default: 1803 unreachable("Invalid hardware generation"); 1804 } 1805 } 1806 1807 1808 1809 /* 3DSTATE_AA_LINE_PARAMETERS::3D Command Sub Opcode */ 1810 1811 1812 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1813 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1814 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1815 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1816 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1817 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1818 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1819 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 1820 1821 static inline uint32_t ATTRIBUTE_PURE 1822 _3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 1823 { 1824 switch (devinfo->gen) { 1825 case 10: return 8; 1826 case 9: return 8; 1827 case 8: return 8; 1828 case 7: 1829 if (devinfo->is_haswell) { 1830 return 8; 1831 } else { 1832 return 8; 1833 } 1834 case 6: return 8; 1835 case 5: return 8; 1836 case 4: 1837 if (devinfo->is_g4x) { 1838 return 8; 1839 } else { 1840 return 0; 1841 } 1842 default: 1843 unreachable("Invalid hardware generation"); 1844 } 1845 } 1846 1847 1848 1849 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1850 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1851 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1852 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1853 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1854 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1855 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1856 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 1857 1858 static inline uint32_t ATTRIBUTE_PURE 1859 _3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 1860 { 1861 switch (devinfo->gen) { 1862 case 10: return 16; 1863 case 9: return 16; 1864 case 8: return 16; 1865 case 7: 1866 if (devinfo->is_haswell) { 1867 return 16; 1868 } else { 1869 return 16; 1870 } 1871 case 6: return 16; 1872 case 5: return 16; 1873 case 4: 1874 if (devinfo->is_g4x) { 1875 return 16; 1876 } else { 1877 return 0; 1878 } 1879 default: 1880 unreachable("Invalid hardware generation"); 1881 } 1882 } 1883 1884 1885 1886 /* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage Bias */ 1887 1888 1889 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1890 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1891 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1892 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1893 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1894 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1895 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1896 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 1897 1898 static inline uint32_t ATTRIBUTE_PURE 1899 _3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits(const struct gen_device_info *devinfo) 1900 { 1901 switch (devinfo->gen) { 1902 case 10: return 8; 1903 case 9: return 8; 1904 case 8: return 8; 1905 case 7: 1906 if (devinfo->is_haswell) { 1907 return 8; 1908 } else { 1909 return 8; 1910 } 1911 case 6: return 8; 1912 case 5: return 8; 1913 case 4: 1914 if (devinfo->is_g4x) { 1915 return 8; 1916 } else { 1917 return 0; 1918 } 1919 default: 1920 unreachable("Invalid hardware generation"); 1921 } 1922 } 1923 1924 1925 1926 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1927 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1928 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1929 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1930 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1931 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1932 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1933 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 1934 1935 static inline uint32_t ATTRIBUTE_PURE 1936 _3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start(const struct gen_device_info *devinfo) 1937 { 1938 switch (devinfo->gen) { 1939 case 10: return 48; 1940 case 9: return 48; 1941 case 8: return 48; 1942 case 7: 1943 if (devinfo->is_haswell) { 1944 return 48; 1945 } else { 1946 return 48; 1947 } 1948 case 6: return 48; 1949 case 5: return 48; 1950 case 4: 1951 if (devinfo->is_g4x) { 1952 return 48; 1953 } else { 1954 return 0; 1955 } 1956 default: 1957 unreachable("Invalid hardware generation"); 1958 } 1959 } 1960 1961 1962 1963 /* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage EndCap Bias */ 1964 1965 1966 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1967 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1968 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1969 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1970 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1971 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1972 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1973 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 1974 1975 static inline uint32_t ATTRIBUTE_PURE 1976 _3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits(const struct gen_device_info *devinfo) 1977 { 1978 switch (devinfo->gen) { 1979 case 10: return 8; 1980 case 9: return 8; 1981 case 8: return 8; 1982 case 7: 1983 if (devinfo->is_haswell) { 1984 return 8; 1985 } else { 1986 return 8; 1987 } 1988 case 6: return 8; 1989 case 5: return 8; 1990 case 4: 1991 if (devinfo->is_g4x) { 1992 return 8; 1993 } else { 1994 return 0; 1995 } 1996 default: 1997 unreachable("Invalid hardware generation"); 1998 } 1999 } 2000 2001 2002 2003 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2004 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2005 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2006 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2007 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2008 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2009 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2010 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 2011 2012 static inline uint32_t ATTRIBUTE_PURE 2013 _3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start(const struct gen_device_info *devinfo) 2014 { 2015 switch (devinfo->gen) { 2016 case 10: return 80; 2017 case 9: return 80; 2018 case 8: return 80; 2019 case 7: 2020 if (devinfo->is_haswell) { 2021 return 80; 2022 } else { 2023 return 80; 2024 } 2025 case 6: return 80; 2026 case 5: return 80; 2027 case 4: 2028 if (devinfo->is_g4x) { 2029 return 80; 2030 } else { 2031 return 0; 2032 } 2033 default: 2034 unreachable("Invalid hardware generation"); 2035 } 2036 } 2037 2038 2039 2040 /* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage EndCap Slope */ 2041 2042 2043 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2044 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2045 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2046 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2047 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2048 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2049 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2050 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 2051 2052 static inline uint32_t ATTRIBUTE_PURE 2053 _3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits(const struct gen_device_info *devinfo) 2054 { 2055 switch (devinfo->gen) { 2056 case 10: return 8; 2057 case 9: return 8; 2058 case 8: return 8; 2059 case 7: 2060 if (devinfo->is_haswell) { 2061 return 8; 2062 } else { 2063 return 8; 2064 } 2065 case 6: return 8; 2066 case 5: return 8; 2067 case 4: 2068 if (devinfo->is_g4x) { 2069 return 8; 2070 } else { 2071 return 0; 2072 } 2073 default: 2074 unreachable("Invalid hardware generation"); 2075 } 2076 } 2077 2078 2079 2080 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2081 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2082 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2083 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2084 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2085 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2086 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2087 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 2088 2089 static inline uint32_t ATTRIBUTE_PURE 2090 _3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start(const struct gen_device_info *devinfo) 2091 { 2092 switch (devinfo->gen) { 2093 case 10: return 64; 2094 case 9: return 64; 2095 case 8: return 64; 2096 case 7: 2097 if (devinfo->is_haswell) { 2098 return 64; 2099 } else { 2100 return 64; 2101 } 2102 case 6: return 64; 2103 case 5: return 64; 2104 case 4: 2105 if (devinfo->is_g4x) { 2106 return 64; 2107 } else { 2108 return 0; 2109 } 2110 default: 2111 unreachable("Invalid hardware generation"); 2112 } 2113 } 2114 2115 2116 2117 /* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage Slope */ 2118 2119 2120 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2121 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2122 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2123 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2124 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2125 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2126 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2127 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 2128 2129 static inline uint32_t ATTRIBUTE_PURE 2130 _3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits(const struct gen_device_info *devinfo) 2131 { 2132 switch (devinfo->gen) { 2133 case 10: return 8; 2134 case 9: return 8; 2135 case 8: return 8; 2136 case 7: 2137 if (devinfo->is_haswell) { 2138 return 8; 2139 } else { 2140 return 8; 2141 } 2142 case 6: return 8; 2143 case 5: return 8; 2144 case 4: 2145 if (devinfo->is_g4x) { 2146 return 8; 2147 } else { 2148 return 0; 2149 } 2150 default: 2151 unreachable("Invalid hardware generation"); 2152 } 2153 } 2154 2155 2156 2157 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2158 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2159 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2160 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2161 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2162 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2163 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2164 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 2165 2166 static inline uint32_t ATTRIBUTE_PURE 2167 _3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start(const struct gen_device_info *devinfo) 2168 { 2169 switch (devinfo->gen) { 2170 case 10: return 32; 2171 case 9: return 32; 2172 case 8: return 32; 2173 case 7: 2174 if (devinfo->is_haswell) { 2175 return 32; 2176 } else { 2177 return 32; 2178 } 2179 case 6: return 32; 2180 case 5: return 32; 2181 case 4: 2182 if (devinfo->is_g4x) { 2183 return 32; 2184 } else { 2185 return 0; 2186 } 2187 default: 2188 unreachable("Invalid hardware generation"); 2189 } 2190 } 2191 2192 2193 2194 /* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage Bias */ 2195 2196 2197 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 2198 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 2199 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 2200 2201 static inline uint32_t ATTRIBUTE_PURE 2202 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits(const struct gen_device_info *devinfo) 2203 { 2204 switch (devinfo->gen) { 2205 case 10: return 8; 2206 case 9: return 8; 2207 case 8: return 8; 2208 case 7: 2209 if (devinfo->is_haswell) { 2210 return 0; 2211 } else { 2212 return 0; 2213 } 2214 case 6: return 0; 2215 case 5: return 0; 2216 case 4: 2217 if (devinfo->is_g4x) { 2218 return 0; 2219 } else { 2220 return 0; 2221 } 2222 default: 2223 unreachable("Invalid hardware generation"); 2224 } 2225 } 2226 2227 2228 2229 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 2230 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 2231 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 2232 2233 static inline uint32_t ATTRIBUTE_PURE 2234 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start(const struct gen_device_info *devinfo) 2235 { 2236 switch (devinfo->gen) { 2237 case 10: return 56; 2238 case 9: return 56; 2239 case 8: return 56; 2240 case 7: 2241 if (devinfo->is_haswell) { 2242 return 0; 2243 } else { 2244 return 0; 2245 } 2246 case 6: return 0; 2247 case 5: return 0; 2248 case 4: 2249 if (devinfo->is_g4x) { 2250 return 0; 2251 } else { 2252 return 0; 2253 } 2254 default: 2255 unreachable("Invalid hardware generation"); 2256 } 2257 } 2258 2259 2260 2261 /* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage EndCap Bias */ 2262 2263 2264 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 2265 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 2266 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 2267 2268 static inline uint32_t ATTRIBUTE_PURE 2269 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits(const struct gen_device_info *devinfo) 2270 { 2271 switch (devinfo->gen) { 2272 case 10: return 8; 2273 case 9: return 8; 2274 case 8: return 8; 2275 case 7: 2276 if (devinfo->is_haswell) { 2277 return 0; 2278 } else { 2279 return 0; 2280 } 2281 case 6: return 0; 2282 case 5: return 0; 2283 case 4: 2284 if (devinfo->is_g4x) { 2285 return 0; 2286 } else { 2287 return 0; 2288 } 2289 default: 2290 unreachable("Invalid hardware generation"); 2291 } 2292 } 2293 2294 2295 2296 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 2297 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 2298 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 2299 2300 static inline uint32_t ATTRIBUTE_PURE 2301 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start(const struct gen_device_info *devinfo) 2302 { 2303 switch (devinfo->gen) { 2304 case 10: return 88; 2305 case 9: return 88; 2306 case 8: return 88; 2307 case 7: 2308 if (devinfo->is_haswell) { 2309 return 0; 2310 } else { 2311 return 0; 2312 } 2313 case 6: return 0; 2314 case 5: return 0; 2315 case 4: 2316 if (devinfo->is_g4x) { 2317 return 0; 2318 } else { 2319 return 0; 2320 } 2321 default: 2322 unreachable("Invalid hardware generation"); 2323 } 2324 } 2325 2326 2327 2328 /* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage EndCap Slope */ 2329 2330 2331 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 2332 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 2333 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 2334 2335 static inline uint32_t ATTRIBUTE_PURE 2336 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits(const struct gen_device_info *devinfo) 2337 { 2338 switch (devinfo->gen) { 2339 case 10: return 8; 2340 case 9: return 8; 2341 case 8: return 8; 2342 case 7: 2343 if (devinfo->is_haswell) { 2344 return 0; 2345 } else { 2346 return 0; 2347 } 2348 case 6: return 0; 2349 case 5: return 0; 2350 case 4: 2351 if (devinfo->is_g4x) { 2352 return 0; 2353 } else { 2354 return 0; 2355 } 2356 default: 2357 unreachable("Invalid hardware generation"); 2358 } 2359 } 2360 2361 2362 2363 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 2364 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 2365 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 2366 2367 static inline uint32_t ATTRIBUTE_PURE 2368 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start(const struct gen_device_info *devinfo) 2369 { 2370 switch (devinfo->gen) { 2371 case 10: return 72; 2372 case 9: return 72; 2373 case 8: return 72; 2374 case 7: 2375 if (devinfo->is_haswell) { 2376 return 0; 2377 } else { 2378 return 0; 2379 } 2380 case 6: return 0; 2381 case 5: return 0; 2382 case 4: 2383 if (devinfo->is_g4x) { 2384 return 0; 2385 } else { 2386 return 0; 2387 } 2388 default: 2389 unreachable("Invalid hardware generation"); 2390 } 2391 } 2392 2393 2394 2395 /* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage Slope */ 2396 2397 2398 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 2399 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 2400 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 2401 2402 static inline uint32_t ATTRIBUTE_PURE 2403 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits(const struct gen_device_info *devinfo) 2404 { 2405 switch (devinfo->gen) { 2406 case 10: return 8; 2407 case 9: return 8; 2408 case 8: return 8; 2409 case 7: 2410 if (devinfo->is_haswell) { 2411 return 0; 2412 } else { 2413 return 0; 2414 } 2415 case 6: return 0; 2416 case 5: return 0; 2417 case 4: 2418 if (devinfo->is_g4x) { 2419 return 0; 2420 } else { 2421 return 0; 2422 } 2423 default: 2424 unreachable("Invalid hardware generation"); 2425 } 2426 } 2427 2428 2429 2430 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 2431 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 2432 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 2433 2434 static inline uint32_t ATTRIBUTE_PURE 2435 _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start(const struct gen_device_info *devinfo) 2436 { 2437 switch (devinfo->gen) { 2438 case 10: return 40; 2439 case 9: return 40; 2440 case 8: return 40; 2441 case 7: 2442 if (devinfo->is_haswell) { 2443 return 0; 2444 } else { 2445 return 0; 2446 } 2447 case 6: return 0; 2448 case 5: return 0; 2449 case 4: 2450 if (devinfo->is_g4x) { 2451 return 0; 2452 } else { 2453 return 0; 2454 } 2455 default: 2456 unreachable("Invalid hardware generation"); 2457 } 2458 } 2459 2460 2461 2462 /* 3DSTATE_AA_LINE_PARAMETERS::Command SubType */ 2463 2464 2465 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2466 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2467 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2468 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2469 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2470 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2471 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2472 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 2473 2474 static inline uint32_t ATTRIBUTE_PURE 2475 _3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits(const struct gen_device_info *devinfo) 2476 { 2477 switch (devinfo->gen) { 2478 case 10: return 2; 2479 case 9: return 2; 2480 case 8: return 2; 2481 case 7: 2482 if (devinfo->is_haswell) { 2483 return 2; 2484 } else { 2485 return 2; 2486 } 2487 case 6: return 2; 2488 case 5: return 2; 2489 case 4: 2490 if (devinfo->is_g4x) { 2491 return 2; 2492 } else { 2493 return 0; 2494 } 2495 default: 2496 unreachable("Invalid hardware generation"); 2497 } 2498 } 2499 2500 2501 2502 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2503 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2504 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2505 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2506 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2507 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2508 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2509 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 2510 2511 static inline uint32_t ATTRIBUTE_PURE 2512 _3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start(const struct gen_device_info *devinfo) 2513 { 2514 switch (devinfo->gen) { 2515 case 10: return 27; 2516 case 9: return 27; 2517 case 8: return 27; 2518 case 7: 2519 if (devinfo->is_haswell) { 2520 return 27; 2521 } else { 2522 return 27; 2523 } 2524 case 6: return 27; 2525 case 5: return 27; 2526 case 4: 2527 if (devinfo->is_g4x) { 2528 return 27; 2529 } else { 2530 return 0; 2531 } 2532 default: 2533 unreachable("Invalid hardware generation"); 2534 } 2535 } 2536 2537 2538 2539 /* 3DSTATE_AA_LINE_PARAMETERS::Command Type */ 2540 2541 2542 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2543 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2544 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2545 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2546 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2547 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2548 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2549 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 2550 2551 static inline uint32_t ATTRIBUTE_PURE 2552 _3DSTATE_AA_LINE_PARAMETERS_CommandType_bits(const struct gen_device_info *devinfo) 2553 { 2554 switch (devinfo->gen) { 2555 case 10: return 3; 2556 case 9: return 3; 2557 case 8: return 3; 2558 case 7: 2559 if (devinfo->is_haswell) { 2560 return 3; 2561 } else { 2562 return 3; 2563 } 2564 case 6: return 3; 2565 case 5: return 3; 2566 case 4: 2567 if (devinfo->is_g4x) { 2568 return 3; 2569 } else { 2570 return 0; 2571 } 2572 default: 2573 unreachable("Invalid hardware generation"); 2574 } 2575 } 2576 2577 2578 2579 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2580 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2581 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2582 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2583 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2584 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2585 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2586 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 2587 2588 static inline uint32_t ATTRIBUTE_PURE 2589 _3DSTATE_AA_LINE_PARAMETERS_CommandType_start(const struct gen_device_info *devinfo) 2590 { 2591 switch (devinfo->gen) { 2592 case 10: return 29; 2593 case 9: return 29; 2594 case 8: return 29; 2595 case 7: 2596 if (devinfo->is_haswell) { 2597 return 29; 2598 } else { 2599 return 29; 2600 } 2601 case 6: return 29; 2602 case 5: return 29; 2603 case 4: 2604 if (devinfo->is_g4x) { 2605 return 29; 2606 } else { 2607 return 0; 2608 } 2609 default: 2610 unreachable("Invalid hardware generation"); 2611 } 2612 } 2613 2614 2615 2616 /* 3DSTATE_AA_LINE_PARAMETERS::DWord Length */ 2617 2618 2619 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2620 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2621 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2622 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2623 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2624 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2625 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2626 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 2627 2628 static inline uint32_t ATTRIBUTE_PURE 2629 _3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits(const struct gen_device_info *devinfo) 2630 { 2631 switch (devinfo->gen) { 2632 case 10: return 8; 2633 case 9: return 8; 2634 case 8: return 8; 2635 case 7: 2636 if (devinfo->is_haswell) { 2637 return 8; 2638 } else { 2639 return 8; 2640 } 2641 case 6: return 8; 2642 case 5: return 8; 2643 case 4: 2644 if (devinfo->is_g4x) { 2645 return 8; 2646 } else { 2647 return 0; 2648 } 2649 default: 2650 unreachable("Invalid hardware generation"); 2651 } 2652 } 2653 2654 2655 2656 #define GEN10_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2657 #define GEN9_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2658 #define GEN8_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2659 #define GEN75_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2660 #define GEN7_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2661 #define GEN6_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2662 #define GEN5_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2663 #define GEN45_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 2664 2665 static inline uint32_t ATTRIBUTE_PURE 2666 _3DSTATE_AA_LINE_PARAMETERS_DWordLength_start(const struct gen_device_info *devinfo) 2667 { 2668 switch (devinfo->gen) { 2669 case 10: return 0; 2670 case 9: return 0; 2671 case 8: return 0; 2672 case 7: 2673 if (devinfo->is_haswell) { 2674 return 0; 2675 } else { 2676 return 0; 2677 } 2678 case 6: return 0; 2679 case 5: return 0; 2680 case 4: 2681 if (devinfo->is_g4x) { 2682 return 0; 2683 } else { 2684 return 0; 2685 } 2686 default: 2687 unreachable("Invalid hardware generation"); 2688 } 2689 } 2690 2691 2692 2693 /* 3DSTATE_BINDING_TABLE_EDIT_DS */ 2694 2695 2696 2697 2698 2699 /* 3DSTATE_BINDING_TABLE_EDIT_DS::3D Command Opcode */ 2700 2701 2702 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 2703 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 2704 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 2705 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 2706 2707 static inline uint32_t ATTRIBUTE_PURE 2708 _3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 2709 { 2710 switch (devinfo->gen) { 2711 case 10: return 3; 2712 case 9: return 3; 2713 case 8: return 3; 2714 case 7: 2715 if (devinfo->is_haswell) { 2716 return 3; 2717 } else { 2718 return 0; 2719 } 2720 case 6: return 0; 2721 case 5: return 0; 2722 case 4: 2723 if (devinfo->is_g4x) { 2724 return 0; 2725 } else { 2726 return 0; 2727 } 2728 default: 2729 unreachable("Invalid hardware generation"); 2730 } 2731 } 2732 2733 2734 2735 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 2736 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 2737 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 2738 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 2739 2740 static inline uint32_t ATTRIBUTE_PURE 2741 _3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 2742 { 2743 switch (devinfo->gen) { 2744 case 10: return 24; 2745 case 9: return 24; 2746 case 8: return 24; 2747 case 7: 2748 if (devinfo->is_haswell) { 2749 return 24; 2750 } else { 2751 return 0; 2752 } 2753 case 6: return 0; 2754 case 5: return 0; 2755 case 4: 2756 if (devinfo->is_g4x) { 2757 return 0; 2758 } else { 2759 return 0; 2760 } 2761 default: 2762 unreachable("Invalid hardware generation"); 2763 } 2764 } 2765 2766 2767 2768 /* 3DSTATE_BINDING_TABLE_EDIT_DS::3D Command Sub Opcode */ 2769 2770 2771 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 2772 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 2773 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 2774 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 2775 2776 static inline uint32_t ATTRIBUTE_PURE 2777 _3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 2778 { 2779 switch (devinfo->gen) { 2780 case 10: return 8; 2781 case 9: return 8; 2782 case 8: return 8; 2783 case 7: 2784 if (devinfo->is_haswell) { 2785 return 8; 2786 } else { 2787 return 0; 2788 } 2789 case 6: return 0; 2790 case 5: return 0; 2791 case 4: 2792 if (devinfo->is_g4x) { 2793 return 0; 2794 } else { 2795 return 0; 2796 } 2797 default: 2798 unreachable("Invalid hardware generation"); 2799 } 2800 } 2801 2802 2803 2804 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 2805 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 2806 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 2807 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 2808 2809 static inline uint32_t ATTRIBUTE_PURE 2810 _3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 2811 { 2812 switch (devinfo->gen) { 2813 case 10: return 16; 2814 case 9: return 16; 2815 case 8: return 16; 2816 case 7: 2817 if (devinfo->is_haswell) { 2818 return 16; 2819 } else { 2820 return 0; 2821 } 2822 case 6: return 0; 2823 case 5: return 0; 2824 case 4: 2825 if (devinfo->is_g4x) { 2826 return 0; 2827 } else { 2828 return 0; 2829 } 2830 default: 2831 unreachable("Invalid hardware generation"); 2832 } 2833 } 2834 2835 2836 2837 /* 3DSTATE_BINDING_TABLE_EDIT_DS::Binding Table Block Clear */ 2838 2839 2840 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 2841 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 2842 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 2843 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 2844 2845 static inline uint32_t ATTRIBUTE_PURE 2846 _3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) 2847 { 2848 switch (devinfo->gen) { 2849 case 10: return 16; 2850 case 9: return 16; 2851 case 8: return 16; 2852 case 7: 2853 if (devinfo->is_haswell) { 2854 return 16; 2855 } else { 2856 return 0; 2857 } 2858 case 6: return 0; 2859 case 5: return 0; 2860 case 4: 2861 if (devinfo->is_g4x) { 2862 return 0; 2863 } else { 2864 return 0; 2865 } 2866 default: 2867 unreachable("Invalid hardware generation"); 2868 } 2869 } 2870 2871 2872 2873 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 2874 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 2875 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 2876 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 2877 2878 static inline uint32_t ATTRIBUTE_PURE 2879 _3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) 2880 { 2881 switch (devinfo->gen) { 2882 case 10: return 48; 2883 case 9: return 48; 2884 case 8: return 48; 2885 case 7: 2886 if (devinfo->is_haswell) { 2887 return 48; 2888 } else { 2889 return 0; 2890 } 2891 case 6: return 0; 2892 case 5: return 0; 2893 case 4: 2894 if (devinfo->is_g4x) { 2895 return 0; 2896 } else { 2897 return 0; 2898 } 2899 default: 2900 unreachable("Invalid hardware generation"); 2901 } 2902 } 2903 2904 2905 2906 /* 3DSTATE_BINDING_TABLE_EDIT_DS::Binding Table Edit Target */ 2907 2908 2909 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 2910 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 2911 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 2912 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 2913 2914 static inline uint32_t ATTRIBUTE_PURE 2915 _3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) 2916 { 2917 switch (devinfo->gen) { 2918 case 10: return 2; 2919 case 9: return 2; 2920 case 8: return 2; 2921 case 7: 2922 if (devinfo->is_haswell) { 2923 return 2; 2924 } else { 2925 return 0; 2926 } 2927 case 6: return 0; 2928 case 5: return 0; 2929 case 4: 2930 if (devinfo->is_g4x) { 2931 return 0; 2932 } else { 2933 return 0; 2934 } 2935 default: 2936 unreachable("Invalid hardware generation"); 2937 } 2938 } 2939 2940 2941 2942 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 2943 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 2944 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 2945 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 2946 2947 static inline uint32_t ATTRIBUTE_PURE 2948 _3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) 2949 { 2950 switch (devinfo->gen) { 2951 case 10: return 32; 2952 case 9: return 32; 2953 case 8: return 32; 2954 case 7: 2955 if (devinfo->is_haswell) { 2956 return 32; 2957 } else { 2958 return 0; 2959 } 2960 case 6: return 0; 2961 case 5: return 0; 2962 case 4: 2963 if (devinfo->is_g4x) { 2964 return 0; 2965 } else { 2966 return 0; 2967 } 2968 default: 2969 unreachable("Invalid hardware generation"); 2970 } 2971 } 2972 2973 2974 2975 /* 3DSTATE_BINDING_TABLE_EDIT_DS::Command SubType */ 2976 2977 2978 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 2979 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 2980 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 2981 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 2982 2983 static inline uint32_t ATTRIBUTE_PURE 2984 _3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits(const struct gen_device_info *devinfo) 2985 { 2986 switch (devinfo->gen) { 2987 case 10: return 2; 2988 case 9: return 2; 2989 case 8: return 2; 2990 case 7: 2991 if (devinfo->is_haswell) { 2992 return 2; 2993 } else { 2994 return 0; 2995 } 2996 case 6: return 0; 2997 case 5: return 0; 2998 case 4: 2999 if (devinfo->is_g4x) { 3000 return 0; 3001 } else { 3002 return 0; 3003 } 3004 default: 3005 unreachable("Invalid hardware generation"); 3006 } 3007 } 3008 3009 3010 3011 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 3012 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 3013 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 3014 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 3015 3016 static inline uint32_t ATTRIBUTE_PURE 3017 _3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start(const struct gen_device_info *devinfo) 3018 { 3019 switch (devinfo->gen) { 3020 case 10: return 27; 3021 case 9: return 27; 3022 case 8: return 27; 3023 case 7: 3024 if (devinfo->is_haswell) { 3025 return 27; 3026 } else { 3027 return 0; 3028 } 3029 case 6: return 0; 3030 case 5: return 0; 3031 case 4: 3032 if (devinfo->is_g4x) { 3033 return 0; 3034 } else { 3035 return 0; 3036 } 3037 default: 3038 unreachable("Invalid hardware generation"); 3039 } 3040 } 3041 3042 3043 3044 /* 3DSTATE_BINDING_TABLE_EDIT_DS::Command Type */ 3045 3046 3047 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 3048 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 3049 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 3050 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 3051 3052 static inline uint32_t ATTRIBUTE_PURE 3053 _3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits(const struct gen_device_info *devinfo) 3054 { 3055 switch (devinfo->gen) { 3056 case 10: return 3; 3057 case 9: return 3; 3058 case 8: return 3; 3059 case 7: 3060 if (devinfo->is_haswell) { 3061 return 3; 3062 } else { 3063 return 0; 3064 } 3065 case 6: return 0; 3066 case 5: return 0; 3067 case 4: 3068 if (devinfo->is_g4x) { 3069 return 0; 3070 } else { 3071 return 0; 3072 } 3073 default: 3074 unreachable("Invalid hardware generation"); 3075 } 3076 } 3077 3078 3079 3080 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 3081 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 3082 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 3083 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 3084 3085 static inline uint32_t ATTRIBUTE_PURE 3086 _3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start(const struct gen_device_info *devinfo) 3087 { 3088 switch (devinfo->gen) { 3089 case 10: return 29; 3090 case 9: return 29; 3091 case 8: return 29; 3092 case 7: 3093 if (devinfo->is_haswell) { 3094 return 29; 3095 } else { 3096 return 0; 3097 } 3098 case 6: return 0; 3099 case 5: return 0; 3100 case 4: 3101 if (devinfo->is_g4x) { 3102 return 0; 3103 } else { 3104 return 0; 3105 } 3106 default: 3107 unreachable("Invalid hardware generation"); 3108 } 3109 } 3110 3111 3112 3113 /* 3DSTATE_BINDING_TABLE_EDIT_DS::DWord Length */ 3114 3115 3116 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 3117 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 3118 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 3119 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 3120 3121 static inline uint32_t ATTRIBUTE_PURE 3122 _3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits(const struct gen_device_info *devinfo) 3123 { 3124 switch (devinfo->gen) { 3125 case 10: return 9; 3126 case 9: return 9; 3127 case 8: return 9; 3128 case 7: 3129 if (devinfo->is_haswell) { 3130 return 9; 3131 } else { 3132 return 0; 3133 } 3134 case 6: return 0; 3135 case 5: return 0; 3136 case 4: 3137 if (devinfo->is_g4x) { 3138 return 0; 3139 } else { 3140 return 0; 3141 } 3142 default: 3143 unreachable("Invalid hardware generation"); 3144 } 3145 } 3146 3147 3148 3149 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 3150 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 3151 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 3152 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 3153 3154 static inline uint32_t ATTRIBUTE_PURE 3155 _3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start(const struct gen_device_info *devinfo) 3156 { 3157 switch (devinfo->gen) { 3158 case 10: return 0; 3159 case 9: return 0; 3160 case 8: return 0; 3161 case 7: 3162 if (devinfo->is_haswell) { 3163 return 0; 3164 } else { 3165 return 0; 3166 } 3167 case 6: return 0; 3168 case 5: return 0; 3169 case 4: 3170 if (devinfo->is_g4x) { 3171 return 0; 3172 } else { 3173 return 0; 3174 } 3175 default: 3176 unreachable("Invalid hardware generation"); 3177 } 3178 } 3179 3180 3181 3182 /* 3DSTATE_BINDING_TABLE_EDIT_DS::Entry [n] */ 3183 3184 3185 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 3186 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 3187 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 3188 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 3189 3190 static inline uint32_t ATTRIBUTE_PURE 3191 _3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits(const struct gen_device_info *devinfo) 3192 { 3193 switch (devinfo->gen) { 3194 case 10: return 32; 3195 case 9: return 32; 3196 case 8: return 32; 3197 case 7: 3198 if (devinfo->is_haswell) { 3199 return 32; 3200 } else { 3201 return 0; 3202 } 3203 case 6: return 0; 3204 case 5: return 0; 3205 case 4: 3206 if (devinfo->is_g4x) { 3207 return 0; 3208 } else { 3209 return 0; 3210 } 3211 default: 3212 unreachable("Invalid hardware generation"); 3213 } 3214 } 3215 3216 3217 3218 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 3219 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 3220 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 3221 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 3222 3223 static inline uint32_t ATTRIBUTE_PURE 3224 _3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start(const struct gen_device_info *devinfo) 3225 { 3226 switch (devinfo->gen) { 3227 case 10: return 0; 3228 case 9: return 0; 3229 case 8: return 0; 3230 case 7: 3231 if (devinfo->is_haswell) { 3232 return 0; 3233 } else { 3234 return 0; 3235 } 3236 case 6: return 0; 3237 case 5: return 0; 3238 case 4: 3239 if (devinfo->is_g4x) { 3240 return 0; 3241 } else { 3242 return 0; 3243 } 3244 default: 3245 unreachable("Invalid hardware generation"); 3246 } 3247 } 3248 3249 3250 3251 /* 3DSTATE_BINDING_TABLE_EDIT_GS */ 3252 3253 3254 3255 3256 3257 /* 3DSTATE_BINDING_TABLE_EDIT_GS::3D Command Opcode */ 3258 3259 3260 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 3261 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 3262 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 3263 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 3264 3265 static inline uint32_t ATTRIBUTE_PURE 3266 _3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 3267 { 3268 switch (devinfo->gen) { 3269 case 10: return 3; 3270 case 9: return 3; 3271 case 8: return 3; 3272 case 7: 3273 if (devinfo->is_haswell) { 3274 return 3; 3275 } else { 3276 return 0; 3277 } 3278 case 6: return 0; 3279 case 5: return 0; 3280 case 4: 3281 if (devinfo->is_g4x) { 3282 return 0; 3283 } else { 3284 return 0; 3285 } 3286 default: 3287 unreachable("Invalid hardware generation"); 3288 } 3289 } 3290 3291 3292 3293 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 3294 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 3295 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 3296 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 3297 3298 static inline uint32_t ATTRIBUTE_PURE 3299 _3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 3300 { 3301 switch (devinfo->gen) { 3302 case 10: return 24; 3303 case 9: return 24; 3304 case 8: return 24; 3305 case 7: 3306 if (devinfo->is_haswell) { 3307 return 24; 3308 } else { 3309 return 0; 3310 } 3311 case 6: return 0; 3312 case 5: return 0; 3313 case 4: 3314 if (devinfo->is_g4x) { 3315 return 0; 3316 } else { 3317 return 0; 3318 } 3319 default: 3320 unreachable("Invalid hardware generation"); 3321 } 3322 } 3323 3324 3325 3326 /* 3DSTATE_BINDING_TABLE_EDIT_GS::3D Command Sub Opcode */ 3327 3328 3329 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 3330 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 3331 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 3332 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 3333 3334 static inline uint32_t ATTRIBUTE_PURE 3335 _3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 3336 { 3337 switch (devinfo->gen) { 3338 case 10: return 8; 3339 case 9: return 8; 3340 case 8: return 8; 3341 case 7: 3342 if (devinfo->is_haswell) { 3343 return 8; 3344 } else { 3345 return 0; 3346 } 3347 case 6: return 0; 3348 case 5: return 0; 3349 case 4: 3350 if (devinfo->is_g4x) { 3351 return 0; 3352 } else { 3353 return 0; 3354 } 3355 default: 3356 unreachable("Invalid hardware generation"); 3357 } 3358 } 3359 3360 3361 3362 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 3363 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 3364 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 3365 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 3366 3367 static inline uint32_t ATTRIBUTE_PURE 3368 _3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 3369 { 3370 switch (devinfo->gen) { 3371 case 10: return 16; 3372 case 9: return 16; 3373 case 8: return 16; 3374 case 7: 3375 if (devinfo->is_haswell) { 3376 return 16; 3377 } else { 3378 return 0; 3379 } 3380 case 6: return 0; 3381 case 5: return 0; 3382 case 4: 3383 if (devinfo->is_g4x) { 3384 return 0; 3385 } else { 3386 return 0; 3387 } 3388 default: 3389 unreachable("Invalid hardware generation"); 3390 } 3391 } 3392 3393 3394 3395 /* 3DSTATE_BINDING_TABLE_EDIT_GS::Binding Table Block Clear */ 3396 3397 3398 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 3399 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 3400 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 3401 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 3402 3403 static inline uint32_t ATTRIBUTE_PURE 3404 _3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) 3405 { 3406 switch (devinfo->gen) { 3407 case 10: return 16; 3408 case 9: return 16; 3409 case 8: return 16; 3410 case 7: 3411 if (devinfo->is_haswell) { 3412 return 16; 3413 } else { 3414 return 0; 3415 } 3416 case 6: return 0; 3417 case 5: return 0; 3418 case 4: 3419 if (devinfo->is_g4x) { 3420 return 0; 3421 } else { 3422 return 0; 3423 } 3424 default: 3425 unreachable("Invalid hardware generation"); 3426 } 3427 } 3428 3429 3430 3431 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 3432 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 3433 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 3434 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 3435 3436 static inline uint32_t ATTRIBUTE_PURE 3437 _3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) 3438 { 3439 switch (devinfo->gen) { 3440 case 10: return 48; 3441 case 9: return 48; 3442 case 8: return 48; 3443 case 7: 3444 if (devinfo->is_haswell) { 3445 return 48; 3446 } else { 3447 return 0; 3448 } 3449 case 6: return 0; 3450 case 5: return 0; 3451 case 4: 3452 if (devinfo->is_g4x) { 3453 return 0; 3454 } else { 3455 return 0; 3456 } 3457 default: 3458 unreachable("Invalid hardware generation"); 3459 } 3460 } 3461 3462 3463 3464 /* 3DSTATE_BINDING_TABLE_EDIT_GS::Binding Table Edit Target */ 3465 3466 3467 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 3468 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 3469 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 3470 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 3471 3472 static inline uint32_t ATTRIBUTE_PURE 3473 _3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) 3474 { 3475 switch (devinfo->gen) { 3476 case 10: return 2; 3477 case 9: return 2; 3478 case 8: return 2; 3479 case 7: 3480 if (devinfo->is_haswell) { 3481 return 2; 3482 } else { 3483 return 0; 3484 } 3485 case 6: return 0; 3486 case 5: return 0; 3487 case 4: 3488 if (devinfo->is_g4x) { 3489 return 0; 3490 } else { 3491 return 0; 3492 } 3493 default: 3494 unreachable("Invalid hardware generation"); 3495 } 3496 } 3497 3498 3499 3500 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 3501 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 3502 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 3503 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 3504 3505 static inline uint32_t ATTRIBUTE_PURE 3506 _3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) 3507 { 3508 switch (devinfo->gen) { 3509 case 10: return 32; 3510 case 9: return 32; 3511 case 8: return 32; 3512 case 7: 3513 if (devinfo->is_haswell) { 3514 return 32; 3515 } else { 3516 return 0; 3517 } 3518 case 6: return 0; 3519 case 5: return 0; 3520 case 4: 3521 if (devinfo->is_g4x) { 3522 return 0; 3523 } else { 3524 return 0; 3525 } 3526 default: 3527 unreachable("Invalid hardware generation"); 3528 } 3529 } 3530 3531 3532 3533 /* 3DSTATE_BINDING_TABLE_EDIT_GS::Command SubType */ 3534 3535 3536 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 3537 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 3538 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 3539 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 3540 3541 static inline uint32_t ATTRIBUTE_PURE 3542 _3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits(const struct gen_device_info *devinfo) 3543 { 3544 switch (devinfo->gen) { 3545 case 10: return 2; 3546 case 9: return 2; 3547 case 8: return 2; 3548 case 7: 3549 if (devinfo->is_haswell) { 3550 return 2; 3551 } else { 3552 return 0; 3553 } 3554 case 6: return 0; 3555 case 5: return 0; 3556 case 4: 3557 if (devinfo->is_g4x) { 3558 return 0; 3559 } else { 3560 return 0; 3561 } 3562 default: 3563 unreachable("Invalid hardware generation"); 3564 } 3565 } 3566 3567 3568 3569 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 3570 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 3571 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 3572 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 3573 3574 static inline uint32_t ATTRIBUTE_PURE 3575 _3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start(const struct gen_device_info *devinfo) 3576 { 3577 switch (devinfo->gen) { 3578 case 10: return 27; 3579 case 9: return 27; 3580 case 8: return 27; 3581 case 7: 3582 if (devinfo->is_haswell) { 3583 return 27; 3584 } else { 3585 return 0; 3586 } 3587 case 6: return 0; 3588 case 5: return 0; 3589 case 4: 3590 if (devinfo->is_g4x) { 3591 return 0; 3592 } else { 3593 return 0; 3594 } 3595 default: 3596 unreachable("Invalid hardware generation"); 3597 } 3598 } 3599 3600 3601 3602 /* 3DSTATE_BINDING_TABLE_EDIT_GS::Command Type */ 3603 3604 3605 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 3606 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 3607 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 3608 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 3609 3610 static inline uint32_t ATTRIBUTE_PURE 3611 _3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits(const struct gen_device_info *devinfo) 3612 { 3613 switch (devinfo->gen) { 3614 case 10: return 3; 3615 case 9: return 3; 3616 case 8: return 3; 3617 case 7: 3618 if (devinfo->is_haswell) { 3619 return 3; 3620 } else { 3621 return 0; 3622 } 3623 case 6: return 0; 3624 case 5: return 0; 3625 case 4: 3626 if (devinfo->is_g4x) { 3627 return 0; 3628 } else { 3629 return 0; 3630 } 3631 default: 3632 unreachable("Invalid hardware generation"); 3633 } 3634 } 3635 3636 3637 3638 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 3639 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 3640 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 3641 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 3642 3643 static inline uint32_t ATTRIBUTE_PURE 3644 _3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start(const struct gen_device_info *devinfo) 3645 { 3646 switch (devinfo->gen) { 3647 case 10: return 29; 3648 case 9: return 29; 3649 case 8: return 29; 3650 case 7: 3651 if (devinfo->is_haswell) { 3652 return 29; 3653 } else { 3654 return 0; 3655 } 3656 case 6: return 0; 3657 case 5: return 0; 3658 case 4: 3659 if (devinfo->is_g4x) { 3660 return 0; 3661 } else { 3662 return 0; 3663 } 3664 default: 3665 unreachable("Invalid hardware generation"); 3666 } 3667 } 3668 3669 3670 3671 /* 3DSTATE_BINDING_TABLE_EDIT_GS::DWord Length */ 3672 3673 3674 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 3675 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 3676 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 3677 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 3678 3679 static inline uint32_t ATTRIBUTE_PURE 3680 _3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits(const struct gen_device_info *devinfo) 3681 { 3682 switch (devinfo->gen) { 3683 case 10: return 9; 3684 case 9: return 9; 3685 case 8: return 9; 3686 case 7: 3687 if (devinfo->is_haswell) { 3688 return 9; 3689 } else { 3690 return 0; 3691 } 3692 case 6: return 0; 3693 case 5: return 0; 3694 case 4: 3695 if (devinfo->is_g4x) { 3696 return 0; 3697 } else { 3698 return 0; 3699 } 3700 default: 3701 unreachable("Invalid hardware generation"); 3702 } 3703 } 3704 3705 3706 3707 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 3708 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 3709 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 3710 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 3711 3712 static inline uint32_t ATTRIBUTE_PURE 3713 _3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start(const struct gen_device_info *devinfo) 3714 { 3715 switch (devinfo->gen) { 3716 case 10: return 0; 3717 case 9: return 0; 3718 case 8: return 0; 3719 case 7: 3720 if (devinfo->is_haswell) { 3721 return 0; 3722 } else { 3723 return 0; 3724 } 3725 case 6: return 0; 3726 case 5: return 0; 3727 case 4: 3728 if (devinfo->is_g4x) { 3729 return 0; 3730 } else { 3731 return 0; 3732 } 3733 default: 3734 unreachable("Invalid hardware generation"); 3735 } 3736 } 3737 3738 3739 3740 /* 3DSTATE_BINDING_TABLE_EDIT_GS::Entry [n] */ 3741 3742 3743 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 3744 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 3745 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 3746 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 3747 3748 static inline uint32_t ATTRIBUTE_PURE 3749 _3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits(const struct gen_device_info *devinfo) 3750 { 3751 switch (devinfo->gen) { 3752 case 10: return 32; 3753 case 9: return 32; 3754 case 8: return 32; 3755 case 7: 3756 if (devinfo->is_haswell) { 3757 return 32; 3758 } else { 3759 return 0; 3760 } 3761 case 6: return 0; 3762 case 5: return 0; 3763 case 4: 3764 if (devinfo->is_g4x) { 3765 return 0; 3766 } else { 3767 return 0; 3768 } 3769 default: 3770 unreachable("Invalid hardware generation"); 3771 } 3772 } 3773 3774 3775 3776 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 3777 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 3778 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 3779 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 3780 3781 static inline uint32_t ATTRIBUTE_PURE 3782 _3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start(const struct gen_device_info *devinfo) 3783 { 3784 switch (devinfo->gen) { 3785 case 10: return 0; 3786 case 9: return 0; 3787 case 8: return 0; 3788 case 7: 3789 if (devinfo->is_haswell) { 3790 return 0; 3791 } else { 3792 return 0; 3793 } 3794 case 6: return 0; 3795 case 5: return 0; 3796 case 4: 3797 if (devinfo->is_g4x) { 3798 return 0; 3799 } else { 3800 return 0; 3801 } 3802 default: 3803 unreachable("Invalid hardware generation"); 3804 } 3805 } 3806 3807 3808 3809 /* 3DSTATE_BINDING_TABLE_EDIT_HS */ 3810 3811 3812 3813 3814 3815 /* 3DSTATE_BINDING_TABLE_EDIT_HS::3D Command Opcode */ 3816 3817 3818 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 3819 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 3820 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 3821 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 3822 3823 static inline uint32_t ATTRIBUTE_PURE 3824 _3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 3825 { 3826 switch (devinfo->gen) { 3827 case 10: return 3; 3828 case 9: return 3; 3829 case 8: return 3; 3830 case 7: 3831 if (devinfo->is_haswell) { 3832 return 3; 3833 } else { 3834 return 0; 3835 } 3836 case 6: return 0; 3837 case 5: return 0; 3838 case 4: 3839 if (devinfo->is_g4x) { 3840 return 0; 3841 } else { 3842 return 0; 3843 } 3844 default: 3845 unreachable("Invalid hardware generation"); 3846 } 3847 } 3848 3849 3850 3851 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 3852 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 3853 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 3854 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 3855 3856 static inline uint32_t ATTRIBUTE_PURE 3857 _3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 3858 { 3859 switch (devinfo->gen) { 3860 case 10: return 24; 3861 case 9: return 24; 3862 case 8: return 24; 3863 case 7: 3864 if (devinfo->is_haswell) { 3865 return 24; 3866 } else { 3867 return 0; 3868 } 3869 case 6: return 0; 3870 case 5: return 0; 3871 case 4: 3872 if (devinfo->is_g4x) { 3873 return 0; 3874 } else { 3875 return 0; 3876 } 3877 default: 3878 unreachable("Invalid hardware generation"); 3879 } 3880 } 3881 3882 3883 3884 /* 3DSTATE_BINDING_TABLE_EDIT_HS::3D Command Sub Opcode */ 3885 3886 3887 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 3888 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 3889 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 3890 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 3891 3892 static inline uint32_t ATTRIBUTE_PURE 3893 _3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 3894 { 3895 switch (devinfo->gen) { 3896 case 10: return 8; 3897 case 9: return 8; 3898 case 8: return 8; 3899 case 7: 3900 if (devinfo->is_haswell) { 3901 return 8; 3902 } else { 3903 return 0; 3904 } 3905 case 6: return 0; 3906 case 5: return 0; 3907 case 4: 3908 if (devinfo->is_g4x) { 3909 return 0; 3910 } else { 3911 return 0; 3912 } 3913 default: 3914 unreachable("Invalid hardware generation"); 3915 } 3916 } 3917 3918 3919 3920 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 3921 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 3922 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 3923 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 3924 3925 static inline uint32_t ATTRIBUTE_PURE 3926 _3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 3927 { 3928 switch (devinfo->gen) { 3929 case 10: return 16; 3930 case 9: return 16; 3931 case 8: return 16; 3932 case 7: 3933 if (devinfo->is_haswell) { 3934 return 16; 3935 } else { 3936 return 0; 3937 } 3938 case 6: return 0; 3939 case 5: return 0; 3940 case 4: 3941 if (devinfo->is_g4x) { 3942 return 0; 3943 } else { 3944 return 0; 3945 } 3946 default: 3947 unreachable("Invalid hardware generation"); 3948 } 3949 } 3950 3951 3952 3953 /* 3DSTATE_BINDING_TABLE_EDIT_HS::Binding Table Block Clear */ 3954 3955 3956 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 3957 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 3958 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 3959 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 3960 3961 static inline uint32_t ATTRIBUTE_PURE 3962 _3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) 3963 { 3964 switch (devinfo->gen) { 3965 case 10: return 16; 3966 case 9: return 16; 3967 case 8: return 16; 3968 case 7: 3969 if (devinfo->is_haswell) { 3970 return 16; 3971 } else { 3972 return 0; 3973 } 3974 case 6: return 0; 3975 case 5: return 0; 3976 case 4: 3977 if (devinfo->is_g4x) { 3978 return 0; 3979 } else { 3980 return 0; 3981 } 3982 default: 3983 unreachable("Invalid hardware generation"); 3984 } 3985 } 3986 3987 3988 3989 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 3990 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 3991 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 3992 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 3993 3994 static inline uint32_t ATTRIBUTE_PURE 3995 _3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) 3996 { 3997 switch (devinfo->gen) { 3998 case 10: return 48; 3999 case 9: return 48; 4000 case 8: return 48; 4001 case 7: 4002 if (devinfo->is_haswell) { 4003 return 48; 4004 } else { 4005 return 0; 4006 } 4007 case 6: return 0; 4008 case 5: return 0; 4009 case 4: 4010 if (devinfo->is_g4x) { 4011 return 0; 4012 } else { 4013 return 0; 4014 } 4015 default: 4016 unreachable("Invalid hardware generation"); 4017 } 4018 } 4019 4020 4021 4022 /* 3DSTATE_BINDING_TABLE_EDIT_HS::Binding Table Edit Target */ 4023 4024 4025 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 4026 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 4027 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 4028 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 4029 4030 static inline uint32_t ATTRIBUTE_PURE 4031 _3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) 4032 { 4033 switch (devinfo->gen) { 4034 case 10: return 2; 4035 case 9: return 2; 4036 case 8: return 2; 4037 case 7: 4038 if (devinfo->is_haswell) { 4039 return 2; 4040 } else { 4041 return 0; 4042 } 4043 case 6: return 0; 4044 case 5: return 0; 4045 case 4: 4046 if (devinfo->is_g4x) { 4047 return 0; 4048 } else { 4049 return 0; 4050 } 4051 default: 4052 unreachable("Invalid hardware generation"); 4053 } 4054 } 4055 4056 4057 4058 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 4059 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 4060 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 4061 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 4062 4063 static inline uint32_t ATTRIBUTE_PURE 4064 _3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) 4065 { 4066 switch (devinfo->gen) { 4067 case 10: return 32; 4068 case 9: return 32; 4069 case 8: return 32; 4070 case 7: 4071 if (devinfo->is_haswell) { 4072 return 32; 4073 } else { 4074 return 0; 4075 } 4076 case 6: return 0; 4077 case 5: return 0; 4078 case 4: 4079 if (devinfo->is_g4x) { 4080 return 0; 4081 } else { 4082 return 0; 4083 } 4084 default: 4085 unreachable("Invalid hardware generation"); 4086 } 4087 } 4088 4089 4090 4091 /* 3DSTATE_BINDING_TABLE_EDIT_HS::Command SubType */ 4092 4093 4094 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 4095 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 4096 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 4097 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 4098 4099 static inline uint32_t ATTRIBUTE_PURE 4100 _3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits(const struct gen_device_info *devinfo) 4101 { 4102 switch (devinfo->gen) { 4103 case 10: return 2; 4104 case 9: return 2; 4105 case 8: return 2; 4106 case 7: 4107 if (devinfo->is_haswell) { 4108 return 2; 4109 } else { 4110 return 0; 4111 } 4112 case 6: return 0; 4113 case 5: return 0; 4114 case 4: 4115 if (devinfo->is_g4x) { 4116 return 0; 4117 } else { 4118 return 0; 4119 } 4120 default: 4121 unreachable("Invalid hardware generation"); 4122 } 4123 } 4124 4125 4126 4127 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 4128 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 4129 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 4130 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 4131 4132 static inline uint32_t ATTRIBUTE_PURE 4133 _3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start(const struct gen_device_info *devinfo) 4134 { 4135 switch (devinfo->gen) { 4136 case 10: return 27; 4137 case 9: return 27; 4138 case 8: return 27; 4139 case 7: 4140 if (devinfo->is_haswell) { 4141 return 27; 4142 } else { 4143 return 0; 4144 } 4145 case 6: return 0; 4146 case 5: return 0; 4147 case 4: 4148 if (devinfo->is_g4x) { 4149 return 0; 4150 } else { 4151 return 0; 4152 } 4153 default: 4154 unreachable("Invalid hardware generation"); 4155 } 4156 } 4157 4158 4159 4160 /* 3DSTATE_BINDING_TABLE_EDIT_HS::Command Type */ 4161 4162 4163 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 4164 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 4165 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 4166 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 4167 4168 static inline uint32_t ATTRIBUTE_PURE 4169 _3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits(const struct gen_device_info *devinfo) 4170 { 4171 switch (devinfo->gen) { 4172 case 10: return 3; 4173 case 9: return 3; 4174 case 8: return 3; 4175 case 7: 4176 if (devinfo->is_haswell) { 4177 return 3; 4178 } else { 4179 return 0; 4180 } 4181 case 6: return 0; 4182 case 5: return 0; 4183 case 4: 4184 if (devinfo->is_g4x) { 4185 return 0; 4186 } else { 4187 return 0; 4188 } 4189 default: 4190 unreachable("Invalid hardware generation"); 4191 } 4192 } 4193 4194 4195 4196 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 4197 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 4198 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 4199 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 4200 4201 static inline uint32_t ATTRIBUTE_PURE 4202 _3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start(const struct gen_device_info *devinfo) 4203 { 4204 switch (devinfo->gen) { 4205 case 10: return 29; 4206 case 9: return 29; 4207 case 8: return 29; 4208 case 7: 4209 if (devinfo->is_haswell) { 4210 return 29; 4211 } else { 4212 return 0; 4213 } 4214 case 6: return 0; 4215 case 5: return 0; 4216 case 4: 4217 if (devinfo->is_g4x) { 4218 return 0; 4219 } else { 4220 return 0; 4221 } 4222 default: 4223 unreachable("Invalid hardware generation"); 4224 } 4225 } 4226 4227 4228 4229 /* 3DSTATE_BINDING_TABLE_EDIT_HS::DWord Length */ 4230 4231 4232 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 4233 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 4234 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 4235 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 4236 4237 static inline uint32_t ATTRIBUTE_PURE 4238 _3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits(const struct gen_device_info *devinfo) 4239 { 4240 switch (devinfo->gen) { 4241 case 10: return 9; 4242 case 9: return 9; 4243 case 8: return 9; 4244 case 7: 4245 if (devinfo->is_haswell) { 4246 return 9; 4247 } else { 4248 return 0; 4249 } 4250 case 6: return 0; 4251 case 5: return 0; 4252 case 4: 4253 if (devinfo->is_g4x) { 4254 return 0; 4255 } else { 4256 return 0; 4257 } 4258 default: 4259 unreachable("Invalid hardware generation"); 4260 } 4261 } 4262 4263 4264 4265 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 4266 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 4267 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 4268 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 4269 4270 static inline uint32_t ATTRIBUTE_PURE 4271 _3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start(const struct gen_device_info *devinfo) 4272 { 4273 switch (devinfo->gen) { 4274 case 10: return 0; 4275 case 9: return 0; 4276 case 8: return 0; 4277 case 7: 4278 if (devinfo->is_haswell) { 4279 return 0; 4280 } else { 4281 return 0; 4282 } 4283 case 6: return 0; 4284 case 5: return 0; 4285 case 4: 4286 if (devinfo->is_g4x) { 4287 return 0; 4288 } else { 4289 return 0; 4290 } 4291 default: 4292 unreachable("Invalid hardware generation"); 4293 } 4294 } 4295 4296 4297 4298 /* 3DSTATE_BINDING_TABLE_EDIT_HS::Entry [n] */ 4299 4300 4301 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 4302 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 4303 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 4304 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 4305 4306 static inline uint32_t ATTRIBUTE_PURE 4307 _3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits(const struct gen_device_info *devinfo) 4308 { 4309 switch (devinfo->gen) { 4310 case 10: return 32; 4311 case 9: return 32; 4312 case 8: return 32; 4313 case 7: 4314 if (devinfo->is_haswell) { 4315 return 32; 4316 } else { 4317 return 0; 4318 } 4319 case 6: return 0; 4320 case 5: return 0; 4321 case 4: 4322 if (devinfo->is_g4x) { 4323 return 0; 4324 } else { 4325 return 0; 4326 } 4327 default: 4328 unreachable("Invalid hardware generation"); 4329 } 4330 } 4331 4332 4333 4334 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 4335 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 4336 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 4337 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 4338 4339 static inline uint32_t ATTRIBUTE_PURE 4340 _3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start(const struct gen_device_info *devinfo) 4341 { 4342 switch (devinfo->gen) { 4343 case 10: return 0; 4344 case 9: return 0; 4345 case 8: return 0; 4346 case 7: 4347 if (devinfo->is_haswell) { 4348 return 0; 4349 } else { 4350 return 0; 4351 } 4352 case 6: return 0; 4353 case 5: return 0; 4354 case 4: 4355 if (devinfo->is_g4x) { 4356 return 0; 4357 } else { 4358 return 0; 4359 } 4360 default: 4361 unreachable("Invalid hardware generation"); 4362 } 4363 } 4364 4365 4366 4367 /* 3DSTATE_BINDING_TABLE_EDIT_PS */ 4368 4369 4370 4371 4372 4373 /* 3DSTATE_BINDING_TABLE_EDIT_PS::3D Command Opcode */ 4374 4375 4376 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 4377 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 4378 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 4379 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 4380 4381 static inline uint32_t ATTRIBUTE_PURE 4382 _3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 4383 { 4384 switch (devinfo->gen) { 4385 case 10: return 3; 4386 case 9: return 3; 4387 case 8: return 3; 4388 case 7: 4389 if (devinfo->is_haswell) { 4390 return 3; 4391 } else { 4392 return 0; 4393 } 4394 case 6: return 0; 4395 case 5: return 0; 4396 case 4: 4397 if (devinfo->is_g4x) { 4398 return 0; 4399 } else { 4400 return 0; 4401 } 4402 default: 4403 unreachable("Invalid hardware generation"); 4404 } 4405 } 4406 4407 4408 4409 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 4410 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 4411 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 4412 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 4413 4414 static inline uint32_t ATTRIBUTE_PURE 4415 _3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 4416 { 4417 switch (devinfo->gen) { 4418 case 10: return 24; 4419 case 9: return 24; 4420 case 8: return 24; 4421 case 7: 4422 if (devinfo->is_haswell) { 4423 return 24; 4424 } else { 4425 return 0; 4426 } 4427 case 6: return 0; 4428 case 5: return 0; 4429 case 4: 4430 if (devinfo->is_g4x) { 4431 return 0; 4432 } else { 4433 return 0; 4434 } 4435 default: 4436 unreachable("Invalid hardware generation"); 4437 } 4438 } 4439 4440 4441 4442 /* 3DSTATE_BINDING_TABLE_EDIT_PS::3D Command Sub Opcode */ 4443 4444 4445 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 4446 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 4447 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 4448 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 4449 4450 static inline uint32_t ATTRIBUTE_PURE 4451 _3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 4452 { 4453 switch (devinfo->gen) { 4454 case 10: return 8; 4455 case 9: return 8; 4456 case 8: return 8; 4457 case 7: 4458 if (devinfo->is_haswell) { 4459 return 8; 4460 } else { 4461 return 0; 4462 } 4463 case 6: return 0; 4464 case 5: return 0; 4465 case 4: 4466 if (devinfo->is_g4x) { 4467 return 0; 4468 } else { 4469 return 0; 4470 } 4471 default: 4472 unreachable("Invalid hardware generation"); 4473 } 4474 } 4475 4476 4477 4478 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 4479 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 4480 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 4481 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 4482 4483 static inline uint32_t ATTRIBUTE_PURE 4484 _3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 4485 { 4486 switch (devinfo->gen) { 4487 case 10: return 16; 4488 case 9: return 16; 4489 case 8: return 16; 4490 case 7: 4491 if (devinfo->is_haswell) { 4492 return 16; 4493 } else { 4494 return 0; 4495 } 4496 case 6: return 0; 4497 case 5: return 0; 4498 case 4: 4499 if (devinfo->is_g4x) { 4500 return 0; 4501 } else { 4502 return 0; 4503 } 4504 default: 4505 unreachable("Invalid hardware generation"); 4506 } 4507 } 4508 4509 4510 4511 /* 3DSTATE_BINDING_TABLE_EDIT_PS::Binding Table Block Clear */ 4512 4513 4514 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 4515 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 4516 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 4517 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 4518 4519 static inline uint32_t ATTRIBUTE_PURE 4520 _3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) 4521 { 4522 switch (devinfo->gen) { 4523 case 10: return 16; 4524 case 9: return 16; 4525 case 8: return 16; 4526 case 7: 4527 if (devinfo->is_haswell) { 4528 return 16; 4529 } else { 4530 return 0; 4531 } 4532 case 6: return 0; 4533 case 5: return 0; 4534 case 4: 4535 if (devinfo->is_g4x) { 4536 return 0; 4537 } else { 4538 return 0; 4539 } 4540 default: 4541 unreachable("Invalid hardware generation"); 4542 } 4543 } 4544 4545 4546 4547 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 4548 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 4549 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 4550 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 4551 4552 static inline uint32_t ATTRIBUTE_PURE 4553 _3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) 4554 { 4555 switch (devinfo->gen) { 4556 case 10: return 48; 4557 case 9: return 48; 4558 case 8: return 48; 4559 case 7: 4560 if (devinfo->is_haswell) { 4561 return 48; 4562 } else { 4563 return 0; 4564 } 4565 case 6: return 0; 4566 case 5: return 0; 4567 case 4: 4568 if (devinfo->is_g4x) { 4569 return 0; 4570 } else { 4571 return 0; 4572 } 4573 default: 4574 unreachable("Invalid hardware generation"); 4575 } 4576 } 4577 4578 4579 4580 /* 3DSTATE_BINDING_TABLE_EDIT_PS::Binding Table Edit Target */ 4581 4582 4583 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 4584 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 4585 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 4586 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 4587 4588 static inline uint32_t ATTRIBUTE_PURE 4589 _3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) 4590 { 4591 switch (devinfo->gen) { 4592 case 10: return 2; 4593 case 9: return 2; 4594 case 8: return 2; 4595 case 7: 4596 if (devinfo->is_haswell) { 4597 return 2; 4598 } else { 4599 return 0; 4600 } 4601 case 6: return 0; 4602 case 5: return 0; 4603 case 4: 4604 if (devinfo->is_g4x) { 4605 return 0; 4606 } else { 4607 return 0; 4608 } 4609 default: 4610 unreachable("Invalid hardware generation"); 4611 } 4612 } 4613 4614 4615 4616 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 4617 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 4618 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 4619 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 4620 4621 static inline uint32_t ATTRIBUTE_PURE 4622 _3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) 4623 { 4624 switch (devinfo->gen) { 4625 case 10: return 32; 4626 case 9: return 32; 4627 case 8: return 32; 4628 case 7: 4629 if (devinfo->is_haswell) { 4630 return 32; 4631 } else { 4632 return 0; 4633 } 4634 case 6: return 0; 4635 case 5: return 0; 4636 case 4: 4637 if (devinfo->is_g4x) { 4638 return 0; 4639 } else { 4640 return 0; 4641 } 4642 default: 4643 unreachable("Invalid hardware generation"); 4644 } 4645 } 4646 4647 4648 4649 /* 3DSTATE_BINDING_TABLE_EDIT_PS::Command SubType */ 4650 4651 4652 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 4653 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 4654 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 4655 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 4656 4657 static inline uint32_t ATTRIBUTE_PURE 4658 _3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits(const struct gen_device_info *devinfo) 4659 { 4660 switch (devinfo->gen) { 4661 case 10: return 2; 4662 case 9: return 2; 4663 case 8: return 2; 4664 case 7: 4665 if (devinfo->is_haswell) { 4666 return 2; 4667 } else { 4668 return 0; 4669 } 4670 case 6: return 0; 4671 case 5: return 0; 4672 case 4: 4673 if (devinfo->is_g4x) { 4674 return 0; 4675 } else { 4676 return 0; 4677 } 4678 default: 4679 unreachable("Invalid hardware generation"); 4680 } 4681 } 4682 4683 4684 4685 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 4686 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 4687 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 4688 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 4689 4690 static inline uint32_t ATTRIBUTE_PURE 4691 _3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start(const struct gen_device_info *devinfo) 4692 { 4693 switch (devinfo->gen) { 4694 case 10: return 27; 4695 case 9: return 27; 4696 case 8: return 27; 4697 case 7: 4698 if (devinfo->is_haswell) { 4699 return 27; 4700 } else { 4701 return 0; 4702 } 4703 case 6: return 0; 4704 case 5: return 0; 4705 case 4: 4706 if (devinfo->is_g4x) { 4707 return 0; 4708 } else { 4709 return 0; 4710 } 4711 default: 4712 unreachable("Invalid hardware generation"); 4713 } 4714 } 4715 4716 4717 4718 /* 3DSTATE_BINDING_TABLE_EDIT_PS::Command Type */ 4719 4720 4721 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 4722 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 4723 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 4724 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 4725 4726 static inline uint32_t ATTRIBUTE_PURE 4727 _3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits(const struct gen_device_info *devinfo) 4728 { 4729 switch (devinfo->gen) { 4730 case 10: return 3; 4731 case 9: return 3; 4732 case 8: return 3; 4733 case 7: 4734 if (devinfo->is_haswell) { 4735 return 3; 4736 } else { 4737 return 0; 4738 } 4739 case 6: return 0; 4740 case 5: return 0; 4741 case 4: 4742 if (devinfo->is_g4x) { 4743 return 0; 4744 } else { 4745 return 0; 4746 } 4747 default: 4748 unreachable("Invalid hardware generation"); 4749 } 4750 } 4751 4752 4753 4754 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 4755 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 4756 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 4757 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 4758 4759 static inline uint32_t ATTRIBUTE_PURE 4760 _3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start(const struct gen_device_info *devinfo) 4761 { 4762 switch (devinfo->gen) { 4763 case 10: return 29; 4764 case 9: return 29; 4765 case 8: return 29; 4766 case 7: 4767 if (devinfo->is_haswell) { 4768 return 29; 4769 } else { 4770 return 0; 4771 } 4772 case 6: return 0; 4773 case 5: return 0; 4774 case 4: 4775 if (devinfo->is_g4x) { 4776 return 0; 4777 } else { 4778 return 0; 4779 } 4780 default: 4781 unreachable("Invalid hardware generation"); 4782 } 4783 } 4784 4785 4786 4787 /* 3DSTATE_BINDING_TABLE_EDIT_PS::DWord Length */ 4788 4789 4790 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 4791 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 4792 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 4793 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 4794 4795 static inline uint32_t ATTRIBUTE_PURE 4796 _3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits(const struct gen_device_info *devinfo) 4797 { 4798 switch (devinfo->gen) { 4799 case 10: return 9; 4800 case 9: return 9; 4801 case 8: return 9; 4802 case 7: 4803 if (devinfo->is_haswell) { 4804 return 9; 4805 } else { 4806 return 0; 4807 } 4808 case 6: return 0; 4809 case 5: return 0; 4810 case 4: 4811 if (devinfo->is_g4x) { 4812 return 0; 4813 } else { 4814 return 0; 4815 } 4816 default: 4817 unreachable("Invalid hardware generation"); 4818 } 4819 } 4820 4821 4822 4823 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 4824 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 4825 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 4826 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 4827 4828 static inline uint32_t ATTRIBUTE_PURE 4829 _3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start(const struct gen_device_info *devinfo) 4830 { 4831 switch (devinfo->gen) { 4832 case 10: return 0; 4833 case 9: return 0; 4834 case 8: return 0; 4835 case 7: 4836 if (devinfo->is_haswell) { 4837 return 0; 4838 } else { 4839 return 0; 4840 } 4841 case 6: return 0; 4842 case 5: return 0; 4843 case 4: 4844 if (devinfo->is_g4x) { 4845 return 0; 4846 } else { 4847 return 0; 4848 } 4849 default: 4850 unreachable("Invalid hardware generation"); 4851 } 4852 } 4853 4854 4855 4856 /* 3DSTATE_BINDING_TABLE_EDIT_PS::Entry [n] */ 4857 4858 4859 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 4860 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 4861 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 4862 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 4863 4864 static inline uint32_t ATTRIBUTE_PURE 4865 _3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits(const struct gen_device_info *devinfo) 4866 { 4867 switch (devinfo->gen) { 4868 case 10: return 32; 4869 case 9: return 32; 4870 case 8: return 32; 4871 case 7: 4872 if (devinfo->is_haswell) { 4873 return 32; 4874 } else { 4875 return 0; 4876 } 4877 case 6: return 0; 4878 case 5: return 0; 4879 case 4: 4880 if (devinfo->is_g4x) { 4881 return 0; 4882 } else { 4883 return 0; 4884 } 4885 default: 4886 unreachable("Invalid hardware generation"); 4887 } 4888 } 4889 4890 4891 4892 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 4893 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 4894 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 4895 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 4896 4897 static inline uint32_t ATTRIBUTE_PURE 4898 _3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start(const struct gen_device_info *devinfo) 4899 { 4900 switch (devinfo->gen) { 4901 case 10: return 0; 4902 case 9: return 0; 4903 case 8: return 0; 4904 case 7: 4905 if (devinfo->is_haswell) { 4906 return 0; 4907 } else { 4908 return 0; 4909 } 4910 case 6: return 0; 4911 case 5: return 0; 4912 case 4: 4913 if (devinfo->is_g4x) { 4914 return 0; 4915 } else { 4916 return 0; 4917 } 4918 default: 4919 unreachable("Invalid hardware generation"); 4920 } 4921 } 4922 4923 4924 4925 /* 3DSTATE_BINDING_TABLE_EDIT_VS */ 4926 4927 4928 4929 4930 4931 /* 3DSTATE_BINDING_TABLE_EDIT_VS::3D Command Opcode */ 4932 4933 4934 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 4935 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 4936 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 4937 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 4938 4939 static inline uint32_t ATTRIBUTE_PURE 4940 _3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 4941 { 4942 switch (devinfo->gen) { 4943 case 10: return 3; 4944 case 9: return 3; 4945 case 8: return 3; 4946 case 7: 4947 if (devinfo->is_haswell) { 4948 return 3; 4949 } else { 4950 return 0; 4951 } 4952 case 6: return 0; 4953 case 5: return 0; 4954 case 4: 4955 if (devinfo->is_g4x) { 4956 return 0; 4957 } else { 4958 return 0; 4959 } 4960 default: 4961 unreachable("Invalid hardware generation"); 4962 } 4963 } 4964 4965 4966 4967 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 4968 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 4969 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 4970 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 4971 4972 static inline uint32_t ATTRIBUTE_PURE 4973 _3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 4974 { 4975 switch (devinfo->gen) { 4976 case 10: return 24; 4977 case 9: return 24; 4978 case 8: return 24; 4979 case 7: 4980 if (devinfo->is_haswell) { 4981 return 24; 4982 } else { 4983 return 0; 4984 } 4985 case 6: return 0; 4986 case 5: return 0; 4987 case 4: 4988 if (devinfo->is_g4x) { 4989 return 0; 4990 } else { 4991 return 0; 4992 } 4993 default: 4994 unreachable("Invalid hardware generation"); 4995 } 4996 } 4997 4998 4999 5000 /* 3DSTATE_BINDING_TABLE_EDIT_VS::3D Command Sub Opcode */ 5001 5002 5003 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 5004 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 5005 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 5006 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 5007 5008 static inline uint32_t ATTRIBUTE_PURE 5009 _3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 5010 { 5011 switch (devinfo->gen) { 5012 case 10: return 8; 5013 case 9: return 8; 5014 case 8: return 8; 5015 case 7: 5016 if (devinfo->is_haswell) { 5017 return 8; 5018 } else { 5019 return 0; 5020 } 5021 case 6: return 0; 5022 case 5: return 0; 5023 case 4: 5024 if (devinfo->is_g4x) { 5025 return 0; 5026 } else { 5027 return 0; 5028 } 5029 default: 5030 unreachable("Invalid hardware generation"); 5031 } 5032 } 5033 5034 5035 5036 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 5037 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 5038 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 5039 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 5040 5041 static inline uint32_t ATTRIBUTE_PURE 5042 _3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 5043 { 5044 switch (devinfo->gen) { 5045 case 10: return 16; 5046 case 9: return 16; 5047 case 8: return 16; 5048 case 7: 5049 if (devinfo->is_haswell) { 5050 return 16; 5051 } else { 5052 return 0; 5053 } 5054 case 6: return 0; 5055 case 5: return 0; 5056 case 4: 5057 if (devinfo->is_g4x) { 5058 return 0; 5059 } else { 5060 return 0; 5061 } 5062 default: 5063 unreachable("Invalid hardware generation"); 5064 } 5065 } 5066 5067 5068 5069 /* 3DSTATE_BINDING_TABLE_EDIT_VS::Binding Table Block Clear */ 5070 5071 5072 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 5073 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 5074 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 5075 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 5076 5077 static inline uint32_t ATTRIBUTE_PURE 5078 _3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) 5079 { 5080 switch (devinfo->gen) { 5081 case 10: return 16; 5082 case 9: return 16; 5083 case 8: return 16; 5084 case 7: 5085 if (devinfo->is_haswell) { 5086 return 16; 5087 } else { 5088 return 0; 5089 } 5090 case 6: return 0; 5091 case 5: return 0; 5092 case 4: 5093 if (devinfo->is_g4x) { 5094 return 0; 5095 } else { 5096 return 0; 5097 } 5098 default: 5099 unreachable("Invalid hardware generation"); 5100 } 5101 } 5102 5103 5104 5105 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 5106 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 5107 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 5108 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 5109 5110 static inline uint32_t ATTRIBUTE_PURE 5111 _3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) 5112 { 5113 switch (devinfo->gen) { 5114 case 10: return 48; 5115 case 9: return 48; 5116 case 8: return 48; 5117 case 7: 5118 if (devinfo->is_haswell) { 5119 return 48; 5120 } else { 5121 return 0; 5122 } 5123 case 6: return 0; 5124 case 5: return 0; 5125 case 4: 5126 if (devinfo->is_g4x) { 5127 return 0; 5128 } else { 5129 return 0; 5130 } 5131 default: 5132 unreachable("Invalid hardware generation"); 5133 } 5134 } 5135 5136 5137 5138 /* 3DSTATE_BINDING_TABLE_EDIT_VS::Binding Table Edit Target */ 5139 5140 5141 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 5142 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 5143 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 5144 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 5145 5146 static inline uint32_t ATTRIBUTE_PURE 5147 _3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) 5148 { 5149 switch (devinfo->gen) { 5150 case 10: return 2; 5151 case 9: return 2; 5152 case 8: return 2; 5153 case 7: 5154 if (devinfo->is_haswell) { 5155 return 2; 5156 } else { 5157 return 0; 5158 } 5159 case 6: return 0; 5160 case 5: return 0; 5161 case 4: 5162 if (devinfo->is_g4x) { 5163 return 0; 5164 } else { 5165 return 0; 5166 } 5167 default: 5168 unreachable("Invalid hardware generation"); 5169 } 5170 } 5171 5172 5173 5174 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 5175 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 5176 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 5177 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 5178 5179 static inline uint32_t ATTRIBUTE_PURE 5180 _3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) 5181 { 5182 switch (devinfo->gen) { 5183 case 10: return 32; 5184 case 9: return 32; 5185 case 8: return 32; 5186 case 7: 5187 if (devinfo->is_haswell) { 5188 return 32; 5189 } else { 5190 return 0; 5191 } 5192 case 6: return 0; 5193 case 5: return 0; 5194 case 4: 5195 if (devinfo->is_g4x) { 5196 return 0; 5197 } else { 5198 return 0; 5199 } 5200 default: 5201 unreachable("Invalid hardware generation"); 5202 } 5203 } 5204 5205 5206 5207 /* 3DSTATE_BINDING_TABLE_EDIT_VS::Command SubType */ 5208 5209 5210 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 5211 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 5212 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 5213 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 5214 5215 static inline uint32_t ATTRIBUTE_PURE 5216 _3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits(const struct gen_device_info *devinfo) 5217 { 5218 switch (devinfo->gen) { 5219 case 10: return 2; 5220 case 9: return 2; 5221 case 8: return 2; 5222 case 7: 5223 if (devinfo->is_haswell) { 5224 return 2; 5225 } else { 5226 return 0; 5227 } 5228 case 6: return 0; 5229 case 5: return 0; 5230 case 4: 5231 if (devinfo->is_g4x) { 5232 return 0; 5233 } else { 5234 return 0; 5235 } 5236 default: 5237 unreachable("Invalid hardware generation"); 5238 } 5239 } 5240 5241 5242 5243 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 5244 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 5245 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 5246 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 5247 5248 static inline uint32_t ATTRIBUTE_PURE 5249 _3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start(const struct gen_device_info *devinfo) 5250 { 5251 switch (devinfo->gen) { 5252 case 10: return 27; 5253 case 9: return 27; 5254 case 8: return 27; 5255 case 7: 5256 if (devinfo->is_haswell) { 5257 return 27; 5258 } else { 5259 return 0; 5260 } 5261 case 6: return 0; 5262 case 5: return 0; 5263 case 4: 5264 if (devinfo->is_g4x) { 5265 return 0; 5266 } else { 5267 return 0; 5268 } 5269 default: 5270 unreachable("Invalid hardware generation"); 5271 } 5272 } 5273 5274 5275 5276 /* 3DSTATE_BINDING_TABLE_EDIT_VS::Command Type */ 5277 5278 5279 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 5280 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 5281 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 5282 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 5283 5284 static inline uint32_t ATTRIBUTE_PURE 5285 _3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits(const struct gen_device_info *devinfo) 5286 { 5287 switch (devinfo->gen) { 5288 case 10: return 3; 5289 case 9: return 3; 5290 case 8: return 3; 5291 case 7: 5292 if (devinfo->is_haswell) { 5293 return 3; 5294 } else { 5295 return 0; 5296 } 5297 case 6: return 0; 5298 case 5: return 0; 5299 case 4: 5300 if (devinfo->is_g4x) { 5301 return 0; 5302 } else { 5303 return 0; 5304 } 5305 default: 5306 unreachable("Invalid hardware generation"); 5307 } 5308 } 5309 5310 5311 5312 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 5313 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 5314 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 5315 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 5316 5317 static inline uint32_t ATTRIBUTE_PURE 5318 _3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start(const struct gen_device_info *devinfo) 5319 { 5320 switch (devinfo->gen) { 5321 case 10: return 29; 5322 case 9: return 29; 5323 case 8: return 29; 5324 case 7: 5325 if (devinfo->is_haswell) { 5326 return 29; 5327 } else { 5328 return 0; 5329 } 5330 case 6: return 0; 5331 case 5: return 0; 5332 case 4: 5333 if (devinfo->is_g4x) { 5334 return 0; 5335 } else { 5336 return 0; 5337 } 5338 default: 5339 unreachable("Invalid hardware generation"); 5340 } 5341 } 5342 5343 5344 5345 /* 3DSTATE_BINDING_TABLE_EDIT_VS::DWord Length */ 5346 5347 5348 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 5349 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 5350 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 5351 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 5352 5353 static inline uint32_t ATTRIBUTE_PURE 5354 _3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits(const struct gen_device_info *devinfo) 5355 { 5356 switch (devinfo->gen) { 5357 case 10: return 9; 5358 case 9: return 9; 5359 case 8: return 9; 5360 case 7: 5361 if (devinfo->is_haswell) { 5362 return 9; 5363 } else { 5364 return 0; 5365 } 5366 case 6: return 0; 5367 case 5: return 0; 5368 case 4: 5369 if (devinfo->is_g4x) { 5370 return 0; 5371 } else { 5372 return 0; 5373 } 5374 default: 5375 unreachable("Invalid hardware generation"); 5376 } 5377 } 5378 5379 5380 5381 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 5382 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 5383 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 5384 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 5385 5386 static inline uint32_t ATTRIBUTE_PURE 5387 _3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start(const struct gen_device_info *devinfo) 5388 { 5389 switch (devinfo->gen) { 5390 case 10: return 0; 5391 case 9: return 0; 5392 case 8: return 0; 5393 case 7: 5394 if (devinfo->is_haswell) { 5395 return 0; 5396 } else { 5397 return 0; 5398 } 5399 case 6: return 0; 5400 case 5: return 0; 5401 case 4: 5402 if (devinfo->is_g4x) { 5403 return 0; 5404 } else { 5405 return 0; 5406 } 5407 default: 5408 unreachable("Invalid hardware generation"); 5409 } 5410 } 5411 5412 5413 5414 /* 3DSTATE_BINDING_TABLE_EDIT_VS::Entry [n] */ 5415 5416 5417 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 5418 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 5419 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 5420 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 5421 5422 static inline uint32_t ATTRIBUTE_PURE 5423 _3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits(const struct gen_device_info *devinfo) 5424 { 5425 switch (devinfo->gen) { 5426 case 10: return 32; 5427 case 9: return 32; 5428 case 8: return 32; 5429 case 7: 5430 if (devinfo->is_haswell) { 5431 return 32; 5432 } else { 5433 return 0; 5434 } 5435 case 6: return 0; 5436 case 5: return 0; 5437 case 4: 5438 if (devinfo->is_g4x) { 5439 return 0; 5440 } else { 5441 return 0; 5442 } 5443 default: 5444 unreachable("Invalid hardware generation"); 5445 } 5446 } 5447 5448 5449 5450 #define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 5451 #define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 5452 #define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 5453 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 5454 5455 static inline uint32_t ATTRIBUTE_PURE 5456 _3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start(const struct gen_device_info *devinfo) 5457 { 5458 switch (devinfo->gen) { 5459 case 10: return 0; 5460 case 9: return 0; 5461 case 8: return 0; 5462 case 7: 5463 if (devinfo->is_haswell) { 5464 return 0; 5465 } else { 5466 return 0; 5467 } 5468 case 6: return 0; 5469 case 5: return 0; 5470 case 4: 5471 if (devinfo->is_g4x) { 5472 return 0; 5473 } else { 5474 return 0; 5475 } 5476 default: 5477 unreachable("Invalid hardware generation"); 5478 } 5479 } 5480 5481 5482 5483 /* 3DSTATE_BINDING_TABLE_POINTERS */ 5484 5485 5486 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_length 4 5487 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_length 6 5488 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_length 6 5489 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_length 6 5490 5491 static inline uint32_t ATTRIBUTE_PURE 5492 _3DSTATE_BINDING_TABLE_POINTERS_length(const struct gen_device_info *devinfo) 5493 { 5494 switch (devinfo->gen) { 5495 case 10: return 0; 5496 case 9: return 0; 5497 case 8: return 0; 5498 case 7: 5499 if (devinfo->is_haswell) { 5500 return 0; 5501 } else { 5502 return 0; 5503 } 5504 case 6: return 4; 5505 case 5: return 6; 5506 case 4: 5507 if (devinfo->is_g4x) { 5508 return 6; 5509 } else { 5510 return 6; 5511 } 5512 default: 5513 unreachable("Invalid hardware generation"); 5514 } 5515 } 5516 5517 5518 5519 /* 3DSTATE_BINDING_TABLE_POINTERS::3D Command Opcode */ 5520 5521 5522 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 5523 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 5524 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 5525 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 5526 5527 static inline uint32_t ATTRIBUTE_PURE 5528 _3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 5529 { 5530 switch (devinfo->gen) { 5531 case 10: return 0; 5532 case 9: return 0; 5533 case 8: return 0; 5534 case 7: 5535 if (devinfo->is_haswell) { 5536 return 0; 5537 } else { 5538 return 0; 5539 } 5540 case 6: return 3; 5541 case 5: return 3; 5542 case 4: 5543 if (devinfo->is_g4x) { 5544 return 3; 5545 } else { 5546 return 3; 5547 } 5548 default: 5549 unreachable("Invalid hardware generation"); 5550 } 5551 } 5552 5553 5554 5555 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 5556 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 5557 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 5558 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 5559 5560 static inline uint32_t ATTRIBUTE_PURE 5561 _3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 5562 { 5563 switch (devinfo->gen) { 5564 case 10: return 0; 5565 case 9: return 0; 5566 case 8: return 0; 5567 case 7: 5568 if (devinfo->is_haswell) { 5569 return 0; 5570 } else { 5571 return 0; 5572 } 5573 case 6: return 24; 5574 case 5: return 24; 5575 case 4: 5576 if (devinfo->is_g4x) { 5577 return 24; 5578 } else { 5579 return 24; 5580 } 5581 default: 5582 unreachable("Invalid hardware generation"); 5583 } 5584 } 5585 5586 5587 5588 /* 3DSTATE_BINDING_TABLE_POINTERS::3D Command Sub Opcode */ 5589 5590 5591 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 5592 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 5593 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 5594 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 5595 5596 static inline uint32_t ATTRIBUTE_PURE 5597 _3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 5598 { 5599 switch (devinfo->gen) { 5600 case 10: return 0; 5601 case 9: return 0; 5602 case 8: return 0; 5603 case 7: 5604 if (devinfo->is_haswell) { 5605 return 0; 5606 } else { 5607 return 0; 5608 } 5609 case 6: return 8; 5610 case 5: return 8; 5611 case 4: 5612 if (devinfo->is_g4x) { 5613 return 8; 5614 } else { 5615 return 8; 5616 } 5617 default: 5618 unreachable("Invalid hardware generation"); 5619 } 5620 } 5621 5622 5623 5624 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 5625 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 5626 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 5627 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 5628 5629 static inline uint32_t ATTRIBUTE_PURE 5630 _3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 5631 { 5632 switch (devinfo->gen) { 5633 case 10: return 0; 5634 case 9: return 0; 5635 case 8: return 0; 5636 case 7: 5637 if (devinfo->is_haswell) { 5638 return 0; 5639 } else { 5640 return 0; 5641 } 5642 case 6: return 16; 5643 case 5: return 16; 5644 case 4: 5645 if (devinfo->is_g4x) { 5646 return 16; 5647 } else { 5648 return 16; 5649 } 5650 default: 5651 unreachable("Invalid hardware generation"); 5652 } 5653 } 5654 5655 5656 5657 /* 3DSTATE_BINDING_TABLE_POINTERS::Command SubType */ 5658 5659 5660 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 5661 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 5662 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 5663 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 5664 5665 static inline uint32_t ATTRIBUTE_PURE 5666 _3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) 5667 { 5668 switch (devinfo->gen) { 5669 case 10: return 0; 5670 case 9: return 0; 5671 case 8: return 0; 5672 case 7: 5673 if (devinfo->is_haswell) { 5674 return 0; 5675 } else { 5676 return 0; 5677 } 5678 case 6: return 2; 5679 case 5: return 2; 5680 case 4: 5681 if (devinfo->is_g4x) { 5682 return 2; 5683 } else { 5684 return 2; 5685 } 5686 default: 5687 unreachable("Invalid hardware generation"); 5688 } 5689 } 5690 5691 5692 5693 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 5694 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 5695 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 5696 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 5697 5698 static inline uint32_t ATTRIBUTE_PURE 5699 _3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) 5700 { 5701 switch (devinfo->gen) { 5702 case 10: return 0; 5703 case 9: return 0; 5704 case 8: return 0; 5705 case 7: 5706 if (devinfo->is_haswell) { 5707 return 0; 5708 } else { 5709 return 0; 5710 } 5711 case 6: return 27; 5712 case 5: return 27; 5713 case 4: 5714 if (devinfo->is_g4x) { 5715 return 27; 5716 } else { 5717 return 27; 5718 } 5719 default: 5720 unreachable("Invalid hardware generation"); 5721 } 5722 } 5723 5724 5725 5726 /* 3DSTATE_BINDING_TABLE_POINTERS::Command Type */ 5727 5728 5729 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 5730 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 5731 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 5732 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 5733 5734 static inline uint32_t ATTRIBUTE_PURE 5735 _3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) 5736 { 5737 switch (devinfo->gen) { 5738 case 10: return 0; 5739 case 9: return 0; 5740 case 8: return 0; 5741 case 7: 5742 if (devinfo->is_haswell) { 5743 return 0; 5744 } else { 5745 return 0; 5746 } 5747 case 6: return 3; 5748 case 5: return 3; 5749 case 4: 5750 if (devinfo->is_g4x) { 5751 return 3; 5752 } else { 5753 return 3; 5754 } 5755 default: 5756 unreachable("Invalid hardware generation"); 5757 } 5758 } 5759 5760 5761 5762 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 5763 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 5764 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 5765 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 5766 5767 static inline uint32_t ATTRIBUTE_PURE 5768 _3DSTATE_BINDING_TABLE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) 5769 { 5770 switch (devinfo->gen) { 5771 case 10: return 0; 5772 case 9: return 0; 5773 case 8: return 0; 5774 case 7: 5775 if (devinfo->is_haswell) { 5776 return 0; 5777 } else { 5778 return 0; 5779 } 5780 case 6: return 29; 5781 case 5: return 29; 5782 case 4: 5783 if (devinfo->is_g4x) { 5784 return 29; 5785 } else { 5786 return 29; 5787 } 5788 default: 5789 unreachable("Invalid hardware generation"); 5790 } 5791 } 5792 5793 5794 5795 /* 3DSTATE_BINDING_TABLE_POINTERS::DWord Length */ 5796 5797 5798 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 5799 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 5800 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 5801 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 5802 5803 static inline uint32_t ATTRIBUTE_PURE 5804 _3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) 5805 { 5806 switch (devinfo->gen) { 5807 case 10: return 0; 5808 case 9: return 0; 5809 case 8: return 0; 5810 case 7: 5811 if (devinfo->is_haswell) { 5812 return 0; 5813 } else { 5814 return 0; 5815 } 5816 case 6: return 8; 5817 case 5: return 8; 5818 case 4: 5819 if (devinfo->is_g4x) { 5820 return 8; 5821 } else { 5822 return 8; 5823 } 5824 default: 5825 unreachable("Invalid hardware generation"); 5826 } 5827 } 5828 5829 5830 5831 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 5832 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 5833 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 5834 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 5835 5836 static inline uint32_t ATTRIBUTE_PURE 5837 _3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) 5838 { 5839 switch (devinfo->gen) { 5840 case 10: return 0; 5841 case 9: return 0; 5842 case 8: return 0; 5843 case 7: 5844 if (devinfo->is_haswell) { 5845 return 0; 5846 } else { 5847 return 0; 5848 } 5849 case 6: return 0; 5850 case 5: return 0; 5851 case 4: 5852 if (devinfo->is_g4x) { 5853 return 0; 5854 } else { 5855 return 0; 5856 } 5857 default: 5858 unreachable("Invalid hardware generation"); 5859 } 5860 } 5861 5862 5863 5864 /* 3DSTATE_BINDING_TABLE_POINTERS::GS Binding Table Change */ 5865 5866 5867 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_bits 1 5868 5869 static inline uint32_t ATTRIBUTE_PURE 5870 _3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_bits(const struct gen_device_info *devinfo) 5871 { 5872 switch (devinfo->gen) { 5873 case 10: return 0; 5874 case 9: return 0; 5875 case 8: return 0; 5876 case 7: 5877 if (devinfo->is_haswell) { 5878 return 0; 5879 } else { 5880 return 0; 5881 } 5882 case 6: return 1; 5883 case 5: return 0; 5884 case 4: 5885 if (devinfo->is_g4x) { 5886 return 0; 5887 } else { 5888 return 0; 5889 } 5890 default: 5891 unreachable("Invalid hardware generation"); 5892 } 5893 } 5894 5895 5896 5897 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_start 9 5898 5899 static inline uint32_t ATTRIBUTE_PURE 5900 _3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_start(const struct gen_device_info *devinfo) 5901 { 5902 switch (devinfo->gen) { 5903 case 10: return 0; 5904 case 9: return 0; 5905 case 8: return 0; 5906 case 7: 5907 if (devinfo->is_haswell) { 5908 return 0; 5909 } else { 5910 return 0; 5911 } 5912 case 6: return 9; 5913 case 5: return 0; 5914 case 4: 5915 if (devinfo->is_g4x) { 5916 return 0; 5917 } else { 5918 return 0; 5919 } 5920 default: 5921 unreachable("Invalid hardware generation"); 5922 } 5923 } 5924 5925 5926 5927 /* 3DSTATE_BINDING_TABLE_POINTERS::PS Binding Table Change */ 5928 5929 5930 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_bits 1 5931 5932 static inline uint32_t ATTRIBUTE_PURE 5933 _3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_bits(const struct gen_device_info *devinfo) 5934 { 5935 switch (devinfo->gen) { 5936 case 10: return 0; 5937 case 9: return 0; 5938 case 8: return 0; 5939 case 7: 5940 if (devinfo->is_haswell) { 5941 return 0; 5942 } else { 5943 return 0; 5944 } 5945 case 6: return 1; 5946 case 5: return 0; 5947 case 4: 5948 if (devinfo->is_g4x) { 5949 return 0; 5950 } else { 5951 return 0; 5952 } 5953 default: 5954 unreachable("Invalid hardware generation"); 5955 } 5956 } 5957 5958 5959 5960 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_start 12 5961 5962 static inline uint32_t ATTRIBUTE_PURE 5963 _3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_start(const struct gen_device_info *devinfo) 5964 { 5965 switch (devinfo->gen) { 5966 case 10: return 0; 5967 case 9: return 0; 5968 case 8: return 0; 5969 case 7: 5970 if (devinfo->is_haswell) { 5971 return 0; 5972 } else { 5973 return 0; 5974 } 5975 case 6: return 12; 5976 case 5: return 0; 5977 case 4: 5978 if (devinfo->is_g4x) { 5979 return 0; 5980 } else { 5981 return 0; 5982 } 5983 default: 5984 unreachable("Invalid hardware generation"); 5985 } 5986 } 5987 5988 5989 5990 /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to CLIP Binding Table */ 5991 5992 5993 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits 27 5994 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits 27 5995 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits 27 5996 5997 static inline uint32_t ATTRIBUTE_PURE 5998 _3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits(const struct gen_device_info *devinfo) 5999 { 6000 switch (devinfo->gen) { 6001 case 10: return 0; 6002 case 9: return 0; 6003 case 8: return 0; 6004 case 7: 6005 if (devinfo->is_haswell) { 6006 return 0; 6007 } else { 6008 return 0; 6009 } 6010 case 6: return 0; 6011 case 5: return 27; 6012 case 4: 6013 if (devinfo->is_g4x) { 6014 return 27; 6015 } else { 6016 return 27; 6017 } 6018 default: 6019 unreachable("Invalid hardware generation"); 6020 } 6021 } 6022 6023 6024 6025 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start 101 6026 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start 101 6027 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start 101 6028 6029 static inline uint32_t ATTRIBUTE_PURE 6030 _3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start(const struct gen_device_info *devinfo) 6031 { 6032 switch (devinfo->gen) { 6033 case 10: return 0; 6034 case 9: return 0; 6035 case 8: return 0; 6036 case 7: 6037 if (devinfo->is_haswell) { 6038 return 0; 6039 } else { 6040 return 0; 6041 } 6042 case 6: return 0; 6043 case 5: return 101; 6044 case 4: 6045 if (devinfo->is_g4x) { 6046 return 101; 6047 } else { 6048 return 101; 6049 } 6050 default: 6051 unreachable("Invalid hardware generation"); 6052 } 6053 } 6054 6055 6056 6057 /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to GS Binding Table */ 6058 6059 6060 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 6061 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 6062 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 6063 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 6064 6065 static inline uint32_t ATTRIBUTE_PURE 6066 _3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits(const struct gen_device_info *devinfo) 6067 { 6068 switch (devinfo->gen) { 6069 case 10: return 0; 6070 case 9: return 0; 6071 case 8: return 0; 6072 case 7: 6073 if (devinfo->is_haswell) { 6074 return 0; 6075 } else { 6076 return 0; 6077 } 6078 case 6: return 27; 6079 case 5: return 27; 6080 case 4: 6081 if (devinfo->is_g4x) { 6082 return 27; 6083 } else { 6084 return 27; 6085 } 6086 default: 6087 unreachable("Invalid hardware generation"); 6088 } 6089 } 6090 6091 6092 6093 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 6094 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 6095 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 6096 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 6097 6098 static inline uint32_t ATTRIBUTE_PURE 6099 _3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start(const struct gen_device_info *devinfo) 6100 { 6101 switch (devinfo->gen) { 6102 case 10: return 0; 6103 case 9: return 0; 6104 case 8: return 0; 6105 case 7: 6106 if (devinfo->is_haswell) { 6107 return 0; 6108 } else { 6109 return 0; 6110 } 6111 case 6: return 69; 6112 case 5: return 69; 6113 case 4: 6114 if (devinfo->is_g4x) { 6115 return 69; 6116 } else { 6117 return 69; 6118 } 6119 default: 6120 unreachable("Invalid hardware generation"); 6121 } 6122 } 6123 6124 6125 6126 /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to PS Binding Table */ 6127 6128 6129 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 6130 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 6131 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 6132 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 6133 6134 static inline uint32_t ATTRIBUTE_PURE 6135 _3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits(const struct gen_device_info *devinfo) 6136 { 6137 switch (devinfo->gen) { 6138 case 10: return 0; 6139 case 9: return 0; 6140 case 8: return 0; 6141 case 7: 6142 if (devinfo->is_haswell) { 6143 return 0; 6144 } else { 6145 return 0; 6146 } 6147 case 6: return 27; 6148 case 5: return 27; 6149 case 4: 6150 if (devinfo->is_g4x) { 6151 return 27; 6152 } else { 6153 return 27; 6154 } 6155 default: 6156 unreachable("Invalid hardware generation"); 6157 } 6158 } 6159 6160 6161 6162 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 101 6163 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 165 6164 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 165 6165 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 165 6166 6167 static inline uint32_t ATTRIBUTE_PURE 6168 _3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start(const struct gen_device_info *devinfo) 6169 { 6170 switch (devinfo->gen) { 6171 case 10: return 0; 6172 case 9: return 0; 6173 case 8: return 0; 6174 case 7: 6175 if (devinfo->is_haswell) { 6176 return 0; 6177 } else { 6178 return 0; 6179 } 6180 case 6: return 101; 6181 case 5: return 165; 6182 case 4: 6183 if (devinfo->is_g4x) { 6184 return 165; 6185 } else { 6186 return 165; 6187 } 6188 default: 6189 unreachable("Invalid hardware generation"); 6190 } 6191 } 6192 6193 6194 6195 /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to SF Binding Table */ 6196 6197 6198 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits 27 6199 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits 27 6200 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits 27 6201 6202 static inline uint32_t ATTRIBUTE_PURE 6203 _3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits(const struct gen_device_info *devinfo) 6204 { 6205 switch (devinfo->gen) { 6206 case 10: return 0; 6207 case 9: return 0; 6208 case 8: return 0; 6209 case 7: 6210 if (devinfo->is_haswell) { 6211 return 0; 6212 } else { 6213 return 0; 6214 } 6215 case 6: return 0; 6216 case 5: return 27; 6217 case 4: 6218 if (devinfo->is_g4x) { 6219 return 27; 6220 } else { 6221 return 27; 6222 } 6223 default: 6224 unreachable("Invalid hardware generation"); 6225 } 6226 } 6227 6228 6229 6230 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start 133 6231 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start 133 6232 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start 133 6233 6234 static inline uint32_t ATTRIBUTE_PURE 6235 _3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start(const struct gen_device_info *devinfo) 6236 { 6237 switch (devinfo->gen) { 6238 case 10: return 0; 6239 case 9: return 0; 6240 case 8: return 0; 6241 case 7: 6242 if (devinfo->is_haswell) { 6243 return 0; 6244 } else { 6245 return 0; 6246 } 6247 case 6: return 0; 6248 case 5: return 133; 6249 case 4: 6250 if (devinfo->is_g4x) { 6251 return 133; 6252 } else { 6253 return 133; 6254 } 6255 default: 6256 unreachable("Invalid hardware generation"); 6257 } 6258 } 6259 6260 6261 6262 /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to VS Binding Table */ 6263 6264 6265 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 6266 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 6267 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 6268 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 6269 6270 static inline uint32_t ATTRIBUTE_PURE 6271 _3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits(const struct gen_device_info *devinfo) 6272 { 6273 switch (devinfo->gen) { 6274 case 10: return 0; 6275 case 9: return 0; 6276 case 8: return 0; 6277 case 7: 6278 if (devinfo->is_haswell) { 6279 return 0; 6280 } else { 6281 return 0; 6282 } 6283 case 6: return 27; 6284 case 5: return 27; 6285 case 4: 6286 if (devinfo->is_g4x) { 6287 return 27; 6288 } else { 6289 return 27; 6290 } 6291 default: 6292 unreachable("Invalid hardware generation"); 6293 } 6294 } 6295 6296 6297 6298 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 6299 #define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 6300 #define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 6301 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 6302 6303 static inline uint32_t ATTRIBUTE_PURE 6304 _3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start(const struct gen_device_info *devinfo) 6305 { 6306 switch (devinfo->gen) { 6307 case 10: return 0; 6308 case 9: return 0; 6309 case 8: return 0; 6310 case 7: 6311 if (devinfo->is_haswell) { 6312 return 0; 6313 } else { 6314 return 0; 6315 } 6316 case 6: return 37; 6317 case 5: return 37; 6318 case 4: 6319 if (devinfo->is_g4x) { 6320 return 37; 6321 } else { 6322 return 37; 6323 } 6324 default: 6325 unreachable("Invalid hardware generation"); 6326 } 6327 } 6328 6329 6330 6331 /* 3DSTATE_BINDING_TABLE_POINTERS::VS Binding Table Change */ 6332 6333 6334 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_bits 1 6335 6336 static inline uint32_t ATTRIBUTE_PURE 6337 _3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_bits(const struct gen_device_info *devinfo) 6338 { 6339 switch (devinfo->gen) { 6340 case 10: return 0; 6341 case 9: return 0; 6342 case 8: return 0; 6343 case 7: 6344 if (devinfo->is_haswell) { 6345 return 0; 6346 } else { 6347 return 0; 6348 } 6349 case 6: return 1; 6350 case 5: return 0; 6351 case 4: 6352 if (devinfo->is_g4x) { 6353 return 0; 6354 } else { 6355 return 0; 6356 } 6357 default: 6358 unreachable("Invalid hardware generation"); 6359 } 6360 } 6361 6362 6363 6364 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_start 8 6365 6366 static inline uint32_t ATTRIBUTE_PURE 6367 _3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_start(const struct gen_device_info *devinfo) 6368 { 6369 switch (devinfo->gen) { 6370 case 10: return 0; 6371 case 9: return 0; 6372 case 8: return 0; 6373 case 7: 6374 if (devinfo->is_haswell) { 6375 return 0; 6376 } else { 6377 return 0; 6378 } 6379 case 6: return 8; 6380 case 5: return 0; 6381 case 4: 6382 if (devinfo->is_g4x) { 6383 return 0; 6384 } else { 6385 return 0; 6386 } 6387 default: 6388 unreachable("Invalid hardware generation"); 6389 } 6390 } 6391 6392 6393 6394 /* 3DSTATE_BINDING_TABLE_POINTERS_DS */ 6395 6396 6397 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 6398 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 6399 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 6400 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 6401 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 6402 6403 static inline uint32_t ATTRIBUTE_PURE 6404 _3DSTATE_BINDING_TABLE_POINTERS_DS_length(const struct gen_device_info *devinfo) 6405 { 6406 switch (devinfo->gen) { 6407 case 10: return 2; 6408 case 9: return 2; 6409 case 8: return 2; 6410 case 7: 6411 if (devinfo->is_haswell) { 6412 return 2; 6413 } else { 6414 return 2; 6415 } 6416 case 6: return 0; 6417 case 5: return 0; 6418 case 4: 6419 if (devinfo->is_g4x) { 6420 return 0; 6421 } else { 6422 return 0; 6423 } 6424 default: 6425 unreachable("Invalid hardware generation"); 6426 } 6427 } 6428 6429 6430 6431 /* 3DSTATE_BINDING_TABLE_POINTERS_DS::3D Command Opcode */ 6432 6433 6434 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 6435 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 6436 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 6437 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 6438 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 6439 6440 static inline uint32_t ATTRIBUTE_PURE 6441 _3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 6442 { 6443 switch (devinfo->gen) { 6444 case 10: return 3; 6445 case 9: return 3; 6446 case 8: return 3; 6447 case 7: 6448 if (devinfo->is_haswell) { 6449 return 3; 6450 } else { 6451 return 3; 6452 } 6453 case 6: return 0; 6454 case 5: return 0; 6455 case 4: 6456 if (devinfo->is_g4x) { 6457 return 0; 6458 } else { 6459 return 0; 6460 } 6461 default: 6462 unreachable("Invalid hardware generation"); 6463 } 6464 } 6465 6466 6467 6468 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 6469 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 6470 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 6471 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 6472 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 6473 6474 static inline uint32_t ATTRIBUTE_PURE 6475 _3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 6476 { 6477 switch (devinfo->gen) { 6478 case 10: return 24; 6479 case 9: return 24; 6480 case 8: return 24; 6481 case 7: 6482 if (devinfo->is_haswell) { 6483 return 24; 6484 } else { 6485 return 24; 6486 } 6487 case 6: return 0; 6488 case 5: return 0; 6489 case 4: 6490 if (devinfo->is_g4x) { 6491 return 0; 6492 } else { 6493 return 0; 6494 } 6495 default: 6496 unreachable("Invalid hardware generation"); 6497 } 6498 } 6499 6500 6501 6502 /* 3DSTATE_BINDING_TABLE_POINTERS_DS::3D Command Sub Opcode */ 6503 6504 6505 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 6506 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 6507 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 6508 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 6509 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 6510 6511 static inline uint32_t ATTRIBUTE_PURE 6512 _3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 6513 { 6514 switch (devinfo->gen) { 6515 case 10: return 8; 6516 case 9: return 8; 6517 case 8: return 8; 6518 case 7: 6519 if (devinfo->is_haswell) { 6520 return 8; 6521 } else { 6522 return 8; 6523 } 6524 case 6: return 0; 6525 case 5: return 0; 6526 case 4: 6527 if (devinfo->is_g4x) { 6528 return 0; 6529 } else { 6530 return 0; 6531 } 6532 default: 6533 unreachable("Invalid hardware generation"); 6534 } 6535 } 6536 6537 6538 6539 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 6540 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 6541 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 6542 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 6543 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 6544 6545 static inline uint32_t ATTRIBUTE_PURE 6546 _3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 6547 { 6548 switch (devinfo->gen) { 6549 case 10: return 16; 6550 case 9: return 16; 6551 case 8: return 16; 6552 case 7: 6553 if (devinfo->is_haswell) { 6554 return 16; 6555 } else { 6556 return 16; 6557 } 6558 case 6: return 0; 6559 case 5: return 0; 6560 case 4: 6561 if (devinfo->is_g4x) { 6562 return 0; 6563 } else { 6564 return 0; 6565 } 6566 default: 6567 unreachable("Invalid hardware generation"); 6568 } 6569 } 6570 6571 6572 6573 /* 3DSTATE_BINDING_TABLE_POINTERS_DS::Command SubType */ 6574 6575 6576 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 6577 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 6578 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 6579 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 6580 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 6581 6582 static inline uint32_t ATTRIBUTE_PURE 6583 _3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits(const struct gen_device_info *devinfo) 6584 { 6585 switch (devinfo->gen) { 6586 case 10: return 2; 6587 case 9: return 2; 6588 case 8: return 2; 6589 case 7: 6590 if (devinfo->is_haswell) { 6591 return 2; 6592 } else { 6593 return 2; 6594 } 6595 case 6: return 0; 6596 case 5: return 0; 6597 case 4: 6598 if (devinfo->is_g4x) { 6599 return 0; 6600 } else { 6601 return 0; 6602 } 6603 default: 6604 unreachable("Invalid hardware generation"); 6605 } 6606 } 6607 6608 6609 6610 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 6611 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 6612 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 6613 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 6614 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 6615 6616 static inline uint32_t ATTRIBUTE_PURE 6617 _3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start(const struct gen_device_info *devinfo) 6618 { 6619 switch (devinfo->gen) { 6620 case 10: return 27; 6621 case 9: return 27; 6622 case 8: return 27; 6623 case 7: 6624 if (devinfo->is_haswell) { 6625 return 27; 6626 } else { 6627 return 27; 6628 } 6629 case 6: return 0; 6630 case 5: return 0; 6631 case 4: 6632 if (devinfo->is_g4x) { 6633 return 0; 6634 } else { 6635 return 0; 6636 } 6637 default: 6638 unreachable("Invalid hardware generation"); 6639 } 6640 } 6641 6642 6643 6644 /* 3DSTATE_BINDING_TABLE_POINTERS_DS::Command Type */ 6645 6646 6647 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 6648 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 6649 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 6650 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 6651 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 6652 6653 static inline uint32_t ATTRIBUTE_PURE 6654 _3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits(const struct gen_device_info *devinfo) 6655 { 6656 switch (devinfo->gen) { 6657 case 10: return 3; 6658 case 9: return 3; 6659 case 8: return 3; 6660 case 7: 6661 if (devinfo->is_haswell) { 6662 return 3; 6663 } else { 6664 return 3; 6665 } 6666 case 6: return 0; 6667 case 5: return 0; 6668 case 4: 6669 if (devinfo->is_g4x) { 6670 return 0; 6671 } else { 6672 return 0; 6673 } 6674 default: 6675 unreachable("Invalid hardware generation"); 6676 } 6677 } 6678 6679 6680 6681 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 6682 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 6683 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 6684 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 6685 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 6686 6687 static inline uint32_t ATTRIBUTE_PURE 6688 _3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start(const struct gen_device_info *devinfo) 6689 { 6690 switch (devinfo->gen) { 6691 case 10: return 29; 6692 case 9: return 29; 6693 case 8: return 29; 6694 case 7: 6695 if (devinfo->is_haswell) { 6696 return 29; 6697 } else { 6698 return 29; 6699 } 6700 case 6: return 0; 6701 case 5: return 0; 6702 case 4: 6703 if (devinfo->is_g4x) { 6704 return 0; 6705 } else { 6706 return 0; 6707 } 6708 default: 6709 unreachable("Invalid hardware generation"); 6710 } 6711 } 6712 6713 6714 6715 /* 3DSTATE_BINDING_TABLE_POINTERS_DS::DWord Length */ 6716 6717 6718 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 6719 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 6720 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 6721 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 6722 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 6723 6724 static inline uint32_t ATTRIBUTE_PURE 6725 _3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits(const struct gen_device_info *devinfo) 6726 { 6727 switch (devinfo->gen) { 6728 case 10: return 8; 6729 case 9: return 8; 6730 case 8: return 8; 6731 case 7: 6732 if (devinfo->is_haswell) { 6733 return 8; 6734 } else { 6735 return 8; 6736 } 6737 case 6: return 0; 6738 case 5: return 0; 6739 case 4: 6740 if (devinfo->is_g4x) { 6741 return 0; 6742 } else { 6743 return 0; 6744 } 6745 default: 6746 unreachable("Invalid hardware generation"); 6747 } 6748 } 6749 6750 6751 6752 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 6753 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 6754 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 6755 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 6756 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 6757 6758 static inline uint32_t ATTRIBUTE_PURE 6759 _3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start(const struct gen_device_info *devinfo) 6760 { 6761 switch (devinfo->gen) { 6762 case 10: return 0; 6763 case 9: return 0; 6764 case 8: return 0; 6765 case 7: 6766 if (devinfo->is_haswell) { 6767 return 0; 6768 } else { 6769 return 0; 6770 } 6771 case 6: return 0; 6772 case 5: return 0; 6773 case 4: 6774 if (devinfo->is_g4x) { 6775 return 0; 6776 } else { 6777 return 0; 6778 } 6779 default: 6780 unreachable("Invalid hardware generation"); 6781 } 6782 } 6783 6784 6785 6786 /* 3DSTATE_BINDING_TABLE_POINTERS_DS::Pointer to DS Binding Table */ 6787 6788 6789 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 6790 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 6791 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 6792 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 6793 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 6794 6795 static inline uint32_t ATTRIBUTE_PURE 6796 _3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits(const struct gen_device_info *devinfo) 6797 { 6798 switch (devinfo->gen) { 6799 case 10: return 11; 6800 case 9: return 11; 6801 case 8: return 11; 6802 case 7: 6803 if (devinfo->is_haswell) { 6804 return 11; 6805 } else { 6806 return 11; 6807 } 6808 case 6: return 0; 6809 case 5: return 0; 6810 case 4: 6811 if (devinfo->is_g4x) { 6812 return 0; 6813 } else { 6814 return 0; 6815 } 6816 default: 6817 unreachable("Invalid hardware generation"); 6818 } 6819 } 6820 6821 6822 6823 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 6824 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 6825 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 6826 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 6827 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 6828 6829 static inline uint32_t ATTRIBUTE_PURE 6830 _3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start(const struct gen_device_info *devinfo) 6831 { 6832 switch (devinfo->gen) { 6833 case 10: return 37; 6834 case 9: return 37; 6835 case 8: return 37; 6836 case 7: 6837 if (devinfo->is_haswell) { 6838 return 37; 6839 } else { 6840 return 37; 6841 } 6842 case 6: return 0; 6843 case 5: return 0; 6844 case 4: 6845 if (devinfo->is_g4x) { 6846 return 0; 6847 } else { 6848 return 0; 6849 } 6850 default: 6851 unreachable("Invalid hardware generation"); 6852 } 6853 } 6854 6855 6856 6857 /* 3DSTATE_BINDING_TABLE_POINTERS_GS */ 6858 6859 6860 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 6861 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 6862 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 6863 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 6864 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 6865 6866 static inline uint32_t ATTRIBUTE_PURE 6867 _3DSTATE_BINDING_TABLE_POINTERS_GS_length(const struct gen_device_info *devinfo) 6868 { 6869 switch (devinfo->gen) { 6870 case 10: return 2; 6871 case 9: return 2; 6872 case 8: return 2; 6873 case 7: 6874 if (devinfo->is_haswell) { 6875 return 2; 6876 } else { 6877 return 2; 6878 } 6879 case 6: return 0; 6880 case 5: return 0; 6881 case 4: 6882 if (devinfo->is_g4x) { 6883 return 0; 6884 } else { 6885 return 0; 6886 } 6887 default: 6888 unreachable("Invalid hardware generation"); 6889 } 6890 } 6891 6892 6893 6894 /* 3DSTATE_BINDING_TABLE_POINTERS_GS::3D Command Opcode */ 6895 6896 6897 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 6898 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 6899 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 6900 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 6901 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 6902 6903 static inline uint32_t ATTRIBUTE_PURE 6904 _3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 6905 { 6906 switch (devinfo->gen) { 6907 case 10: return 3; 6908 case 9: return 3; 6909 case 8: return 3; 6910 case 7: 6911 if (devinfo->is_haswell) { 6912 return 3; 6913 } else { 6914 return 3; 6915 } 6916 case 6: return 0; 6917 case 5: return 0; 6918 case 4: 6919 if (devinfo->is_g4x) { 6920 return 0; 6921 } else { 6922 return 0; 6923 } 6924 default: 6925 unreachable("Invalid hardware generation"); 6926 } 6927 } 6928 6929 6930 6931 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 6932 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 6933 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 6934 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 6935 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 6936 6937 static inline uint32_t ATTRIBUTE_PURE 6938 _3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 6939 { 6940 switch (devinfo->gen) { 6941 case 10: return 24; 6942 case 9: return 24; 6943 case 8: return 24; 6944 case 7: 6945 if (devinfo->is_haswell) { 6946 return 24; 6947 } else { 6948 return 24; 6949 } 6950 case 6: return 0; 6951 case 5: return 0; 6952 case 4: 6953 if (devinfo->is_g4x) { 6954 return 0; 6955 } else { 6956 return 0; 6957 } 6958 default: 6959 unreachable("Invalid hardware generation"); 6960 } 6961 } 6962 6963 6964 6965 /* 3DSTATE_BINDING_TABLE_POINTERS_GS::3D Command Sub Opcode */ 6966 6967 6968 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 6969 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 6970 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 6971 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 6972 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 6973 6974 static inline uint32_t ATTRIBUTE_PURE 6975 _3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 6976 { 6977 switch (devinfo->gen) { 6978 case 10: return 8; 6979 case 9: return 8; 6980 case 8: return 8; 6981 case 7: 6982 if (devinfo->is_haswell) { 6983 return 8; 6984 } else { 6985 return 8; 6986 } 6987 case 6: return 0; 6988 case 5: return 0; 6989 case 4: 6990 if (devinfo->is_g4x) { 6991 return 0; 6992 } else { 6993 return 0; 6994 } 6995 default: 6996 unreachable("Invalid hardware generation"); 6997 } 6998 } 6999 7000 7001 7002 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 7003 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 7004 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 7005 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 7006 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 7007 7008 static inline uint32_t ATTRIBUTE_PURE 7009 _3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 7010 { 7011 switch (devinfo->gen) { 7012 case 10: return 16; 7013 case 9: return 16; 7014 case 8: return 16; 7015 case 7: 7016 if (devinfo->is_haswell) { 7017 return 16; 7018 } else { 7019 return 16; 7020 } 7021 case 6: return 0; 7022 case 5: return 0; 7023 case 4: 7024 if (devinfo->is_g4x) { 7025 return 0; 7026 } else { 7027 return 0; 7028 } 7029 default: 7030 unreachable("Invalid hardware generation"); 7031 } 7032 } 7033 7034 7035 7036 /* 3DSTATE_BINDING_TABLE_POINTERS_GS::Command SubType */ 7037 7038 7039 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 7040 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 7041 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 7042 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 7043 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 7044 7045 static inline uint32_t ATTRIBUTE_PURE 7046 _3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits(const struct gen_device_info *devinfo) 7047 { 7048 switch (devinfo->gen) { 7049 case 10: return 2; 7050 case 9: return 2; 7051 case 8: return 2; 7052 case 7: 7053 if (devinfo->is_haswell) { 7054 return 2; 7055 } else { 7056 return 2; 7057 } 7058 case 6: return 0; 7059 case 5: return 0; 7060 case 4: 7061 if (devinfo->is_g4x) { 7062 return 0; 7063 } else { 7064 return 0; 7065 } 7066 default: 7067 unreachable("Invalid hardware generation"); 7068 } 7069 } 7070 7071 7072 7073 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 7074 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 7075 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 7076 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 7077 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 7078 7079 static inline uint32_t ATTRIBUTE_PURE 7080 _3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start(const struct gen_device_info *devinfo) 7081 { 7082 switch (devinfo->gen) { 7083 case 10: return 27; 7084 case 9: return 27; 7085 case 8: return 27; 7086 case 7: 7087 if (devinfo->is_haswell) { 7088 return 27; 7089 } else { 7090 return 27; 7091 } 7092 case 6: return 0; 7093 case 5: return 0; 7094 case 4: 7095 if (devinfo->is_g4x) { 7096 return 0; 7097 } else { 7098 return 0; 7099 } 7100 default: 7101 unreachable("Invalid hardware generation"); 7102 } 7103 } 7104 7105 7106 7107 /* 3DSTATE_BINDING_TABLE_POINTERS_GS::Command Type */ 7108 7109 7110 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 7111 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 7112 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 7113 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 7114 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 7115 7116 static inline uint32_t ATTRIBUTE_PURE 7117 _3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits(const struct gen_device_info *devinfo) 7118 { 7119 switch (devinfo->gen) { 7120 case 10: return 3; 7121 case 9: return 3; 7122 case 8: return 3; 7123 case 7: 7124 if (devinfo->is_haswell) { 7125 return 3; 7126 } else { 7127 return 3; 7128 } 7129 case 6: return 0; 7130 case 5: return 0; 7131 case 4: 7132 if (devinfo->is_g4x) { 7133 return 0; 7134 } else { 7135 return 0; 7136 } 7137 default: 7138 unreachable("Invalid hardware generation"); 7139 } 7140 } 7141 7142 7143 7144 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 7145 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 7146 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 7147 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 7148 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 7149 7150 static inline uint32_t ATTRIBUTE_PURE 7151 _3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start(const struct gen_device_info *devinfo) 7152 { 7153 switch (devinfo->gen) { 7154 case 10: return 29; 7155 case 9: return 29; 7156 case 8: return 29; 7157 case 7: 7158 if (devinfo->is_haswell) { 7159 return 29; 7160 } else { 7161 return 29; 7162 } 7163 case 6: return 0; 7164 case 5: return 0; 7165 case 4: 7166 if (devinfo->is_g4x) { 7167 return 0; 7168 } else { 7169 return 0; 7170 } 7171 default: 7172 unreachable("Invalid hardware generation"); 7173 } 7174 } 7175 7176 7177 7178 /* 3DSTATE_BINDING_TABLE_POINTERS_GS::DWord Length */ 7179 7180 7181 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 7182 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 7183 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 7184 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 7185 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 7186 7187 static inline uint32_t ATTRIBUTE_PURE 7188 _3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits(const struct gen_device_info *devinfo) 7189 { 7190 switch (devinfo->gen) { 7191 case 10: return 8; 7192 case 9: return 8; 7193 case 8: return 8; 7194 case 7: 7195 if (devinfo->is_haswell) { 7196 return 8; 7197 } else { 7198 return 8; 7199 } 7200 case 6: return 0; 7201 case 5: return 0; 7202 case 4: 7203 if (devinfo->is_g4x) { 7204 return 0; 7205 } else { 7206 return 0; 7207 } 7208 default: 7209 unreachable("Invalid hardware generation"); 7210 } 7211 } 7212 7213 7214 7215 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 7216 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 7217 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 7218 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 7219 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 7220 7221 static inline uint32_t ATTRIBUTE_PURE 7222 _3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start(const struct gen_device_info *devinfo) 7223 { 7224 switch (devinfo->gen) { 7225 case 10: return 0; 7226 case 9: return 0; 7227 case 8: return 0; 7228 case 7: 7229 if (devinfo->is_haswell) { 7230 return 0; 7231 } else { 7232 return 0; 7233 } 7234 case 6: return 0; 7235 case 5: return 0; 7236 case 4: 7237 if (devinfo->is_g4x) { 7238 return 0; 7239 } else { 7240 return 0; 7241 } 7242 default: 7243 unreachable("Invalid hardware generation"); 7244 } 7245 } 7246 7247 7248 7249 /* 3DSTATE_BINDING_TABLE_POINTERS_GS::Pointer to GS Binding Table */ 7250 7251 7252 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 7253 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 7254 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 7255 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 7256 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 7257 7258 static inline uint32_t ATTRIBUTE_PURE 7259 _3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits(const struct gen_device_info *devinfo) 7260 { 7261 switch (devinfo->gen) { 7262 case 10: return 11; 7263 case 9: return 11; 7264 case 8: return 11; 7265 case 7: 7266 if (devinfo->is_haswell) { 7267 return 11; 7268 } else { 7269 return 11; 7270 } 7271 case 6: return 0; 7272 case 5: return 0; 7273 case 4: 7274 if (devinfo->is_g4x) { 7275 return 0; 7276 } else { 7277 return 0; 7278 } 7279 default: 7280 unreachable("Invalid hardware generation"); 7281 } 7282 } 7283 7284 7285 7286 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 7287 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 7288 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 7289 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 7290 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 7291 7292 static inline uint32_t ATTRIBUTE_PURE 7293 _3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start(const struct gen_device_info *devinfo) 7294 { 7295 switch (devinfo->gen) { 7296 case 10: return 37; 7297 case 9: return 37; 7298 case 8: return 37; 7299 case 7: 7300 if (devinfo->is_haswell) { 7301 return 37; 7302 } else { 7303 return 37; 7304 } 7305 case 6: return 0; 7306 case 5: return 0; 7307 case 4: 7308 if (devinfo->is_g4x) { 7309 return 0; 7310 } else { 7311 return 0; 7312 } 7313 default: 7314 unreachable("Invalid hardware generation"); 7315 } 7316 } 7317 7318 7319 7320 /* 3DSTATE_BINDING_TABLE_POINTERS_HS */ 7321 7322 7323 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 7324 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 7325 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 7326 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 7327 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 7328 7329 static inline uint32_t ATTRIBUTE_PURE 7330 _3DSTATE_BINDING_TABLE_POINTERS_HS_length(const struct gen_device_info *devinfo) 7331 { 7332 switch (devinfo->gen) { 7333 case 10: return 2; 7334 case 9: return 2; 7335 case 8: return 2; 7336 case 7: 7337 if (devinfo->is_haswell) { 7338 return 2; 7339 } else { 7340 return 2; 7341 } 7342 case 6: return 0; 7343 case 5: return 0; 7344 case 4: 7345 if (devinfo->is_g4x) { 7346 return 0; 7347 } else { 7348 return 0; 7349 } 7350 default: 7351 unreachable("Invalid hardware generation"); 7352 } 7353 } 7354 7355 7356 7357 /* 3DSTATE_BINDING_TABLE_POINTERS_HS::3D Command Opcode */ 7358 7359 7360 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 7361 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 7362 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 7363 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 7364 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 7365 7366 static inline uint32_t ATTRIBUTE_PURE 7367 _3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 7368 { 7369 switch (devinfo->gen) { 7370 case 10: return 3; 7371 case 9: return 3; 7372 case 8: return 3; 7373 case 7: 7374 if (devinfo->is_haswell) { 7375 return 3; 7376 } else { 7377 return 3; 7378 } 7379 case 6: return 0; 7380 case 5: return 0; 7381 case 4: 7382 if (devinfo->is_g4x) { 7383 return 0; 7384 } else { 7385 return 0; 7386 } 7387 default: 7388 unreachable("Invalid hardware generation"); 7389 } 7390 } 7391 7392 7393 7394 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 7395 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 7396 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 7397 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 7398 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 7399 7400 static inline uint32_t ATTRIBUTE_PURE 7401 _3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 7402 { 7403 switch (devinfo->gen) { 7404 case 10: return 24; 7405 case 9: return 24; 7406 case 8: return 24; 7407 case 7: 7408 if (devinfo->is_haswell) { 7409 return 24; 7410 } else { 7411 return 24; 7412 } 7413 case 6: return 0; 7414 case 5: return 0; 7415 case 4: 7416 if (devinfo->is_g4x) { 7417 return 0; 7418 } else { 7419 return 0; 7420 } 7421 default: 7422 unreachable("Invalid hardware generation"); 7423 } 7424 } 7425 7426 7427 7428 /* 3DSTATE_BINDING_TABLE_POINTERS_HS::3D Command Sub Opcode */ 7429 7430 7431 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 7432 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 7433 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 7434 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 7435 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 7436 7437 static inline uint32_t ATTRIBUTE_PURE 7438 _3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 7439 { 7440 switch (devinfo->gen) { 7441 case 10: return 8; 7442 case 9: return 8; 7443 case 8: return 8; 7444 case 7: 7445 if (devinfo->is_haswell) { 7446 return 8; 7447 } else { 7448 return 8; 7449 } 7450 case 6: return 0; 7451 case 5: return 0; 7452 case 4: 7453 if (devinfo->is_g4x) { 7454 return 0; 7455 } else { 7456 return 0; 7457 } 7458 default: 7459 unreachable("Invalid hardware generation"); 7460 } 7461 } 7462 7463 7464 7465 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 7466 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 7467 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 7468 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 7469 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 7470 7471 static inline uint32_t ATTRIBUTE_PURE 7472 _3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 7473 { 7474 switch (devinfo->gen) { 7475 case 10: return 16; 7476 case 9: return 16; 7477 case 8: return 16; 7478 case 7: 7479 if (devinfo->is_haswell) { 7480 return 16; 7481 } else { 7482 return 16; 7483 } 7484 case 6: return 0; 7485 case 5: return 0; 7486 case 4: 7487 if (devinfo->is_g4x) { 7488 return 0; 7489 } else { 7490 return 0; 7491 } 7492 default: 7493 unreachable("Invalid hardware generation"); 7494 } 7495 } 7496 7497 7498 7499 /* 3DSTATE_BINDING_TABLE_POINTERS_HS::Command SubType */ 7500 7501 7502 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 7503 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 7504 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 7505 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 7506 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 7507 7508 static inline uint32_t ATTRIBUTE_PURE 7509 _3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits(const struct gen_device_info *devinfo) 7510 { 7511 switch (devinfo->gen) { 7512 case 10: return 2; 7513 case 9: return 2; 7514 case 8: return 2; 7515 case 7: 7516 if (devinfo->is_haswell) { 7517 return 2; 7518 } else { 7519 return 2; 7520 } 7521 case 6: return 0; 7522 case 5: return 0; 7523 case 4: 7524 if (devinfo->is_g4x) { 7525 return 0; 7526 } else { 7527 return 0; 7528 } 7529 default: 7530 unreachable("Invalid hardware generation"); 7531 } 7532 } 7533 7534 7535 7536 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 7537 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 7538 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 7539 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 7540 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 7541 7542 static inline uint32_t ATTRIBUTE_PURE 7543 _3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start(const struct gen_device_info *devinfo) 7544 { 7545 switch (devinfo->gen) { 7546 case 10: return 27; 7547 case 9: return 27; 7548 case 8: return 27; 7549 case 7: 7550 if (devinfo->is_haswell) { 7551 return 27; 7552 } else { 7553 return 27; 7554 } 7555 case 6: return 0; 7556 case 5: return 0; 7557 case 4: 7558 if (devinfo->is_g4x) { 7559 return 0; 7560 } else { 7561 return 0; 7562 } 7563 default: 7564 unreachable("Invalid hardware generation"); 7565 } 7566 } 7567 7568 7569 7570 /* 3DSTATE_BINDING_TABLE_POINTERS_HS::Command Type */ 7571 7572 7573 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 7574 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 7575 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 7576 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 7577 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 7578 7579 static inline uint32_t ATTRIBUTE_PURE 7580 _3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits(const struct gen_device_info *devinfo) 7581 { 7582 switch (devinfo->gen) { 7583 case 10: return 3; 7584 case 9: return 3; 7585 case 8: return 3; 7586 case 7: 7587 if (devinfo->is_haswell) { 7588 return 3; 7589 } else { 7590 return 3; 7591 } 7592 case 6: return 0; 7593 case 5: return 0; 7594 case 4: 7595 if (devinfo->is_g4x) { 7596 return 0; 7597 } else { 7598 return 0; 7599 } 7600 default: 7601 unreachable("Invalid hardware generation"); 7602 } 7603 } 7604 7605 7606 7607 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 7608 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 7609 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 7610 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 7611 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 7612 7613 static inline uint32_t ATTRIBUTE_PURE 7614 _3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start(const struct gen_device_info *devinfo) 7615 { 7616 switch (devinfo->gen) { 7617 case 10: return 29; 7618 case 9: return 29; 7619 case 8: return 29; 7620 case 7: 7621 if (devinfo->is_haswell) { 7622 return 29; 7623 } else { 7624 return 29; 7625 } 7626 case 6: return 0; 7627 case 5: return 0; 7628 case 4: 7629 if (devinfo->is_g4x) { 7630 return 0; 7631 } else { 7632 return 0; 7633 } 7634 default: 7635 unreachable("Invalid hardware generation"); 7636 } 7637 } 7638 7639 7640 7641 /* 3DSTATE_BINDING_TABLE_POINTERS_HS::DWord Length */ 7642 7643 7644 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 7645 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 7646 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 7647 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 7648 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 7649 7650 static inline uint32_t ATTRIBUTE_PURE 7651 _3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits(const struct gen_device_info *devinfo) 7652 { 7653 switch (devinfo->gen) { 7654 case 10: return 8; 7655 case 9: return 8; 7656 case 8: return 8; 7657 case 7: 7658 if (devinfo->is_haswell) { 7659 return 8; 7660 } else { 7661 return 8; 7662 } 7663 case 6: return 0; 7664 case 5: return 0; 7665 case 4: 7666 if (devinfo->is_g4x) { 7667 return 0; 7668 } else { 7669 return 0; 7670 } 7671 default: 7672 unreachable("Invalid hardware generation"); 7673 } 7674 } 7675 7676 7677 7678 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 7679 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 7680 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 7681 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 7682 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 7683 7684 static inline uint32_t ATTRIBUTE_PURE 7685 _3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start(const struct gen_device_info *devinfo) 7686 { 7687 switch (devinfo->gen) { 7688 case 10: return 0; 7689 case 9: return 0; 7690 case 8: return 0; 7691 case 7: 7692 if (devinfo->is_haswell) { 7693 return 0; 7694 } else { 7695 return 0; 7696 } 7697 case 6: return 0; 7698 case 5: return 0; 7699 case 4: 7700 if (devinfo->is_g4x) { 7701 return 0; 7702 } else { 7703 return 0; 7704 } 7705 default: 7706 unreachable("Invalid hardware generation"); 7707 } 7708 } 7709 7710 7711 7712 /* 3DSTATE_BINDING_TABLE_POINTERS_HS::Pointer to HS Binding Table */ 7713 7714 7715 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 7716 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 7717 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 7718 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 7719 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 7720 7721 static inline uint32_t ATTRIBUTE_PURE 7722 _3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits(const struct gen_device_info *devinfo) 7723 { 7724 switch (devinfo->gen) { 7725 case 10: return 11; 7726 case 9: return 11; 7727 case 8: return 11; 7728 case 7: 7729 if (devinfo->is_haswell) { 7730 return 11; 7731 } else { 7732 return 11; 7733 } 7734 case 6: return 0; 7735 case 5: return 0; 7736 case 4: 7737 if (devinfo->is_g4x) { 7738 return 0; 7739 } else { 7740 return 0; 7741 } 7742 default: 7743 unreachable("Invalid hardware generation"); 7744 } 7745 } 7746 7747 7748 7749 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 7750 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 7751 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 7752 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 7753 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 7754 7755 static inline uint32_t ATTRIBUTE_PURE 7756 _3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start(const struct gen_device_info *devinfo) 7757 { 7758 switch (devinfo->gen) { 7759 case 10: return 37; 7760 case 9: return 37; 7761 case 8: return 37; 7762 case 7: 7763 if (devinfo->is_haswell) { 7764 return 37; 7765 } else { 7766 return 37; 7767 } 7768 case 6: return 0; 7769 case 5: return 0; 7770 case 4: 7771 if (devinfo->is_g4x) { 7772 return 0; 7773 } else { 7774 return 0; 7775 } 7776 default: 7777 unreachable("Invalid hardware generation"); 7778 } 7779 } 7780 7781 7782 7783 /* 3DSTATE_BINDING_TABLE_POINTERS_PS */ 7784 7785 7786 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 7787 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 7788 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 7789 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 7790 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 7791 7792 static inline uint32_t ATTRIBUTE_PURE 7793 _3DSTATE_BINDING_TABLE_POINTERS_PS_length(const struct gen_device_info *devinfo) 7794 { 7795 switch (devinfo->gen) { 7796 case 10: return 2; 7797 case 9: return 2; 7798 case 8: return 2; 7799 case 7: 7800 if (devinfo->is_haswell) { 7801 return 2; 7802 } else { 7803 return 2; 7804 } 7805 case 6: return 0; 7806 case 5: return 0; 7807 case 4: 7808 if (devinfo->is_g4x) { 7809 return 0; 7810 } else { 7811 return 0; 7812 } 7813 default: 7814 unreachable("Invalid hardware generation"); 7815 } 7816 } 7817 7818 7819 7820 /* 3DSTATE_BINDING_TABLE_POINTERS_PS::3D Command Opcode */ 7821 7822 7823 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 7824 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 7825 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 7826 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 7827 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 7828 7829 static inline uint32_t ATTRIBUTE_PURE 7830 _3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 7831 { 7832 switch (devinfo->gen) { 7833 case 10: return 3; 7834 case 9: return 3; 7835 case 8: return 3; 7836 case 7: 7837 if (devinfo->is_haswell) { 7838 return 3; 7839 } else { 7840 return 3; 7841 } 7842 case 6: return 0; 7843 case 5: return 0; 7844 case 4: 7845 if (devinfo->is_g4x) { 7846 return 0; 7847 } else { 7848 return 0; 7849 } 7850 default: 7851 unreachable("Invalid hardware generation"); 7852 } 7853 } 7854 7855 7856 7857 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 7858 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 7859 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 7860 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 7861 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 7862 7863 static inline uint32_t ATTRIBUTE_PURE 7864 _3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 7865 { 7866 switch (devinfo->gen) { 7867 case 10: return 24; 7868 case 9: return 24; 7869 case 8: return 24; 7870 case 7: 7871 if (devinfo->is_haswell) { 7872 return 24; 7873 } else { 7874 return 24; 7875 } 7876 case 6: return 0; 7877 case 5: return 0; 7878 case 4: 7879 if (devinfo->is_g4x) { 7880 return 0; 7881 } else { 7882 return 0; 7883 } 7884 default: 7885 unreachable("Invalid hardware generation"); 7886 } 7887 } 7888 7889 7890 7891 /* 3DSTATE_BINDING_TABLE_POINTERS_PS::3D Command Sub Opcode */ 7892 7893 7894 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 7895 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 7896 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 7897 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 7898 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 7899 7900 static inline uint32_t ATTRIBUTE_PURE 7901 _3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 7902 { 7903 switch (devinfo->gen) { 7904 case 10: return 8; 7905 case 9: return 8; 7906 case 8: return 8; 7907 case 7: 7908 if (devinfo->is_haswell) { 7909 return 8; 7910 } else { 7911 return 8; 7912 } 7913 case 6: return 0; 7914 case 5: return 0; 7915 case 4: 7916 if (devinfo->is_g4x) { 7917 return 0; 7918 } else { 7919 return 0; 7920 } 7921 default: 7922 unreachable("Invalid hardware generation"); 7923 } 7924 } 7925 7926 7927 7928 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 7929 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 7930 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 7931 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 7932 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 7933 7934 static inline uint32_t ATTRIBUTE_PURE 7935 _3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 7936 { 7937 switch (devinfo->gen) { 7938 case 10: return 16; 7939 case 9: return 16; 7940 case 8: return 16; 7941 case 7: 7942 if (devinfo->is_haswell) { 7943 return 16; 7944 } else { 7945 return 16; 7946 } 7947 case 6: return 0; 7948 case 5: return 0; 7949 case 4: 7950 if (devinfo->is_g4x) { 7951 return 0; 7952 } else { 7953 return 0; 7954 } 7955 default: 7956 unreachable("Invalid hardware generation"); 7957 } 7958 } 7959 7960 7961 7962 /* 3DSTATE_BINDING_TABLE_POINTERS_PS::Command SubType */ 7963 7964 7965 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 7966 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 7967 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 7968 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 7969 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 7970 7971 static inline uint32_t ATTRIBUTE_PURE 7972 _3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits(const struct gen_device_info *devinfo) 7973 { 7974 switch (devinfo->gen) { 7975 case 10: return 2; 7976 case 9: return 2; 7977 case 8: return 2; 7978 case 7: 7979 if (devinfo->is_haswell) { 7980 return 2; 7981 } else { 7982 return 2; 7983 } 7984 case 6: return 0; 7985 case 5: return 0; 7986 case 4: 7987 if (devinfo->is_g4x) { 7988 return 0; 7989 } else { 7990 return 0; 7991 } 7992 default: 7993 unreachable("Invalid hardware generation"); 7994 } 7995 } 7996 7997 7998 7999 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 8000 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 8001 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 8002 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 8003 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 8004 8005 static inline uint32_t ATTRIBUTE_PURE 8006 _3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start(const struct gen_device_info *devinfo) 8007 { 8008 switch (devinfo->gen) { 8009 case 10: return 27; 8010 case 9: return 27; 8011 case 8: return 27; 8012 case 7: 8013 if (devinfo->is_haswell) { 8014 return 27; 8015 } else { 8016 return 27; 8017 } 8018 case 6: return 0; 8019 case 5: return 0; 8020 case 4: 8021 if (devinfo->is_g4x) { 8022 return 0; 8023 } else { 8024 return 0; 8025 } 8026 default: 8027 unreachable("Invalid hardware generation"); 8028 } 8029 } 8030 8031 8032 8033 /* 3DSTATE_BINDING_TABLE_POINTERS_PS::Command Type */ 8034 8035 8036 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 8037 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 8038 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 8039 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 8040 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 8041 8042 static inline uint32_t ATTRIBUTE_PURE 8043 _3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits(const struct gen_device_info *devinfo) 8044 { 8045 switch (devinfo->gen) { 8046 case 10: return 3; 8047 case 9: return 3; 8048 case 8: return 3; 8049 case 7: 8050 if (devinfo->is_haswell) { 8051 return 3; 8052 } else { 8053 return 3; 8054 } 8055 case 6: return 0; 8056 case 5: return 0; 8057 case 4: 8058 if (devinfo->is_g4x) { 8059 return 0; 8060 } else { 8061 return 0; 8062 } 8063 default: 8064 unreachable("Invalid hardware generation"); 8065 } 8066 } 8067 8068 8069 8070 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 8071 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 8072 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 8073 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 8074 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 8075 8076 static inline uint32_t ATTRIBUTE_PURE 8077 _3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start(const struct gen_device_info *devinfo) 8078 { 8079 switch (devinfo->gen) { 8080 case 10: return 29; 8081 case 9: return 29; 8082 case 8: return 29; 8083 case 7: 8084 if (devinfo->is_haswell) { 8085 return 29; 8086 } else { 8087 return 29; 8088 } 8089 case 6: return 0; 8090 case 5: return 0; 8091 case 4: 8092 if (devinfo->is_g4x) { 8093 return 0; 8094 } else { 8095 return 0; 8096 } 8097 default: 8098 unreachable("Invalid hardware generation"); 8099 } 8100 } 8101 8102 8103 8104 /* 3DSTATE_BINDING_TABLE_POINTERS_PS::DWord Length */ 8105 8106 8107 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 8108 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 8109 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 8110 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 8111 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 8112 8113 static inline uint32_t ATTRIBUTE_PURE 8114 _3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits(const struct gen_device_info *devinfo) 8115 { 8116 switch (devinfo->gen) { 8117 case 10: return 8; 8118 case 9: return 8; 8119 case 8: return 8; 8120 case 7: 8121 if (devinfo->is_haswell) { 8122 return 8; 8123 } else { 8124 return 8; 8125 } 8126 case 6: return 0; 8127 case 5: return 0; 8128 case 4: 8129 if (devinfo->is_g4x) { 8130 return 0; 8131 } else { 8132 return 0; 8133 } 8134 default: 8135 unreachable("Invalid hardware generation"); 8136 } 8137 } 8138 8139 8140 8141 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 8142 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 8143 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 8144 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 8145 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 8146 8147 static inline uint32_t ATTRIBUTE_PURE 8148 _3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start(const struct gen_device_info *devinfo) 8149 { 8150 switch (devinfo->gen) { 8151 case 10: return 0; 8152 case 9: return 0; 8153 case 8: return 0; 8154 case 7: 8155 if (devinfo->is_haswell) { 8156 return 0; 8157 } else { 8158 return 0; 8159 } 8160 case 6: return 0; 8161 case 5: return 0; 8162 case 4: 8163 if (devinfo->is_g4x) { 8164 return 0; 8165 } else { 8166 return 0; 8167 } 8168 default: 8169 unreachable("Invalid hardware generation"); 8170 } 8171 } 8172 8173 8174 8175 /* 3DSTATE_BINDING_TABLE_POINTERS_PS::Pointer to PS Binding Table */ 8176 8177 8178 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 8179 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 8180 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 8181 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 8182 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 8183 8184 static inline uint32_t ATTRIBUTE_PURE 8185 _3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits(const struct gen_device_info *devinfo) 8186 { 8187 switch (devinfo->gen) { 8188 case 10: return 11; 8189 case 9: return 11; 8190 case 8: return 11; 8191 case 7: 8192 if (devinfo->is_haswell) { 8193 return 11; 8194 } else { 8195 return 11; 8196 } 8197 case 6: return 0; 8198 case 5: return 0; 8199 case 4: 8200 if (devinfo->is_g4x) { 8201 return 0; 8202 } else { 8203 return 0; 8204 } 8205 default: 8206 unreachable("Invalid hardware generation"); 8207 } 8208 } 8209 8210 8211 8212 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 8213 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 8214 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 8215 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 8216 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 8217 8218 static inline uint32_t ATTRIBUTE_PURE 8219 _3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start(const struct gen_device_info *devinfo) 8220 { 8221 switch (devinfo->gen) { 8222 case 10: return 37; 8223 case 9: return 37; 8224 case 8: return 37; 8225 case 7: 8226 if (devinfo->is_haswell) { 8227 return 37; 8228 } else { 8229 return 37; 8230 } 8231 case 6: return 0; 8232 case 5: return 0; 8233 case 4: 8234 if (devinfo->is_g4x) { 8235 return 0; 8236 } else { 8237 return 0; 8238 } 8239 default: 8240 unreachable("Invalid hardware generation"); 8241 } 8242 } 8243 8244 8245 8246 /* 3DSTATE_BINDING_TABLE_POINTERS_VS */ 8247 8248 8249 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 8250 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 8251 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 8252 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 8253 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 8254 8255 static inline uint32_t ATTRIBUTE_PURE 8256 _3DSTATE_BINDING_TABLE_POINTERS_VS_length(const struct gen_device_info *devinfo) 8257 { 8258 switch (devinfo->gen) { 8259 case 10: return 2; 8260 case 9: return 2; 8261 case 8: return 2; 8262 case 7: 8263 if (devinfo->is_haswell) { 8264 return 2; 8265 } else { 8266 return 2; 8267 } 8268 case 6: return 0; 8269 case 5: return 0; 8270 case 4: 8271 if (devinfo->is_g4x) { 8272 return 0; 8273 } else { 8274 return 0; 8275 } 8276 default: 8277 unreachable("Invalid hardware generation"); 8278 } 8279 } 8280 8281 8282 8283 /* 3DSTATE_BINDING_TABLE_POINTERS_VS::3D Command Opcode */ 8284 8285 8286 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 8287 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 8288 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 8289 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 8290 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 8291 8292 static inline uint32_t ATTRIBUTE_PURE 8293 _3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 8294 { 8295 switch (devinfo->gen) { 8296 case 10: return 3; 8297 case 9: return 3; 8298 case 8: return 3; 8299 case 7: 8300 if (devinfo->is_haswell) { 8301 return 3; 8302 } else { 8303 return 3; 8304 } 8305 case 6: return 0; 8306 case 5: return 0; 8307 case 4: 8308 if (devinfo->is_g4x) { 8309 return 0; 8310 } else { 8311 return 0; 8312 } 8313 default: 8314 unreachable("Invalid hardware generation"); 8315 } 8316 } 8317 8318 8319 8320 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 8321 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 8322 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 8323 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 8324 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 8325 8326 static inline uint32_t ATTRIBUTE_PURE 8327 _3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 8328 { 8329 switch (devinfo->gen) { 8330 case 10: return 24; 8331 case 9: return 24; 8332 case 8: return 24; 8333 case 7: 8334 if (devinfo->is_haswell) { 8335 return 24; 8336 } else { 8337 return 24; 8338 } 8339 case 6: return 0; 8340 case 5: return 0; 8341 case 4: 8342 if (devinfo->is_g4x) { 8343 return 0; 8344 } else { 8345 return 0; 8346 } 8347 default: 8348 unreachable("Invalid hardware generation"); 8349 } 8350 } 8351 8352 8353 8354 /* 3DSTATE_BINDING_TABLE_POINTERS_VS::3D Command Sub Opcode */ 8355 8356 8357 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 8358 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 8359 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 8360 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 8361 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 8362 8363 static inline uint32_t ATTRIBUTE_PURE 8364 _3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 8365 { 8366 switch (devinfo->gen) { 8367 case 10: return 8; 8368 case 9: return 8; 8369 case 8: return 8; 8370 case 7: 8371 if (devinfo->is_haswell) { 8372 return 8; 8373 } else { 8374 return 8; 8375 } 8376 case 6: return 0; 8377 case 5: return 0; 8378 case 4: 8379 if (devinfo->is_g4x) { 8380 return 0; 8381 } else { 8382 return 0; 8383 } 8384 default: 8385 unreachable("Invalid hardware generation"); 8386 } 8387 } 8388 8389 8390 8391 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 8392 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 8393 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 8394 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 8395 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 8396 8397 static inline uint32_t ATTRIBUTE_PURE 8398 _3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 8399 { 8400 switch (devinfo->gen) { 8401 case 10: return 16; 8402 case 9: return 16; 8403 case 8: return 16; 8404 case 7: 8405 if (devinfo->is_haswell) { 8406 return 16; 8407 } else { 8408 return 16; 8409 } 8410 case 6: return 0; 8411 case 5: return 0; 8412 case 4: 8413 if (devinfo->is_g4x) { 8414 return 0; 8415 } else { 8416 return 0; 8417 } 8418 default: 8419 unreachable("Invalid hardware generation"); 8420 } 8421 } 8422 8423 8424 8425 /* 3DSTATE_BINDING_TABLE_POINTERS_VS::Command SubType */ 8426 8427 8428 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 8429 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 8430 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 8431 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 8432 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 8433 8434 static inline uint32_t ATTRIBUTE_PURE 8435 _3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits(const struct gen_device_info *devinfo) 8436 { 8437 switch (devinfo->gen) { 8438 case 10: return 2; 8439 case 9: return 2; 8440 case 8: return 2; 8441 case 7: 8442 if (devinfo->is_haswell) { 8443 return 2; 8444 } else { 8445 return 2; 8446 } 8447 case 6: return 0; 8448 case 5: return 0; 8449 case 4: 8450 if (devinfo->is_g4x) { 8451 return 0; 8452 } else { 8453 return 0; 8454 } 8455 default: 8456 unreachable("Invalid hardware generation"); 8457 } 8458 } 8459 8460 8461 8462 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 8463 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 8464 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 8465 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 8466 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 8467 8468 static inline uint32_t ATTRIBUTE_PURE 8469 _3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start(const struct gen_device_info *devinfo) 8470 { 8471 switch (devinfo->gen) { 8472 case 10: return 27; 8473 case 9: return 27; 8474 case 8: return 27; 8475 case 7: 8476 if (devinfo->is_haswell) { 8477 return 27; 8478 } else { 8479 return 27; 8480 } 8481 case 6: return 0; 8482 case 5: return 0; 8483 case 4: 8484 if (devinfo->is_g4x) { 8485 return 0; 8486 } else { 8487 return 0; 8488 } 8489 default: 8490 unreachable("Invalid hardware generation"); 8491 } 8492 } 8493 8494 8495 8496 /* 3DSTATE_BINDING_TABLE_POINTERS_VS::Command Type */ 8497 8498 8499 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 8500 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 8501 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 8502 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 8503 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 8504 8505 static inline uint32_t ATTRIBUTE_PURE 8506 _3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits(const struct gen_device_info *devinfo) 8507 { 8508 switch (devinfo->gen) { 8509 case 10: return 3; 8510 case 9: return 3; 8511 case 8: return 3; 8512 case 7: 8513 if (devinfo->is_haswell) { 8514 return 3; 8515 } else { 8516 return 3; 8517 } 8518 case 6: return 0; 8519 case 5: return 0; 8520 case 4: 8521 if (devinfo->is_g4x) { 8522 return 0; 8523 } else { 8524 return 0; 8525 } 8526 default: 8527 unreachable("Invalid hardware generation"); 8528 } 8529 } 8530 8531 8532 8533 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 8534 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 8535 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 8536 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 8537 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 8538 8539 static inline uint32_t ATTRIBUTE_PURE 8540 _3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start(const struct gen_device_info *devinfo) 8541 { 8542 switch (devinfo->gen) { 8543 case 10: return 29; 8544 case 9: return 29; 8545 case 8: return 29; 8546 case 7: 8547 if (devinfo->is_haswell) { 8548 return 29; 8549 } else { 8550 return 29; 8551 } 8552 case 6: return 0; 8553 case 5: return 0; 8554 case 4: 8555 if (devinfo->is_g4x) { 8556 return 0; 8557 } else { 8558 return 0; 8559 } 8560 default: 8561 unreachable("Invalid hardware generation"); 8562 } 8563 } 8564 8565 8566 8567 /* 3DSTATE_BINDING_TABLE_POINTERS_VS::DWord Length */ 8568 8569 8570 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 8571 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 8572 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 8573 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 8574 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 8575 8576 static inline uint32_t ATTRIBUTE_PURE 8577 _3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits(const struct gen_device_info *devinfo) 8578 { 8579 switch (devinfo->gen) { 8580 case 10: return 8; 8581 case 9: return 8; 8582 case 8: return 8; 8583 case 7: 8584 if (devinfo->is_haswell) { 8585 return 8; 8586 } else { 8587 return 8; 8588 } 8589 case 6: return 0; 8590 case 5: return 0; 8591 case 4: 8592 if (devinfo->is_g4x) { 8593 return 0; 8594 } else { 8595 return 0; 8596 } 8597 default: 8598 unreachable("Invalid hardware generation"); 8599 } 8600 } 8601 8602 8603 8604 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 8605 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 8606 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 8607 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 8608 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 8609 8610 static inline uint32_t ATTRIBUTE_PURE 8611 _3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start(const struct gen_device_info *devinfo) 8612 { 8613 switch (devinfo->gen) { 8614 case 10: return 0; 8615 case 9: return 0; 8616 case 8: return 0; 8617 case 7: 8618 if (devinfo->is_haswell) { 8619 return 0; 8620 } else { 8621 return 0; 8622 } 8623 case 6: return 0; 8624 case 5: return 0; 8625 case 4: 8626 if (devinfo->is_g4x) { 8627 return 0; 8628 } else { 8629 return 0; 8630 } 8631 default: 8632 unreachable("Invalid hardware generation"); 8633 } 8634 } 8635 8636 8637 8638 /* 3DSTATE_BINDING_TABLE_POINTERS_VS::Pointer to VS Binding Table */ 8639 8640 8641 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 8642 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 8643 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 8644 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 8645 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 8646 8647 static inline uint32_t ATTRIBUTE_PURE 8648 _3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits(const struct gen_device_info *devinfo) 8649 { 8650 switch (devinfo->gen) { 8651 case 10: return 11; 8652 case 9: return 11; 8653 case 8: return 11; 8654 case 7: 8655 if (devinfo->is_haswell) { 8656 return 11; 8657 } else { 8658 return 11; 8659 } 8660 case 6: return 0; 8661 case 5: return 0; 8662 case 4: 8663 if (devinfo->is_g4x) { 8664 return 0; 8665 } else { 8666 return 0; 8667 } 8668 default: 8669 unreachable("Invalid hardware generation"); 8670 } 8671 } 8672 8673 8674 8675 #define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 8676 #define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 8677 #define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 8678 #define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 8679 #define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 8680 8681 static inline uint32_t ATTRIBUTE_PURE 8682 _3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start(const struct gen_device_info *devinfo) 8683 { 8684 switch (devinfo->gen) { 8685 case 10: return 37; 8686 case 9: return 37; 8687 case 8: return 37; 8688 case 7: 8689 if (devinfo->is_haswell) { 8690 return 37; 8691 } else { 8692 return 37; 8693 } 8694 case 6: return 0; 8695 case 5: return 0; 8696 case 4: 8697 if (devinfo->is_g4x) { 8698 return 0; 8699 } else { 8700 return 0; 8701 } 8702 default: 8703 unreachable("Invalid hardware generation"); 8704 } 8705 } 8706 8707 8708 8709 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC */ 8710 8711 8712 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 8713 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 8714 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 8715 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 3 8716 8717 static inline uint32_t ATTRIBUTE_PURE 8718 _3DSTATE_BINDING_TABLE_POOL_ALLOC_length(const struct gen_device_info *devinfo) 8719 { 8720 switch (devinfo->gen) { 8721 case 10: return 4; 8722 case 9: return 4; 8723 case 8: return 4; 8724 case 7: 8725 if (devinfo->is_haswell) { 8726 return 3; 8727 } else { 8728 return 0; 8729 } 8730 case 6: return 0; 8731 case 5: return 0; 8732 case 4: 8733 if (devinfo->is_g4x) { 8734 return 0; 8735 } else { 8736 return 0; 8737 } 8738 default: 8739 unreachable("Invalid hardware generation"); 8740 } 8741 } 8742 8743 8744 8745 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::3D Command Opcode */ 8746 8747 8748 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 8749 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 8750 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 8751 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 8752 8753 static inline uint32_t ATTRIBUTE_PURE 8754 _3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 8755 { 8756 switch (devinfo->gen) { 8757 case 10: return 3; 8758 case 9: return 3; 8759 case 8: return 3; 8760 case 7: 8761 if (devinfo->is_haswell) { 8762 return 3; 8763 } else { 8764 return 0; 8765 } 8766 case 6: return 0; 8767 case 5: return 0; 8768 case 4: 8769 if (devinfo->is_g4x) { 8770 return 0; 8771 } else { 8772 return 0; 8773 } 8774 default: 8775 unreachable("Invalid hardware generation"); 8776 } 8777 } 8778 8779 8780 8781 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 8782 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 8783 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 8784 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 8785 8786 static inline uint32_t ATTRIBUTE_PURE 8787 _3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start(const struct gen_device_info *devinfo) 8788 { 8789 switch (devinfo->gen) { 8790 case 10: return 24; 8791 case 9: return 24; 8792 case 8: return 24; 8793 case 7: 8794 if (devinfo->is_haswell) { 8795 return 24; 8796 } else { 8797 return 0; 8798 } 8799 case 6: return 0; 8800 case 5: return 0; 8801 case 4: 8802 if (devinfo->is_g4x) { 8803 return 0; 8804 } else { 8805 return 0; 8806 } 8807 default: 8808 unreachable("Invalid hardware generation"); 8809 } 8810 } 8811 8812 8813 8814 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::3D Command Sub Opcode */ 8815 8816 8817 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 8818 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 8819 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 8820 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 8821 8822 static inline uint32_t ATTRIBUTE_PURE 8823 _3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 8824 { 8825 switch (devinfo->gen) { 8826 case 10: return 8; 8827 case 9: return 8; 8828 case 8: return 8; 8829 case 7: 8830 if (devinfo->is_haswell) { 8831 return 8; 8832 } else { 8833 return 0; 8834 } 8835 case 6: return 0; 8836 case 5: return 0; 8837 case 4: 8838 if (devinfo->is_g4x) { 8839 return 0; 8840 } else { 8841 return 0; 8842 } 8843 default: 8844 unreachable("Invalid hardware generation"); 8845 } 8846 } 8847 8848 8849 8850 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 8851 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 8852 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 8853 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 8854 8855 static inline uint32_t ATTRIBUTE_PURE 8856 _3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 8857 { 8858 switch (devinfo->gen) { 8859 case 10: return 16; 8860 case 9: return 16; 8861 case 8: return 16; 8862 case 7: 8863 if (devinfo->is_haswell) { 8864 return 16; 8865 } else { 8866 return 0; 8867 } 8868 case 6: return 0; 8869 case 5: return 0; 8870 case 4: 8871 if (devinfo->is_g4x) { 8872 return 0; 8873 } else { 8874 return 0; 8875 } 8876 default: 8877 unreachable("Invalid hardware generation"); 8878 } 8879 } 8880 8881 8882 8883 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Base Address */ 8884 8885 8886 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 8887 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 8888 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 8889 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 20 8890 8891 static inline uint32_t ATTRIBUTE_PURE 8892 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits(const struct gen_device_info *devinfo) 8893 { 8894 switch (devinfo->gen) { 8895 case 10: return 52; 8896 case 9: return 52; 8897 case 8: return 52; 8898 case 7: 8899 if (devinfo->is_haswell) { 8900 return 20; 8901 } else { 8902 return 0; 8903 } 8904 case 6: return 0; 8905 case 5: return 0; 8906 case 4: 8907 if (devinfo->is_g4x) { 8908 return 0; 8909 } else { 8910 return 0; 8911 } 8912 default: 8913 unreachable("Invalid hardware generation"); 8914 } 8915 } 8916 8917 8918 8919 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 8920 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 8921 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 8922 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 8923 8924 static inline uint32_t ATTRIBUTE_PURE 8925 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start(const struct gen_device_info *devinfo) 8926 { 8927 switch (devinfo->gen) { 8928 case 10: return 44; 8929 case 9: return 44; 8930 case 8: return 44; 8931 case 7: 8932 if (devinfo->is_haswell) { 8933 return 44; 8934 } else { 8935 return 0; 8936 } 8937 case 6: return 0; 8938 case 5: return 0; 8939 case 4: 8940 if (devinfo->is_g4x) { 8941 return 0; 8942 } else { 8943 return 0; 8944 } 8945 default: 8946 unreachable("Invalid hardware generation"); 8947 } 8948 } 8949 8950 8951 8952 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Buffer Size */ 8953 8954 8955 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 8956 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 8957 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 8958 8959 static inline uint32_t ATTRIBUTE_PURE 8960 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits(const struct gen_device_info *devinfo) 8961 { 8962 switch (devinfo->gen) { 8963 case 10: return 20; 8964 case 9: return 20; 8965 case 8: return 20; 8966 case 7: 8967 if (devinfo->is_haswell) { 8968 return 0; 8969 } else { 8970 return 0; 8971 } 8972 case 6: return 0; 8973 case 5: return 0; 8974 case 4: 8975 if (devinfo->is_g4x) { 8976 return 0; 8977 } else { 8978 return 0; 8979 } 8980 default: 8981 unreachable("Invalid hardware generation"); 8982 } 8983 } 8984 8985 8986 8987 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 8988 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 8989 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 8990 8991 static inline uint32_t ATTRIBUTE_PURE 8992 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start(const struct gen_device_info *devinfo) 8993 { 8994 switch (devinfo->gen) { 8995 case 10: return 108; 8996 case 9: return 108; 8997 case 8: return 108; 8998 case 7: 8999 if (devinfo->is_haswell) { 9000 return 0; 9001 } else { 9002 return 0; 9003 } 9004 case 6: return 0; 9005 case 5: return 0; 9006 case 4: 9007 if (devinfo->is_g4x) { 9008 return 0; 9009 } else { 9010 return 0; 9011 } 9012 default: 9013 unreachable("Invalid hardware generation"); 9014 } 9015 } 9016 9017 9018 9019 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Enable */ 9020 9021 9022 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 9023 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 9024 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 9025 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 9026 9027 static inline uint32_t ATTRIBUTE_PURE 9028 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits(const struct gen_device_info *devinfo) 9029 { 9030 switch (devinfo->gen) { 9031 case 10: return 1; 9032 case 9: return 1; 9033 case 8: return 1; 9034 case 7: 9035 if (devinfo->is_haswell) { 9036 return 1; 9037 } else { 9038 return 0; 9039 } 9040 case 6: return 0; 9041 case 5: return 0; 9042 case 4: 9043 if (devinfo->is_g4x) { 9044 return 0; 9045 } else { 9046 return 0; 9047 } 9048 default: 9049 unreachable("Invalid hardware generation"); 9050 } 9051 } 9052 9053 9054 9055 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 9056 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 9057 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 9058 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 9059 9060 static inline uint32_t ATTRIBUTE_PURE 9061 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start(const struct gen_device_info *devinfo) 9062 { 9063 switch (devinfo->gen) { 9064 case 10: return 43; 9065 case 9: return 43; 9066 case 8: return 43; 9067 case 7: 9068 if (devinfo->is_haswell) { 9069 return 43; 9070 } else { 9071 return 0; 9072 } 9073 case 6: return 0; 9074 case 5: return 0; 9075 case 4: 9076 if (devinfo->is_g4x) { 9077 return 0; 9078 } else { 9079 return 0; 9080 } 9081 default: 9082 unreachable("Invalid hardware generation"); 9083 } 9084 } 9085 9086 9087 9088 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Upper Bound */ 9089 9090 9091 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_bits 20 9092 9093 static inline uint32_t ATTRIBUTE_PURE 9094 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_bits(const struct gen_device_info *devinfo) 9095 { 9096 switch (devinfo->gen) { 9097 case 10: return 0; 9098 case 9: return 0; 9099 case 8: return 0; 9100 case 7: 9101 if (devinfo->is_haswell) { 9102 return 20; 9103 } else { 9104 return 0; 9105 } 9106 case 6: return 0; 9107 case 5: return 0; 9108 case 4: 9109 if (devinfo->is_g4x) { 9110 return 0; 9111 } else { 9112 return 0; 9113 } 9114 default: 9115 unreachable("Invalid hardware generation"); 9116 } 9117 } 9118 9119 9120 9121 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_start 76 9122 9123 static inline uint32_t ATTRIBUTE_PURE 9124 _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_start(const struct gen_device_info *devinfo) 9125 { 9126 switch (devinfo->gen) { 9127 case 10: return 0; 9128 case 9: return 0; 9129 case 8: return 0; 9130 case 7: 9131 if (devinfo->is_haswell) { 9132 return 76; 9133 } else { 9134 return 0; 9135 } 9136 case 6: return 0; 9137 case 5: return 0; 9138 case 4: 9139 if (devinfo->is_g4x) { 9140 return 0; 9141 } else { 9142 return 0; 9143 } 9144 default: 9145 unreachable("Invalid hardware generation"); 9146 } 9147 } 9148 9149 9150 9151 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Command SubType */ 9152 9153 9154 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 9155 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 9156 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 9157 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 9158 9159 static inline uint32_t ATTRIBUTE_PURE 9160 _3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits(const struct gen_device_info *devinfo) 9161 { 9162 switch (devinfo->gen) { 9163 case 10: return 2; 9164 case 9: return 2; 9165 case 8: return 2; 9166 case 7: 9167 if (devinfo->is_haswell) { 9168 return 2; 9169 } else { 9170 return 0; 9171 } 9172 case 6: return 0; 9173 case 5: return 0; 9174 case 4: 9175 if (devinfo->is_g4x) { 9176 return 0; 9177 } else { 9178 return 0; 9179 } 9180 default: 9181 unreachable("Invalid hardware generation"); 9182 } 9183 } 9184 9185 9186 9187 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 9188 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 9189 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 9190 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 9191 9192 static inline uint32_t ATTRIBUTE_PURE 9193 _3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start(const struct gen_device_info *devinfo) 9194 { 9195 switch (devinfo->gen) { 9196 case 10: return 27; 9197 case 9: return 27; 9198 case 8: return 27; 9199 case 7: 9200 if (devinfo->is_haswell) { 9201 return 27; 9202 } else { 9203 return 0; 9204 } 9205 case 6: return 0; 9206 case 5: return 0; 9207 case 4: 9208 if (devinfo->is_g4x) { 9209 return 0; 9210 } else { 9211 return 0; 9212 } 9213 default: 9214 unreachable("Invalid hardware generation"); 9215 } 9216 } 9217 9218 9219 9220 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Command Type */ 9221 9222 9223 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 9224 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 9225 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 9226 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 9227 9228 static inline uint32_t ATTRIBUTE_PURE 9229 _3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits(const struct gen_device_info *devinfo) 9230 { 9231 switch (devinfo->gen) { 9232 case 10: return 3; 9233 case 9: return 3; 9234 case 8: return 3; 9235 case 7: 9236 if (devinfo->is_haswell) { 9237 return 3; 9238 } else { 9239 return 0; 9240 } 9241 case 6: return 0; 9242 case 5: return 0; 9243 case 4: 9244 if (devinfo->is_g4x) { 9245 return 0; 9246 } else { 9247 return 0; 9248 } 9249 default: 9250 unreachable("Invalid hardware generation"); 9251 } 9252 } 9253 9254 9255 9256 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 9257 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 9258 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 9259 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 9260 9261 static inline uint32_t ATTRIBUTE_PURE 9262 _3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start(const struct gen_device_info *devinfo) 9263 { 9264 switch (devinfo->gen) { 9265 case 10: return 29; 9266 case 9: return 29; 9267 case 8: return 29; 9268 case 7: 9269 if (devinfo->is_haswell) { 9270 return 29; 9271 } else { 9272 return 0; 9273 } 9274 case 6: return 0; 9275 case 5: return 0; 9276 case 4: 9277 if (devinfo->is_g4x) { 9278 return 0; 9279 } else { 9280 return 0; 9281 } 9282 default: 9283 unreachable("Invalid hardware generation"); 9284 } 9285 } 9286 9287 9288 9289 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::DWord Length */ 9290 9291 9292 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 9293 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 9294 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 9295 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 9296 9297 static inline uint32_t ATTRIBUTE_PURE 9298 _3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits(const struct gen_device_info *devinfo) 9299 { 9300 switch (devinfo->gen) { 9301 case 10: return 8; 9302 case 9: return 8; 9303 case 8: return 8; 9304 case 7: 9305 if (devinfo->is_haswell) { 9306 return 8; 9307 } else { 9308 return 0; 9309 } 9310 case 6: return 0; 9311 case 5: return 0; 9312 case 4: 9313 if (devinfo->is_g4x) { 9314 return 0; 9315 } else { 9316 return 0; 9317 } 9318 default: 9319 unreachable("Invalid hardware generation"); 9320 } 9321 } 9322 9323 9324 9325 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 9326 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 9327 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 9328 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 9329 9330 static inline uint32_t ATTRIBUTE_PURE 9331 _3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start(const struct gen_device_info *devinfo) 9332 { 9333 switch (devinfo->gen) { 9334 case 10: return 0; 9335 case 9: return 0; 9336 case 8: return 0; 9337 case 7: 9338 if (devinfo->is_haswell) { 9339 return 0; 9340 } else { 9341 return 0; 9342 } 9343 case 6: return 0; 9344 case 5: return 0; 9345 case 4: 9346 if (devinfo->is_g4x) { 9347 return 0; 9348 } else { 9349 return 0; 9350 } 9351 default: 9352 unreachable("Invalid hardware generation"); 9353 } 9354 } 9355 9356 9357 9358 /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Surface Object Control State */ 9359 9360 9361 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 7 9362 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 7 9363 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 7 9364 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 4 9365 9366 static inline uint32_t ATTRIBUTE_PURE 9367 _3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits(const struct gen_device_info *devinfo) 9368 { 9369 switch (devinfo->gen) { 9370 case 10: return 7; 9371 case 9: return 7; 9372 case 8: return 7; 9373 case 7: 9374 if (devinfo->is_haswell) { 9375 return 4; 9376 } else { 9377 return 0; 9378 } 9379 case 6: return 0; 9380 case 5: return 0; 9381 case 4: 9382 if (devinfo->is_g4x) { 9383 return 0; 9384 } else { 9385 return 0; 9386 } 9387 default: 9388 unreachable("Invalid hardware generation"); 9389 } 9390 } 9391 9392 9393 9394 #define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 32 9395 #define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 32 9396 #define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 32 9397 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 39 9398 9399 static inline uint32_t ATTRIBUTE_PURE 9400 _3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start(const struct gen_device_info *devinfo) 9401 { 9402 switch (devinfo->gen) { 9403 case 10: return 32; 9404 case 9: return 32; 9405 case 8: return 32; 9406 case 7: 9407 if (devinfo->is_haswell) { 9408 return 39; 9409 } else { 9410 return 0; 9411 } 9412 case 6: return 0; 9413 case 5: return 0; 9414 case 4: 9415 if (devinfo->is_g4x) { 9416 return 0; 9417 } else { 9418 return 0; 9419 } 9420 default: 9421 unreachable("Invalid hardware generation"); 9422 } 9423 } 9424 9425 9426 9427 /* 3DSTATE_BLEND_STATE_POINTERS */ 9428 9429 9430 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_length 2 9431 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_length 2 9432 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_length 2 9433 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_length 2 9434 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_length 2 9435 9436 static inline uint32_t ATTRIBUTE_PURE 9437 _3DSTATE_BLEND_STATE_POINTERS_length(const struct gen_device_info *devinfo) 9438 { 9439 switch (devinfo->gen) { 9440 case 10: return 2; 9441 case 9: return 2; 9442 case 8: return 2; 9443 case 7: 9444 if (devinfo->is_haswell) { 9445 return 2; 9446 } else { 9447 return 2; 9448 } 9449 case 6: return 0; 9450 case 5: return 0; 9451 case 4: 9452 if (devinfo->is_g4x) { 9453 return 0; 9454 } else { 9455 return 0; 9456 } 9457 default: 9458 unreachable("Invalid hardware generation"); 9459 } 9460 } 9461 9462 9463 9464 /* 3DSTATE_BLEND_STATE_POINTERS::3D Command Opcode */ 9465 9466 9467 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 9468 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 9469 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 9470 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 9471 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 9472 9473 static inline uint32_t ATTRIBUTE_PURE 9474 _3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 9475 { 9476 switch (devinfo->gen) { 9477 case 10: return 3; 9478 case 9: return 3; 9479 case 8: return 3; 9480 case 7: 9481 if (devinfo->is_haswell) { 9482 return 3; 9483 } else { 9484 return 3; 9485 } 9486 case 6: return 0; 9487 case 5: return 0; 9488 case 4: 9489 if (devinfo->is_g4x) { 9490 return 0; 9491 } else { 9492 return 0; 9493 } 9494 default: 9495 unreachable("Invalid hardware generation"); 9496 } 9497 } 9498 9499 9500 9501 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 9502 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 9503 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 9504 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 9505 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 9506 9507 static inline uint32_t ATTRIBUTE_PURE 9508 _3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 9509 { 9510 switch (devinfo->gen) { 9511 case 10: return 24; 9512 case 9: return 24; 9513 case 8: return 24; 9514 case 7: 9515 if (devinfo->is_haswell) { 9516 return 24; 9517 } else { 9518 return 24; 9519 } 9520 case 6: return 0; 9521 case 5: return 0; 9522 case 4: 9523 if (devinfo->is_g4x) { 9524 return 0; 9525 } else { 9526 return 0; 9527 } 9528 default: 9529 unreachable("Invalid hardware generation"); 9530 } 9531 } 9532 9533 9534 9535 /* 3DSTATE_BLEND_STATE_POINTERS::3D Command Sub Opcode */ 9536 9537 9538 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 9539 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 9540 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 9541 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 9542 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 9543 9544 static inline uint32_t ATTRIBUTE_PURE 9545 _3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 9546 { 9547 switch (devinfo->gen) { 9548 case 10: return 8; 9549 case 9: return 8; 9550 case 8: return 8; 9551 case 7: 9552 if (devinfo->is_haswell) { 9553 return 8; 9554 } else { 9555 return 8; 9556 } 9557 case 6: return 0; 9558 case 5: return 0; 9559 case 4: 9560 if (devinfo->is_g4x) { 9561 return 0; 9562 } else { 9563 return 0; 9564 } 9565 default: 9566 unreachable("Invalid hardware generation"); 9567 } 9568 } 9569 9570 9571 9572 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 9573 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 9574 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 9575 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 9576 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 9577 9578 static inline uint32_t ATTRIBUTE_PURE 9579 _3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 9580 { 9581 switch (devinfo->gen) { 9582 case 10: return 16; 9583 case 9: return 16; 9584 case 8: return 16; 9585 case 7: 9586 if (devinfo->is_haswell) { 9587 return 16; 9588 } else { 9589 return 16; 9590 } 9591 case 6: return 0; 9592 case 5: return 0; 9593 case 4: 9594 if (devinfo->is_g4x) { 9595 return 0; 9596 } else { 9597 return 0; 9598 } 9599 default: 9600 unreachable("Invalid hardware generation"); 9601 } 9602 } 9603 9604 9605 9606 /* 3DSTATE_BLEND_STATE_POINTERS::Blend State Pointer */ 9607 9608 9609 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 9610 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 9611 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 9612 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 9613 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 9614 9615 static inline uint32_t ATTRIBUTE_PURE 9616 _3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits(const struct gen_device_info *devinfo) 9617 { 9618 switch (devinfo->gen) { 9619 case 10: return 26; 9620 case 9: return 26; 9621 case 8: return 26; 9622 case 7: 9623 if (devinfo->is_haswell) { 9624 return 26; 9625 } else { 9626 return 26; 9627 } 9628 case 6: return 0; 9629 case 5: return 0; 9630 case 4: 9631 if (devinfo->is_g4x) { 9632 return 0; 9633 } else { 9634 return 0; 9635 } 9636 default: 9637 unreachable("Invalid hardware generation"); 9638 } 9639 } 9640 9641 9642 9643 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 9644 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 9645 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 9646 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 9647 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 9648 9649 static inline uint32_t ATTRIBUTE_PURE 9650 _3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start(const struct gen_device_info *devinfo) 9651 { 9652 switch (devinfo->gen) { 9653 case 10: return 38; 9654 case 9: return 38; 9655 case 8: return 38; 9656 case 7: 9657 if (devinfo->is_haswell) { 9658 return 38; 9659 } else { 9660 return 38; 9661 } 9662 case 6: return 0; 9663 case 5: return 0; 9664 case 4: 9665 if (devinfo->is_g4x) { 9666 return 0; 9667 } else { 9668 return 0; 9669 } 9670 default: 9671 unreachable("Invalid hardware generation"); 9672 } 9673 } 9674 9675 9676 9677 /* 3DSTATE_BLEND_STATE_POINTERS::Blend State Pointer Valid */ 9678 9679 9680 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 9681 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 9682 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 9683 9684 static inline uint32_t ATTRIBUTE_PURE 9685 _3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits(const struct gen_device_info *devinfo) 9686 { 9687 switch (devinfo->gen) { 9688 case 10: return 1; 9689 case 9: return 1; 9690 case 8: return 1; 9691 case 7: 9692 if (devinfo->is_haswell) { 9693 return 0; 9694 } else { 9695 return 0; 9696 } 9697 case 6: return 0; 9698 case 5: return 0; 9699 case 4: 9700 if (devinfo->is_g4x) { 9701 return 0; 9702 } else { 9703 return 0; 9704 } 9705 default: 9706 unreachable("Invalid hardware generation"); 9707 } 9708 } 9709 9710 9711 9712 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 9713 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 9714 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 9715 9716 static inline uint32_t ATTRIBUTE_PURE 9717 _3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start(const struct gen_device_info *devinfo) 9718 { 9719 switch (devinfo->gen) { 9720 case 10: return 32; 9721 case 9: return 32; 9722 case 8: return 32; 9723 case 7: 9724 if (devinfo->is_haswell) { 9725 return 0; 9726 } else { 9727 return 0; 9728 } 9729 case 6: return 0; 9730 case 5: return 0; 9731 case 4: 9732 if (devinfo->is_g4x) { 9733 return 0; 9734 } else { 9735 return 0; 9736 } 9737 default: 9738 unreachable("Invalid hardware generation"); 9739 } 9740 } 9741 9742 9743 9744 /* 3DSTATE_BLEND_STATE_POINTERS::Command SubType */ 9745 9746 9747 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 9748 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 9749 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 9750 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 9751 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 9752 9753 static inline uint32_t ATTRIBUTE_PURE 9754 _3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) 9755 { 9756 switch (devinfo->gen) { 9757 case 10: return 2; 9758 case 9: return 2; 9759 case 8: return 2; 9760 case 7: 9761 if (devinfo->is_haswell) { 9762 return 2; 9763 } else { 9764 return 2; 9765 } 9766 case 6: return 0; 9767 case 5: return 0; 9768 case 4: 9769 if (devinfo->is_g4x) { 9770 return 0; 9771 } else { 9772 return 0; 9773 } 9774 default: 9775 unreachable("Invalid hardware generation"); 9776 } 9777 } 9778 9779 9780 9781 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 9782 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 9783 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 9784 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 9785 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 9786 9787 static inline uint32_t ATTRIBUTE_PURE 9788 _3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) 9789 { 9790 switch (devinfo->gen) { 9791 case 10: return 27; 9792 case 9: return 27; 9793 case 8: return 27; 9794 case 7: 9795 if (devinfo->is_haswell) { 9796 return 27; 9797 } else { 9798 return 27; 9799 } 9800 case 6: return 0; 9801 case 5: return 0; 9802 case 4: 9803 if (devinfo->is_g4x) { 9804 return 0; 9805 } else { 9806 return 0; 9807 } 9808 default: 9809 unreachable("Invalid hardware generation"); 9810 } 9811 } 9812 9813 9814 9815 /* 3DSTATE_BLEND_STATE_POINTERS::Command Type */ 9816 9817 9818 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 9819 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 9820 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 9821 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 9822 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 9823 9824 static inline uint32_t ATTRIBUTE_PURE 9825 _3DSTATE_BLEND_STATE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) 9826 { 9827 switch (devinfo->gen) { 9828 case 10: return 3; 9829 case 9: return 3; 9830 case 8: return 3; 9831 case 7: 9832 if (devinfo->is_haswell) { 9833 return 3; 9834 } else { 9835 return 3; 9836 } 9837 case 6: return 0; 9838 case 5: return 0; 9839 case 4: 9840 if (devinfo->is_g4x) { 9841 return 0; 9842 } else { 9843 return 0; 9844 } 9845 default: 9846 unreachable("Invalid hardware generation"); 9847 } 9848 } 9849 9850 9851 9852 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 9853 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 9854 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 9855 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 9856 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 9857 9858 static inline uint32_t ATTRIBUTE_PURE 9859 _3DSTATE_BLEND_STATE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) 9860 { 9861 switch (devinfo->gen) { 9862 case 10: return 29; 9863 case 9: return 29; 9864 case 8: return 29; 9865 case 7: 9866 if (devinfo->is_haswell) { 9867 return 29; 9868 } else { 9869 return 29; 9870 } 9871 case 6: return 0; 9872 case 5: return 0; 9873 case 4: 9874 if (devinfo->is_g4x) { 9875 return 0; 9876 } else { 9877 return 0; 9878 } 9879 default: 9880 unreachable("Invalid hardware generation"); 9881 } 9882 } 9883 9884 9885 9886 /* 3DSTATE_BLEND_STATE_POINTERS::DWord Length */ 9887 9888 9889 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 9890 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 9891 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 9892 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 9893 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 9894 9895 static inline uint32_t ATTRIBUTE_PURE 9896 _3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) 9897 { 9898 switch (devinfo->gen) { 9899 case 10: return 8; 9900 case 9: return 8; 9901 case 8: return 8; 9902 case 7: 9903 if (devinfo->is_haswell) { 9904 return 8; 9905 } else { 9906 return 8; 9907 } 9908 case 6: return 0; 9909 case 5: return 0; 9910 case 4: 9911 if (devinfo->is_g4x) { 9912 return 0; 9913 } else { 9914 return 0; 9915 } 9916 default: 9917 unreachable("Invalid hardware generation"); 9918 } 9919 } 9920 9921 9922 9923 #define GEN10_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 9924 #define GEN9_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 9925 #define GEN8_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 9926 #define GEN75_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 9927 #define GEN7_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 9928 9929 static inline uint32_t ATTRIBUTE_PURE 9930 _3DSTATE_BLEND_STATE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) 9931 { 9932 switch (devinfo->gen) { 9933 case 10: return 0; 9934 case 9: return 0; 9935 case 8: return 0; 9936 case 7: 9937 if (devinfo->is_haswell) { 9938 return 0; 9939 } else { 9940 return 0; 9941 } 9942 case 6: return 0; 9943 case 5: return 0; 9944 case 4: 9945 if (devinfo->is_g4x) { 9946 return 0; 9947 } else { 9948 return 0; 9949 } 9950 default: 9951 unreachable("Invalid hardware generation"); 9952 } 9953 } 9954 9955 9956 9957 /* 3DSTATE_CC_STATE_POINTERS */ 9958 9959 9960 #define GEN10_3DSTATE_CC_STATE_POINTERS_length 2 9961 #define GEN9_3DSTATE_CC_STATE_POINTERS_length 2 9962 #define GEN8_3DSTATE_CC_STATE_POINTERS_length 2 9963 #define GEN75_3DSTATE_CC_STATE_POINTERS_length 2 9964 #define GEN7_3DSTATE_CC_STATE_POINTERS_length 2 9965 #define GEN6_3DSTATE_CC_STATE_POINTERS_length 4 9966 9967 static inline uint32_t ATTRIBUTE_PURE 9968 _3DSTATE_CC_STATE_POINTERS_length(const struct gen_device_info *devinfo) 9969 { 9970 switch (devinfo->gen) { 9971 case 10: return 2; 9972 case 9: return 2; 9973 case 8: return 2; 9974 case 7: 9975 if (devinfo->is_haswell) { 9976 return 2; 9977 } else { 9978 return 2; 9979 } 9980 case 6: return 4; 9981 case 5: return 0; 9982 case 4: 9983 if (devinfo->is_g4x) { 9984 return 0; 9985 } else { 9986 return 0; 9987 } 9988 default: 9989 unreachable("Invalid hardware generation"); 9990 } 9991 } 9992 9993 9994 9995 /* 3DSTATE_CC_STATE_POINTERS::3D Command Opcode */ 9996 9997 9998 #define GEN10_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 9999 #define GEN9_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 10000 #define GEN8_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 10001 #define GEN75_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 10002 #define GEN7_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 10003 #define GEN6_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 10004 10005 static inline uint32_t ATTRIBUTE_PURE 10006 _3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 10007 { 10008 switch (devinfo->gen) { 10009 case 10: return 3; 10010 case 9: return 3; 10011 case 8: return 3; 10012 case 7: 10013 if (devinfo->is_haswell) { 10014 return 3; 10015 } else { 10016 return 3; 10017 } 10018 case 6: return 3; 10019 case 5: return 0; 10020 case 4: 10021 if (devinfo->is_g4x) { 10022 return 0; 10023 } else { 10024 return 0; 10025 } 10026 default: 10027 unreachable("Invalid hardware generation"); 10028 } 10029 } 10030 10031 10032 10033 #define GEN10_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 10034 #define GEN9_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 10035 #define GEN8_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 10036 #define GEN75_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 10037 #define GEN7_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 10038 #define GEN6_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 10039 10040 static inline uint32_t ATTRIBUTE_PURE 10041 _3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 10042 { 10043 switch (devinfo->gen) { 10044 case 10: return 24; 10045 case 9: return 24; 10046 case 8: return 24; 10047 case 7: 10048 if (devinfo->is_haswell) { 10049 return 24; 10050 } else { 10051 return 24; 10052 } 10053 case 6: return 24; 10054 case 5: return 0; 10055 case 4: 10056 if (devinfo->is_g4x) { 10057 return 0; 10058 } else { 10059 return 0; 10060 } 10061 default: 10062 unreachable("Invalid hardware generation"); 10063 } 10064 } 10065 10066 10067 10068 /* 3DSTATE_CC_STATE_POINTERS::3D Command Sub Opcode */ 10069 10070 10071 #define GEN10_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 10072 #define GEN9_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 10073 #define GEN8_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 10074 #define GEN75_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 10075 #define GEN7_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 10076 #define GEN6_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 10077 10078 static inline uint32_t ATTRIBUTE_PURE 10079 _3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 10080 { 10081 switch (devinfo->gen) { 10082 case 10: return 8; 10083 case 9: return 8; 10084 case 8: return 8; 10085 case 7: 10086 if (devinfo->is_haswell) { 10087 return 8; 10088 } else { 10089 return 8; 10090 } 10091 case 6: return 8; 10092 case 5: return 0; 10093 case 4: 10094 if (devinfo->is_g4x) { 10095 return 0; 10096 } else { 10097 return 0; 10098 } 10099 default: 10100 unreachable("Invalid hardware generation"); 10101 } 10102 } 10103 10104 10105 10106 #define GEN10_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 10107 #define GEN9_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 10108 #define GEN8_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 10109 #define GEN75_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 10110 #define GEN7_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 10111 #define GEN6_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 10112 10113 static inline uint32_t ATTRIBUTE_PURE 10114 _3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 10115 { 10116 switch (devinfo->gen) { 10117 case 10: return 16; 10118 case 9: return 16; 10119 case 8: return 16; 10120 case 7: 10121 if (devinfo->is_haswell) { 10122 return 16; 10123 } else { 10124 return 16; 10125 } 10126 case 6: return 16; 10127 case 5: return 0; 10128 case 4: 10129 if (devinfo->is_g4x) { 10130 return 0; 10131 } else { 10132 return 0; 10133 } 10134 default: 10135 unreachable("Invalid hardware generation"); 10136 } 10137 } 10138 10139 10140 10141 /* 3DSTATE_CC_STATE_POINTERS::BLEND_STATE Change */ 10142 10143 10144 #define GEN6_3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_bits 1 10145 10146 static inline uint32_t ATTRIBUTE_PURE 10147 _3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_bits(const struct gen_device_info *devinfo) 10148 { 10149 switch (devinfo->gen) { 10150 case 10: return 0; 10151 case 9: return 0; 10152 case 8: return 0; 10153 case 7: 10154 if (devinfo->is_haswell) { 10155 return 0; 10156 } else { 10157 return 0; 10158 } 10159 case 6: return 1; 10160 case 5: return 0; 10161 case 4: 10162 if (devinfo->is_g4x) { 10163 return 0; 10164 } else { 10165 return 0; 10166 } 10167 default: 10168 unreachable("Invalid hardware generation"); 10169 } 10170 } 10171 10172 10173 10174 #define GEN6_3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_start 32 10175 10176 static inline uint32_t ATTRIBUTE_PURE 10177 _3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_start(const struct gen_device_info *devinfo) 10178 { 10179 switch (devinfo->gen) { 10180 case 10: return 0; 10181 case 9: return 0; 10182 case 8: return 0; 10183 case 7: 10184 if (devinfo->is_haswell) { 10185 return 0; 10186 } else { 10187 return 0; 10188 } 10189 case 6: return 32; 10190 case 5: return 0; 10191 case 4: 10192 if (devinfo->is_g4x) { 10193 return 0; 10194 } else { 10195 return 0; 10196 } 10197 default: 10198 unreachable("Invalid hardware generation"); 10199 } 10200 } 10201 10202 10203 10204 /* 3DSTATE_CC_STATE_POINTERS::Color Calc State Pointer */ 10205 10206 10207 #define GEN10_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 10208 #define GEN9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 10209 #define GEN8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 10210 #define GEN75_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 10211 #define GEN7_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 10212 #define GEN6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 10213 10214 static inline uint32_t ATTRIBUTE_PURE 10215 _3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits(const struct gen_device_info *devinfo) 10216 { 10217 switch (devinfo->gen) { 10218 case 10: return 26; 10219 case 9: return 26; 10220 case 8: return 26; 10221 case 7: 10222 if (devinfo->is_haswell) { 10223 return 26; 10224 } else { 10225 return 26; 10226 } 10227 case 6: return 26; 10228 case 5: return 0; 10229 case 4: 10230 if (devinfo->is_g4x) { 10231 return 0; 10232 } else { 10233 return 0; 10234 } 10235 default: 10236 unreachable("Invalid hardware generation"); 10237 } 10238 } 10239 10240 10241 10242 #define GEN10_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 10243 #define GEN9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 10244 #define GEN8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 10245 #define GEN75_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 10246 #define GEN7_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 10247 #define GEN6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 102 10248 10249 static inline uint32_t ATTRIBUTE_PURE 10250 _3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start(const struct gen_device_info *devinfo) 10251 { 10252 switch (devinfo->gen) { 10253 case 10: return 38; 10254 case 9: return 38; 10255 case 8: return 38; 10256 case 7: 10257 if (devinfo->is_haswell) { 10258 return 38; 10259 } else { 10260 return 38; 10261 } 10262 case 6: return 102; 10263 case 5: return 0; 10264 case 4: 10265 if (devinfo->is_g4x) { 10266 return 0; 10267 } else { 10268 return 0; 10269 } 10270 default: 10271 unreachable("Invalid hardware generation"); 10272 } 10273 } 10274 10275 10276 10277 /* 3DSTATE_CC_STATE_POINTERS::Color Calc State Pointer Valid */ 10278 10279 10280 #define GEN10_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 10281 #define GEN9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 10282 #define GEN8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 10283 #define GEN6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 10284 10285 static inline uint32_t ATTRIBUTE_PURE 10286 _3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits(const struct gen_device_info *devinfo) 10287 { 10288 switch (devinfo->gen) { 10289 case 10: return 1; 10290 case 9: return 1; 10291 case 8: return 1; 10292 case 7: 10293 if (devinfo->is_haswell) { 10294 return 0; 10295 } else { 10296 return 0; 10297 } 10298 case 6: return 1; 10299 case 5: return 0; 10300 case 4: 10301 if (devinfo->is_g4x) { 10302 return 0; 10303 } else { 10304 return 0; 10305 } 10306 default: 10307 unreachable("Invalid hardware generation"); 10308 } 10309 } 10310 10311 10312 10313 #define GEN10_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 10314 #define GEN9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 10315 #define GEN8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 10316 #define GEN6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 96 10317 10318 static inline uint32_t ATTRIBUTE_PURE 10319 _3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start(const struct gen_device_info *devinfo) 10320 { 10321 switch (devinfo->gen) { 10322 case 10: return 32; 10323 case 9: return 32; 10324 case 8: return 32; 10325 case 7: 10326 if (devinfo->is_haswell) { 10327 return 0; 10328 } else { 10329 return 0; 10330 } 10331 case 6: return 96; 10332 case 5: return 0; 10333 case 4: 10334 if (devinfo->is_g4x) { 10335 return 0; 10336 } else { 10337 return 0; 10338 } 10339 default: 10340 unreachable("Invalid hardware generation"); 10341 } 10342 } 10343 10344 10345 10346 /* 3DSTATE_CC_STATE_POINTERS::Command SubType */ 10347 10348 10349 #define GEN10_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 10350 #define GEN9_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 10351 #define GEN8_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 10352 #define GEN75_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 10353 #define GEN7_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 10354 #define GEN6_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 10355 10356 static inline uint32_t ATTRIBUTE_PURE 10357 _3DSTATE_CC_STATE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) 10358 { 10359 switch (devinfo->gen) { 10360 case 10: return 2; 10361 case 9: return 2; 10362 case 8: return 2; 10363 case 7: 10364 if (devinfo->is_haswell) { 10365 return 2; 10366 } else { 10367 return 2; 10368 } 10369 case 6: return 2; 10370 case 5: return 0; 10371 case 4: 10372 if (devinfo->is_g4x) { 10373 return 0; 10374 } else { 10375 return 0; 10376 } 10377 default: 10378 unreachable("Invalid hardware generation"); 10379 } 10380 } 10381 10382 10383 10384 #define GEN10_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 10385 #define GEN9_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 10386 #define GEN8_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 10387 #define GEN75_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 10388 #define GEN7_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 10389 #define GEN6_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 10390 10391 static inline uint32_t ATTRIBUTE_PURE 10392 _3DSTATE_CC_STATE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) 10393 { 10394 switch (devinfo->gen) { 10395 case 10: return 27; 10396 case 9: return 27; 10397 case 8: return 27; 10398 case 7: 10399 if (devinfo->is_haswell) { 10400 return 27; 10401 } else { 10402 return 27; 10403 } 10404 case 6: return 27; 10405 case 5: return 0; 10406 case 4: 10407 if (devinfo->is_g4x) { 10408 return 0; 10409 } else { 10410 return 0; 10411 } 10412 default: 10413 unreachable("Invalid hardware generation"); 10414 } 10415 } 10416 10417 10418 10419 /* 3DSTATE_CC_STATE_POINTERS::Command Type */ 10420 10421 10422 #define GEN10_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 10423 #define GEN9_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 10424 #define GEN8_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 10425 #define GEN75_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 10426 #define GEN7_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 10427 #define GEN6_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 10428 10429 static inline uint32_t ATTRIBUTE_PURE 10430 _3DSTATE_CC_STATE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) 10431 { 10432 switch (devinfo->gen) { 10433 case 10: return 3; 10434 case 9: return 3; 10435 case 8: return 3; 10436 case 7: 10437 if (devinfo->is_haswell) { 10438 return 3; 10439 } else { 10440 return 3; 10441 } 10442 case 6: return 3; 10443 case 5: return 0; 10444 case 4: 10445 if (devinfo->is_g4x) { 10446 return 0; 10447 } else { 10448 return 0; 10449 } 10450 default: 10451 unreachable("Invalid hardware generation"); 10452 } 10453 } 10454 10455 10456 10457 #define GEN10_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 10458 #define GEN9_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 10459 #define GEN8_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 10460 #define GEN75_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 10461 #define GEN7_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 10462 #define GEN6_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 10463 10464 static inline uint32_t ATTRIBUTE_PURE 10465 _3DSTATE_CC_STATE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) 10466 { 10467 switch (devinfo->gen) { 10468 case 10: return 29; 10469 case 9: return 29; 10470 case 8: return 29; 10471 case 7: 10472 if (devinfo->is_haswell) { 10473 return 29; 10474 } else { 10475 return 29; 10476 } 10477 case 6: return 29; 10478 case 5: return 0; 10479 case 4: 10480 if (devinfo->is_g4x) { 10481 return 0; 10482 } else { 10483 return 0; 10484 } 10485 default: 10486 unreachable("Invalid hardware generation"); 10487 } 10488 } 10489 10490 10491 10492 /* 3DSTATE_CC_STATE_POINTERS::DEPTH_STENCIL_STATE Change */ 10493 10494 10495 #define GEN6_3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_bits 1 10496 10497 static inline uint32_t ATTRIBUTE_PURE 10498 _3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_bits(const struct gen_device_info *devinfo) 10499 { 10500 switch (devinfo->gen) { 10501 case 10: return 0; 10502 case 9: return 0; 10503 case 8: return 0; 10504 case 7: 10505 if (devinfo->is_haswell) { 10506 return 0; 10507 } else { 10508 return 0; 10509 } 10510 case 6: return 1; 10511 case 5: return 0; 10512 case 4: 10513 if (devinfo->is_g4x) { 10514 return 0; 10515 } else { 10516 return 0; 10517 } 10518 default: 10519 unreachable("Invalid hardware generation"); 10520 } 10521 } 10522 10523 10524 10525 #define GEN6_3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_start 64 10526 10527 static inline uint32_t ATTRIBUTE_PURE 10528 _3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_start(const struct gen_device_info *devinfo) 10529 { 10530 switch (devinfo->gen) { 10531 case 10: return 0; 10532 case 9: return 0; 10533 case 8: return 0; 10534 case 7: 10535 if (devinfo->is_haswell) { 10536 return 0; 10537 } else { 10538 return 0; 10539 } 10540 case 6: return 64; 10541 case 5: return 0; 10542 case 4: 10543 if (devinfo->is_g4x) { 10544 return 0; 10545 } else { 10546 return 0; 10547 } 10548 default: 10549 unreachable("Invalid hardware generation"); 10550 } 10551 } 10552 10553 10554 10555 /* 3DSTATE_CC_STATE_POINTERS::DWord Length */ 10556 10557 10558 #define GEN10_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 10559 #define GEN9_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 10560 #define GEN8_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 10561 #define GEN75_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 10562 #define GEN7_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 10563 #define GEN6_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 10564 10565 static inline uint32_t ATTRIBUTE_PURE 10566 _3DSTATE_CC_STATE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) 10567 { 10568 switch (devinfo->gen) { 10569 case 10: return 8; 10570 case 9: return 8; 10571 case 8: return 8; 10572 case 7: 10573 if (devinfo->is_haswell) { 10574 return 8; 10575 } else { 10576 return 8; 10577 } 10578 case 6: return 8; 10579 case 5: return 0; 10580 case 4: 10581 if (devinfo->is_g4x) { 10582 return 0; 10583 } else { 10584 return 0; 10585 } 10586 default: 10587 unreachable("Invalid hardware generation"); 10588 } 10589 } 10590 10591 10592 10593 #define GEN10_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 10594 #define GEN9_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 10595 #define GEN8_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 10596 #define GEN75_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 10597 #define GEN7_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 10598 #define GEN6_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 10599 10600 static inline uint32_t ATTRIBUTE_PURE 10601 _3DSTATE_CC_STATE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) 10602 { 10603 switch (devinfo->gen) { 10604 case 10: return 0; 10605 case 9: return 0; 10606 case 8: return 0; 10607 case 7: 10608 if (devinfo->is_haswell) { 10609 return 0; 10610 } else { 10611 return 0; 10612 } 10613 case 6: return 0; 10614 case 5: return 0; 10615 case 4: 10616 if (devinfo->is_g4x) { 10617 return 0; 10618 } else { 10619 return 0; 10620 } 10621 default: 10622 unreachable("Invalid hardware generation"); 10623 } 10624 } 10625 10626 10627 10628 /* 3DSTATE_CC_STATE_POINTERS::Pointer to BLEND_STATE */ 10629 10630 10631 #define GEN6_3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_bits 26 10632 10633 static inline uint32_t ATTRIBUTE_PURE 10634 _3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_bits(const struct gen_device_info *devinfo) 10635 { 10636 switch (devinfo->gen) { 10637 case 10: return 0; 10638 case 9: return 0; 10639 case 8: return 0; 10640 case 7: 10641 if (devinfo->is_haswell) { 10642 return 0; 10643 } else { 10644 return 0; 10645 } 10646 case 6: return 26; 10647 case 5: return 0; 10648 case 4: 10649 if (devinfo->is_g4x) { 10650 return 0; 10651 } else { 10652 return 0; 10653 } 10654 default: 10655 unreachable("Invalid hardware generation"); 10656 } 10657 } 10658 10659 10660 10661 #define GEN6_3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_start 38 10662 10663 static inline uint32_t ATTRIBUTE_PURE 10664 _3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_start(const struct gen_device_info *devinfo) 10665 { 10666 switch (devinfo->gen) { 10667 case 10: return 0; 10668 case 9: return 0; 10669 case 8: return 0; 10670 case 7: 10671 if (devinfo->is_haswell) { 10672 return 0; 10673 } else { 10674 return 0; 10675 } 10676 case 6: return 38; 10677 case 5: return 0; 10678 case 4: 10679 if (devinfo->is_g4x) { 10680 return 0; 10681 } else { 10682 return 0; 10683 } 10684 default: 10685 unreachable("Invalid hardware generation"); 10686 } 10687 } 10688 10689 10690 10691 /* 3DSTATE_CC_STATE_POINTERS::Pointer to DEPTH_STENCIL_STATE */ 10692 10693 10694 #define GEN6_3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits 26 10695 10696 static inline uint32_t ATTRIBUTE_PURE 10697 _3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits(const struct gen_device_info *devinfo) 10698 { 10699 switch (devinfo->gen) { 10700 case 10: return 0; 10701 case 9: return 0; 10702 case 8: return 0; 10703 case 7: 10704 if (devinfo->is_haswell) { 10705 return 0; 10706 } else { 10707 return 0; 10708 } 10709 case 6: return 26; 10710 case 5: return 0; 10711 case 4: 10712 if (devinfo->is_g4x) { 10713 return 0; 10714 } else { 10715 return 0; 10716 } 10717 default: 10718 unreachable("Invalid hardware generation"); 10719 } 10720 } 10721 10722 10723 10724 #define GEN6_3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start 70 10725 10726 static inline uint32_t ATTRIBUTE_PURE 10727 _3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start(const struct gen_device_info *devinfo) 10728 { 10729 switch (devinfo->gen) { 10730 case 10: return 0; 10731 case 9: return 0; 10732 case 8: return 0; 10733 case 7: 10734 if (devinfo->is_haswell) { 10735 return 0; 10736 } else { 10737 return 0; 10738 } 10739 case 6: return 70; 10740 case 5: return 0; 10741 case 4: 10742 if (devinfo->is_g4x) { 10743 return 0; 10744 } else { 10745 return 0; 10746 } 10747 default: 10748 unreachable("Invalid hardware generation"); 10749 } 10750 } 10751 10752 10753 10754 /* 3DSTATE_CHROMA_KEY */ 10755 10756 10757 #define GEN10_3DSTATE_CHROMA_KEY_length 4 10758 #define GEN9_3DSTATE_CHROMA_KEY_length 4 10759 #define GEN8_3DSTATE_CHROMA_KEY_length 4 10760 #define GEN75_3DSTATE_CHROMA_KEY_length 4 10761 #define GEN7_3DSTATE_CHROMA_KEY_length 4 10762 #define GEN6_3DSTATE_CHROMA_KEY_length 4 10763 10764 static inline uint32_t ATTRIBUTE_PURE 10765 _3DSTATE_CHROMA_KEY_length(const struct gen_device_info *devinfo) 10766 { 10767 switch (devinfo->gen) { 10768 case 10: return 4; 10769 case 9: return 4; 10770 case 8: return 4; 10771 case 7: 10772 if (devinfo->is_haswell) { 10773 return 4; 10774 } else { 10775 return 4; 10776 } 10777 case 6: return 4; 10778 case 5: return 0; 10779 case 4: 10780 if (devinfo->is_g4x) { 10781 return 0; 10782 } else { 10783 return 0; 10784 } 10785 default: 10786 unreachable("Invalid hardware generation"); 10787 } 10788 } 10789 10790 10791 10792 /* 3DSTATE_CHROMA_KEY::3D Command Opcode */ 10793 10794 10795 #define GEN10_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 10796 #define GEN9_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 10797 #define GEN8_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 10798 #define GEN75_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 10799 #define GEN7_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 10800 #define GEN6_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 10801 10802 static inline uint32_t ATTRIBUTE_PURE 10803 _3DSTATE_CHROMA_KEY_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 10804 { 10805 switch (devinfo->gen) { 10806 case 10: return 3; 10807 case 9: return 3; 10808 case 8: return 3; 10809 case 7: 10810 if (devinfo->is_haswell) { 10811 return 3; 10812 } else { 10813 return 3; 10814 } 10815 case 6: return 3; 10816 case 5: return 0; 10817 case 4: 10818 if (devinfo->is_g4x) { 10819 return 0; 10820 } else { 10821 return 0; 10822 } 10823 default: 10824 unreachable("Invalid hardware generation"); 10825 } 10826 } 10827 10828 10829 10830 #define GEN10_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 10831 #define GEN9_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 10832 #define GEN8_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 10833 #define GEN75_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 10834 #define GEN7_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 10835 #define GEN6_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 10836 10837 static inline uint32_t ATTRIBUTE_PURE 10838 _3DSTATE_CHROMA_KEY_3DCommandOpcode_start(const struct gen_device_info *devinfo) 10839 { 10840 switch (devinfo->gen) { 10841 case 10: return 24; 10842 case 9: return 24; 10843 case 8: return 24; 10844 case 7: 10845 if (devinfo->is_haswell) { 10846 return 24; 10847 } else { 10848 return 24; 10849 } 10850 case 6: return 24; 10851 case 5: return 0; 10852 case 4: 10853 if (devinfo->is_g4x) { 10854 return 0; 10855 } else { 10856 return 0; 10857 } 10858 default: 10859 unreachable("Invalid hardware generation"); 10860 } 10861 } 10862 10863 10864 10865 /* 3DSTATE_CHROMA_KEY::3D Command Sub Opcode */ 10866 10867 10868 #define GEN10_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 10869 #define GEN9_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 10870 #define GEN8_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 10871 #define GEN75_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 10872 #define GEN7_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 10873 #define GEN6_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 10874 10875 static inline uint32_t ATTRIBUTE_PURE 10876 _3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 10877 { 10878 switch (devinfo->gen) { 10879 case 10: return 8; 10880 case 9: return 8; 10881 case 8: return 8; 10882 case 7: 10883 if (devinfo->is_haswell) { 10884 return 8; 10885 } else { 10886 return 8; 10887 } 10888 case 6: return 8; 10889 case 5: return 0; 10890 case 4: 10891 if (devinfo->is_g4x) { 10892 return 0; 10893 } else { 10894 return 0; 10895 } 10896 default: 10897 unreachable("Invalid hardware generation"); 10898 } 10899 } 10900 10901 10902 10903 #define GEN10_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 10904 #define GEN9_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 10905 #define GEN8_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 10906 #define GEN75_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 10907 #define GEN7_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 10908 #define GEN6_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 10909 10910 static inline uint32_t ATTRIBUTE_PURE 10911 _3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 10912 { 10913 switch (devinfo->gen) { 10914 case 10: return 16; 10915 case 9: return 16; 10916 case 8: return 16; 10917 case 7: 10918 if (devinfo->is_haswell) { 10919 return 16; 10920 } else { 10921 return 16; 10922 } 10923 case 6: return 16; 10924 case 5: return 0; 10925 case 4: 10926 if (devinfo->is_g4x) { 10927 return 0; 10928 } else { 10929 return 0; 10930 } 10931 default: 10932 unreachable("Invalid hardware generation"); 10933 } 10934 } 10935 10936 10937 10938 /* 3DSTATE_CHROMA_KEY::ChromaKey High Value */ 10939 10940 10941 #define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 10942 #define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 10943 #define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 10944 #define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 10945 #define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 10946 #define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 10947 10948 static inline uint32_t ATTRIBUTE_PURE 10949 _3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits(const struct gen_device_info *devinfo) 10950 { 10951 switch (devinfo->gen) { 10952 case 10: return 32; 10953 case 9: return 32; 10954 case 8: return 32; 10955 case 7: 10956 if (devinfo->is_haswell) { 10957 return 32; 10958 } else { 10959 return 32; 10960 } 10961 case 6: return 32; 10962 case 5: return 0; 10963 case 4: 10964 if (devinfo->is_g4x) { 10965 return 0; 10966 } else { 10967 return 0; 10968 } 10969 default: 10970 unreachable("Invalid hardware generation"); 10971 } 10972 } 10973 10974 10975 10976 #define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 10977 #define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 10978 #define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 10979 #define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 10980 #define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 10981 #define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 10982 10983 static inline uint32_t ATTRIBUTE_PURE 10984 _3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start(const struct gen_device_info *devinfo) 10985 { 10986 switch (devinfo->gen) { 10987 case 10: return 96; 10988 case 9: return 96; 10989 case 8: return 96; 10990 case 7: 10991 if (devinfo->is_haswell) { 10992 return 96; 10993 } else { 10994 return 96; 10995 } 10996 case 6: return 96; 10997 case 5: return 0; 10998 case 4: 10999 if (devinfo->is_g4x) { 11000 return 0; 11001 } else { 11002 return 0; 11003 } 11004 default: 11005 unreachable("Invalid hardware generation"); 11006 } 11007 } 11008 11009 11010 11011 /* 3DSTATE_CHROMA_KEY::ChromaKey Low Value */ 11012 11013 11014 #define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 11015 #define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 11016 #define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 11017 #define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 11018 #define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 11019 #define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 11020 11021 static inline uint32_t ATTRIBUTE_PURE 11022 _3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits(const struct gen_device_info *devinfo) 11023 { 11024 switch (devinfo->gen) { 11025 case 10: return 32; 11026 case 9: return 32; 11027 case 8: return 32; 11028 case 7: 11029 if (devinfo->is_haswell) { 11030 return 32; 11031 } else { 11032 return 32; 11033 } 11034 case 6: return 32; 11035 case 5: return 0; 11036 case 4: 11037 if (devinfo->is_g4x) { 11038 return 0; 11039 } else { 11040 return 0; 11041 } 11042 default: 11043 unreachable("Invalid hardware generation"); 11044 } 11045 } 11046 11047 11048 11049 #define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 11050 #define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 11051 #define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 11052 #define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 11053 #define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 11054 #define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 11055 11056 static inline uint32_t ATTRIBUTE_PURE 11057 _3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start(const struct gen_device_info *devinfo) 11058 { 11059 switch (devinfo->gen) { 11060 case 10: return 64; 11061 case 9: return 64; 11062 case 8: return 64; 11063 case 7: 11064 if (devinfo->is_haswell) { 11065 return 64; 11066 } else { 11067 return 64; 11068 } 11069 case 6: return 64; 11070 case 5: return 0; 11071 case 4: 11072 if (devinfo->is_g4x) { 11073 return 0; 11074 } else { 11075 return 0; 11076 } 11077 default: 11078 unreachable("Invalid hardware generation"); 11079 } 11080 } 11081 11082 11083 11084 /* 3DSTATE_CHROMA_KEY::ChromaKey Table Index */ 11085 11086 11087 #define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 11088 #define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 11089 #define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 11090 #define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 11091 #define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 11092 #define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 11093 11094 static inline uint32_t ATTRIBUTE_PURE 11095 _3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits(const struct gen_device_info *devinfo) 11096 { 11097 switch (devinfo->gen) { 11098 case 10: return 2; 11099 case 9: return 2; 11100 case 8: return 2; 11101 case 7: 11102 if (devinfo->is_haswell) { 11103 return 2; 11104 } else { 11105 return 2; 11106 } 11107 case 6: return 2; 11108 case 5: return 0; 11109 case 4: 11110 if (devinfo->is_g4x) { 11111 return 0; 11112 } else { 11113 return 0; 11114 } 11115 default: 11116 unreachable("Invalid hardware generation"); 11117 } 11118 } 11119 11120 11121 11122 #define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 11123 #define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 11124 #define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 11125 #define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 11126 #define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 11127 #define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 11128 11129 static inline uint32_t ATTRIBUTE_PURE 11130 _3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start(const struct gen_device_info *devinfo) 11131 { 11132 switch (devinfo->gen) { 11133 case 10: return 62; 11134 case 9: return 62; 11135 case 8: return 62; 11136 case 7: 11137 if (devinfo->is_haswell) { 11138 return 62; 11139 } else { 11140 return 62; 11141 } 11142 case 6: return 62; 11143 case 5: return 0; 11144 case 4: 11145 if (devinfo->is_g4x) { 11146 return 0; 11147 } else { 11148 return 0; 11149 } 11150 default: 11151 unreachable("Invalid hardware generation"); 11152 } 11153 } 11154 11155 11156 11157 /* 3DSTATE_CHROMA_KEY::Command SubType */ 11158 11159 11160 #define GEN10_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 11161 #define GEN9_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 11162 #define GEN8_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 11163 #define GEN75_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 11164 #define GEN7_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 11165 #define GEN6_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 11166 11167 static inline uint32_t ATTRIBUTE_PURE 11168 _3DSTATE_CHROMA_KEY_CommandSubType_bits(const struct gen_device_info *devinfo) 11169 { 11170 switch (devinfo->gen) { 11171 case 10: return 2; 11172 case 9: return 2; 11173 case 8: return 2; 11174 case 7: 11175 if (devinfo->is_haswell) { 11176 return 2; 11177 } else { 11178 return 2; 11179 } 11180 case 6: return 2; 11181 case 5: return 0; 11182 case 4: 11183 if (devinfo->is_g4x) { 11184 return 0; 11185 } else { 11186 return 0; 11187 } 11188 default: 11189 unreachable("Invalid hardware generation"); 11190 } 11191 } 11192 11193 11194 11195 #define GEN10_3DSTATE_CHROMA_KEY_CommandSubType_start 27 11196 #define GEN9_3DSTATE_CHROMA_KEY_CommandSubType_start 27 11197 #define GEN8_3DSTATE_CHROMA_KEY_CommandSubType_start 27 11198 #define GEN75_3DSTATE_CHROMA_KEY_CommandSubType_start 27 11199 #define GEN7_3DSTATE_CHROMA_KEY_CommandSubType_start 27 11200 #define GEN6_3DSTATE_CHROMA_KEY_CommandSubType_start 27 11201 11202 static inline uint32_t ATTRIBUTE_PURE 11203 _3DSTATE_CHROMA_KEY_CommandSubType_start(const struct gen_device_info *devinfo) 11204 { 11205 switch (devinfo->gen) { 11206 case 10: return 27; 11207 case 9: return 27; 11208 case 8: return 27; 11209 case 7: 11210 if (devinfo->is_haswell) { 11211 return 27; 11212 } else { 11213 return 27; 11214 } 11215 case 6: return 27; 11216 case 5: return 0; 11217 case 4: 11218 if (devinfo->is_g4x) { 11219 return 0; 11220 } else { 11221 return 0; 11222 } 11223 default: 11224 unreachable("Invalid hardware generation"); 11225 } 11226 } 11227 11228 11229 11230 /* 3DSTATE_CHROMA_KEY::Command Type */ 11231 11232 11233 #define GEN10_3DSTATE_CHROMA_KEY_CommandType_bits 3 11234 #define GEN9_3DSTATE_CHROMA_KEY_CommandType_bits 3 11235 #define GEN8_3DSTATE_CHROMA_KEY_CommandType_bits 3 11236 #define GEN75_3DSTATE_CHROMA_KEY_CommandType_bits 3 11237 #define GEN7_3DSTATE_CHROMA_KEY_CommandType_bits 3 11238 #define GEN6_3DSTATE_CHROMA_KEY_CommandType_bits 3 11239 11240 static inline uint32_t ATTRIBUTE_PURE 11241 _3DSTATE_CHROMA_KEY_CommandType_bits(const struct gen_device_info *devinfo) 11242 { 11243 switch (devinfo->gen) { 11244 case 10: return 3; 11245 case 9: return 3; 11246 case 8: return 3; 11247 case 7: 11248 if (devinfo->is_haswell) { 11249 return 3; 11250 } else { 11251 return 3; 11252 } 11253 case 6: return 3; 11254 case 5: return 0; 11255 case 4: 11256 if (devinfo->is_g4x) { 11257 return 0; 11258 } else { 11259 return 0; 11260 } 11261 default: 11262 unreachable("Invalid hardware generation"); 11263 } 11264 } 11265 11266 11267 11268 #define GEN10_3DSTATE_CHROMA_KEY_CommandType_start 29 11269 #define GEN9_3DSTATE_CHROMA_KEY_CommandType_start 29 11270 #define GEN8_3DSTATE_CHROMA_KEY_CommandType_start 29 11271 #define GEN75_3DSTATE_CHROMA_KEY_CommandType_start 29 11272 #define GEN7_3DSTATE_CHROMA_KEY_CommandType_start 29 11273 #define GEN6_3DSTATE_CHROMA_KEY_CommandType_start 29 11274 11275 static inline uint32_t ATTRIBUTE_PURE 11276 _3DSTATE_CHROMA_KEY_CommandType_start(const struct gen_device_info *devinfo) 11277 { 11278 switch (devinfo->gen) { 11279 case 10: return 29; 11280 case 9: return 29; 11281 case 8: return 29; 11282 case 7: 11283 if (devinfo->is_haswell) { 11284 return 29; 11285 } else { 11286 return 29; 11287 } 11288 case 6: return 29; 11289 case 5: return 0; 11290 case 4: 11291 if (devinfo->is_g4x) { 11292 return 0; 11293 } else { 11294 return 0; 11295 } 11296 default: 11297 unreachable("Invalid hardware generation"); 11298 } 11299 } 11300 11301 11302 11303 /* 3DSTATE_CHROMA_KEY::DWord Length */ 11304 11305 11306 #define GEN10_3DSTATE_CHROMA_KEY_DWordLength_bits 8 11307 #define GEN9_3DSTATE_CHROMA_KEY_DWordLength_bits 8 11308 #define GEN8_3DSTATE_CHROMA_KEY_DWordLength_bits 8 11309 #define GEN75_3DSTATE_CHROMA_KEY_DWordLength_bits 8 11310 #define GEN7_3DSTATE_CHROMA_KEY_DWordLength_bits 8 11311 #define GEN6_3DSTATE_CHROMA_KEY_DWordLength_bits 8 11312 11313 static inline uint32_t ATTRIBUTE_PURE 11314 _3DSTATE_CHROMA_KEY_DWordLength_bits(const struct gen_device_info *devinfo) 11315 { 11316 switch (devinfo->gen) { 11317 case 10: return 8; 11318 case 9: return 8; 11319 case 8: return 8; 11320 case 7: 11321 if (devinfo->is_haswell) { 11322 return 8; 11323 } else { 11324 return 8; 11325 } 11326 case 6: return 8; 11327 case 5: return 0; 11328 case 4: 11329 if (devinfo->is_g4x) { 11330 return 0; 11331 } else { 11332 return 0; 11333 } 11334 default: 11335 unreachable("Invalid hardware generation"); 11336 } 11337 } 11338 11339 11340 11341 #define GEN10_3DSTATE_CHROMA_KEY_DWordLength_start 0 11342 #define GEN9_3DSTATE_CHROMA_KEY_DWordLength_start 0 11343 #define GEN8_3DSTATE_CHROMA_KEY_DWordLength_start 0 11344 #define GEN75_3DSTATE_CHROMA_KEY_DWordLength_start 0 11345 #define GEN7_3DSTATE_CHROMA_KEY_DWordLength_start 0 11346 #define GEN6_3DSTATE_CHROMA_KEY_DWordLength_start 0 11347 11348 static inline uint32_t ATTRIBUTE_PURE 11349 _3DSTATE_CHROMA_KEY_DWordLength_start(const struct gen_device_info *devinfo) 11350 { 11351 switch (devinfo->gen) { 11352 case 10: return 0; 11353 case 9: return 0; 11354 case 8: return 0; 11355 case 7: 11356 if (devinfo->is_haswell) { 11357 return 0; 11358 } else { 11359 return 0; 11360 } 11361 case 6: return 0; 11362 case 5: return 0; 11363 case 4: 11364 if (devinfo->is_g4x) { 11365 return 0; 11366 } else { 11367 return 0; 11368 } 11369 default: 11370 unreachable("Invalid hardware generation"); 11371 } 11372 } 11373 11374 11375 11376 /* 3DSTATE_CLEAR_PARAMS */ 11377 11378 11379 #define GEN10_3DSTATE_CLEAR_PARAMS_length 3 11380 #define GEN9_3DSTATE_CLEAR_PARAMS_length 3 11381 #define GEN8_3DSTATE_CLEAR_PARAMS_length 3 11382 #define GEN75_3DSTATE_CLEAR_PARAMS_length 3 11383 #define GEN7_3DSTATE_CLEAR_PARAMS_length 3 11384 #define GEN6_3DSTATE_CLEAR_PARAMS_length 2 11385 #define GEN5_3DSTATE_CLEAR_PARAMS_length 2 11386 11387 static inline uint32_t ATTRIBUTE_PURE 11388 _3DSTATE_CLEAR_PARAMS_length(const struct gen_device_info *devinfo) 11389 { 11390 switch (devinfo->gen) { 11391 case 10: return 3; 11392 case 9: return 3; 11393 case 8: return 3; 11394 case 7: 11395 if (devinfo->is_haswell) { 11396 return 3; 11397 } else { 11398 return 3; 11399 } 11400 case 6: return 2; 11401 case 5: return 2; 11402 case 4: 11403 if (devinfo->is_g4x) { 11404 return 0; 11405 } else { 11406 return 0; 11407 } 11408 default: 11409 unreachable("Invalid hardware generation"); 11410 } 11411 } 11412 11413 11414 11415 /* 3DSTATE_CLEAR_PARAMS::3D Command Opcode */ 11416 11417 11418 #define GEN10_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11419 #define GEN9_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11420 #define GEN8_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11421 #define GEN75_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11422 #define GEN7_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11423 #define GEN6_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11424 #define GEN5_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 11425 11426 static inline uint32_t ATTRIBUTE_PURE 11427 _3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 11428 { 11429 switch (devinfo->gen) { 11430 case 10: return 3; 11431 case 9: return 3; 11432 case 8: return 3; 11433 case 7: 11434 if (devinfo->is_haswell) { 11435 return 3; 11436 } else { 11437 return 3; 11438 } 11439 case 6: return 3; 11440 case 5: return 3; 11441 case 4: 11442 if (devinfo->is_g4x) { 11443 return 0; 11444 } else { 11445 return 0; 11446 } 11447 default: 11448 unreachable("Invalid hardware generation"); 11449 } 11450 } 11451 11452 11453 11454 #define GEN10_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11455 #define GEN9_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11456 #define GEN8_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11457 #define GEN75_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11458 #define GEN7_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11459 #define GEN6_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11460 #define GEN5_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 11461 11462 static inline uint32_t ATTRIBUTE_PURE 11463 _3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 11464 { 11465 switch (devinfo->gen) { 11466 case 10: return 24; 11467 case 9: return 24; 11468 case 8: return 24; 11469 case 7: 11470 if (devinfo->is_haswell) { 11471 return 24; 11472 } else { 11473 return 24; 11474 } 11475 case 6: return 24; 11476 case 5: return 24; 11477 case 4: 11478 if (devinfo->is_g4x) { 11479 return 0; 11480 } else { 11481 return 0; 11482 } 11483 default: 11484 unreachable("Invalid hardware generation"); 11485 } 11486 } 11487 11488 11489 11490 /* 3DSTATE_CLEAR_PARAMS::3D Command Sub Opcode */ 11491 11492 11493 #define GEN10_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11494 #define GEN9_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11495 #define GEN8_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11496 #define GEN75_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11497 #define GEN7_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11498 #define GEN6_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11499 #define GEN5_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 11500 11501 static inline uint32_t ATTRIBUTE_PURE 11502 _3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 11503 { 11504 switch (devinfo->gen) { 11505 case 10: return 8; 11506 case 9: return 8; 11507 case 8: return 8; 11508 case 7: 11509 if (devinfo->is_haswell) { 11510 return 8; 11511 } else { 11512 return 8; 11513 } 11514 case 6: return 8; 11515 case 5: return 8; 11516 case 4: 11517 if (devinfo->is_g4x) { 11518 return 0; 11519 } else { 11520 return 0; 11521 } 11522 default: 11523 unreachable("Invalid hardware generation"); 11524 } 11525 } 11526 11527 11528 11529 #define GEN10_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11530 #define GEN9_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11531 #define GEN8_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11532 #define GEN75_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11533 #define GEN7_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11534 #define GEN6_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11535 #define GEN5_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 11536 11537 static inline uint32_t ATTRIBUTE_PURE 11538 _3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 11539 { 11540 switch (devinfo->gen) { 11541 case 10: return 16; 11542 case 9: return 16; 11543 case 8: return 16; 11544 case 7: 11545 if (devinfo->is_haswell) { 11546 return 16; 11547 } else { 11548 return 16; 11549 } 11550 case 6: return 16; 11551 case 5: return 16; 11552 case 4: 11553 if (devinfo->is_g4x) { 11554 return 0; 11555 } else { 11556 return 0; 11557 } 11558 default: 11559 unreachable("Invalid hardware generation"); 11560 } 11561 } 11562 11563 11564 11565 /* 3DSTATE_CLEAR_PARAMS::Command SubType */ 11566 11567 11568 #define GEN10_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11569 #define GEN9_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11570 #define GEN8_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11571 #define GEN75_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11572 #define GEN7_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11573 #define GEN6_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11574 #define GEN5_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 11575 11576 static inline uint32_t ATTRIBUTE_PURE 11577 _3DSTATE_CLEAR_PARAMS_CommandSubType_bits(const struct gen_device_info *devinfo) 11578 { 11579 switch (devinfo->gen) { 11580 case 10: return 2; 11581 case 9: return 2; 11582 case 8: return 2; 11583 case 7: 11584 if (devinfo->is_haswell) { 11585 return 2; 11586 } else { 11587 return 2; 11588 } 11589 case 6: return 2; 11590 case 5: return 2; 11591 case 4: 11592 if (devinfo->is_g4x) { 11593 return 0; 11594 } else { 11595 return 0; 11596 } 11597 default: 11598 unreachable("Invalid hardware generation"); 11599 } 11600 } 11601 11602 11603 11604 #define GEN10_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11605 #define GEN9_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11606 #define GEN8_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11607 #define GEN75_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11608 #define GEN7_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11609 #define GEN6_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11610 #define GEN5_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 11611 11612 static inline uint32_t ATTRIBUTE_PURE 11613 _3DSTATE_CLEAR_PARAMS_CommandSubType_start(const struct gen_device_info *devinfo) 11614 { 11615 switch (devinfo->gen) { 11616 case 10: return 27; 11617 case 9: return 27; 11618 case 8: return 27; 11619 case 7: 11620 if (devinfo->is_haswell) { 11621 return 27; 11622 } else { 11623 return 27; 11624 } 11625 case 6: return 27; 11626 case 5: return 27; 11627 case 4: 11628 if (devinfo->is_g4x) { 11629 return 0; 11630 } else { 11631 return 0; 11632 } 11633 default: 11634 unreachable("Invalid hardware generation"); 11635 } 11636 } 11637 11638 11639 11640 /* 3DSTATE_CLEAR_PARAMS::Command Type */ 11641 11642 11643 #define GEN10_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11644 #define GEN9_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11645 #define GEN8_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11646 #define GEN75_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11647 #define GEN7_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11648 #define GEN6_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11649 #define GEN5_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 11650 11651 static inline uint32_t ATTRIBUTE_PURE 11652 _3DSTATE_CLEAR_PARAMS_CommandType_bits(const struct gen_device_info *devinfo) 11653 { 11654 switch (devinfo->gen) { 11655 case 10: return 3; 11656 case 9: return 3; 11657 case 8: return 3; 11658 case 7: 11659 if (devinfo->is_haswell) { 11660 return 3; 11661 } else { 11662 return 3; 11663 } 11664 case 6: return 3; 11665 case 5: return 3; 11666 case 4: 11667 if (devinfo->is_g4x) { 11668 return 0; 11669 } else { 11670 return 0; 11671 } 11672 default: 11673 unreachable("Invalid hardware generation"); 11674 } 11675 } 11676 11677 11678 11679 #define GEN10_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11680 #define GEN9_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11681 #define GEN8_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11682 #define GEN75_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11683 #define GEN7_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11684 #define GEN6_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11685 #define GEN5_3DSTATE_CLEAR_PARAMS_CommandType_start 29 11686 11687 static inline uint32_t ATTRIBUTE_PURE 11688 _3DSTATE_CLEAR_PARAMS_CommandType_start(const struct gen_device_info *devinfo) 11689 { 11690 switch (devinfo->gen) { 11691 case 10: return 29; 11692 case 9: return 29; 11693 case 8: return 29; 11694 case 7: 11695 if (devinfo->is_haswell) { 11696 return 29; 11697 } else { 11698 return 29; 11699 } 11700 case 6: return 29; 11701 case 5: return 29; 11702 case 4: 11703 if (devinfo->is_g4x) { 11704 return 0; 11705 } else { 11706 return 0; 11707 } 11708 default: 11709 unreachable("Invalid hardware generation"); 11710 } 11711 } 11712 11713 11714 11715 /* 3DSTATE_CLEAR_PARAMS::DWord Length */ 11716 11717 11718 #define GEN10_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11719 #define GEN9_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11720 #define GEN8_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11721 #define GEN75_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11722 #define GEN7_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11723 #define GEN6_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11724 #define GEN5_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 11725 11726 static inline uint32_t ATTRIBUTE_PURE 11727 _3DSTATE_CLEAR_PARAMS_DWordLength_bits(const struct gen_device_info *devinfo) 11728 { 11729 switch (devinfo->gen) { 11730 case 10: return 8; 11731 case 9: return 8; 11732 case 8: return 8; 11733 case 7: 11734 if (devinfo->is_haswell) { 11735 return 8; 11736 } else { 11737 return 8; 11738 } 11739 case 6: return 8; 11740 case 5: return 8; 11741 case 4: 11742 if (devinfo->is_g4x) { 11743 return 0; 11744 } else { 11745 return 0; 11746 } 11747 default: 11748 unreachable("Invalid hardware generation"); 11749 } 11750 } 11751 11752 11753 11754 #define GEN10_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11755 #define GEN9_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11756 #define GEN8_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11757 #define GEN75_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11758 #define GEN7_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11759 #define GEN6_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11760 #define GEN5_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 11761 11762 static inline uint32_t ATTRIBUTE_PURE 11763 _3DSTATE_CLEAR_PARAMS_DWordLength_start(const struct gen_device_info *devinfo) 11764 { 11765 switch (devinfo->gen) { 11766 case 10: return 0; 11767 case 9: return 0; 11768 case 8: return 0; 11769 case 7: 11770 if (devinfo->is_haswell) { 11771 return 0; 11772 } else { 11773 return 0; 11774 } 11775 case 6: return 0; 11776 case 5: return 0; 11777 case 4: 11778 if (devinfo->is_g4x) { 11779 return 0; 11780 } else { 11781 return 0; 11782 } 11783 default: 11784 unreachable("Invalid hardware generation"); 11785 } 11786 } 11787 11788 11789 11790 /* 3DSTATE_CLEAR_PARAMS::Depth Clear Value */ 11791 11792 11793 #define GEN10_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11794 #define GEN9_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11795 #define GEN8_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11796 #define GEN75_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11797 #define GEN7_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11798 #define GEN6_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11799 #define GEN5_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 11800 11801 static inline uint32_t ATTRIBUTE_PURE 11802 _3DSTATE_CLEAR_PARAMS_DepthClearValue_bits(const struct gen_device_info *devinfo) 11803 { 11804 switch (devinfo->gen) { 11805 case 10: return 32; 11806 case 9: return 32; 11807 case 8: return 32; 11808 case 7: 11809 if (devinfo->is_haswell) { 11810 return 32; 11811 } else { 11812 return 32; 11813 } 11814 case 6: return 32; 11815 case 5: return 32; 11816 case 4: 11817 if (devinfo->is_g4x) { 11818 return 0; 11819 } else { 11820 return 0; 11821 } 11822 default: 11823 unreachable("Invalid hardware generation"); 11824 } 11825 } 11826 11827 11828 11829 #define GEN10_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11830 #define GEN9_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11831 #define GEN8_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11832 #define GEN75_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11833 #define GEN7_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11834 #define GEN6_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11835 #define GEN5_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 11836 11837 static inline uint32_t ATTRIBUTE_PURE 11838 _3DSTATE_CLEAR_PARAMS_DepthClearValue_start(const struct gen_device_info *devinfo) 11839 { 11840 switch (devinfo->gen) { 11841 case 10: return 32; 11842 case 9: return 32; 11843 case 8: return 32; 11844 case 7: 11845 if (devinfo->is_haswell) { 11846 return 32; 11847 } else { 11848 return 32; 11849 } 11850 case 6: return 32; 11851 case 5: return 32; 11852 case 4: 11853 if (devinfo->is_g4x) { 11854 return 0; 11855 } else { 11856 return 0; 11857 } 11858 default: 11859 unreachable("Invalid hardware generation"); 11860 } 11861 } 11862 11863 11864 11865 /* 3DSTATE_CLEAR_PARAMS::Depth Clear Value Valid */ 11866 11867 11868 #define GEN10_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11869 #define GEN9_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11870 #define GEN8_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11871 #define GEN75_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11872 #define GEN7_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11873 #define GEN6_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11874 #define GEN5_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 11875 11876 static inline uint32_t ATTRIBUTE_PURE 11877 _3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits(const struct gen_device_info *devinfo) 11878 { 11879 switch (devinfo->gen) { 11880 case 10: return 1; 11881 case 9: return 1; 11882 case 8: return 1; 11883 case 7: 11884 if (devinfo->is_haswell) { 11885 return 1; 11886 } else { 11887 return 1; 11888 } 11889 case 6: return 1; 11890 case 5: return 1; 11891 case 4: 11892 if (devinfo->is_g4x) { 11893 return 0; 11894 } else { 11895 return 0; 11896 } 11897 default: 11898 unreachable("Invalid hardware generation"); 11899 } 11900 } 11901 11902 11903 11904 #define GEN10_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 11905 #define GEN9_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 11906 #define GEN8_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 11907 #define GEN75_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 11908 #define GEN7_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 11909 #define GEN6_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 15 11910 #define GEN5_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 15 11911 11912 static inline uint32_t ATTRIBUTE_PURE 11913 _3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start(const struct gen_device_info *devinfo) 11914 { 11915 switch (devinfo->gen) { 11916 case 10: return 64; 11917 case 9: return 64; 11918 case 8: return 64; 11919 case 7: 11920 if (devinfo->is_haswell) { 11921 return 64; 11922 } else { 11923 return 64; 11924 } 11925 case 6: return 15; 11926 case 5: return 15; 11927 case 4: 11928 if (devinfo->is_g4x) { 11929 return 0; 11930 } else { 11931 return 0; 11932 } 11933 default: 11934 unreachable("Invalid hardware generation"); 11935 } 11936 } 11937 11938 11939 11940 /* 3DSTATE_CLIP */ 11941 11942 11943 #define GEN10_3DSTATE_CLIP_length 4 11944 #define GEN9_3DSTATE_CLIP_length 4 11945 #define GEN8_3DSTATE_CLIP_length 4 11946 #define GEN75_3DSTATE_CLIP_length 4 11947 #define GEN7_3DSTATE_CLIP_length 4 11948 #define GEN6_3DSTATE_CLIP_length 4 11949 11950 static inline uint32_t ATTRIBUTE_PURE 11951 _3DSTATE_CLIP_length(const struct gen_device_info *devinfo) 11952 { 11953 switch (devinfo->gen) { 11954 case 10: return 4; 11955 case 9: return 4; 11956 case 8: return 4; 11957 case 7: 11958 if (devinfo->is_haswell) { 11959 return 4; 11960 } else { 11961 return 4; 11962 } 11963 case 6: return 4; 11964 case 5: return 0; 11965 case 4: 11966 if (devinfo->is_g4x) { 11967 return 0; 11968 } else { 11969 return 0; 11970 } 11971 default: 11972 unreachable("Invalid hardware generation"); 11973 } 11974 } 11975 11976 11977 11978 /* 3DSTATE_CLIP::3D Command Opcode */ 11979 11980 11981 #define GEN10_3DSTATE_CLIP_3DCommandOpcode_bits 3 11982 #define GEN9_3DSTATE_CLIP_3DCommandOpcode_bits 3 11983 #define GEN8_3DSTATE_CLIP_3DCommandOpcode_bits 3 11984 #define GEN75_3DSTATE_CLIP_3DCommandOpcode_bits 3 11985 #define GEN7_3DSTATE_CLIP_3DCommandOpcode_bits 3 11986 #define GEN6_3DSTATE_CLIP_3DCommandOpcode_bits 3 11987 11988 static inline uint32_t ATTRIBUTE_PURE 11989 _3DSTATE_CLIP_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 11990 { 11991 switch (devinfo->gen) { 11992 case 10: return 3; 11993 case 9: return 3; 11994 case 8: return 3; 11995 case 7: 11996 if (devinfo->is_haswell) { 11997 return 3; 11998 } else { 11999 return 3; 12000 } 12001 case 6: return 3; 12002 case 5: return 0; 12003 case 4: 12004 if (devinfo->is_g4x) { 12005 return 0; 12006 } else { 12007 return 0; 12008 } 12009 default: 12010 unreachable("Invalid hardware generation"); 12011 } 12012 } 12013 12014 12015 12016 #define GEN10_3DSTATE_CLIP_3DCommandOpcode_start 24 12017 #define GEN9_3DSTATE_CLIP_3DCommandOpcode_start 24 12018 #define GEN8_3DSTATE_CLIP_3DCommandOpcode_start 24 12019 #define GEN75_3DSTATE_CLIP_3DCommandOpcode_start 24 12020 #define GEN7_3DSTATE_CLIP_3DCommandOpcode_start 24 12021 #define GEN6_3DSTATE_CLIP_3DCommandOpcode_start 24 12022 12023 static inline uint32_t ATTRIBUTE_PURE 12024 _3DSTATE_CLIP_3DCommandOpcode_start(const struct gen_device_info *devinfo) 12025 { 12026 switch (devinfo->gen) { 12027 case 10: return 24; 12028 case 9: return 24; 12029 case 8: return 24; 12030 case 7: 12031 if (devinfo->is_haswell) { 12032 return 24; 12033 } else { 12034 return 24; 12035 } 12036 case 6: return 24; 12037 case 5: return 0; 12038 case 4: 12039 if (devinfo->is_g4x) { 12040 return 0; 12041 } else { 12042 return 0; 12043 } 12044 default: 12045 unreachable("Invalid hardware generation"); 12046 } 12047 } 12048 12049 12050 12051 /* 3DSTATE_CLIP::3D Command Sub Opcode */ 12052 12053 12054 #define GEN10_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 12055 #define GEN9_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 12056 #define GEN8_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 12057 #define GEN75_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 12058 #define GEN7_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 12059 #define GEN6_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 12060 12061 static inline uint32_t ATTRIBUTE_PURE 12062 _3DSTATE_CLIP_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 12063 { 12064 switch (devinfo->gen) { 12065 case 10: return 8; 12066 case 9: return 8; 12067 case 8: return 8; 12068 case 7: 12069 if (devinfo->is_haswell) { 12070 return 8; 12071 } else { 12072 return 8; 12073 } 12074 case 6: return 8; 12075 case 5: return 0; 12076 case 4: 12077 if (devinfo->is_g4x) { 12078 return 0; 12079 } else { 12080 return 0; 12081 } 12082 default: 12083 unreachable("Invalid hardware generation"); 12084 } 12085 } 12086 12087 12088 12089 #define GEN10_3DSTATE_CLIP_3DCommandSubOpcode_start 16 12090 #define GEN9_3DSTATE_CLIP_3DCommandSubOpcode_start 16 12091 #define GEN8_3DSTATE_CLIP_3DCommandSubOpcode_start 16 12092 #define GEN75_3DSTATE_CLIP_3DCommandSubOpcode_start 16 12093 #define GEN7_3DSTATE_CLIP_3DCommandSubOpcode_start 16 12094 #define GEN6_3DSTATE_CLIP_3DCommandSubOpcode_start 16 12095 12096 static inline uint32_t ATTRIBUTE_PURE 12097 _3DSTATE_CLIP_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 12098 { 12099 switch (devinfo->gen) { 12100 case 10: return 16; 12101 case 9: return 16; 12102 case 8: return 16; 12103 case 7: 12104 if (devinfo->is_haswell) { 12105 return 16; 12106 } else { 12107 return 16; 12108 } 12109 case 6: return 16; 12110 case 5: return 0; 12111 case 4: 12112 if (devinfo->is_g4x) { 12113 return 0; 12114 } else { 12115 return 0; 12116 } 12117 default: 12118 unreachable("Invalid hardware generation"); 12119 } 12120 } 12121 12122 12123 12124 /* 3DSTATE_CLIP::API Mode */ 12125 12126 12127 #define GEN10_3DSTATE_CLIP_APIMode_bits 1 12128 #define GEN9_3DSTATE_CLIP_APIMode_bits 1 12129 #define GEN8_3DSTATE_CLIP_APIMode_bits 1 12130 #define GEN75_3DSTATE_CLIP_APIMode_bits 1 12131 #define GEN7_3DSTATE_CLIP_APIMode_bits 1 12132 #define GEN6_3DSTATE_CLIP_APIMode_bits 1 12133 12134 static inline uint32_t ATTRIBUTE_PURE 12135 _3DSTATE_CLIP_APIMode_bits(const struct gen_device_info *devinfo) 12136 { 12137 switch (devinfo->gen) { 12138 case 10: return 1; 12139 case 9: return 1; 12140 case 8: return 1; 12141 case 7: 12142 if (devinfo->is_haswell) { 12143 return 1; 12144 } else { 12145 return 1; 12146 } 12147 case 6: return 1; 12148 case 5: return 0; 12149 case 4: 12150 if (devinfo->is_g4x) { 12151 return 0; 12152 } else { 12153 return 0; 12154 } 12155 default: 12156 unreachable("Invalid hardware generation"); 12157 } 12158 } 12159 12160 12161 12162 #define GEN10_3DSTATE_CLIP_APIMode_start 94 12163 #define GEN9_3DSTATE_CLIP_APIMode_start 94 12164 #define GEN8_3DSTATE_CLIP_APIMode_start 94 12165 #define GEN75_3DSTATE_CLIP_APIMode_start 94 12166 #define GEN7_3DSTATE_CLIP_APIMode_start 94 12167 #define GEN6_3DSTATE_CLIP_APIMode_start 94 12168 12169 static inline uint32_t ATTRIBUTE_PURE 12170 _3DSTATE_CLIP_APIMode_start(const struct gen_device_info *devinfo) 12171 { 12172 switch (devinfo->gen) { 12173 case 10: return 94; 12174 case 9: return 94; 12175 case 8: return 94; 12176 case 7: 12177 if (devinfo->is_haswell) { 12178 return 94; 12179 } else { 12180 return 94; 12181 } 12182 case 6: return 94; 12183 case 5: return 0; 12184 case 4: 12185 if (devinfo->is_g4x) { 12186 return 0; 12187 } else { 12188 return 0; 12189 } 12190 default: 12191 unreachable("Invalid hardware generation"); 12192 } 12193 } 12194 12195 12196 12197 /* 3DSTATE_CLIP::Clip Enable */ 12198 12199 12200 #define GEN10_3DSTATE_CLIP_ClipEnable_bits 1 12201 #define GEN9_3DSTATE_CLIP_ClipEnable_bits 1 12202 #define GEN8_3DSTATE_CLIP_ClipEnable_bits 1 12203 #define GEN75_3DSTATE_CLIP_ClipEnable_bits 1 12204 #define GEN7_3DSTATE_CLIP_ClipEnable_bits 1 12205 #define GEN6_3DSTATE_CLIP_ClipEnable_bits 1 12206 12207 static inline uint32_t ATTRIBUTE_PURE 12208 _3DSTATE_CLIP_ClipEnable_bits(const struct gen_device_info *devinfo) 12209 { 12210 switch (devinfo->gen) { 12211 case 10: return 1; 12212 case 9: return 1; 12213 case 8: return 1; 12214 case 7: 12215 if (devinfo->is_haswell) { 12216 return 1; 12217 } else { 12218 return 1; 12219 } 12220 case 6: return 1; 12221 case 5: return 0; 12222 case 4: 12223 if (devinfo->is_g4x) { 12224 return 0; 12225 } else { 12226 return 0; 12227 } 12228 default: 12229 unreachable("Invalid hardware generation"); 12230 } 12231 } 12232 12233 12234 12235 #define GEN10_3DSTATE_CLIP_ClipEnable_start 95 12236 #define GEN9_3DSTATE_CLIP_ClipEnable_start 95 12237 #define GEN8_3DSTATE_CLIP_ClipEnable_start 95 12238 #define GEN75_3DSTATE_CLIP_ClipEnable_start 95 12239 #define GEN7_3DSTATE_CLIP_ClipEnable_start 95 12240 #define GEN6_3DSTATE_CLIP_ClipEnable_start 95 12241 12242 static inline uint32_t ATTRIBUTE_PURE 12243 _3DSTATE_CLIP_ClipEnable_start(const struct gen_device_info *devinfo) 12244 { 12245 switch (devinfo->gen) { 12246 case 10: return 95; 12247 case 9: return 95; 12248 case 8: return 95; 12249 case 7: 12250 if (devinfo->is_haswell) { 12251 return 95; 12252 } else { 12253 return 95; 12254 } 12255 case 6: return 95; 12256 case 5: return 0; 12257 case 4: 12258 if (devinfo->is_g4x) { 12259 return 0; 12260 } else { 12261 return 0; 12262 } 12263 default: 12264 unreachable("Invalid hardware generation"); 12265 } 12266 } 12267 12268 12269 12270 /* 3DSTATE_CLIP::Clip Mode */ 12271 12272 12273 #define GEN10_3DSTATE_CLIP_ClipMode_bits 3 12274 #define GEN9_3DSTATE_CLIP_ClipMode_bits 3 12275 #define GEN8_3DSTATE_CLIP_ClipMode_bits 3 12276 #define GEN75_3DSTATE_CLIP_ClipMode_bits 3 12277 #define GEN7_3DSTATE_CLIP_ClipMode_bits 3 12278 #define GEN6_3DSTATE_CLIP_ClipMode_bits 3 12279 12280 static inline uint32_t ATTRIBUTE_PURE 12281 _3DSTATE_CLIP_ClipMode_bits(const struct gen_device_info *devinfo) 12282 { 12283 switch (devinfo->gen) { 12284 case 10: return 3; 12285 case 9: return 3; 12286 case 8: return 3; 12287 case 7: 12288 if (devinfo->is_haswell) { 12289 return 3; 12290 } else { 12291 return 3; 12292 } 12293 case 6: return 3; 12294 case 5: return 0; 12295 case 4: 12296 if (devinfo->is_g4x) { 12297 return 0; 12298 } else { 12299 return 0; 12300 } 12301 default: 12302 unreachable("Invalid hardware generation"); 12303 } 12304 } 12305 12306 12307 12308 #define GEN10_3DSTATE_CLIP_ClipMode_start 77 12309 #define GEN9_3DSTATE_CLIP_ClipMode_start 77 12310 #define GEN8_3DSTATE_CLIP_ClipMode_start 77 12311 #define GEN75_3DSTATE_CLIP_ClipMode_start 77 12312 #define GEN7_3DSTATE_CLIP_ClipMode_start 77 12313 #define GEN6_3DSTATE_CLIP_ClipMode_start 77 12314 12315 static inline uint32_t ATTRIBUTE_PURE 12316 _3DSTATE_CLIP_ClipMode_start(const struct gen_device_info *devinfo) 12317 { 12318 switch (devinfo->gen) { 12319 case 10: return 77; 12320 case 9: return 77; 12321 case 8: return 77; 12322 case 7: 12323 if (devinfo->is_haswell) { 12324 return 77; 12325 } else { 12326 return 77; 12327 } 12328 case 6: return 77; 12329 case 5: return 0; 12330 case 4: 12331 if (devinfo->is_g4x) { 12332 return 0; 12333 } else { 12334 return 0; 12335 } 12336 default: 12337 unreachable("Invalid hardware generation"); 12338 } 12339 } 12340 12341 12342 12343 /* 3DSTATE_CLIP::Command SubType */ 12344 12345 12346 #define GEN10_3DSTATE_CLIP_CommandSubType_bits 2 12347 #define GEN9_3DSTATE_CLIP_CommandSubType_bits 2 12348 #define GEN8_3DSTATE_CLIP_CommandSubType_bits 2 12349 #define GEN75_3DSTATE_CLIP_CommandSubType_bits 2 12350 #define GEN7_3DSTATE_CLIP_CommandSubType_bits 2 12351 #define GEN6_3DSTATE_CLIP_CommandSubType_bits 2 12352 12353 static inline uint32_t ATTRIBUTE_PURE 12354 _3DSTATE_CLIP_CommandSubType_bits(const struct gen_device_info *devinfo) 12355 { 12356 switch (devinfo->gen) { 12357 case 10: return 2; 12358 case 9: return 2; 12359 case 8: return 2; 12360 case 7: 12361 if (devinfo->is_haswell) { 12362 return 2; 12363 } else { 12364 return 2; 12365 } 12366 case 6: return 2; 12367 case 5: return 0; 12368 case 4: 12369 if (devinfo->is_g4x) { 12370 return 0; 12371 } else { 12372 return 0; 12373 } 12374 default: 12375 unreachable("Invalid hardware generation"); 12376 } 12377 } 12378 12379 12380 12381 #define GEN10_3DSTATE_CLIP_CommandSubType_start 27 12382 #define GEN9_3DSTATE_CLIP_CommandSubType_start 27 12383 #define GEN8_3DSTATE_CLIP_CommandSubType_start 27 12384 #define GEN75_3DSTATE_CLIP_CommandSubType_start 27 12385 #define GEN7_3DSTATE_CLIP_CommandSubType_start 27 12386 #define GEN6_3DSTATE_CLIP_CommandSubType_start 27 12387 12388 static inline uint32_t ATTRIBUTE_PURE 12389 _3DSTATE_CLIP_CommandSubType_start(const struct gen_device_info *devinfo) 12390 { 12391 switch (devinfo->gen) { 12392 case 10: return 27; 12393 case 9: return 27; 12394 case 8: return 27; 12395 case 7: 12396 if (devinfo->is_haswell) { 12397 return 27; 12398 } else { 12399 return 27; 12400 } 12401 case 6: return 27; 12402 case 5: return 0; 12403 case 4: 12404 if (devinfo->is_g4x) { 12405 return 0; 12406 } else { 12407 return 0; 12408 } 12409 default: 12410 unreachable("Invalid hardware generation"); 12411 } 12412 } 12413 12414 12415 12416 /* 3DSTATE_CLIP::Command Type */ 12417 12418 12419 #define GEN10_3DSTATE_CLIP_CommandType_bits 3 12420 #define GEN9_3DSTATE_CLIP_CommandType_bits 3 12421 #define GEN8_3DSTATE_CLIP_CommandType_bits 3 12422 #define GEN75_3DSTATE_CLIP_CommandType_bits 3 12423 #define GEN7_3DSTATE_CLIP_CommandType_bits 3 12424 #define GEN6_3DSTATE_CLIP_CommandType_bits 3 12425 12426 static inline uint32_t ATTRIBUTE_PURE 12427 _3DSTATE_CLIP_CommandType_bits(const struct gen_device_info *devinfo) 12428 { 12429 switch (devinfo->gen) { 12430 case 10: return 3; 12431 case 9: return 3; 12432 case 8: return 3; 12433 case 7: 12434 if (devinfo->is_haswell) { 12435 return 3; 12436 } else { 12437 return 3; 12438 } 12439 case 6: return 3; 12440 case 5: return 0; 12441 case 4: 12442 if (devinfo->is_g4x) { 12443 return 0; 12444 } else { 12445 return 0; 12446 } 12447 default: 12448 unreachable("Invalid hardware generation"); 12449 } 12450 } 12451 12452 12453 12454 #define GEN10_3DSTATE_CLIP_CommandType_start 29 12455 #define GEN9_3DSTATE_CLIP_CommandType_start 29 12456 #define GEN8_3DSTATE_CLIP_CommandType_start 29 12457 #define GEN75_3DSTATE_CLIP_CommandType_start 29 12458 #define GEN7_3DSTATE_CLIP_CommandType_start 29 12459 #define GEN6_3DSTATE_CLIP_CommandType_start 29 12460 12461 static inline uint32_t ATTRIBUTE_PURE 12462 _3DSTATE_CLIP_CommandType_start(const struct gen_device_info *devinfo) 12463 { 12464 switch (devinfo->gen) { 12465 case 10: return 29; 12466 case 9: return 29; 12467 case 8: return 29; 12468 case 7: 12469 if (devinfo->is_haswell) { 12470 return 29; 12471 } else { 12472 return 29; 12473 } 12474 case 6: return 29; 12475 case 5: return 0; 12476 case 4: 12477 if (devinfo->is_g4x) { 12478 return 0; 12479 } else { 12480 return 0; 12481 } 12482 default: 12483 unreachable("Invalid hardware generation"); 12484 } 12485 } 12486 12487 12488 12489 /* 3DSTATE_CLIP::Cull Mode */ 12490 12491 12492 #define GEN75_3DSTATE_CLIP_CullMode_bits 2 12493 #define GEN7_3DSTATE_CLIP_CullMode_bits 2 12494 12495 static inline uint32_t ATTRIBUTE_PURE 12496 _3DSTATE_CLIP_CullMode_bits(const struct gen_device_info *devinfo) 12497 { 12498 switch (devinfo->gen) { 12499 case 10: return 0; 12500 case 9: return 0; 12501 case 8: return 0; 12502 case 7: 12503 if (devinfo->is_haswell) { 12504 return 2; 12505 } else { 12506 return 2; 12507 } 12508 case 6: return 0; 12509 case 5: return 0; 12510 case 4: 12511 if (devinfo->is_g4x) { 12512 return 0; 12513 } else { 12514 return 0; 12515 } 12516 default: 12517 unreachable("Invalid hardware generation"); 12518 } 12519 } 12520 12521 12522 12523 #define GEN75_3DSTATE_CLIP_CullMode_start 48 12524 #define GEN7_3DSTATE_CLIP_CullMode_start 48 12525 12526 static inline uint32_t ATTRIBUTE_PURE 12527 _3DSTATE_CLIP_CullMode_start(const struct gen_device_info *devinfo) 12528 { 12529 switch (devinfo->gen) { 12530 case 10: return 0; 12531 case 9: return 0; 12532 case 8: return 0; 12533 case 7: 12534 if (devinfo->is_haswell) { 12535 return 48; 12536 } else { 12537 return 48; 12538 } 12539 case 6: return 0; 12540 case 5: return 0; 12541 case 4: 12542 if (devinfo->is_g4x) { 12543 return 0; 12544 } else { 12545 return 0; 12546 } 12547 default: 12548 unreachable("Invalid hardware generation"); 12549 } 12550 } 12551 12552 12553 12554 /* 3DSTATE_CLIP::DWord Length */ 12555 12556 12557 #define GEN10_3DSTATE_CLIP_DWordLength_bits 8 12558 #define GEN9_3DSTATE_CLIP_DWordLength_bits 8 12559 #define GEN8_3DSTATE_CLIP_DWordLength_bits 8 12560 #define GEN75_3DSTATE_CLIP_DWordLength_bits 8 12561 #define GEN7_3DSTATE_CLIP_DWordLength_bits 8 12562 #define GEN6_3DSTATE_CLIP_DWordLength_bits 8 12563 12564 static inline uint32_t ATTRIBUTE_PURE 12565 _3DSTATE_CLIP_DWordLength_bits(const struct gen_device_info *devinfo) 12566 { 12567 switch (devinfo->gen) { 12568 case 10: return 8; 12569 case 9: return 8; 12570 case 8: return 8; 12571 case 7: 12572 if (devinfo->is_haswell) { 12573 return 8; 12574 } else { 12575 return 8; 12576 } 12577 case 6: return 8; 12578 case 5: return 0; 12579 case 4: 12580 if (devinfo->is_g4x) { 12581 return 0; 12582 } else { 12583 return 0; 12584 } 12585 default: 12586 unreachable("Invalid hardware generation"); 12587 } 12588 } 12589 12590 12591 12592 #define GEN10_3DSTATE_CLIP_DWordLength_start 0 12593 #define GEN9_3DSTATE_CLIP_DWordLength_start 0 12594 #define GEN8_3DSTATE_CLIP_DWordLength_start 0 12595 #define GEN75_3DSTATE_CLIP_DWordLength_start 0 12596 #define GEN7_3DSTATE_CLIP_DWordLength_start 0 12597 #define GEN6_3DSTATE_CLIP_DWordLength_start 0 12598 12599 static inline uint32_t ATTRIBUTE_PURE 12600 _3DSTATE_CLIP_DWordLength_start(const struct gen_device_info *devinfo) 12601 { 12602 switch (devinfo->gen) { 12603 case 10: return 0; 12604 case 9: return 0; 12605 case 8: return 0; 12606 case 7: 12607 if (devinfo->is_haswell) { 12608 return 0; 12609 } else { 12610 return 0; 12611 } 12612 case 6: return 0; 12613 case 5: return 0; 12614 case 4: 12615 if (devinfo->is_g4x) { 12616 return 0; 12617 } else { 12618 return 0; 12619 } 12620 default: 12621 unreachable("Invalid hardware generation"); 12622 } 12623 } 12624 12625 12626 12627 /* 3DSTATE_CLIP::Early Cull Enable */ 12628 12629 12630 #define GEN10_3DSTATE_CLIP_EarlyCullEnable_bits 1 12631 #define GEN9_3DSTATE_CLIP_EarlyCullEnable_bits 1 12632 #define GEN8_3DSTATE_CLIP_EarlyCullEnable_bits 1 12633 #define GEN75_3DSTATE_CLIP_EarlyCullEnable_bits 1 12634 #define GEN7_3DSTATE_CLIP_EarlyCullEnable_bits 1 12635 12636 static inline uint32_t ATTRIBUTE_PURE 12637 _3DSTATE_CLIP_EarlyCullEnable_bits(const struct gen_device_info *devinfo) 12638 { 12639 switch (devinfo->gen) { 12640 case 10: return 1; 12641 case 9: return 1; 12642 case 8: return 1; 12643 case 7: 12644 if (devinfo->is_haswell) { 12645 return 1; 12646 } else { 12647 return 1; 12648 } 12649 case 6: return 0; 12650 case 5: return 0; 12651 case 4: 12652 if (devinfo->is_g4x) { 12653 return 0; 12654 } else { 12655 return 0; 12656 } 12657 default: 12658 unreachable("Invalid hardware generation"); 12659 } 12660 } 12661 12662 12663 12664 #define GEN10_3DSTATE_CLIP_EarlyCullEnable_start 50 12665 #define GEN9_3DSTATE_CLIP_EarlyCullEnable_start 50 12666 #define GEN8_3DSTATE_CLIP_EarlyCullEnable_start 50 12667 #define GEN75_3DSTATE_CLIP_EarlyCullEnable_start 50 12668 #define GEN7_3DSTATE_CLIP_EarlyCullEnable_start 50 12669 12670 static inline uint32_t ATTRIBUTE_PURE 12671 _3DSTATE_CLIP_EarlyCullEnable_start(const struct gen_device_info *devinfo) 12672 { 12673 switch (devinfo->gen) { 12674 case 10: return 50; 12675 case 9: return 50; 12676 case 8: return 50; 12677 case 7: 12678 if (devinfo->is_haswell) { 12679 return 50; 12680 } else { 12681 return 50; 12682 } 12683 case 6: return 0; 12684 case 5: return 0; 12685 case 4: 12686 if (devinfo->is_g4x) { 12687 return 0; 12688 } else { 12689 return 0; 12690 } 12691 default: 12692 unreachable("Invalid hardware generation"); 12693 } 12694 } 12695 12696 12697 12698 /* 3DSTATE_CLIP::Force Clip Mode */ 12699 12700 12701 #define GEN10_3DSTATE_CLIP_ForceClipMode_bits 1 12702 #define GEN9_3DSTATE_CLIP_ForceClipMode_bits 1 12703 #define GEN8_3DSTATE_CLIP_ForceClipMode_bits 1 12704 12705 static inline uint32_t ATTRIBUTE_PURE 12706 _3DSTATE_CLIP_ForceClipMode_bits(const struct gen_device_info *devinfo) 12707 { 12708 switch (devinfo->gen) { 12709 case 10: return 1; 12710 case 9: return 1; 12711 case 8: return 1; 12712 case 7: 12713 if (devinfo->is_haswell) { 12714 return 0; 12715 } else { 12716 return 0; 12717 } 12718 case 6: return 0; 12719 case 5: return 0; 12720 case 4: 12721 if (devinfo->is_g4x) { 12722 return 0; 12723 } else { 12724 return 0; 12725 } 12726 default: 12727 unreachable("Invalid hardware generation"); 12728 } 12729 } 12730 12731 12732 12733 #define GEN10_3DSTATE_CLIP_ForceClipMode_start 48 12734 #define GEN9_3DSTATE_CLIP_ForceClipMode_start 48 12735 #define GEN8_3DSTATE_CLIP_ForceClipMode_start 48 12736 12737 static inline uint32_t ATTRIBUTE_PURE 12738 _3DSTATE_CLIP_ForceClipMode_start(const struct gen_device_info *devinfo) 12739 { 12740 switch (devinfo->gen) { 12741 case 10: return 48; 12742 case 9: return 48; 12743 case 8: return 48; 12744 case 7: 12745 if (devinfo->is_haswell) { 12746 return 0; 12747 } else { 12748 return 0; 12749 } 12750 case 6: return 0; 12751 case 5: return 0; 12752 case 4: 12753 if (devinfo->is_g4x) { 12754 return 0; 12755 } else { 12756 return 0; 12757 } 12758 default: 12759 unreachable("Invalid hardware generation"); 12760 } 12761 } 12762 12763 12764 12765 /* 3DSTATE_CLIP::Force User Clip Distance Clip Test Enable Bitmask */ 12766 12767 12768 #define GEN10_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 12769 #define GEN9_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 12770 #define GEN8_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 12771 12772 static inline uint32_t ATTRIBUTE_PURE 12773 _3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits(const struct gen_device_info *devinfo) 12774 { 12775 switch (devinfo->gen) { 12776 case 10: return 1; 12777 case 9: return 1; 12778 case 8: return 1; 12779 case 7: 12780 if (devinfo->is_haswell) { 12781 return 0; 12782 } else { 12783 return 0; 12784 } 12785 case 6: return 0; 12786 case 5: return 0; 12787 case 4: 12788 if (devinfo->is_g4x) { 12789 return 0; 12790 } else { 12791 return 0; 12792 } 12793 default: 12794 unreachable("Invalid hardware generation"); 12795 } 12796 } 12797 12798 12799 12800 #define GEN10_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 12801 #define GEN9_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 12802 #define GEN8_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 12803 12804 static inline uint32_t ATTRIBUTE_PURE 12805 _3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start(const struct gen_device_info *devinfo) 12806 { 12807 switch (devinfo->gen) { 12808 case 10: return 49; 12809 case 9: return 49; 12810 case 8: return 49; 12811 case 7: 12812 if (devinfo->is_haswell) { 12813 return 0; 12814 } else { 12815 return 0; 12816 } 12817 case 6: return 0; 12818 case 5: return 0; 12819 case 4: 12820 if (devinfo->is_g4x) { 12821 return 0; 12822 } else { 12823 return 0; 12824 } 12825 default: 12826 unreachable("Invalid hardware generation"); 12827 } 12828 } 12829 12830 12831 12832 /* 3DSTATE_CLIP::Force User Clip Distance Cull Test Enable Bitmask */ 12833 12834 12835 #define GEN10_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 12836 #define GEN9_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 12837 #define GEN8_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 12838 12839 static inline uint32_t ATTRIBUTE_PURE 12840 _3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits(const struct gen_device_info *devinfo) 12841 { 12842 switch (devinfo->gen) { 12843 case 10: return 1; 12844 case 9: return 1; 12845 case 8: return 1; 12846 case 7: 12847 if (devinfo->is_haswell) { 12848 return 0; 12849 } else { 12850 return 0; 12851 } 12852 case 6: return 0; 12853 case 5: return 0; 12854 case 4: 12855 if (devinfo->is_g4x) { 12856 return 0; 12857 } else { 12858 return 0; 12859 } 12860 default: 12861 unreachable("Invalid hardware generation"); 12862 } 12863 } 12864 12865 12866 12867 #define GEN10_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 12868 #define GEN9_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 12869 #define GEN8_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 12870 12871 static inline uint32_t ATTRIBUTE_PURE 12872 _3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start(const struct gen_device_info *devinfo) 12873 { 12874 switch (devinfo->gen) { 12875 case 10: return 52; 12876 case 9: return 52; 12877 case 8: return 52; 12878 case 7: 12879 if (devinfo->is_haswell) { 12880 return 0; 12881 } else { 12882 return 0; 12883 } 12884 case 6: return 0; 12885 case 5: return 0; 12886 case 4: 12887 if (devinfo->is_g4x) { 12888 return 0; 12889 } else { 12890 return 0; 12891 } 12892 default: 12893 unreachable("Invalid hardware generation"); 12894 } 12895 } 12896 12897 12898 12899 /* 3DSTATE_CLIP::Force Zero RTA Index Enable */ 12900 12901 12902 #define GEN10_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 12903 #define GEN9_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 12904 #define GEN8_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 12905 #define GEN75_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 12906 #define GEN7_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 12907 #define GEN6_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 12908 12909 static inline uint32_t ATTRIBUTE_PURE 12910 _3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits(const struct gen_device_info *devinfo) 12911 { 12912 switch (devinfo->gen) { 12913 case 10: return 1; 12914 case 9: return 1; 12915 case 8: return 1; 12916 case 7: 12917 if (devinfo->is_haswell) { 12918 return 1; 12919 } else { 12920 return 1; 12921 } 12922 case 6: return 1; 12923 case 5: return 0; 12924 case 4: 12925 if (devinfo->is_g4x) { 12926 return 0; 12927 } else { 12928 return 0; 12929 } 12930 default: 12931 unreachable("Invalid hardware generation"); 12932 } 12933 } 12934 12935 12936 12937 #define GEN10_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 12938 #define GEN9_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 12939 #define GEN8_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 12940 #define GEN75_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 12941 #define GEN7_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 12942 #define GEN6_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 12943 12944 static inline uint32_t ATTRIBUTE_PURE 12945 _3DSTATE_CLIP_ForceZeroRTAIndexEnable_start(const struct gen_device_info *devinfo) 12946 { 12947 switch (devinfo->gen) { 12948 case 10: return 101; 12949 case 9: return 101; 12950 case 8: return 101; 12951 case 7: 12952 if (devinfo->is_haswell) { 12953 return 101; 12954 } else { 12955 return 101; 12956 } 12957 case 6: return 101; 12958 case 5: return 0; 12959 case 4: 12960 if (devinfo->is_g4x) { 12961 return 0; 12962 } else { 12963 return 0; 12964 } 12965 default: 12966 unreachable("Invalid hardware generation"); 12967 } 12968 } 12969 12970 12971 12972 /* 3DSTATE_CLIP::Front Winding */ 12973 12974 12975 #define GEN75_3DSTATE_CLIP_FrontWinding_bits 1 12976 #define GEN7_3DSTATE_CLIP_FrontWinding_bits 1 12977 12978 static inline uint32_t ATTRIBUTE_PURE 12979 _3DSTATE_CLIP_FrontWinding_bits(const struct gen_device_info *devinfo) 12980 { 12981 switch (devinfo->gen) { 12982 case 10: return 0; 12983 case 9: return 0; 12984 case 8: return 0; 12985 case 7: 12986 if (devinfo->is_haswell) { 12987 return 1; 12988 } else { 12989 return 1; 12990 } 12991 case 6: return 0; 12992 case 5: return 0; 12993 case 4: 12994 if (devinfo->is_g4x) { 12995 return 0; 12996 } else { 12997 return 0; 12998 } 12999 default: 13000 unreachable("Invalid hardware generation"); 13001 } 13002 } 13003 13004 13005 13006 #define GEN75_3DSTATE_CLIP_FrontWinding_start 52 13007 #define GEN7_3DSTATE_CLIP_FrontWinding_start 52 13008 13009 static inline uint32_t ATTRIBUTE_PURE 13010 _3DSTATE_CLIP_FrontWinding_start(const struct gen_device_info *devinfo) 13011 { 13012 switch (devinfo->gen) { 13013 case 10: return 0; 13014 case 9: return 0; 13015 case 8: return 0; 13016 case 7: 13017 if (devinfo->is_haswell) { 13018 return 52; 13019 } else { 13020 return 52; 13021 } 13022 case 6: return 0; 13023 case 5: return 0; 13024 case 4: 13025 if (devinfo->is_g4x) { 13026 return 0; 13027 } else { 13028 return 0; 13029 } 13030 default: 13031 unreachable("Invalid hardware generation"); 13032 } 13033 } 13034 13035 13036 13037 /* 3DSTATE_CLIP::Guardband Clip Test Enable */ 13038 13039 13040 #define GEN10_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 13041 #define GEN9_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 13042 #define GEN8_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 13043 #define GEN75_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 13044 #define GEN7_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 13045 #define GEN6_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 13046 13047 static inline uint32_t ATTRIBUTE_PURE 13048 _3DSTATE_CLIP_GuardbandClipTestEnable_bits(const struct gen_device_info *devinfo) 13049 { 13050 switch (devinfo->gen) { 13051 case 10: return 1; 13052 case 9: return 1; 13053 case 8: return 1; 13054 case 7: 13055 if (devinfo->is_haswell) { 13056 return 1; 13057 } else { 13058 return 1; 13059 } 13060 case 6: return 1; 13061 case 5: return 0; 13062 case 4: 13063 if (devinfo->is_g4x) { 13064 return 0; 13065 } else { 13066 return 0; 13067 } 13068 default: 13069 unreachable("Invalid hardware generation"); 13070 } 13071 } 13072 13073 13074 13075 #define GEN10_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 13076 #define GEN9_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 13077 #define GEN8_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 13078 #define GEN75_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 13079 #define GEN7_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 13080 #define GEN6_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 13081 13082 static inline uint32_t ATTRIBUTE_PURE 13083 _3DSTATE_CLIP_GuardbandClipTestEnable_start(const struct gen_device_info *devinfo) 13084 { 13085 switch (devinfo->gen) { 13086 case 10: return 90; 13087 case 9: return 90; 13088 case 8: return 90; 13089 case 7: 13090 if (devinfo->is_haswell) { 13091 return 90; 13092 } else { 13093 return 90; 13094 } 13095 case 6: return 90; 13096 case 5: return 0; 13097 case 4: 13098 if (devinfo->is_g4x) { 13099 return 0; 13100 } else { 13101 return 0; 13102 } 13103 default: 13104 unreachable("Invalid hardware generation"); 13105 } 13106 } 13107 13108 13109 13110 /* 3DSTATE_CLIP::Line Strip/List Provoking Vertex Select */ 13111 13112 13113 #define GEN10_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 13114 #define GEN9_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 13115 #define GEN8_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 13116 #define GEN75_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 13117 #define GEN7_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 13118 #define GEN6_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 13119 13120 static inline uint32_t ATTRIBUTE_PURE 13121 _3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits(const struct gen_device_info *devinfo) 13122 { 13123 switch (devinfo->gen) { 13124 case 10: return 2; 13125 case 9: return 2; 13126 case 8: return 2; 13127 case 7: 13128 if (devinfo->is_haswell) { 13129 return 2; 13130 } else { 13131 return 2; 13132 } 13133 case 6: return 2; 13134 case 5: return 0; 13135 case 4: 13136 if (devinfo->is_g4x) { 13137 return 0; 13138 } else { 13139 return 0; 13140 } 13141 default: 13142 unreachable("Invalid hardware generation"); 13143 } 13144 } 13145 13146 13147 13148 #define GEN10_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 13149 #define GEN9_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 13150 #define GEN8_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 13151 #define GEN75_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 13152 #define GEN7_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 13153 #define GEN6_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 13154 13155 static inline uint32_t ATTRIBUTE_PURE 13156 _3DSTATE_CLIP_LineStripListProvokingVertexSelect_start(const struct gen_device_info *devinfo) 13157 { 13158 switch (devinfo->gen) { 13159 case 10: return 66; 13160 case 9: return 66; 13161 case 8: return 66; 13162 case 7: 13163 if (devinfo->is_haswell) { 13164 return 66; 13165 } else { 13166 return 66; 13167 } 13168 case 6: return 66; 13169 case 5: return 0; 13170 case 4: 13171 if (devinfo->is_g4x) { 13172 return 0; 13173 } else { 13174 return 0; 13175 } 13176 default: 13177 unreachable("Invalid hardware generation"); 13178 } 13179 } 13180 13181 13182 13183 /* 3DSTATE_CLIP::Maximum Point Width */ 13184 13185 13186 #define GEN10_3DSTATE_CLIP_MaximumPointWidth_bits 11 13187 #define GEN9_3DSTATE_CLIP_MaximumPointWidth_bits 11 13188 #define GEN8_3DSTATE_CLIP_MaximumPointWidth_bits 11 13189 #define GEN75_3DSTATE_CLIP_MaximumPointWidth_bits 11 13190 #define GEN7_3DSTATE_CLIP_MaximumPointWidth_bits 11 13191 #define GEN6_3DSTATE_CLIP_MaximumPointWidth_bits 11 13192 13193 static inline uint32_t ATTRIBUTE_PURE 13194 _3DSTATE_CLIP_MaximumPointWidth_bits(const struct gen_device_info *devinfo) 13195 { 13196 switch (devinfo->gen) { 13197 case 10: return 11; 13198 case 9: return 11; 13199 case 8: return 11; 13200 case 7: 13201 if (devinfo->is_haswell) { 13202 return 11; 13203 } else { 13204 return 11; 13205 } 13206 case 6: return 11; 13207 case 5: return 0; 13208 case 4: 13209 if (devinfo->is_g4x) { 13210 return 0; 13211 } else { 13212 return 0; 13213 } 13214 default: 13215 unreachable("Invalid hardware generation"); 13216 } 13217 } 13218 13219 13220 13221 #define GEN10_3DSTATE_CLIP_MaximumPointWidth_start 102 13222 #define GEN9_3DSTATE_CLIP_MaximumPointWidth_start 102 13223 #define GEN8_3DSTATE_CLIP_MaximumPointWidth_start 102 13224 #define GEN75_3DSTATE_CLIP_MaximumPointWidth_start 102 13225 #define GEN7_3DSTATE_CLIP_MaximumPointWidth_start 102 13226 #define GEN6_3DSTATE_CLIP_MaximumPointWidth_start 102 13227 13228 static inline uint32_t ATTRIBUTE_PURE 13229 _3DSTATE_CLIP_MaximumPointWidth_start(const struct gen_device_info *devinfo) 13230 { 13231 switch (devinfo->gen) { 13232 case 10: return 102; 13233 case 9: return 102; 13234 case 8: return 102; 13235 case 7: 13236 if (devinfo->is_haswell) { 13237 return 102; 13238 } else { 13239 return 102; 13240 } 13241 case 6: return 102; 13242 case 5: return 0; 13243 case 4: 13244 if (devinfo->is_g4x) { 13245 return 0; 13246 } else { 13247 return 0; 13248 } 13249 default: 13250 unreachable("Invalid hardware generation"); 13251 } 13252 } 13253 13254 13255 13256 /* 3DSTATE_CLIP::Maximum VP Index */ 13257 13258 13259 #define GEN10_3DSTATE_CLIP_MaximumVPIndex_bits 4 13260 #define GEN9_3DSTATE_CLIP_MaximumVPIndex_bits 4 13261 #define GEN8_3DSTATE_CLIP_MaximumVPIndex_bits 4 13262 #define GEN75_3DSTATE_CLIP_MaximumVPIndex_bits 4 13263 #define GEN7_3DSTATE_CLIP_MaximumVPIndex_bits 4 13264 #define GEN6_3DSTATE_CLIP_MaximumVPIndex_bits 4 13265 13266 static inline uint32_t ATTRIBUTE_PURE 13267 _3DSTATE_CLIP_MaximumVPIndex_bits(const struct gen_device_info *devinfo) 13268 { 13269 switch (devinfo->gen) { 13270 case 10: return 4; 13271 case 9: return 4; 13272 case 8: return 4; 13273 case 7: 13274 if (devinfo->is_haswell) { 13275 return 4; 13276 } else { 13277 return 4; 13278 } 13279 case 6: return 4; 13280 case 5: return 0; 13281 case 4: 13282 if (devinfo->is_g4x) { 13283 return 0; 13284 } else { 13285 return 0; 13286 } 13287 default: 13288 unreachable("Invalid hardware generation"); 13289 } 13290 } 13291 13292 13293 13294 #define GEN10_3DSTATE_CLIP_MaximumVPIndex_start 96 13295 #define GEN9_3DSTATE_CLIP_MaximumVPIndex_start 96 13296 #define GEN8_3DSTATE_CLIP_MaximumVPIndex_start 96 13297 #define GEN75_3DSTATE_CLIP_MaximumVPIndex_start 96 13298 #define GEN7_3DSTATE_CLIP_MaximumVPIndex_start 96 13299 #define GEN6_3DSTATE_CLIP_MaximumVPIndex_start 96 13300 13301 static inline uint32_t ATTRIBUTE_PURE 13302 _3DSTATE_CLIP_MaximumVPIndex_start(const struct gen_device_info *devinfo) 13303 { 13304 switch (devinfo->gen) { 13305 case 10: return 96; 13306 case 9: return 96; 13307 case 8: return 96; 13308 case 7: 13309 if (devinfo->is_haswell) { 13310 return 96; 13311 } else { 13312 return 96; 13313 } 13314 case 6: return 96; 13315 case 5: return 0; 13316 case 4: 13317 if (devinfo->is_g4x) { 13318 return 0; 13319 } else { 13320 return 0; 13321 } 13322 default: 13323 unreachable("Invalid hardware generation"); 13324 } 13325 } 13326 13327 13328 13329 /* 3DSTATE_CLIP::Minimum Point Width */ 13330 13331 13332 #define GEN10_3DSTATE_CLIP_MinimumPointWidth_bits 11 13333 #define GEN9_3DSTATE_CLIP_MinimumPointWidth_bits 11 13334 #define GEN8_3DSTATE_CLIP_MinimumPointWidth_bits 11 13335 #define GEN75_3DSTATE_CLIP_MinimumPointWidth_bits 11 13336 #define GEN7_3DSTATE_CLIP_MinimumPointWidth_bits 11 13337 #define GEN6_3DSTATE_CLIP_MinimumPointWidth_bits 11 13338 13339 static inline uint32_t ATTRIBUTE_PURE 13340 _3DSTATE_CLIP_MinimumPointWidth_bits(const struct gen_device_info *devinfo) 13341 { 13342 switch (devinfo->gen) { 13343 case 10: return 11; 13344 case 9: return 11; 13345 case 8: return 11; 13346 case 7: 13347 if (devinfo->is_haswell) { 13348 return 11; 13349 } else { 13350 return 11; 13351 } 13352 case 6: return 11; 13353 case 5: return 0; 13354 case 4: 13355 if (devinfo->is_g4x) { 13356 return 0; 13357 } else { 13358 return 0; 13359 } 13360 default: 13361 unreachable("Invalid hardware generation"); 13362 } 13363 } 13364 13365 13366 13367 #define GEN10_3DSTATE_CLIP_MinimumPointWidth_start 113 13368 #define GEN9_3DSTATE_CLIP_MinimumPointWidth_start 113 13369 #define GEN8_3DSTATE_CLIP_MinimumPointWidth_start 113 13370 #define GEN75_3DSTATE_CLIP_MinimumPointWidth_start 113 13371 #define GEN7_3DSTATE_CLIP_MinimumPointWidth_start 113 13372 #define GEN6_3DSTATE_CLIP_MinimumPointWidth_start 113 13373 13374 static inline uint32_t ATTRIBUTE_PURE 13375 _3DSTATE_CLIP_MinimumPointWidth_start(const struct gen_device_info *devinfo) 13376 { 13377 switch (devinfo->gen) { 13378 case 10: return 113; 13379 case 9: return 113; 13380 case 8: return 113; 13381 case 7: 13382 if (devinfo->is_haswell) { 13383 return 113; 13384 } else { 13385 return 113; 13386 } 13387 case 6: return 113; 13388 case 5: return 0; 13389 case 4: 13390 if (devinfo->is_g4x) { 13391 return 0; 13392 } else { 13393 return 0; 13394 } 13395 default: 13396 unreachable("Invalid hardware generation"); 13397 } 13398 } 13399 13400 13401 13402 /* 3DSTATE_CLIP::Non-Perspective Barycentric Enable */ 13403 13404 13405 #define GEN10_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 13406 #define GEN9_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 13407 #define GEN8_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 13408 #define GEN75_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 13409 #define GEN7_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 13410 #define GEN6_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 13411 13412 static inline uint32_t ATTRIBUTE_PURE 13413 _3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits(const struct gen_device_info *devinfo) 13414 { 13415 switch (devinfo->gen) { 13416 case 10: return 1; 13417 case 9: return 1; 13418 case 8: return 1; 13419 case 7: 13420 if (devinfo->is_haswell) { 13421 return 1; 13422 } else { 13423 return 1; 13424 } 13425 case 6: return 1; 13426 case 5: return 0; 13427 case 4: 13428 if (devinfo->is_g4x) { 13429 return 0; 13430 } else { 13431 return 0; 13432 } 13433 default: 13434 unreachable("Invalid hardware generation"); 13435 } 13436 } 13437 13438 13439 13440 #define GEN10_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 13441 #define GEN9_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 13442 #define GEN8_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 13443 #define GEN75_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 13444 #define GEN7_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 13445 #define GEN6_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 13446 13447 static inline uint32_t ATTRIBUTE_PURE 13448 _3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start(const struct gen_device_info *devinfo) 13449 { 13450 switch (devinfo->gen) { 13451 case 10: return 72; 13452 case 9: return 72; 13453 case 8: return 72; 13454 case 7: 13455 if (devinfo->is_haswell) { 13456 return 72; 13457 } else { 13458 return 72; 13459 } 13460 case 6: return 72; 13461 case 5: return 0; 13462 case 4: 13463 if (devinfo->is_g4x) { 13464 return 0; 13465 } else { 13466 return 0; 13467 } 13468 default: 13469 unreachable("Invalid hardware generation"); 13470 } 13471 } 13472 13473 13474 13475 /* 3DSTATE_CLIP::Perspective Divide Disable */ 13476 13477 13478 #define GEN10_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 13479 #define GEN9_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 13480 #define GEN8_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 13481 #define GEN75_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 13482 #define GEN7_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 13483 #define GEN6_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 13484 13485 static inline uint32_t ATTRIBUTE_PURE 13486 _3DSTATE_CLIP_PerspectiveDivideDisable_bits(const struct gen_device_info *devinfo) 13487 { 13488 switch (devinfo->gen) { 13489 case 10: return 1; 13490 case 9: return 1; 13491 case 8: return 1; 13492 case 7: 13493 if (devinfo->is_haswell) { 13494 return 1; 13495 } else { 13496 return 1; 13497 } 13498 case 6: return 1; 13499 case 5: return 0; 13500 case 4: 13501 if (devinfo->is_g4x) { 13502 return 0; 13503 } else { 13504 return 0; 13505 } 13506 default: 13507 unreachable("Invalid hardware generation"); 13508 } 13509 } 13510 13511 13512 13513 #define GEN10_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 13514 #define GEN9_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 13515 #define GEN8_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 13516 #define GEN75_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 13517 #define GEN7_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 13518 #define GEN6_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 13519 13520 static inline uint32_t ATTRIBUTE_PURE 13521 _3DSTATE_CLIP_PerspectiveDivideDisable_start(const struct gen_device_info *devinfo) 13522 { 13523 switch (devinfo->gen) { 13524 case 10: return 73; 13525 case 9: return 73; 13526 case 8: return 73; 13527 case 7: 13528 if (devinfo->is_haswell) { 13529 return 73; 13530 } else { 13531 return 73; 13532 } 13533 case 6: return 73; 13534 case 5: return 0; 13535 case 4: 13536 if (devinfo->is_g4x) { 13537 return 0; 13538 } else { 13539 return 0; 13540 } 13541 default: 13542 unreachable("Invalid hardware generation"); 13543 } 13544 } 13545 13546 13547 13548 /* 3DSTATE_CLIP::Statistics Enable */ 13549 13550 13551 #define GEN10_3DSTATE_CLIP_StatisticsEnable_bits 1 13552 #define GEN9_3DSTATE_CLIP_StatisticsEnable_bits 1 13553 #define GEN8_3DSTATE_CLIP_StatisticsEnable_bits 1 13554 #define GEN75_3DSTATE_CLIP_StatisticsEnable_bits 1 13555 #define GEN7_3DSTATE_CLIP_StatisticsEnable_bits 1 13556 #define GEN6_3DSTATE_CLIP_StatisticsEnable_bits 1 13557 13558 static inline uint32_t ATTRIBUTE_PURE 13559 _3DSTATE_CLIP_StatisticsEnable_bits(const struct gen_device_info *devinfo) 13560 { 13561 switch (devinfo->gen) { 13562 case 10: return 1; 13563 case 9: return 1; 13564 case 8: return 1; 13565 case 7: 13566 if (devinfo->is_haswell) { 13567 return 1; 13568 } else { 13569 return 1; 13570 } 13571 case 6: return 1; 13572 case 5: return 0; 13573 case 4: 13574 if (devinfo->is_g4x) { 13575 return 0; 13576 } else { 13577 return 0; 13578 } 13579 default: 13580 unreachable("Invalid hardware generation"); 13581 } 13582 } 13583 13584 13585 13586 #define GEN10_3DSTATE_CLIP_StatisticsEnable_start 42 13587 #define GEN9_3DSTATE_CLIP_StatisticsEnable_start 42 13588 #define GEN8_3DSTATE_CLIP_StatisticsEnable_start 42 13589 #define GEN75_3DSTATE_CLIP_StatisticsEnable_start 42 13590 #define GEN7_3DSTATE_CLIP_StatisticsEnable_start 42 13591 #define GEN6_3DSTATE_CLIP_StatisticsEnable_start 42 13592 13593 static inline uint32_t ATTRIBUTE_PURE 13594 _3DSTATE_CLIP_StatisticsEnable_start(const struct gen_device_info *devinfo) 13595 { 13596 switch (devinfo->gen) { 13597 case 10: return 42; 13598 case 9: return 42; 13599 case 8: return 42; 13600 case 7: 13601 if (devinfo->is_haswell) { 13602 return 42; 13603 } else { 13604 return 42; 13605 } 13606 case 6: return 42; 13607 case 5: return 0; 13608 case 4: 13609 if (devinfo->is_g4x) { 13610 return 0; 13611 } else { 13612 return 0; 13613 } 13614 default: 13615 unreachable("Invalid hardware generation"); 13616 } 13617 } 13618 13619 13620 13621 /* 3DSTATE_CLIP::Triangle Fan Provoking Vertex Select */ 13622 13623 13624 #define GEN10_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 13625 #define GEN9_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 13626 #define GEN8_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 13627 #define GEN75_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 13628 #define GEN7_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 13629 #define GEN6_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 13630 13631 static inline uint32_t ATTRIBUTE_PURE 13632 _3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits(const struct gen_device_info *devinfo) 13633 { 13634 switch (devinfo->gen) { 13635 case 10: return 2; 13636 case 9: return 2; 13637 case 8: return 2; 13638 case 7: 13639 if (devinfo->is_haswell) { 13640 return 2; 13641 } else { 13642 return 2; 13643 } 13644 case 6: return 2; 13645 case 5: return 0; 13646 case 4: 13647 if (devinfo->is_g4x) { 13648 return 0; 13649 } else { 13650 return 0; 13651 } 13652 default: 13653 unreachable("Invalid hardware generation"); 13654 } 13655 } 13656 13657 13658 13659 #define GEN10_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 13660 #define GEN9_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 13661 #define GEN8_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 13662 #define GEN75_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 13663 #define GEN7_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 13664 #define GEN6_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 13665 13666 static inline uint32_t ATTRIBUTE_PURE 13667 _3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start(const struct gen_device_info *devinfo) 13668 { 13669 switch (devinfo->gen) { 13670 case 10: return 64; 13671 case 9: return 64; 13672 case 8: return 64; 13673 case 7: 13674 if (devinfo->is_haswell) { 13675 return 64; 13676 } else { 13677 return 64; 13678 } 13679 case 6: return 64; 13680 case 5: return 0; 13681 case 4: 13682 if (devinfo->is_g4x) { 13683 return 0; 13684 } else { 13685 return 0; 13686 } 13687 default: 13688 unreachable("Invalid hardware generation"); 13689 } 13690 } 13691 13692 13693 13694 /* 3DSTATE_CLIP::Triangle Strip/List Provoking Vertex Select */ 13695 13696 13697 #define GEN10_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 13698 #define GEN9_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 13699 #define GEN8_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 13700 #define GEN75_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 13701 #define GEN7_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 13702 #define GEN6_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 13703 13704 static inline uint32_t ATTRIBUTE_PURE 13705 _3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits(const struct gen_device_info *devinfo) 13706 { 13707 switch (devinfo->gen) { 13708 case 10: return 2; 13709 case 9: return 2; 13710 case 8: return 2; 13711 case 7: 13712 if (devinfo->is_haswell) { 13713 return 2; 13714 } else { 13715 return 2; 13716 } 13717 case 6: return 2; 13718 case 5: return 0; 13719 case 4: 13720 if (devinfo->is_g4x) { 13721 return 0; 13722 } else { 13723 return 0; 13724 } 13725 default: 13726 unreachable("Invalid hardware generation"); 13727 } 13728 } 13729 13730 13731 13732 #define GEN10_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 13733 #define GEN9_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 13734 #define GEN8_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 13735 #define GEN75_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 13736 #define GEN7_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 13737 #define GEN6_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 13738 13739 static inline uint32_t ATTRIBUTE_PURE 13740 _3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start(const struct gen_device_info *devinfo) 13741 { 13742 switch (devinfo->gen) { 13743 case 10: return 68; 13744 case 9: return 68; 13745 case 8: return 68; 13746 case 7: 13747 if (devinfo->is_haswell) { 13748 return 68; 13749 } else { 13750 return 68; 13751 } 13752 case 6: return 68; 13753 case 5: return 0; 13754 case 4: 13755 if (devinfo->is_g4x) { 13756 return 0; 13757 } else { 13758 return 0; 13759 } 13760 default: 13761 unreachable("Invalid hardware generation"); 13762 } 13763 } 13764 13765 13766 13767 /* 3DSTATE_CLIP::User Clip Distance Clip Test Enable Bitmask */ 13768 13769 13770 #define GEN10_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 13771 #define GEN9_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 13772 #define GEN8_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 13773 #define GEN75_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 13774 #define GEN7_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 13775 #define GEN6_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 13776 13777 static inline uint32_t ATTRIBUTE_PURE 13778 _3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits(const struct gen_device_info *devinfo) 13779 { 13780 switch (devinfo->gen) { 13781 case 10: return 8; 13782 case 9: return 8; 13783 case 8: return 8; 13784 case 7: 13785 if (devinfo->is_haswell) { 13786 return 8; 13787 } else { 13788 return 8; 13789 } 13790 case 6: return 8; 13791 case 5: return 0; 13792 case 4: 13793 if (devinfo->is_g4x) { 13794 return 0; 13795 } else { 13796 return 0; 13797 } 13798 default: 13799 unreachable("Invalid hardware generation"); 13800 } 13801 } 13802 13803 13804 13805 #define GEN10_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 13806 #define GEN9_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 13807 #define GEN8_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 13808 #define GEN75_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 13809 #define GEN7_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 13810 #define GEN6_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 13811 13812 static inline uint32_t ATTRIBUTE_PURE 13813 _3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start(const struct gen_device_info *devinfo) 13814 { 13815 switch (devinfo->gen) { 13816 case 10: return 80; 13817 case 9: return 80; 13818 case 8: return 80; 13819 case 7: 13820 if (devinfo->is_haswell) { 13821 return 80; 13822 } else { 13823 return 80; 13824 } 13825 case 6: return 80; 13826 case 5: return 0; 13827 case 4: 13828 if (devinfo->is_g4x) { 13829 return 0; 13830 } else { 13831 return 0; 13832 } 13833 default: 13834 unreachable("Invalid hardware generation"); 13835 } 13836 } 13837 13838 13839 13840 /* 3DSTATE_CLIP::User Clip Distance Cull Test Enable Bitmask */ 13841 13842 13843 #define GEN10_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 13844 #define GEN9_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 13845 #define GEN8_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 13846 #define GEN75_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 13847 #define GEN7_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 13848 #define GEN6_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 13849 13850 static inline uint32_t ATTRIBUTE_PURE 13851 _3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits(const struct gen_device_info *devinfo) 13852 { 13853 switch (devinfo->gen) { 13854 case 10: return 8; 13855 case 9: return 8; 13856 case 8: return 8; 13857 case 7: 13858 if (devinfo->is_haswell) { 13859 return 8; 13860 } else { 13861 return 8; 13862 } 13863 case 6: return 8; 13864 case 5: return 0; 13865 case 4: 13866 if (devinfo->is_g4x) { 13867 return 0; 13868 } else { 13869 return 0; 13870 } 13871 default: 13872 unreachable("Invalid hardware generation"); 13873 } 13874 } 13875 13876 13877 13878 #define GEN10_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 13879 #define GEN9_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 13880 #define GEN8_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 13881 #define GEN75_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 13882 #define GEN7_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 13883 #define GEN6_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 13884 13885 static inline uint32_t ATTRIBUTE_PURE 13886 _3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start(const struct gen_device_info *devinfo) 13887 { 13888 switch (devinfo->gen) { 13889 case 10: return 32; 13890 case 9: return 32; 13891 case 8: return 32; 13892 case 7: 13893 if (devinfo->is_haswell) { 13894 return 32; 13895 } else { 13896 return 32; 13897 } 13898 case 6: return 32; 13899 case 5: return 0; 13900 case 4: 13901 if (devinfo->is_g4x) { 13902 return 0; 13903 } else { 13904 return 0; 13905 } 13906 default: 13907 unreachable("Invalid hardware generation"); 13908 } 13909 } 13910 13911 13912 13913 /* 3DSTATE_CLIP::Vertex Sub Pixel Precision Select */ 13914 13915 13916 #define GEN10_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 13917 #define GEN9_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 13918 #define GEN8_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 13919 #define GEN75_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 13920 #define GEN7_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 13921 13922 static inline uint32_t ATTRIBUTE_PURE 13923 _3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits(const struct gen_device_info *devinfo) 13924 { 13925 switch (devinfo->gen) { 13926 case 10: return 1; 13927 case 9: return 1; 13928 case 8: return 1; 13929 case 7: 13930 if (devinfo->is_haswell) { 13931 return 1; 13932 } else { 13933 return 1; 13934 } 13935 case 6: return 0; 13936 case 5: return 0; 13937 case 4: 13938 if (devinfo->is_g4x) { 13939 return 0; 13940 } else { 13941 return 0; 13942 } 13943 default: 13944 unreachable("Invalid hardware generation"); 13945 } 13946 } 13947 13948 13949 13950 #define GEN10_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 13951 #define GEN9_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 13952 #define GEN8_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 13953 #define GEN75_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 13954 #define GEN7_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 13955 13956 static inline uint32_t ATTRIBUTE_PURE 13957 _3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start(const struct gen_device_info *devinfo) 13958 { 13959 switch (devinfo->gen) { 13960 case 10: return 51; 13961 case 9: return 51; 13962 case 8: return 51; 13963 case 7: 13964 if (devinfo->is_haswell) { 13965 return 51; 13966 } else { 13967 return 51; 13968 } 13969 case 6: return 0; 13970 case 5: return 0; 13971 case 4: 13972 if (devinfo->is_g4x) { 13973 return 0; 13974 } else { 13975 return 0; 13976 } 13977 default: 13978 unreachable("Invalid hardware generation"); 13979 } 13980 } 13981 13982 13983 13984 /* 3DSTATE_CLIP::Viewport XY Clip Test Enable */ 13985 13986 13987 #define GEN10_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 13988 #define GEN9_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 13989 #define GEN8_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 13990 #define GEN75_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 13991 #define GEN7_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 13992 #define GEN6_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 13993 13994 static inline uint32_t ATTRIBUTE_PURE 13995 _3DSTATE_CLIP_ViewportXYClipTestEnable_bits(const struct gen_device_info *devinfo) 13996 { 13997 switch (devinfo->gen) { 13998 case 10: return 1; 13999 case 9: return 1; 14000 case 8: return 1; 14001 case 7: 14002 if (devinfo->is_haswell) { 14003 return 1; 14004 } else { 14005 return 1; 14006 } 14007 case 6: return 1; 14008 case 5: return 0; 14009 case 4: 14010 if (devinfo->is_g4x) { 14011 return 0; 14012 } else { 14013 return 0; 14014 } 14015 default: 14016 unreachable("Invalid hardware generation"); 14017 } 14018 } 14019 14020 14021 14022 #define GEN10_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 14023 #define GEN9_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 14024 #define GEN8_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 14025 #define GEN75_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 14026 #define GEN7_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 14027 #define GEN6_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 14028 14029 static inline uint32_t ATTRIBUTE_PURE 14030 _3DSTATE_CLIP_ViewportXYClipTestEnable_start(const struct gen_device_info *devinfo) 14031 { 14032 switch (devinfo->gen) { 14033 case 10: return 92; 14034 case 9: return 92; 14035 case 8: return 92; 14036 case 7: 14037 if (devinfo->is_haswell) { 14038 return 92; 14039 } else { 14040 return 92; 14041 } 14042 case 6: return 92; 14043 case 5: return 0; 14044 case 4: 14045 if (devinfo->is_g4x) { 14046 return 0; 14047 } else { 14048 return 0; 14049 } 14050 default: 14051 unreachable("Invalid hardware generation"); 14052 } 14053 } 14054 14055 14056 14057 /* 3DSTATE_CLIP::Viewport Z Clip Test Enable */ 14058 14059 14060 #define GEN75_3DSTATE_CLIP_ViewportZClipTestEnable_bits 1 14061 #define GEN7_3DSTATE_CLIP_ViewportZClipTestEnable_bits 1 14062 #define GEN6_3DSTATE_CLIP_ViewportZClipTestEnable_bits 1 14063 14064 static inline uint32_t ATTRIBUTE_PURE 14065 _3DSTATE_CLIP_ViewportZClipTestEnable_bits(const struct gen_device_info *devinfo) 14066 { 14067 switch (devinfo->gen) { 14068 case 10: return 0; 14069 case 9: return 0; 14070 case 8: return 0; 14071 case 7: 14072 if (devinfo->is_haswell) { 14073 return 1; 14074 } else { 14075 return 1; 14076 } 14077 case 6: return 1; 14078 case 5: return 0; 14079 case 4: 14080 if (devinfo->is_g4x) { 14081 return 0; 14082 } else { 14083 return 0; 14084 } 14085 default: 14086 unreachable("Invalid hardware generation"); 14087 } 14088 } 14089 14090 14091 14092 #define GEN75_3DSTATE_CLIP_ViewportZClipTestEnable_start 91 14093 #define GEN7_3DSTATE_CLIP_ViewportZClipTestEnable_start 91 14094 #define GEN6_3DSTATE_CLIP_ViewportZClipTestEnable_start 91 14095 14096 static inline uint32_t ATTRIBUTE_PURE 14097 _3DSTATE_CLIP_ViewportZClipTestEnable_start(const struct gen_device_info *devinfo) 14098 { 14099 switch (devinfo->gen) { 14100 case 10: return 0; 14101 case 9: return 0; 14102 case 8: return 0; 14103 case 7: 14104 if (devinfo->is_haswell) { 14105 return 91; 14106 } else { 14107 return 91; 14108 } 14109 case 6: return 91; 14110 case 5: return 0; 14111 case 4: 14112 if (devinfo->is_g4x) { 14113 return 0; 14114 } else { 14115 return 0; 14116 } 14117 default: 14118 unreachable("Invalid hardware generation"); 14119 } 14120 } 14121 14122 14123 14124 /* 3DSTATE_CONSTANT_BODY */ 14125 14126 14127 #define GEN10_3DSTATE_CONSTANT_BODY_length 10 14128 #define GEN9_3DSTATE_CONSTANT_BODY_length 10 14129 #define GEN8_3DSTATE_CONSTANT_BODY_length 10 14130 #define GEN75_3DSTATE_CONSTANT_BODY_length 6 14131 #define GEN7_3DSTATE_CONSTANT_BODY_length 6 14132 14133 static inline uint32_t ATTRIBUTE_PURE 14134 _3DSTATE_CONSTANT_BODY_length(const struct gen_device_info *devinfo) 14135 { 14136 switch (devinfo->gen) { 14137 case 10: return 10; 14138 case 9: return 10; 14139 case 8: return 10; 14140 case 7: 14141 if (devinfo->is_haswell) { 14142 return 6; 14143 } else { 14144 return 6; 14145 } 14146 case 6: return 0; 14147 case 5: return 0; 14148 case 4: 14149 if (devinfo->is_g4x) { 14150 return 0; 14151 } else { 14152 return 0; 14153 } 14154 default: 14155 unreachable("Invalid hardware generation"); 14156 } 14157 } 14158 14159 14160 14161 /* 3DSTATE_CONSTANT_BODY::Buffer */ 14162 14163 14164 #define GEN10_3DSTATE_CONSTANT_BODY_Buffer_bits 59 14165 #define GEN9_3DSTATE_CONSTANT_BODY_Buffer_bits 59 14166 #define GEN8_3DSTATE_CONSTANT_BODY_Buffer_bits 59 14167 #define GEN75_3DSTATE_CONSTANT_BODY_Buffer_bits 27 14168 #define GEN7_3DSTATE_CONSTANT_BODY_Buffer_bits 27 14169 14170 static inline uint32_t ATTRIBUTE_PURE 14171 _3DSTATE_CONSTANT_BODY_Buffer_bits(const struct gen_device_info *devinfo) 14172 { 14173 switch (devinfo->gen) { 14174 case 10: return 59; 14175 case 9: return 59; 14176 case 8: return 59; 14177 case 7: 14178 if (devinfo->is_haswell) { 14179 return 27; 14180 } else { 14181 return 27; 14182 } 14183 case 6: return 0; 14184 case 5: return 0; 14185 case 4: 14186 if (devinfo->is_g4x) { 14187 return 0; 14188 } else { 14189 return 0; 14190 } 14191 default: 14192 unreachable("Invalid hardware generation"); 14193 } 14194 } 14195 14196 14197 14198 #define GEN10_3DSTATE_CONSTANT_BODY_Buffer_start 5 14199 #define GEN9_3DSTATE_CONSTANT_BODY_Buffer_start 5 14200 #define GEN8_3DSTATE_CONSTANT_BODY_Buffer_start 5 14201 #define GEN75_3DSTATE_CONSTANT_BODY_Buffer_start 5 14202 #define GEN7_3DSTATE_CONSTANT_BODY_Buffer_start 5 14203 14204 static inline uint32_t ATTRIBUTE_PURE 14205 _3DSTATE_CONSTANT_BODY_Buffer_start(const struct gen_device_info *devinfo) 14206 { 14207 switch (devinfo->gen) { 14208 case 10: return 5; 14209 case 9: return 5; 14210 case 8: return 5; 14211 case 7: 14212 if (devinfo->is_haswell) { 14213 return 5; 14214 } else { 14215 return 5; 14216 } 14217 case 6: return 0; 14218 case 5: return 0; 14219 case 4: 14220 if (devinfo->is_g4x) { 14221 return 0; 14222 } else { 14223 return 0; 14224 } 14225 default: 14226 unreachable("Invalid hardware generation"); 14227 } 14228 } 14229 14230 14231 14232 /* 3DSTATE_CONSTANT_BODY::Constant Buffer Object Control State */ 14233 14234 14235 #define GEN75_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_bits 5 14236 #define GEN7_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_bits 5 14237 14238 static inline uint32_t ATTRIBUTE_PURE 14239 _3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) 14240 { 14241 switch (devinfo->gen) { 14242 case 10: return 0; 14243 case 9: return 0; 14244 case 8: return 0; 14245 case 7: 14246 if (devinfo->is_haswell) { 14247 return 5; 14248 } else { 14249 return 5; 14250 } 14251 case 6: return 0; 14252 case 5: return 0; 14253 case 4: 14254 if (devinfo->is_g4x) { 14255 return 0; 14256 } else { 14257 return 0; 14258 } 14259 default: 14260 unreachable("Invalid hardware generation"); 14261 } 14262 } 14263 14264 14265 14266 #define GEN75_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_start 64 14267 #define GEN7_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_start 64 14268 14269 static inline uint32_t ATTRIBUTE_PURE 14270 _3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) 14271 { 14272 switch (devinfo->gen) { 14273 case 10: return 0; 14274 case 9: return 0; 14275 case 8: return 0; 14276 case 7: 14277 if (devinfo->is_haswell) { 14278 return 64; 14279 } else { 14280 return 64; 14281 } 14282 case 6: return 0; 14283 case 5: return 0; 14284 case 4: 14285 if (devinfo->is_g4x) { 14286 return 0; 14287 } else { 14288 return 0; 14289 } 14290 default: 14291 unreachable("Invalid hardware generation"); 14292 } 14293 } 14294 14295 14296 14297 /* 3DSTATE_CONSTANT_BODY::Read Length */ 14298 14299 14300 #define GEN10_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 14301 #define GEN9_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 14302 #define GEN8_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 14303 #define GEN75_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 14304 #define GEN7_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 14305 14306 static inline uint32_t ATTRIBUTE_PURE 14307 _3DSTATE_CONSTANT_BODY_ReadLength_bits(const struct gen_device_info *devinfo) 14308 { 14309 switch (devinfo->gen) { 14310 case 10: return 16; 14311 case 9: return 16; 14312 case 8: return 16; 14313 case 7: 14314 if (devinfo->is_haswell) { 14315 return 16; 14316 } else { 14317 return 16; 14318 } 14319 case 6: return 0; 14320 case 5: return 0; 14321 case 4: 14322 if (devinfo->is_g4x) { 14323 return 0; 14324 } else { 14325 return 0; 14326 } 14327 default: 14328 unreachable("Invalid hardware generation"); 14329 } 14330 } 14331 14332 14333 14334 #define GEN10_3DSTATE_CONSTANT_BODY_ReadLength_start 0 14335 #define GEN9_3DSTATE_CONSTANT_BODY_ReadLength_start 0 14336 #define GEN8_3DSTATE_CONSTANT_BODY_ReadLength_start 0 14337 #define GEN75_3DSTATE_CONSTANT_BODY_ReadLength_start 0 14338 #define GEN7_3DSTATE_CONSTANT_BODY_ReadLength_start 0 14339 14340 static inline uint32_t ATTRIBUTE_PURE 14341 _3DSTATE_CONSTANT_BODY_ReadLength_start(const struct gen_device_info *devinfo) 14342 { 14343 switch (devinfo->gen) { 14344 case 10: return 0; 14345 case 9: return 0; 14346 case 8: return 0; 14347 case 7: 14348 if (devinfo->is_haswell) { 14349 return 0; 14350 } else { 14351 return 0; 14352 } 14353 case 6: return 0; 14354 case 5: return 0; 14355 case 4: 14356 if (devinfo->is_g4x) { 14357 return 0; 14358 } else { 14359 return 0; 14360 } 14361 default: 14362 unreachable("Invalid hardware generation"); 14363 } 14364 } 14365 14366 14367 14368 /* 3DSTATE_CONSTANT_COLOR */ 14369 14370 14371 #define GEN5_3DSTATE_CONSTANT_COLOR_length 5 14372 #define GEN45_3DSTATE_CONSTANT_COLOR_length 5 14373 #define GEN4_3DSTATE_CONSTANT_COLOR_length 5 14374 14375 static inline uint32_t ATTRIBUTE_PURE 14376 _3DSTATE_CONSTANT_COLOR_length(const struct gen_device_info *devinfo) 14377 { 14378 switch (devinfo->gen) { 14379 case 10: return 0; 14380 case 9: return 0; 14381 case 8: return 0; 14382 case 7: 14383 if (devinfo->is_haswell) { 14384 return 0; 14385 } else { 14386 return 0; 14387 } 14388 case 6: return 0; 14389 case 5: return 5; 14390 case 4: 14391 if (devinfo->is_g4x) { 14392 return 5; 14393 } else { 14394 return 5; 14395 } 14396 default: 14397 unreachable("Invalid hardware generation"); 14398 } 14399 } 14400 14401 14402 14403 /* 3DSTATE_CONSTANT_COLOR::3D Command Opcode */ 14404 14405 14406 #define GEN5_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits 3 14407 #define GEN45_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits 3 14408 #define GEN4_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits 3 14409 14410 static inline uint32_t ATTRIBUTE_PURE 14411 _3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 14412 { 14413 switch (devinfo->gen) { 14414 case 10: return 0; 14415 case 9: return 0; 14416 case 8: return 0; 14417 case 7: 14418 if (devinfo->is_haswell) { 14419 return 0; 14420 } else { 14421 return 0; 14422 } 14423 case 6: return 0; 14424 case 5: return 3; 14425 case 4: 14426 if (devinfo->is_g4x) { 14427 return 3; 14428 } else { 14429 return 3; 14430 } 14431 default: 14432 unreachable("Invalid hardware generation"); 14433 } 14434 } 14435 14436 14437 14438 #define GEN5_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start 24 14439 #define GEN45_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start 24 14440 #define GEN4_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start 24 14441 14442 static inline uint32_t ATTRIBUTE_PURE 14443 _3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start(const struct gen_device_info *devinfo) 14444 { 14445 switch (devinfo->gen) { 14446 case 10: return 0; 14447 case 9: return 0; 14448 case 8: return 0; 14449 case 7: 14450 if (devinfo->is_haswell) { 14451 return 0; 14452 } else { 14453 return 0; 14454 } 14455 case 6: return 0; 14456 case 5: return 24; 14457 case 4: 14458 if (devinfo->is_g4x) { 14459 return 24; 14460 } else { 14461 return 24; 14462 } 14463 default: 14464 unreachable("Invalid hardware generation"); 14465 } 14466 } 14467 14468 14469 14470 /* 3DSTATE_CONSTANT_COLOR::3D Command Sub Opcode */ 14471 14472 14473 #define GEN5_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits 8 14474 #define GEN45_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits 8 14475 #define GEN4_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits 8 14476 14477 static inline uint32_t ATTRIBUTE_PURE 14478 _3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 14479 { 14480 switch (devinfo->gen) { 14481 case 10: return 0; 14482 case 9: return 0; 14483 case 8: return 0; 14484 case 7: 14485 if (devinfo->is_haswell) { 14486 return 0; 14487 } else { 14488 return 0; 14489 } 14490 case 6: return 0; 14491 case 5: return 8; 14492 case 4: 14493 if (devinfo->is_g4x) { 14494 return 8; 14495 } else { 14496 return 8; 14497 } 14498 default: 14499 unreachable("Invalid hardware generation"); 14500 } 14501 } 14502 14503 14504 14505 #define GEN5_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start 16 14506 #define GEN45_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start 16 14507 #define GEN4_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start 16 14508 14509 static inline uint32_t ATTRIBUTE_PURE 14510 _3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 14511 { 14512 switch (devinfo->gen) { 14513 case 10: return 0; 14514 case 9: return 0; 14515 case 8: return 0; 14516 case 7: 14517 if (devinfo->is_haswell) { 14518 return 0; 14519 } else { 14520 return 0; 14521 } 14522 case 6: return 0; 14523 case 5: return 16; 14524 case 4: 14525 if (devinfo->is_g4x) { 14526 return 16; 14527 } else { 14528 return 16; 14529 } 14530 default: 14531 unreachable("Invalid hardware generation"); 14532 } 14533 } 14534 14535 14536 14537 /* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Alpha */ 14538 14539 14540 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits 32 14541 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits 32 14542 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits 32 14543 14544 static inline uint32_t ATTRIBUTE_PURE 14545 _3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits(const struct gen_device_info *devinfo) 14546 { 14547 switch (devinfo->gen) { 14548 case 10: return 0; 14549 case 9: return 0; 14550 case 8: return 0; 14551 case 7: 14552 if (devinfo->is_haswell) { 14553 return 0; 14554 } else { 14555 return 0; 14556 } 14557 case 6: return 0; 14558 case 5: return 32; 14559 case 4: 14560 if (devinfo->is_g4x) { 14561 return 32; 14562 } else { 14563 return 32; 14564 } 14565 default: 14566 unreachable("Invalid hardware generation"); 14567 } 14568 } 14569 14570 14571 14572 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start 128 14573 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start 128 14574 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start 128 14575 14576 static inline uint32_t ATTRIBUTE_PURE 14577 _3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start(const struct gen_device_info *devinfo) 14578 { 14579 switch (devinfo->gen) { 14580 case 10: return 0; 14581 case 9: return 0; 14582 case 8: return 0; 14583 case 7: 14584 if (devinfo->is_haswell) { 14585 return 0; 14586 } else { 14587 return 0; 14588 } 14589 case 6: return 0; 14590 case 5: return 128; 14591 case 4: 14592 if (devinfo->is_g4x) { 14593 return 128; 14594 } else { 14595 return 128; 14596 } 14597 default: 14598 unreachable("Invalid hardware generation"); 14599 } 14600 } 14601 14602 14603 14604 /* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Blue */ 14605 14606 14607 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits 32 14608 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits 32 14609 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits 32 14610 14611 static inline uint32_t ATTRIBUTE_PURE 14612 _3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits(const struct gen_device_info *devinfo) 14613 { 14614 switch (devinfo->gen) { 14615 case 10: return 0; 14616 case 9: return 0; 14617 case 8: return 0; 14618 case 7: 14619 if (devinfo->is_haswell) { 14620 return 0; 14621 } else { 14622 return 0; 14623 } 14624 case 6: return 0; 14625 case 5: return 32; 14626 case 4: 14627 if (devinfo->is_g4x) { 14628 return 32; 14629 } else { 14630 return 32; 14631 } 14632 default: 14633 unreachable("Invalid hardware generation"); 14634 } 14635 } 14636 14637 14638 14639 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start 96 14640 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start 96 14641 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start 96 14642 14643 static inline uint32_t ATTRIBUTE_PURE 14644 _3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start(const struct gen_device_info *devinfo) 14645 { 14646 switch (devinfo->gen) { 14647 case 10: return 0; 14648 case 9: return 0; 14649 case 8: return 0; 14650 case 7: 14651 if (devinfo->is_haswell) { 14652 return 0; 14653 } else { 14654 return 0; 14655 } 14656 case 6: return 0; 14657 case 5: return 96; 14658 case 4: 14659 if (devinfo->is_g4x) { 14660 return 96; 14661 } else { 14662 return 96; 14663 } 14664 default: 14665 unreachable("Invalid hardware generation"); 14666 } 14667 } 14668 14669 14670 14671 /* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Green */ 14672 14673 14674 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits 32 14675 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits 32 14676 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits 32 14677 14678 static inline uint32_t ATTRIBUTE_PURE 14679 _3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits(const struct gen_device_info *devinfo) 14680 { 14681 switch (devinfo->gen) { 14682 case 10: return 0; 14683 case 9: return 0; 14684 case 8: return 0; 14685 case 7: 14686 if (devinfo->is_haswell) { 14687 return 0; 14688 } else { 14689 return 0; 14690 } 14691 case 6: return 0; 14692 case 5: return 32; 14693 case 4: 14694 if (devinfo->is_g4x) { 14695 return 32; 14696 } else { 14697 return 32; 14698 } 14699 default: 14700 unreachable("Invalid hardware generation"); 14701 } 14702 } 14703 14704 14705 14706 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start 64 14707 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start 64 14708 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start 64 14709 14710 static inline uint32_t ATTRIBUTE_PURE 14711 _3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start(const struct gen_device_info *devinfo) 14712 { 14713 switch (devinfo->gen) { 14714 case 10: return 0; 14715 case 9: return 0; 14716 case 8: return 0; 14717 case 7: 14718 if (devinfo->is_haswell) { 14719 return 0; 14720 } else { 14721 return 0; 14722 } 14723 case 6: return 0; 14724 case 5: return 64; 14725 case 4: 14726 if (devinfo->is_g4x) { 14727 return 64; 14728 } else { 14729 return 64; 14730 } 14731 default: 14732 unreachable("Invalid hardware generation"); 14733 } 14734 } 14735 14736 14737 14738 /* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Red */ 14739 14740 14741 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits 32 14742 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits 32 14743 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits 32 14744 14745 static inline uint32_t ATTRIBUTE_PURE 14746 _3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits(const struct gen_device_info *devinfo) 14747 { 14748 switch (devinfo->gen) { 14749 case 10: return 0; 14750 case 9: return 0; 14751 case 8: return 0; 14752 case 7: 14753 if (devinfo->is_haswell) { 14754 return 0; 14755 } else { 14756 return 0; 14757 } 14758 case 6: return 0; 14759 case 5: return 32; 14760 case 4: 14761 if (devinfo->is_g4x) { 14762 return 32; 14763 } else { 14764 return 32; 14765 } 14766 default: 14767 unreachable("Invalid hardware generation"); 14768 } 14769 } 14770 14771 14772 14773 #define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start 32 14774 #define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start 32 14775 #define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start 32 14776 14777 static inline uint32_t ATTRIBUTE_PURE 14778 _3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start(const struct gen_device_info *devinfo) 14779 { 14780 switch (devinfo->gen) { 14781 case 10: return 0; 14782 case 9: return 0; 14783 case 8: return 0; 14784 case 7: 14785 if (devinfo->is_haswell) { 14786 return 0; 14787 } else { 14788 return 0; 14789 } 14790 case 6: return 0; 14791 case 5: return 32; 14792 case 4: 14793 if (devinfo->is_g4x) { 14794 return 32; 14795 } else { 14796 return 32; 14797 } 14798 default: 14799 unreachable("Invalid hardware generation"); 14800 } 14801 } 14802 14803 14804 14805 /* 3DSTATE_CONSTANT_COLOR::Command SubType */ 14806 14807 14808 #define GEN5_3DSTATE_CONSTANT_COLOR_CommandSubType_bits 2 14809 #define GEN45_3DSTATE_CONSTANT_COLOR_CommandSubType_bits 2 14810 #define GEN4_3DSTATE_CONSTANT_COLOR_CommandSubType_bits 2 14811 14812 static inline uint32_t ATTRIBUTE_PURE 14813 _3DSTATE_CONSTANT_COLOR_CommandSubType_bits(const struct gen_device_info *devinfo) 14814 { 14815 switch (devinfo->gen) { 14816 case 10: return 0; 14817 case 9: return 0; 14818 case 8: return 0; 14819 case 7: 14820 if (devinfo->is_haswell) { 14821 return 0; 14822 } else { 14823 return 0; 14824 } 14825 case 6: return 0; 14826 case 5: return 2; 14827 case 4: 14828 if (devinfo->is_g4x) { 14829 return 2; 14830 } else { 14831 return 2; 14832 } 14833 default: 14834 unreachable("Invalid hardware generation"); 14835 } 14836 } 14837 14838 14839 14840 #define GEN5_3DSTATE_CONSTANT_COLOR_CommandSubType_start 27 14841 #define GEN45_3DSTATE_CONSTANT_COLOR_CommandSubType_start 27 14842 #define GEN4_3DSTATE_CONSTANT_COLOR_CommandSubType_start 27 14843 14844 static inline uint32_t ATTRIBUTE_PURE 14845 _3DSTATE_CONSTANT_COLOR_CommandSubType_start(const struct gen_device_info *devinfo) 14846 { 14847 switch (devinfo->gen) { 14848 case 10: return 0; 14849 case 9: return 0; 14850 case 8: return 0; 14851 case 7: 14852 if (devinfo->is_haswell) { 14853 return 0; 14854 } else { 14855 return 0; 14856 } 14857 case 6: return 0; 14858 case 5: return 27; 14859 case 4: 14860 if (devinfo->is_g4x) { 14861 return 27; 14862 } else { 14863 return 27; 14864 } 14865 default: 14866 unreachable("Invalid hardware generation"); 14867 } 14868 } 14869 14870 14871 14872 /* 3DSTATE_CONSTANT_COLOR::Command Type */ 14873 14874 14875 #define GEN5_3DSTATE_CONSTANT_COLOR_CommandType_bits 3 14876 #define GEN45_3DSTATE_CONSTANT_COLOR_CommandType_bits 3 14877 #define GEN4_3DSTATE_CONSTANT_COLOR_CommandType_bits 3 14878 14879 static inline uint32_t ATTRIBUTE_PURE 14880 _3DSTATE_CONSTANT_COLOR_CommandType_bits(const struct gen_device_info *devinfo) 14881 { 14882 switch (devinfo->gen) { 14883 case 10: return 0; 14884 case 9: return 0; 14885 case 8: return 0; 14886 case 7: 14887 if (devinfo->is_haswell) { 14888 return 0; 14889 } else { 14890 return 0; 14891 } 14892 case 6: return 0; 14893 case 5: return 3; 14894 case 4: 14895 if (devinfo->is_g4x) { 14896 return 3; 14897 } else { 14898 return 3; 14899 } 14900 default: 14901 unreachable("Invalid hardware generation"); 14902 } 14903 } 14904 14905 14906 14907 #define GEN5_3DSTATE_CONSTANT_COLOR_CommandType_start 29 14908 #define GEN45_3DSTATE_CONSTANT_COLOR_CommandType_start 29 14909 #define GEN4_3DSTATE_CONSTANT_COLOR_CommandType_start 29 14910 14911 static inline uint32_t ATTRIBUTE_PURE 14912 _3DSTATE_CONSTANT_COLOR_CommandType_start(const struct gen_device_info *devinfo) 14913 { 14914 switch (devinfo->gen) { 14915 case 10: return 0; 14916 case 9: return 0; 14917 case 8: return 0; 14918 case 7: 14919 if (devinfo->is_haswell) { 14920 return 0; 14921 } else { 14922 return 0; 14923 } 14924 case 6: return 0; 14925 case 5: return 29; 14926 case 4: 14927 if (devinfo->is_g4x) { 14928 return 29; 14929 } else { 14930 return 29; 14931 } 14932 default: 14933 unreachable("Invalid hardware generation"); 14934 } 14935 } 14936 14937 14938 14939 /* 3DSTATE_CONSTANT_COLOR::DWord Length */ 14940 14941 14942 #define GEN5_3DSTATE_CONSTANT_COLOR_DWordLength_bits 8 14943 #define GEN45_3DSTATE_CONSTANT_COLOR_DWordLength_bits 8 14944 #define GEN4_3DSTATE_CONSTANT_COLOR_DWordLength_bits 8 14945 14946 static inline uint32_t ATTRIBUTE_PURE 14947 _3DSTATE_CONSTANT_COLOR_DWordLength_bits(const struct gen_device_info *devinfo) 14948 { 14949 switch (devinfo->gen) { 14950 case 10: return 0; 14951 case 9: return 0; 14952 case 8: return 0; 14953 case 7: 14954 if (devinfo->is_haswell) { 14955 return 0; 14956 } else { 14957 return 0; 14958 } 14959 case 6: return 0; 14960 case 5: return 8; 14961 case 4: 14962 if (devinfo->is_g4x) { 14963 return 8; 14964 } else { 14965 return 8; 14966 } 14967 default: 14968 unreachable("Invalid hardware generation"); 14969 } 14970 } 14971 14972 14973 14974 #define GEN5_3DSTATE_CONSTANT_COLOR_DWordLength_start 0 14975 #define GEN45_3DSTATE_CONSTANT_COLOR_DWordLength_start 0 14976 #define GEN4_3DSTATE_CONSTANT_COLOR_DWordLength_start 0 14977 14978 static inline uint32_t ATTRIBUTE_PURE 14979 _3DSTATE_CONSTANT_COLOR_DWordLength_start(const struct gen_device_info *devinfo) 14980 { 14981 switch (devinfo->gen) { 14982 case 10: return 0; 14983 case 9: return 0; 14984 case 8: return 0; 14985 case 7: 14986 if (devinfo->is_haswell) { 14987 return 0; 14988 } else { 14989 return 0; 14990 } 14991 case 6: return 0; 14992 case 5: return 0; 14993 case 4: 14994 if (devinfo->is_g4x) { 14995 return 0; 14996 } else { 14997 return 0; 14998 } 14999 default: 15000 unreachable("Invalid hardware generation"); 15001 } 15002 } 15003 15004 15005 15006 /* 3DSTATE_CONSTANT_DS */ 15007 15008 15009 #define GEN10_3DSTATE_CONSTANT_DS_length 11 15010 #define GEN9_3DSTATE_CONSTANT_DS_length 11 15011 #define GEN8_3DSTATE_CONSTANT_DS_length 11 15012 #define GEN75_3DSTATE_CONSTANT_DS_length 7 15013 #define GEN7_3DSTATE_CONSTANT_DS_length 7 15014 15015 static inline uint32_t ATTRIBUTE_PURE 15016 _3DSTATE_CONSTANT_DS_length(const struct gen_device_info *devinfo) 15017 { 15018 switch (devinfo->gen) { 15019 case 10: return 11; 15020 case 9: return 11; 15021 case 8: return 11; 15022 case 7: 15023 if (devinfo->is_haswell) { 15024 return 7; 15025 } else { 15026 return 7; 15027 } 15028 case 6: return 0; 15029 case 5: return 0; 15030 case 4: 15031 if (devinfo->is_g4x) { 15032 return 0; 15033 } else { 15034 return 0; 15035 } 15036 default: 15037 unreachable("Invalid hardware generation"); 15038 } 15039 } 15040 15041 15042 15043 /* 3DSTATE_CONSTANT_DS::3D Command Opcode */ 15044 15045 15046 #define GEN10_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 15047 #define GEN9_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 15048 #define GEN8_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 15049 #define GEN75_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 15050 #define GEN7_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 15051 15052 static inline uint32_t ATTRIBUTE_PURE 15053 _3DSTATE_CONSTANT_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 15054 { 15055 switch (devinfo->gen) { 15056 case 10: return 3; 15057 case 9: return 3; 15058 case 8: return 3; 15059 case 7: 15060 if (devinfo->is_haswell) { 15061 return 3; 15062 } else { 15063 return 3; 15064 } 15065 case 6: return 0; 15066 case 5: return 0; 15067 case 4: 15068 if (devinfo->is_g4x) { 15069 return 0; 15070 } else { 15071 return 0; 15072 } 15073 default: 15074 unreachable("Invalid hardware generation"); 15075 } 15076 } 15077 15078 15079 15080 #define GEN10_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 15081 #define GEN9_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 15082 #define GEN8_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 15083 #define GEN75_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 15084 #define GEN7_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 15085 15086 static inline uint32_t ATTRIBUTE_PURE 15087 _3DSTATE_CONSTANT_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 15088 { 15089 switch (devinfo->gen) { 15090 case 10: return 24; 15091 case 9: return 24; 15092 case 8: return 24; 15093 case 7: 15094 if (devinfo->is_haswell) { 15095 return 24; 15096 } else { 15097 return 24; 15098 } 15099 case 6: return 0; 15100 case 5: return 0; 15101 case 4: 15102 if (devinfo->is_g4x) { 15103 return 0; 15104 } else { 15105 return 0; 15106 } 15107 default: 15108 unreachable("Invalid hardware generation"); 15109 } 15110 } 15111 15112 15113 15114 /* 3DSTATE_CONSTANT_DS::3D Command Sub Opcode */ 15115 15116 15117 #define GEN10_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 15118 #define GEN9_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 15119 #define GEN8_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 15120 #define GEN75_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 15121 #define GEN7_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 15122 15123 static inline uint32_t ATTRIBUTE_PURE 15124 _3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 15125 { 15126 switch (devinfo->gen) { 15127 case 10: return 8; 15128 case 9: return 8; 15129 case 8: return 8; 15130 case 7: 15131 if (devinfo->is_haswell) { 15132 return 8; 15133 } else { 15134 return 8; 15135 } 15136 case 6: return 0; 15137 case 5: return 0; 15138 case 4: 15139 if (devinfo->is_g4x) { 15140 return 0; 15141 } else { 15142 return 0; 15143 } 15144 default: 15145 unreachable("Invalid hardware generation"); 15146 } 15147 } 15148 15149 15150 15151 #define GEN10_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 15152 #define GEN9_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 15153 #define GEN8_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 15154 #define GEN75_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 15155 #define GEN7_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 15156 15157 static inline uint32_t ATTRIBUTE_PURE 15158 _3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 15159 { 15160 switch (devinfo->gen) { 15161 case 10: return 16; 15162 case 9: return 16; 15163 case 8: return 16; 15164 case 7: 15165 if (devinfo->is_haswell) { 15166 return 16; 15167 } else { 15168 return 16; 15169 } 15170 case 6: return 0; 15171 case 5: return 0; 15172 case 4: 15173 if (devinfo->is_g4x) { 15174 return 0; 15175 } else { 15176 return 0; 15177 } 15178 default: 15179 unreachable("Invalid hardware generation"); 15180 } 15181 } 15182 15183 15184 15185 /* 3DSTATE_CONSTANT_DS::Command SubType */ 15186 15187 15188 #define GEN10_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 15189 #define GEN9_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 15190 #define GEN8_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 15191 #define GEN75_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 15192 #define GEN7_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 15193 15194 static inline uint32_t ATTRIBUTE_PURE 15195 _3DSTATE_CONSTANT_DS_CommandSubType_bits(const struct gen_device_info *devinfo) 15196 { 15197 switch (devinfo->gen) { 15198 case 10: return 2; 15199 case 9: return 2; 15200 case 8: return 2; 15201 case 7: 15202 if (devinfo->is_haswell) { 15203 return 2; 15204 } else { 15205 return 2; 15206 } 15207 case 6: return 0; 15208 case 5: return 0; 15209 case 4: 15210 if (devinfo->is_g4x) { 15211 return 0; 15212 } else { 15213 return 0; 15214 } 15215 default: 15216 unreachable("Invalid hardware generation"); 15217 } 15218 } 15219 15220 15221 15222 #define GEN10_3DSTATE_CONSTANT_DS_CommandSubType_start 27 15223 #define GEN9_3DSTATE_CONSTANT_DS_CommandSubType_start 27 15224 #define GEN8_3DSTATE_CONSTANT_DS_CommandSubType_start 27 15225 #define GEN75_3DSTATE_CONSTANT_DS_CommandSubType_start 27 15226 #define GEN7_3DSTATE_CONSTANT_DS_CommandSubType_start 27 15227 15228 static inline uint32_t ATTRIBUTE_PURE 15229 _3DSTATE_CONSTANT_DS_CommandSubType_start(const struct gen_device_info *devinfo) 15230 { 15231 switch (devinfo->gen) { 15232 case 10: return 27; 15233 case 9: return 27; 15234 case 8: return 27; 15235 case 7: 15236 if (devinfo->is_haswell) { 15237 return 27; 15238 } else { 15239 return 27; 15240 } 15241 case 6: return 0; 15242 case 5: return 0; 15243 case 4: 15244 if (devinfo->is_g4x) { 15245 return 0; 15246 } else { 15247 return 0; 15248 } 15249 default: 15250 unreachable("Invalid hardware generation"); 15251 } 15252 } 15253 15254 15255 15256 /* 3DSTATE_CONSTANT_DS::Command Type */ 15257 15258 15259 #define GEN10_3DSTATE_CONSTANT_DS_CommandType_bits 3 15260 #define GEN9_3DSTATE_CONSTANT_DS_CommandType_bits 3 15261 #define GEN8_3DSTATE_CONSTANT_DS_CommandType_bits 3 15262 #define GEN75_3DSTATE_CONSTANT_DS_CommandType_bits 3 15263 #define GEN7_3DSTATE_CONSTANT_DS_CommandType_bits 3 15264 15265 static inline uint32_t ATTRIBUTE_PURE 15266 _3DSTATE_CONSTANT_DS_CommandType_bits(const struct gen_device_info *devinfo) 15267 { 15268 switch (devinfo->gen) { 15269 case 10: return 3; 15270 case 9: return 3; 15271 case 8: return 3; 15272 case 7: 15273 if (devinfo->is_haswell) { 15274 return 3; 15275 } else { 15276 return 3; 15277 } 15278 case 6: return 0; 15279 case 5: return 0; 15280 case 4: 15281 if (devinfo->is_g4x) { 15282 return 0; 15283 } else { 15284 return 0; 15285 } 15286 default: 15287 unreachable("Invalid hardware generation"); 15288 } 15289 } 15290 15291 15292 15293 #define GEN10_3DSTATE_CONSTANT_DS_CommandType_start 29 15294 #define GEN9_3DSTATE_CONSTANT_DS_CommandType_start 29 15295 #define GEN8_3DSTATE_CONSTANT_DS_CommandType_start 29 15296 #define GEN75_3DSTATE_CONSTANT_DS_CommandType_start 29 15297 #define GEN7_3DSTATE_CONSTANT_DS_CommandType_start 29 15298 15299 static inline uint32_t ATTRIBUTE_PURE 15300 _3DSTATE_CONSTANT_DS_CommandType_start(const struct gen_device_info *devinfo) 15301 { 15302 switch (devinfo->gen) { 15303 case 10: return 29; 15304 case 9: return 29; 15305 case 8: return 29; 15306 case 7: 15307 if (devinfo->is_haswell) { 15308 return 29; 15309 } else { 15310 return 29; 15311 } 15312 case 6: return 0; 15313 case 5: return 0; 15314 case 4: 15315 if (devinfo->is_g4x) { 15316 return 0; 15317 } else { 15318 return 0; 15319 } 15320 default: 15321 unreachable("Invalid hardware generation"); 15322 } 15323 } 15324 15325 15326 15327 /* 3DSTATE_CONSTANT_DS::Constant Body */ 15328 15329 15330 #define GEN10_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 15331 #define GEN9_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 15332 #define GEN8_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 15333 #define GEN75_3DSTATE_CONSTANT_DS_ConstantBody_bits 192 15334 #define GEN7_3DSTATE_CONSTANT_DS_ConstantBody_bits 192 15335 15336 static inline uint32_t ATTRIBUTE_PURE 15337 _3DSTATE_CONSTANT_DS_ConstantBody_bits(const struct gen_device_info *devinfo) 15338 { 15339 switch (devinfo->gen) { 15340 case 10: return 320; 15341 case 9: return 320; 15342 case 8: return 320; 15343 case 7: 15344 if (devinfo->is_haswell) { 15345 return 192; 15346 } else { 15347 return 192; 15348 } 15349 case 6: return 0; 15350 case 5: return 0; 15351 case 4: 15352 if (devinfo->is_g4x) { 15353 return 0; 15354 } else { 15355 return 0; 15356 } 15357 default: 15358 unreachable("Invalid hardware generation"); 15359 } 15360 } 15361 15362 15363 15364 #define GEN10_3DSTATE_CONSTANT_DS_ConstantBody_start 32 15365 #define GEN9_3DSTATE_CONSTANT_DS_ConstantBody_start 32 15366 #define GEN8_3DSTATE_CONSTANT_DS_ConstantBody_start 32 15367 #define GEN75_3DSTATE_CONSTANT_DS_ConstantBody_start 32 15368 #define GEN7_3DSTATE_CONSTANT_DS_ConstantBody_start 32 15369 15370 static inline uint32_t ATTRIBUTE_PURE 15371 _3DSTATE_CONSTANT_DS_ConstantBody_start(const struct gen_device_info *devinfo) 15372 { 15373 switch (devinfo->gen) { 15374 case 10: return 32; 15375 case 9: return 32; 15376 case 8: return 32; 15377 case 7: 15378 if (devinfo->is_haswell) { 15379 return 32; 15380 } else { 15381 return 32; 15382 } 15383 case 6: return 0; 15384 case 5: return 0; 15385 case 4: 15386 if (devinfo->is_g4x) { 15387 return 0; 15388 } else { 15389 return 0; 15390 } 15391 default: 15392 unreachable("Invalid hardware generation"); 15393 } 15394 } 15395 15396 15397 15398 /* 3DSTATE_CONSTANT_DS::Constant Buffer Object Control State */ 15399 15400 15401 #define GEN10_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits 7 15402 #define GEN9_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits 7 15403 #define GEN8_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits 7 15404 15405 static inline uint32_t ATTRIBUTE_PURE 15406 _3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) 15407 { 15408 switch (devinfo->gen) { 15409 case 10: return 7; 15410 case 9: return 7; 15411 case 8: return 7; 15412 case 7: 15413 if (devinfo->is_haswell) { 15414 return 0; 15415 } else { 15416 return 0; 15417 } 15418 case 6: return 0; 15419 case 5: return 0; 15420 case 4: 15421 if (devinfo->is_g4x) { 15422 return 0; 15423 } else { 15424 return 0; 15425 } 15426 default: 15427 unreachable("Invalid hardware generation"); 15428 } 15429 } 15430 15431 15432 15433 #define GEN10_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start 8 15434 #define GEN9_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start 8 15435 #define GEN8_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start 8 15436 15437 static inline uint32_t ATTRIBUTE_PURE 15438 _3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) 15439 { 15440 switch (devinfo->gen) { 15441 case 10: return 8; 15442 case 9: return 8; 15443 case 8: return 8; 15444 case 7: 15445 if (devinfo->is_haswell) { 15446 return 0; 15447 } else { 15448 return 0; 15449 } 15450 case 6: return 0; 15451 case 5: return 0; 15452 case 4: 15453 if (devinfo->is_g4x) { 15454 return 0; 15455 } else { 15456 return 0; 15457 } 15458 default: 15459 unreachable("Invalid hardware generation"); 15460 } 15461 } 15462 15463 15464 15465 /* 3DSTATE_CONSTANT_DS::DWord Length */ 15466 15467 15468 #define GEN10_3DSTATE_CONSTANT_DS_DWordLength_bits 8 15469 #define GEN9_3DSTATE_CONSTANT_DS_DWordLength_bits 8 15470 #define GEN8_3DSTATE_CONSTANT_DS_DWordLength_bits 8 15471 #define GEN75_3DSTATE_CONSTANT_DS_DWordLength_bits 8 15472 #define GEN7_3DSTATE_CONSTANT_DS_DWordLength_bits 8 15473 15474 static inline uint32_t ATTRIBUTE_PURE 15475 _3DSTATE_CONSTANT_DS_DWordLength_bits(const struct gen_device_info *devinfo) 15476 { 15477 switch (devinfo->gen) { 15478 case 10: return 8; 15479 case 9: return 8; 15480 case 8: return 8; 15481 case 7: 15482 if (devinfo->is_haswell) { 15483 return 8; 15484 } else { 15485 return 8; 15486 } 15487 case 6: return 0; 15488 case 5: return 0; 15489 case 4: 15490 if (devinfo->is_g4x) { 15491 return 0; 15492 } else { 15493 return 0; 15494 } 15495 default: 15496 unreachable("Invalid hardware generation"); 15497 } 15498 } 15499 15500 15501 15502 #define GEN10_3DSTATE_CONSTANT_DS_DWordLength_start 0 15503 #define GEN9_3DSTATE_CONSTANT_DS_DWordLength_start 0 15504 #define GEN8_3DSTATE_CONSTANT_DS_DWordLength_start 0 15505 #define GEN75_3DSTATE_CONSTANT_DS_DWordLength_start 0 15506 #define GEN7_3DSTATE_CONSTANT_DS_DWordLength_start 0 15507 15508 static inline uint32_t ATTRIBUTE_PURE 15509 _3DSTATE_CONSTANT_DS_DWordLength_start(const struct gen_device_info *devinfo) 15510 { 15511 switch (devinfo->gen) { 15512 case 10: return 0; 15513 case 9: return 0; 15514 case 8: return 0; 15515 case 7: 15516 if (devinfo->is_haswell) { 15517 return 0; 15518 } else { 15519 return 0; 15520 } 15521 case 6: return 0; 15522 case 5: return 0; 15523 case 4: 15524 if (devinfo->is_g4x) { 15525 return 0; 15526 } else { 15527 return 0; 15528 } 15529 default: 15530 unreachable("Invalid hardware generation"); 15531 } 15532 } 15533 15534 15535 15536 /* 3DSTATE_CONSTANT_GS */ 15537 15538 15539 #define GEN10_3DSTATE_CONSTANT_GS_length 11 15540 #define GEN9_3DSTATE_CONSTANT_GS_length 11 15541 #define GEN8_3DSTATE_CONSTANT_GS_length 11 15542 #define GEN75_3DSTATE_CONSTANT_GS_length 7 15543 #define GEN7_3DSTATE_CONSTANT_GS_length 7 15544 #define GEN6_3DSTATE_CONSTANT_GS_length 5 15545 15546 static inline uint32_t ATTRIBUTE_PURE 15547 _3DSTATE_CONSTANT_GS_length(const struct gen_device_info *devinfo) 15548 { 15549 switch (devinfo->gen) { 15550 case 10: return 11; 15551 case 9: return 11; 15552 case 8: return 11; 15553 case 7: 15554 if (devinfo->is_haswell) { 15555 return 7; 15556 } else { 15557 return 7; 15558 } 15559 case 6: return 5; 15560 case 5: return 0; 15561 case 4: 15562 if (devinfo->is_g4x) { 15563 return 0; 15564 } else { 15565 return 0; 15566 } 15567 default: 15568 unreachable("Invalid hardware generation"); 15569 } 15570 } 15571 15572 15573 15574 /* 3DSTATE_CONSTANT_GS::3D Command Opcode */ 15575 15576 15577 #define GEN10_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 15578 #define GEN9_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 15579 #define GEN8_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 15580 #define GEN75_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 15581 #define GEN7_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 15582 #define GEN6_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 15583 15584 static inline uint32_t ATTRIBUTE_PURE 15585 _3DSTATE_CONSTANT_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 15586 { 15587 switch (devinfo->gen) { 15588 case 10: return 3; 15589 case 9: return 3; 15590 case 8: return 3; 15591 case 7: 15592 if (devinfo->is_haswell) { 15593 return 3; 15594 } else { 15595 return 3; 15596 } 15597 case 6: return 3; 15598 case 5: return 0; 15599 case 4: 15600 if (devinfo->is_g4x) { 15601 return 0; 15602 } else { 15603 return 0; 15604 } 15605 default: 15606 unreachable("Invalid hardware generation"); 15607 } 15608 } 15609 15610 15611 15612 #define GEN10_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 15613 #define GEN9_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 15614 #define GEN8_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 15615 #define GEN75_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 15616 #define GEN7_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 15617 #define GEN6_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 15618 15619 static inline uint32_t ATTRIBUTE_PURE 15620 _3DSTATE_CONSTANT_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 15621 { 15622 switch (devinfo->gen) { 15623 case 10: return 24; 15624 case 9: return 24; 15625 case 8: return 24; 15626 case 7: 15627 if (devinfo->is_haswell) { 15628 return 24; 15629 } else { 15630 return 24; 15631 } 15632 case 6: return 24; 15633 case 5: return 0; 15634 case 4: 15635 if (devinfo->is_g4x) { 15636 return 0; 15637 } else { 15638 return 0; 15639 } 15640 default: 15641 unreachable("Invalid hardware generation"); 15642 } 15643 } 15644 15645 15646 15647 /* 3DSTATE_CONSTANT_GS::3D Command Sub Opcode */ 15648 15649 15650 #define GEN10_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 15651 #define GEN9_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 15652 #define GEN8_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 15653 #define GEN75_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 15654 #define GEN7_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 15655 #define GEN6_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 15656 15657 static inline uint32_t ATTRIBUTE_PURE 15658 _3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 15659 { 15660 switch (devinfo->gen) { 15661 case 10: return 8; 15662 case 9: return 8; 15663 case 8: return 8; 15664 case 7: 15665 if (devinfo->is_haswell) { 15666 return 8; 15667 } else { 15668 return 8; 15669 } 15670 case 6: return 8; 15671 case 5: return 0; 15672 case 4: 15673 if (devinfo->is_g4x) { 15674 return 0; 15675 } else { 15676 return 0; 15677 } 15678 default: 15679 unreachable("Invalid hardware generation"); 15680 } 15681 } 15682 15683 15684 15685 #define GEN10_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 15686 #define GEN9_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 15687 #define GEN8_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 15688 #define GEN75_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 15689 #define GEN7_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 15690 #define GEN6_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 15691 15692 static inline uint32_t ATTRIBUTE_PURE 15693 _3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 15694 { 15695 switch (devinfo->gen) { 15696 case 10: return 16; 15697 case 9: return 16; 15698 case 8: return 16; 15699 case 7: 15700 if (devinfo->is_haswell) { 15701 return 16; 15702 } else { 15703 return 16; 15704 } 15705 case 6: return 16; 15706 case 5: return 0; 15707 case 4: 15708 if (devinfo->is_g4x) { 15709 return 0; 15710 } else { 15711 return 0; 15712 } 15713 default: 15714 unreachable("Invalid hardware generation"); 15715 } 15716 } 15717 15718 15719 15720 /* 3DSTATE_CONSTANT_GS::Buffer 0 Valid */ 15721 15722 15723 #define GEN6_3DSTATE_CONSTANT_GS_Buffer0Valid_bits 1 15724 15725 static inline uint32_t ATTRIBUTE_PURE 15726 _3DSTATE_CONSTANT_GS_Buffer0Valid_bits(const struct gen_device_info *devinfo) 15727 { 15728 switch (devinfo->gen) { 15729 case 10: return 0; 15730 case 9: return 0; 15731 case 8: return 0; 15732 case 7: 15733 if (devinfo->is_haswell) { 15734 return 0; 15735 } else { 15736 return 0; 15737 } 15738 case 6: return 1; 15739 case 5: return 0; 15740 case 4: 15741 if (devinfo->is_g4x) { 15742 return 0; 15743 } else { 15744 return 0; 15745 } 15746 default: 15747 unreachable("Invalid hardware generation"); 15748 } 15749 } 15750 15751 15752 15753 #define GEN6_3DSTATE_CONSTANT_GS_Buffer0Valid_start 12 15754 15755 static inline uint32_t ATTRIBUTE_PURE 15756 _3DSTATE_CONSTANT_GS_Buffer0Valid_start(const struct gen_device_info *devinfo) 15757 { 15758 switch (devinfo->gen) { 15759 case 10: return 0; 15760 case 9: return 0; 15761 case 8: return 0; 15762 case 7: 15763 if (devinfo->is_haswell) { 15764 return 0; 15765 } else { 15766 return 0; 15767 } 15768 case 6: return 12; 15769 case 5: return 0; 15770 case 4: 15771 if (devinfo->is_g4x) { 15772 return 0; 15773 } else { 15774 return 0; 15775 } 15776 default: 15777 unreachable("Invalid hardware generation"); 15778 } 15779 } 15780 15781 15782 15783 /* 3DSTATE_CONSTANT_GS::Buffer 1 Valid */ 15784 15785 15786 #define GEN6_3DSTATE_CONSTANT_GS_Buffer1Valid_bits 1 15787 15788 static inline uint32_t ATTRIBUTE_PURE 15789 _3DSTATE_CONSTANT_GS_Buffer1Valid_bits(const struct gen_device_info *devinfo) 15790 { 15791 switch (devinfo->gen) { 15792 case 10: return 0; 15793 case 9: return 0; 15794 case 8: return 0; 15795 case 7: 15796 if (devinfo->is_haswell) { 15797 return 0; 15798 } else { 15799 return 0; 15800 } 15801 case 6: return 1; 15802 case 5: return 0; 15803 case 4: 15804 if (devinfo->is_g4x) { 15805 return 0; 15806 } else { 15807 return 0; 15808 } 15809 default: 15810 unreachable("Invalid hardware generation"); 15811 } 15812 } 15813 15814 15815 15816 #define GEN6_3DSTATE_CONSTANT_GS_Buffer1Valid_start 13 15817 15818 static inline uint32_t ATTRIBUTE_PURE 15819 _3DSTATE_CONSTANT_GS_Buffer1Valid_start(const struct gen_device_info *devinfo) 15820 { 15821 switch (devinfo->gen) { 15822 case 10: return 0; 15823 case 9: return 0; 15824 case 8: return 0; 15825 case 7: 15826 if (devinfo->is_haswell) { 15827 return 0; 15828 } else { 15829 return 0; 15830 } 15831 case 6: return 13; 15832 case 5: return 0; 15833 case 4: 15834 if (devinfo->is_g4x) { 15835 return 0; 15836 } else { 15837 return 0; 15838 } 15839 default: 15840 unreachable("Invalid hardware generation"); 15841 } 15842 } 15843 15844 15845 15846 /* 3DSTATE_CONSTANT_GS::Buffer 2 Valid */ 15847 15848 15849 #define GEN6_3DSTATE_CONSTANT_GS_Buffer2Valid_bits 1 15850 15851 static inline uint32_t ATTRIBUTE_PURE 15852 _3DSTATE_CONSTANT_GS_Buffer2Valid_bits(const struct gen_device_info *devinfo) 15853 { 15854 switch (devinfo->gen) { 15855 case 10: return 0; 15856 case 9: return 0; 15857 case 8: return 0; 15858 case 7: 15859 if (devinfo->is_haswell) { 15860 return 0; 15861 } else { 15862 return 0; 15863 } 15864 case 6: return 1; 15865 case 5: return 0; 15866 case 4: 15867 if (devinfo->is_g4x) { 15868 return 0; 15869 } else { 15870 return 0; 15871 } 15872 default: 15873 unreachable("Invalid hardware generation"); 15874 } 15875 } 15876 15877 15878 15879 #define GEN6_3DSTATE_CONSTANT_GS_Buffer2Valid_start 14 15880 15881 static inline uint32_t ATTRIBUTE_PURE 15882 _3DSTATE_CONSTANT_GS_Buffer2Valid_start(const struct gen_device_info *devinfo) 15883 { 15884 switch (devinfo->gen) { 15885 case 10: return 0; 15886 case 9: return 0; 15887 case 8: return 0; 15888 case 7: 15889 if (devinfo->is_haswell) { 15890 return 0; 15891 } else { 15892 return 0; 15893 } 15894 case 6: return 14; 15895 case 5: return 0; 15896 case 4: 15897 if (devinfo->is_g4x) { 15898 return 0; 15899 } else { 15900 return 0; 15901 } 15902 default: 15903 unreachable("Invalid hardware generation"); 15904 } 15905 } 15906 15907 15908 15909 /* 3DSTATE_CONSTANT_GS::Buffer 3 Valid */ 15910 15911 15912 #define GEN6_3DSTATE_CONSTANT_GS_Buffer3Valid_bits 1 15913 15914 static inline uint32_t ATTRIBUTE_PURE 15915 _3DSTATE_CONSTANT_GS_Buffer3Valid_bits(const struct gen_device_info *devinfo) 15916 { 15917 switch (devinfo->gen) { 15918 case 10: return 0; 15919 case 9: return 0; 15920 case 8: return 0; 15921 case 7: 15922 if (devinfo->is_haswell) { 15923 return 0; 15924 } else { 15925 return 0; 15926 } 15927 case 6: return 1; 15928 case 5: return 0; 15929 case 4: 15930 if (devinfo->is_g4x) { 15931 return 0; 15932 } else { 15933 return 0; 15934 } 15935 default: 15936 unreachable("Invalid hardware generation"); 15937 } 15938 } 15939 15940 15941 15942 #define GEN6_3DSTATE_CONSTANT_GS_Buffer3Valid_start 15 15943 15944 static inline uint32_t ATTRIBUTE_PURE 15945 _3DSTATE_CONSTANT_GS_Buffer3Valid_start(const struct gen_device_info *devinfo) 15946 { 15947 switch (devinfo->gen) { 15948 case 10: return 0; 15949 case 9: return 0; 15950 case 8: return 0; 15951 case 7: 15952 if (devinfo->is_haswell) { 15953 return 0; 15954 } else { 15955 return 0; 15956 } 15957 case 6: return 15; 15958 case 5: return 0; 15959 case 4: 15960 if (devinfo->is_g4x) { 15961 return 0; 15962 } else { 15963 return 0; 15964 } 15965 default: 15966 unreachable("Invalid hardware generation"); 15967 } 15968 } 15969 15970 15971 15972 /* 3DSTATE_CONSTANT_GS::Command SubType */ 15973 15974 15975 #define GEN10_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 15976 #define GEN9_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 15977 #define GEN8_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 15978 #define GEN75_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 15979 #define GEN7_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 15980 #define GEN6_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 15981 15982 static inline uint32_t ATTRIBUTE_PURE 15983 _3DSTATE_CONSTANT_GS_CommandSubType_bits(const struct gen_device_info *devinfo) 15984 { 15985 switch (devinfo->gen) { 15986 case 10: return 2; 15987 case 9: return 2; 15988 case 8: return 2; 15989 case 7: 15990 if (devinfo->is_haswell) { 15991 return 2; 15992 } else { 15993 return 2; 15994 } 15995 case 6: return 2; 15996 case 5: return 0; 15997 case 4: 15998 if (devinfo->is_g4x) { 15999 return 0; 16000 } else { 16001 return 0; 16002 } 16003 default: 16004 unreachable("Invalid hardware generation"); 16005 } 16006 } 16007 16008 16009 16010 #define GEN10_3DSTATE_CONSTANT_GS_CommandSubType_start 27 16011 #define GEN9_3DSTATE_CONSTANT_GS_CommandSubType_start 27 16012 #define GEN8_3DSTATE_CONSTANT_GS_CommandSubType_start 27 16013 #define GEN75_3DSTATE_CONSTANT_GS_CommandSubType_start 27 16014 #define GEN7_3DSTATE_CONSTANT_GS_CommandSubType_start 27 16015 #define GEN6_3DSTATE_CONSTANT_GS_CommandSubType_start 27 16016 16017 static inline uint32_t ATTRIBUTE_PURE 16018 _3DSTATE_CONSTANT_GS_CommandSubType_start(const struct gen_device_info *devinfo) 16019 { 16020 switch (devinfo->gen) { 16021 case 10: return 27; 16022 case 9: return 27; 16023 case 8: return 27; 16024 case 7: 16025 if (devinfo->is_haswell) { 16026 return 27; 16027 } else { 16028 return 27; 16029 } 16030 case 6: return 27; 16031 case 5: return 0; 16032 case 4: 16033 if (devinfo->is_g4x) { 16034 return 0; 16035 } else { 16036 return 0; 16037 } 16038 default: 16039 unreachable("Invalid hardware generation"); 16040 } 16041 } 16042 16043 16044 16045 /* 3DSTATE_CONSTANT_GS::Command Type */ 16046 16047 16048 #define GEN10_3DSTATE_CONSTANT_GS_CommandType_bits 3 16049 #define GEN9_3DSTATE_CONSTANT_GS_CommandType_bits 3 16050 #define GEN8_3DSTATE_CONSTANT_GS_CommandType_bits 3 16051 #define GEN75_3DSTATE_CONSTANT_GS_CommandType_bits 3 16052 #define GEN7_3DSTATE_CONSTANT_GS_CommandType_bits 3 16053 #define GEN6_3DSTATE_CONSTANT_GS_CommandType_bits 3 16054 16055 static inline uint32_t ATTRIBUTE_PURE 16056 _3DSTATE_CONSTANT_GS_CommandType_bits(const struct gen_device_info *devinfo) 16057 { 16058 switch (devinfo->gen) { 16059 case 10: return 3; 16060 case 9: return 3; 16061 case 8: return 3; 16062 case 7: 16063 if (devinfo->is_haswell) { 16064 return 3; 16065 } else { 16066 return 3; 16067 } 16068 case 6: return 3; 16069 case 5: return 0; 16070 case 4: 16071 if (devinfo->is_g4x) { 16072 return 0; 16073 } else { 16074 return 0; 16075 } 16076 default: 16077 unreachable("Invalid hardware generation"); 16078 } 16079 } 16080 16081 16082 16083 #define GEN10_3DSTATE_CONSTANT_GS_CommandType_start 29 16084 #define GEN9_3DSTATE_CONSTANT_GS_CommandType_start 29 16085 #define GEN8_3DSTATE_CONSTANT_GS_CommandType_start 29 16086 #define GEN75_3DSTATE_CONSTANT_GS_CommandType_start 29 16087 #define GEN7_3DSTATE_CONSTANT_GS_CommandType_start 29 16088 #define GEN6_3DSTATE_CONSTANT_GS_CommandType_start 29 16089 16090 static inline uint32_t ATTRIBUTE_PURE 16091 _3DSTATE_CONSTANT_GS_CommandType_start(const struct gen_device_info *devinfo) 16092 { 16093 switch (devinfo->gen) { 16094 case 10: return 29; 16095 case 9: return 29; 16096 case 8: return 29; 16097 case 7: 16098 if (devinfo->is_haswell) { 16099 return 29; 16100 } else { 16101 return 29; 16102 } 16103 case 6: return 29; 16104 case 5: return 0; 16105 case 4: 16106 if (devinfo->is_g4x) { 16107 return 0; 16108 } else { 16109 return 0; 16110 } 16111 default: 16112 unreachable("Invalid hardware generation"); 16113 } 16114 } 16115 16116 16117 16118 /* 3DSTATE_CONSTANT_GS::Constant Body */ 16119 16120 16121 #define GEN10_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 16122 #define GEN9_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 16123 #define GEN8_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 16124 #define GEN75_3DSTATE_CONSTANT_GS_ConstantBody_bits 192 16125 #define GEN7_3DSTATE_CONSTANT_GS_ConstantBody_bits 192 16126 16127 static inline uint32_t ATTRIBUTE_PURE 16128 _3DSTATE_CONSTANT_GS_ConstantBody_bits(const struct gen_device_info *devinfo) 16129 { 16130 switch (devinfo->gen) { 16131 case 10: return 320; 16132 case 9: return 320; 16133 case 8: return 320; 16134 case 7: 16135 if (devinfo->is_haswell) { 16136 return 192; 16137 } else { 16138 return 192; 16139 } 16140 case 6: return 0; 16141 case 5: return 0; 16142 case 4: 16143 if (devinfo->is_g4x) { 16144 return 0; 16145 } else { 16146 return 0; 16147 } 16148 default: 16149 unreachable("Invalid hardware generation"); 16150 } 16151 } 16152 16153 16154 16155 #define GEN10_3DSTATE_CONSTANT_GS_ConstantBody_start 32 16156 #define GEN9_3DSTATE_CONSTANT_GS_ConstantBody_start 32 16157 #define GEN8_3DSTATE_CONSTANT_GS_ConstantBody_start 32 16158 #define GEN75_3DSTATE_CONSTANT_GS_ConstantBody_start 32 16159 #define GEN7_3DSTATE_CONSTANT_GS_ConstantBody_start 32 16160 16161 static inline uint32_t ATTRIBUTE_PURE 16162 _3DSTATE_CONSTANT_GS_ConstantBody_start(const struct gen_device_info *devinfo) 16163 { 16164 switch (devinfo->gen) { 16165 case 10: return 32; 16166 case 9: return 32; 16167 case 8: return 32; 16168 case 7: 16169 if (devinfo->is_haswell) { 16170 return 32; 16171 } else { 16172 return 32; 16173 } 16174 case 6: return 0; 16175 case 5: return 0; 16176 case 4: 16177 if (devinfo->is_g4x) { 16178 return 0; 16179 } else { 16180 return 0; 16181 } 16182 default: 16183 unreachable("Invalid hardware generation"); 16184 } 16185 } 16186 16187 16188 16189 /* 3DSTATE_CONSTANT_GS::Constant Buffer Object Control State */ 16190 16191 16192 #define GEN10_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 7 16193 #define GEN9_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 7 16194 #define GEN8_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 7 16195 #define GEN6_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 4 16196 16197 static inline uint32_t ATTRIBUTE_PURE 16198 _3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) 16199 { 16200 switch (devinfo->gen) { 16201 case 10: return 7; 16202 case 9: return 7; 16203 case 8: return 7; 16204 case 7: 16205 if (devinfo->is_haswell) { 16206 return 0; 16207 } else { 16208 return 0; 16209 } 16210 case 6: return 4; 16211 case 5: return 0; 16212 case 4: 16213 if (devinfo->is_g4x) { 16214 return 0; 16215 } else { 16216 return 0; 16217 } 16218 default: 16219 unreachable("Invalid hardware generation"); 16220 } 16221 } 16222 16223 16224 16225 #define GEN10_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 16226 #define GEN9_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 16227 #define GEN8_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 16228 #define GEN6_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 16229 16230 static inline uint32_t ATTRIBUTE_PURE 16231 _3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) 16232 { 16233 switch (devinfo->gen) { 16234 case 10: return 8; 16235 case 9: return 8; 16236 case 8: return 8; 16237 case 7: 16238 if (devinfo->is_haswell) { 16239 return 0; 16240 } else { 16241 return 0; 16242 } 16243 case 6: return 8; 16244 case 5: return 0; 16245 case 4: 16246 if (devinfo->is_g4x) { 16247 return 0; 16248 } else { 16249 return 0; 16250 } 16251 default: 16252 unreachable("Invalid hardware generation"); 16253 } 16254 } 16255 16256 16257 16258 /* 3DSTATE_CONSTANT_GS::DWord Length */ 16259 16260 16261 #define GEN10_3DSTATE_CONSTANT_GS_DWordLength_bits 8 16262 #define GEN9_3DSTATE_CONSTANT_GS_DWordLength_bits 8 16263 #define GEN8_3DSTATE_CONSTANT_GS_DWordLength_bits 8 16264 #define GEN75_3DSTATE_CONSTANT_GS_DWordLength_bits 8 16265 #define GEN7_3DSTATE_CONSTANT_GS_DWordLength_bits 8 16266 #define GEN6_3DSTATE_CONSTANT_GS_DWordLength_bits 8 16267 16268 static inline uint32_t ATTRIBUTE_PURE 16269 _3DSTATE_CONSTANT_GS_DWordLength_bits(const struct gen_device_info *devinfo) 16270 { 16271 switch (devinfo->gen) { 16272 case 10: return 8; 16273 case 9: return 8; 16274 case 8: return 8; 16275 case 7: 16276 if (devinfo->is_haswell) { 16277 return 8; 16278 } else { 16279 return 8; 16280 } 16281 case 6: return 8; 16282 case 5: return 0; 16283 case 4: 16284 if (devinfo->is_g4x) { 16285 return 0; 16286 } else { 16287 return 0; 16288 } 16289 default: 16290 unreachable("Invalid hardware generation"); 16291 } 16292 } 16293 16294 16295 16296 #define GEN10_3DSTATE_CONSTANT_GS_DWordLength_start 0 16297 #define GEN9_3DSTATE_CONSTANT_GS_DWordLength_start 0 16298 #define GEN8_3DSTATE_CONSTANT_GS_DWordLength_start 0 16299 #define GEN75_3DSTATE_CONSTANT_GS_DWordLength_start 0 16300 #define GEN7_3DSTATE_CONSTANT_GS_DWordLength_start 0 16301 #define GEN6_3DSTATE_CONSTANT_GS_DWordLength_start 0 16302 16303 static inline uint32_t ATTRIBUTE_PURE 16304 _3DSTATE_CONSTANT_GS_DWordLength_start(const struct gen_device_info *devinfo) 16305 { 16306 switch (devinfo->gen) { 16307 case 10: return 0; 16308 case 9: return 0; 16309 case 8: return 0; 16310 case 7: 16311 if (devinfo->is_haswell) { 16312 return 0; 16313 } else { 16314 return 0; 16315 } 16316 case 6: return 0; 16317 case 5: return 0; 16318 case 4: 16319 if (devinfo->is_g4x) { 16320 return 0; 16321 } else { 16322 return 0; 16323 } 16324 default: 16325 unreachable("Invalid hardware generation"); 16326 } 16327 } 16328 16329 16330 16331 /* 3DSTATE_CONSTANT_GS::GS Constant Buffer 0 Read Length */ 16332 16333 16334 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer0ReadLength_bits 5 16335 16336 static inline uint32_t ATTRIBUTE_PURE 16337 _3DSTATE_CONSTANT_GS_GSConstantBuffer0ReadLength_bits(const struct gen_device_info *devinfo) 16338 { 16339 switch (devinfo->gen) { 16340 case 10: return 0; 16341 case 9: return 0; 16342 case 8: return 0; 16343 case 7: 16344 if (devinfo->is_haswell) { 16345 return 0; 16346 } else { 16347 return 0; 16348 } 16349 case 6: return 5; 16350 case 5: return 0; 16351 case 4: 16352 if (devinfo->is_g4x) { 16353 return 0; 16354 } else { 16355 return 0; 16356 } 16357 default: 16358 unreachable("Invalid hardware generation"); 16359 } 16360 } 16361 16362 16363 16364 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer0ReadLength_start 32 16365 16366 static inline uint32_t ATTRIBUTE_PURE 16367 _3DSTATE_CONSTANT_GS_GSConstantBuffer0ReadLength_start(const struct gen_device_info *devinfo) 16368 { 16369 switch (devinfo->gen) { 16370 case 10: return 0; 16371 case 9: return 0; 16372 case 8: return 0; 16373 case 7: 16374 if (devinfo->is_haswell) { 16375 return 0; 16376 } else { 16377 return 0; 16378 } 16379 case 6: return 32; 16380 case 5: return 0; 16381 case 4: 16382 if (devinfo->is_g4x) { 16383 return 0; 16384 } else { 16385 return 0; 16386 } 16387 default: 16388 unreachable("Invalid hardware generation"); 16389 } 16390 } 16391 16392 16393 16394 /* 3DSTATE_CONSTANT_GS::GS Constant Buffer 1 Read Length */ 16395 16396 16397 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer1ReadLength_bits 5 16398 16399 static inline uint32_t ATTRIBUTE_PURE 16400 _3DSTATE_CONSTANT_GS_GSConstantBuffer1ReadLength_bits(const struct gen_device_info *devinfo) 16401 { 16402 switch (devinfo->gen) { 16403 case 10: return 0; 16404 case 9: return 0; 16405 case 8: return 0; 16406 case 7: 16407 if (devinfo->is_haswell) { 16408 return 0; 16409 } else { 16410 return 0; 16411 } 16412 case 6: return 5; 16413 case 5: return 0; 16414 case 4: 16415 if (devinfo->is_g4x) { 16416 return 0; 16417 } else { 16418 return 0; 16419 } 16420 default: 16421 unreachable("Invalid hardware generation"); 16422 } 16423 } 16424 16425 16426 16427 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer1ReadLength_start 64 16428 16429 static inline uint32_t ATTRIBUTE_PURE 16430 _3DSTATE_CONSTANT_GS_GSConstantBuffer1ReadLength_start(const struct gen_device_info *devinfo) 16431 { 16432 switch (devinfo->gen) { 16433 case 10: return 0; 16434 case 9: return 0; 16435 case 8: return 0; 16436 case 7: 16437 if (devinfo->is_haswell) { 16438 return 0; 16439 } else { 16440 return 0; 16441 } 16442 case 6: return 64; 16443 case 5: return 0; 16444 case 4: 16445 if (devinfo->is_g4x) { 16446 return 0; 16447 } else { 16448 return 0; 16449 } 16450 default: 16451 unreachable("Invalid hardware generation"); 16452 } 16453 } 16454 16455 16456 16457 /* 3DSTATE_CONSTANT_GS::GS Constant Buffer 2 Read Length */ 16458 16459 16460 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer2ReadLength_bits 5 16461 16462 static inline uint32_t ATTRIBUTE_PURE 16463 _3DSTATE_CONSTANT_GS_GSConstantBuffer2ReadLength_bits(const struct gen_device_info *devinfo) 16464 { 16465 switch (devinfo->gen) { 16466 case 10: return 0; 16467 case 9: return 0; 16468 case 8: return 0; 16469 case 7: 16470 if (devinfo->is_haswell) { 16471 return 0; 16472 } else { 16473 return 0; 16474 } 16475 case 6: return 5; 16476 case 5: return 0; 16477 case 4: 16478 if (devinfo->is_g4x) { 16479 return 0; 16480 } else { 16481 return 0; 16482 } 16483 default: 16484 unreachable("Invalid hardware generation"); 16485 } 16486 } 16487 16488 16489 16490 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer2ReadLength_start 96 16491 16492 static inline uint32_t ATTRIBUTE_PURE 16493 _3DSTATE_CONSTANT_GS_GSConstantBuffer2ReadLength_start(const struct gen_device_info *devinfo) 16494 { 16495 switch (devinfo->gen) { 16496 case 10: return 0; 16497 case 9: return 0; 16498 case 8: return 0; 16499 case 7: 16500 if (devinfo->is_haswell) { 16501 return 0; 16502 } else { 16503 return 0; 16504 } 16505 case 6: return 96; 16506 case 5: return 0; 16507 case 4: 16508 if (devinfo->is_g4x) { 16509 return 0; 16510 } else { 16511 return 0; 16512 } 16513 default: 16514 unreachable("Invalid hardware generation"); 16515 } 16516 } 16517 16518 16519 16520 /* 3DSTATE_CONSTANT_GS::GS Constant Buffer 3 Read Length */ 16521 16522 16523 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer3ReadLength_bits 5 16524 16525 static inline uint32_t ATTRIBUTE_PURE 16526 _3DSTATE_CONSTANT_GS_GSConstantBuffer3ReadLength_bits(const struct gen_device_info *devinfo) 16527 { 16528 switch (devinfo->gen) { 16529 case 10: return 0; 16530 case 9: return 0; 16531 case 8: return 0; 16532 case 7: 16533 if (devinfo->is_haswell) { 16534 return 0; 16535 } else { 16536 return 0; 16537 } 16538 case 6: return 5; 16539 case 5: return 0; 16540 case 4: 16541 if (devinfo->is_g4x) { 16542 return 0; 16543 } else { 16544 return 0; 16545 } 16546 default: 16547 unreachable("Invalid hardware generation"); 16548 } 16549 } 16550 16551 16552 16553 #define GEN6_3DSTATE_CONSTANT_GS_GSConstantBuffer3ReadLength_start 128 16554 16555 static inline uint32_t ATTRIBUTE_PURE 16556 _3DSTATE_CONSTANT_GS_GSConstantBuffer3ReadLength_start(const struct gen_device_info *devinfo) 16557 { 16558 switch (devinfo->gen) { 16559 case 10: return 0; 16560 case 9: return 0; 16561 case 8: return 0; 16562 case 7: 16563 if (devinfo->is_haswell) { 16564 return 0; 16565 } else { 16566 return 0; 16567 } 16568 case 6: return 128; 16569 case 5: return 0; 16570 case 4: 16571 if (devinfo->is_g4x) { 16572 return 0; 16573 } else { 16574 return 0; 16575 } 16576 default: 16577 unreachable("Invalid hardware generation"); 16578 } 16579 } 16580 16581 16582 16583 /* 3DSTATE_CONSTANT_GS::Pointer to GS Constant Buffer 0 */ 16584 16585 16586 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer0_bits 27 16587 16588 static inline uint32_t ATTRIBUTE_PURE 16589 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer0_bits(const struct gen_device_info *devinfo) 16590 { 16591 switch (devinfo->gen) { 16592 case 10: return 0; 16593 case 9: return 0; 16594 case 8: return 0; 16595 case 7: 16596 if (devinfo->is_haswell) { 16597 return 0; 16598 } else { 16599 return 0; 16600 } 16601 case 6: return 27; 16602 case 5: return 0; 16603 case 4: 16604 if (devinfo->is_g4x) { 16605 return 0; 16606 } else { 16607 return 0; 16608 } 16609 default: 16610 unreachable("Invalid hardware generation"); 16611 } 16612 } 16613 16614 16615 16616 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer0_start 37 16617 16618 static inline uint32_t ATTRIBUTE_PURE 16619 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer0_start(const struct gen_device_info *devinfo) 16620 { 16621 switch (devinfo->gen) { 16622 case 10: return 0; 16623 case 9: return 0; 16624 case 8: return 0; 16625 case 7: 16626 if (devinfo->is_haswell) { 16627 return 0; 16628 } else { 16629 return 0; 16630 } 16631 case 6: return 37; 16632 case 5: return 0; 16633 case 4: 16634 if (devinfo->is_g4x) { 16635 return 0; 16636 } else { 16637 return 0; 16638 } 16639 default: 16640 unreachable("Invalid hardware generation"); 16641 } 16642 } 16643 16644 16645 16646 /* 3DSTATE_CONSTANT_GS::Pointer to GS Constant Buffer 1 */ 16647 16648 16649 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer1_bits 27 16650 16651 static inline uint32_t ATTRIBUTE_PURE 16652 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer1_bits(const struct gen_device_info *devinfo) 16653 { 16654 switch (devinfo->gen) { 16655 case 10: return 0; 16656 case 9: return 0; 16657 case 8: return 0; 16658 case 7: 16659 if (devinfo->is_haswell) { 16660 return 0; 16661 } else { 16662 return 0; 16663 } 16664 case 6: return 27; 16665 case 5: return 0; 16666 case 4: 16667 if (devinfo->is_g4x) { 16668 return 0; 16669 } else { 16670 return 0; 16671 } 16672 default: 16673 unreachable("Invalid hardware generation"); 16674 } 16675 } 16676 16677 16678 16679 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer1_start 69 16680 16681 static inline uint32_t ATTRIBUTE_PURE 16682 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer1_start(const struct gen_device_info *devinfo) 16683 { 16684 switch (devinfo->gen) { 16685 case 10: return 0; 16686 case 9: return 0; 16687 case 8: return 0; 16688 case 7: 16689 if (devinfo->is_haswell) { 16690 return 0; 16691 } else { 16692 return 0; 16693 } 16694 case 6: return 69; 16695 case 5: return 0; 16696 case 4: 16697 if (devinfo->is_g4x) { 16698 return 0; 16699 } else { 16700 return 0; 16701 } 16702 default: 16703 unreachable("Invalid hardware generation"); 16704 } 16705 } 16706 16707 16708 16709 /* 3DSTATE_CONSTANT_GS::Pointer to GS Constant Buffer 2 */ 16710 16711 16712 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer2_bits 27 16713 16714 static inline uint32_t ATTRIBUTE_PURE 16715 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer2_bits(const struct gen_device_info *devinfo) 16716 { 16717 switch (devinfo->gen) { 16718 case 10: return 0; 16719 case 9: return 0; 16720 case 8: return 0; 16721 case 7: 16722 if (devinfo->is_haswell) { 16723 return 0; 16724 } else { 16725 return 0; 16726 } 16727 case 6: return 27; 16728 case 5: return 0; 16729 case 4: 16730 if (devinfo->is_g4x) { 16731 return 0; 16732 } else { 16733 return 0; 16734 } 16735 default: 16736 unreachable("Invalid hardware generation"); 16737 } 16738 } 16739 16740 16741 16742 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer2_start 101 16743 16744 static inline uint32_t ATTRIBUTE_PURE 16745 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer2_start(const struct gen_device_info *devinfo) 16746 { 16747 switch (devinfo->gen) { 16748 case 10: return 0; 16749 case 9: return 0; 16750 case 8: return 0; 16751 case 7: 16752 if (devinfo->is_haswell) { 16753 return 0; 16754 } else { 16755 return 0; 16756 } 16757 case 6: return 101; 16758 case 5: return 0; 16759 case 4: 16760 if (devinfo->is_g4x) { 16761 return 0; 16762 } else { 16763 return 0; 16764 } 16765 default: 16766 unreachable("Invalid hardware generation"); 16767 } 16768 } 16769 16770 16771 16772 /* 3DSTATE_CONSTANT_GS::Pointer to GS Constant Buffer 3 */ 16773 16774 16775 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer3_bits 27 16776 16777 static inline uint32_t ATTRIBUTE_PURE 16778 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer3_bits(const struct gen_device_info *devinfo) 16779 { 16780 switch (devinfo->gen) { 16781 case 10: return 0; 16782 case 9: return 0; 16783 case 8: return 0; 16784 case 7: 16785 if (devinfo->is_haswell) { 16786 return 0; 16787 } else { 16788 return 0; 16789 } 16790 case 6: return 27; 16791 case 5: return 0; 16792 case 4: 16793 if (devinfo->is_g4x) { 16794 return 0; 16795 } else { 16796 return 0; 16797 } 16798 default: 16799 unreachable("Invalid hardware generation"); 16800 } 16801 } 16802 16803 16804 16805 #define GEN6_3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer3_start 133 16806 16807 static inline uint32_t ATTRIBUTE_PURE 16808 _3DSTATE_CONSTANT_GS_PointertoGSConstantBuffer3_start(const struct gen_device_info *devinfo) 16809 { 16810 switch (devinfo->gen) { 16811 case 10: return 0; 16812 case 9: return 0; 16813 case 8: return 0; 16814 case 7: 16815 if (devinfo->is_haswell) { 16816 return 0; 16817 } else { 16818 return 0; 16819 } 16820 case 6: return 133; 16821 case 5: return 0; 16822 case 4: 16823 if (devinfo->is_g4x) { 16824 return 0; 16825 } else { 16826 return 0; 16827 } 16828 default: 16829 unreachable("Invalid hardware generation"); 16830 } 16831 } 16832 16833 16834 16835 /* 3DSTATE_CONSTANT_HS */ 16836 16837 16838 #define GEN10_3DSTATE_CONSTANT_HS_length 11 16839 #define GEN9_3DSTATE_CONSTANT_HS_length 11 16840 #define GEN8_3DSTATE_CONSTANT_HS_length 11 16841 #define GEN75_3DSTATE_CONSTANT_HS_length 7 16842 #define GEN7_3DSTATE_CONSTANT_HS_length 7 16843 16844 static inline uint32_t ATTRIBUTE_PURE 16845 _3DSTATE_CONSTANT_HS_length(const struct gen_device_info *devinfo) 16846 { 16847 switch (devinfo->gen) { 16848 case 10: return 11; 16849 case 9: return 11; 16850 case 8: return 11; 16851 case 7: 16852 if (devinfo->is_haswell) { 16853 return 7; 16854 } else { 16855 return 7; 16856 } 16857 case 6: return 0; 16858 case 5: return 0; 16859 case 4: 16860 if (devinfo->is_g4x) { 16861 return 0; 16862 } else { 16863 return 0; 16864 } 16865 default: 16866 unreachable("Invalid hardware generation"); 16867 } 16868 } 16869 16870 16871 16872 /* 3DSTATE_CONSTANT_HS::3D Command Opcode */ 16873 16874 16875 #define GEN10_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 16876 #define GEN9_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 16877 #define GEN8_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 16878 #define GEN75_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 16879 #define GEN7_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 16880 16881 static inline uint32_t ATTRIBUTE_PURE 16882 _3DSTATE_CONSTANT_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 16883 { 16884 switch (devinfo->gen) { 16885 case 10: return 3; 16886 case 9: return 3; 16887 case 8: return 3; 16888 case 7: 16889 if (devinfo->is_haswell) { 16890 return 3; 16891 } else { 16892 return 3; 16893 } 16894 case 6: return 0; 16895 case 5: return 0; 16896 case 4: 16897 if (devinfo->is_g4x) { 16898 return 0; 16899 } else { 16900 return 0; 16901 } 16902 default: 16903 unreachable("Invalid hardware generation"); 16904 } 16905 } 16906 16907 16908 16909 #define GEN10_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 16910 #define GEN9_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 16911 #define GEN8_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 16912 #define GEN75_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 16913 #define GEN7_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 16914 16915 static inline uint32_t ATTRIBUTE_PURE 16916 _3DSTATE_CONSTANT_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 16917 { 16918 switch (devinfo->gen) { 16919 case 10: return 24; 16920 case 9: return 24; 16921 case 8: return 24; 16922 case 7: 16923 if (devinfo->is_haswell) { 16924 return 24; 16925 } else { 16926 return 24; 16927 } 16928 case 6: return 0; 16929 case 5: return 0; 16930 case 4: 16931 if (devinfo->is_g4x) { 16932 return 0; 16933 } else { 16934 return 0; 16935 } 16936 default: 16937 unreachable("Invalid hardware generation"); 16938 } 16939 } 16940 16941 16942 16943 /* 3DSTATE_CONSTANT_HS::3D Command Sub Opcode */ 16944 16945 16946 #define GEN10_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 16947 #define GEN9_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 16948 #define GEN8_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 16949 #define GEN75_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 16950 #define GEN7_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 16951 16952 static inline uint32_t ATTRIBUTE_PURE 16953 _3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 16954 { 16955 switch (devinfo->gen) { 16956 case 10: return 8; 16957 case 9: return 8; 16958 case 8: return 8; 16959 case 7: 16960 if (devinfo->is_haswell) { 16961 return 8; 16962 } else { 16963 return 8; 16964 } 16965 case 6: return 0; 16966 case 5: return 0; 16967 case 4: 16968 if (devinfo->is_g4x) { 16969 return 0; 16970 } else { 16971 return 0; 16972 } 16973 default: 16974 unreachable("Invalid hardware generation"); 16975 } 16976 } 16977 16978 16979 16980 #define GEN10_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 16981 #define GEN9_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 16982 #define GEN8_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 16983 #define GEN75_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 16984 #define GEN7_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 16985 16986 static inline uint32_t ATTRIBUTE_PURE 16987 _3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 16988 { 16989 switch (devinfo->gen) { 16990 case 10: return 16; 16991 case 9: return 16; 16992 case 8: return 16; 16993 case 7: 16994 if (devinfo->is_haswell) { 16995 return 16; 16996 } else { 16997 return 16; 16998 } 16999 case 6: return 0; 17000 case 5: return 0; 17001 case 4: 17002 if (devinfo->is_g4x) { 17003 return 0; 17004 } else { 17005 return 0; 17006 } 17007 default: 17008 unreachable("Invalid hardware generation"); 17009 } 17010 } 17011 17012 17013 17014 /* 3DSTATE_CONSTANT_HS::Command SubType */ 17015 17016 17017 #define GEN10_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 17018 #define GEN9_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 17019 #define GEN8_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 17020 #define GEN75_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 17021 #define GEN7_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 17022 17023 static inline uint32_t ATTRIBUTE_PURE 17024 _3DSTATE_CONSTANT_HS_CommandSubType_bits(const struct gen_device_info *devinfo) 17025 { 17026 switch (devinfo->gen) { 17027 case 10: return 2; 17028 case 9: return 2; 17029 case 8: return 2; 17030 case 7: 17031 if (devinfo->is_haswell) { 17032 return 2; 17033 } else { 17034 return 2; 17035 } 17036 case 6: return 0; 17037 case 5: return 0; 17038 case 4: 17039 if (devinfo->is_g4x) { 17040 return 0; 17041 } else { 17042 return 0; 17043 } 17044 default: 17045 unreachable("Invalid hardware generation"); 17046 } 17047 } 17048 17049 17050 17051 #define GEN10_3DSTATE_CONSTANT_HS_CommandSubType_start 27 17052 #define GEN9_3DSTATE_CONSTANT_HS_CommandSubType_start 27 17053 #define GEN8_3DSTATE_CONSTANT_HS_CommandSubType_start 27 17054 #define GEN75_3DSTATE_CONSTANT_HS_CommandSubType_start 27 17055 #define GEN7_3DSTATE_CONSTANT_HS_CommandSubType_start 27 17056 17057 static inline uint32_t ATTRIBUTE_PURE 17058 _3DSTATE_CONSTANT_HS_CommandSubType_start(const struct gen_device_info *devinfo) 17059 { 17060 switch (devinfo->gen) { 17061 case 10: return 27; 17062 case 9: return 27; 17063 case 8: return 27; 17064 case 7: 17065 if (devinfo->is_haswell) { 17066 return 27; 17067 } else { 17068 return 27; 17069 } 17070 case 6: return 0; 17071 case 5: return 0; 17072 case 4: 17073 if (devinfo->is_g4x) { 17074 return 0; 17075 } else { 17076 return 0; 17077 } 17078 default: 17079 unreachable("Invalid hardware generation"); 17080 } 17081 } 17082 17083 17084 17085 /* 3DSTATE_CONSTANT_HS::Command Type */ 17086 17087 17088 #define GEN10_3DSTATE_CONSTANT_HS_CommandType_bits 3 17089 #define GEN9_3DSTATE_CONSTANT_HS_CommandType_bits 3 17090 #define GEN8_3DSTATE_CONSTANT_HS_CommandType_bits 3 17091 #define GEN75_3DSTATE_CONSTANT_HS_CommandType_bits 3 17092 #define GEN7_3DSTATE_CONSTANT_HS_CommandType_bits 3 17093 17094 static inline uint32_t ATTRIBUTE_PURE 17095 _3DSTATE_CONSTANT_HS_CommandType_bits(const struct gen_device_info *devinfo) 17096 { 17097 switch (devinfo->gen) { 17098 case 10: return 3; 17099 case 9: return 3; 17100 case 8: return 3; 17101 case 7: 17102 if (devinfo->is_haswell) { 17103 return 3; 17104 } else { 17105 return 3; 17106 } 17107 case 6: return 0; 17108 case 5: return 0; 17109 case 4: 17110 if (devinfo->is_g4x) { 17111 return 0; 17112 } else { 17113 return 0; 17114 } 17115 default: 17116 unreachable("Invalid hardware generation"); 17117 } 17118 } 17119 17120 17121 17122 #define GEN10_3DSTATE_CONSTANT_HS_CommandType_start 29 17123 #define GEN9_3DSTATE_CONSTANT_HS_CommandType_start 29 17124 #define GEN8_3DSTATE_CONSTANT_HS_CommandType_start 29 17125 #define GEN75_3DSTATE_CONSTANT_HS_CommandType_start 29 17126 #define GEN7_3DSTATE_CONSTANT_HS_CommandType_start 29 17127 17128 static inline uint32_t ATTRIBUTE_PURE 17129 _3DSTATE_CONSTANT_HS_CommandType_start(const struct gen_device_info *devinfo) 17130 { 17131 switch (devinfo->gen) { 17132 case 10: return 29; 17133 case 9: return 29; 17134 case 8: return 29; 17135 case 7: 17136 if (devinfo->is_haswell) { 17137 return 29; 17138 } else { 17139 return 29; 17140 } 17141 case 6: return 0; 17142 case 5: return 0; 17143 case 4: 17144 if (devinfo->is_g4x) { 17145 return 0; 17146 } else { 17147 return 0; 17148 } 17149 default: 17150 unreachable("Invalid hardware generation"); 17151 } 17152 } 17153 17154 17155 17156 /* 3DSTATE_CONSTANT_HS::Constant Body */ 17157 17158 17159 #define GEN10_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 17160 #define GEN9_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 17161 #define GEN8_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 17162 #define GEN75_3DSTATE_CONSTANT_HS_ConstantBody_bits 192 17163 #define GEN7_3DSTATE_CONSTANT_HS_ConstantBody_bits 192 17164 17165 static inline uint32_t ATTRIBUTE_PURE 17166 _3DSTATE_CONSTANT_HS_ConstantBody_bits(const struct gen_device_info *devinfo) 17167 { 17168 switch (devinfo->gen) { 17169 case 10: return 320; 17170 case 9: return 320; 17171 case 8: return 320; 17172 case 7: 17173 if (devinfo->is_haswell) { 17174 return 192; 17175 } else { 17176 return 192; 17177 } 17178 case 6: return 0; 17179 case 5: return 0; 17180 case 4: 17181 if (devinfo->is_g4x) { 17182 return 0; 17183 } else { 17184 return 0; 17185 } 17186 default: 17187 unreachable("Invalid hardware generation"); 17188 } 17189 } 17190 17191 17192 17193 #define GEN10_3DSTATE_CONSTANT_HS_ConstantBody_start 32 17194 #define GEN9_3DSTATE_CONSTANT_HS_ConstantBody_start 32 17195 #define GEN8_3DSTATE_CONSTANT_HS_ConstantBody_start 32 17196 #define GEN75_3DSTATE_CONSTANT_HS_ConstantBody_start 32 17197 #define GEN7_3DSTATE_CONSTANT_HS_ConstantBody_start 32 17198 17199 static inline uint32_t ATTRIBUTE_PURE 17200 _3DSTATE_CONSTANT_HS_ConstantBody_start(const struct gen_device_info *devinfo) 17201 { 17202 switch (devinfo->gen) { 17203 case 10: return 32; 17204 case 9: return 32; 17205 case 8: return 32; 17206 case 7: 17207 if (devinfo->is_haswell) { 17208 return 32; 17209 } else { 17210 return 32; 17211 } 17212 case 6: return 0; 17213 case 5: return 0; 17214 case 4: 17215 if (devinfo->is_g4x) { 17216 return 0; 17217 } else { 17218 return 0; 17219 } 17220 default: 17221 unreachable("Invalid hardware generation"); 17222 } 17223 } 17224 17225 17226 17227 /* 3DSTATE_CONSTANT_HS::Constant Buffer Object Control State */ 17228 17229 17230 #define GEN10_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits 7 17231 #define GEN9_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits 7 17232 #define GEN8_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits 7 17233 17234 static inline uint32_t ATTRIBUTE_PURE 17235 _3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) 17236 { 17237 switch (devinfo->gen) { 17238 case 10: return 7; 17239 case 9: return 7; 17240 case 8: return 7; 17241 case 7: 17242 if (devinfo->is_haswell) { 17243 return 0; 17244 } else { 17245 return 0; 17246 } 17247 case 6: return 0; 17248 case 5: return 0; 17249 case 4: 17250 if (devinfo->is_g4x) { 17251 return 0; 17252 } else { 17253 return 0; 17254 } 17255 default: 17256 unreachable("Invalid hardware generation"); 17257 } 17258 } 17259 17260 17261 17262 #define GEN10_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start 8 17263 #define GEN9_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start 8 17264 #define GEN8_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start 8 17265 17266 static inline uint32_t ATTRIBUTE_PURE 17267 _3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) 17268 { 17269 switch (devinfo->gen) { 17270 case 10: return 8; 17271 case 9: return 8; 17272 case 8: return 8; 17273 case 7: 17274 if (devinfo->is_haswell) { 17275 return 0; 17276 } else { 17277 return 0; 17278 } 17279 case 6: return 0; 17280 case 5: return 0; 17281 case 4: 17282 if (devinfo->is_g4x) { 17283 return 0; 17284 } else { 17285 return 0; 17286 } 17287 default: 17288 unreachable("Invalid hardware generation"); 17289 } 17290 } 17291 17292 17293 17294 /* 3DSTATE_CONSTANT_HS::DWord Length */ 17295 17296 17297 #define GEN10_3DSTATE_CONSTANT_HS_DWordLength_bits 8 17298 #define GEN9_3DSTATE_CONSTANT_HS_DWordLength_bits 8 17299 #define GEN8_3DSTATE_CONSTANT_HS_DWordLength_bits 8 17300 #define GEN75_3DSTATE_CONSTANT_HS_DWordLength_bits 8 17301 #define GEN7_3DSTATE_CONSTANT_HS_DWordLength_bits 8 17302 17303 static inline uint32_t ATTRIBUTE_PURE 17304 _3DSTATE_CONSTANT_HS_DWordLength_bits(const struct gen_device_info *devinfo) 17305 { 17306 switch (devinfo->gen) { 17307 case 10: return 8; 17308 case 9: return 8; 17309 case 8: return 8; 17310 case 7: 17311 if (devinfo->is_haswell) { 17312 return 8; 17313 } else { 17314 return 8; 17315 } 17316 case 6: return 0; 17317 case 5: return 0; 17318 case 4: 17319 if (devinfo->is_g4x) { 17320 return 0; 17321 } else { 17322 return 0; 17323 } 17324 default: 17325 unreachable("Invalid hardware generation"); 17326 } 17327 } 17328 17329 17330 17331 #define GEN10_3DSTATE_CONSTANT_HS_DWordLength_start 0 17332 #define GEN9_3DSTATE_CONSTANT_HS_DWordLength_start 0 17333 #define GEN8_3DSTATE_CONSTANT_HS_DWordLength_start 0 17334 #define GEN75_3DSTATE_CONSTANT_HS_DWordLength_start 0 17335 #define GEN7_3DSTATE_CONSTANT_HS_DWordLength_start 0 17336 17337 static inline uint32_t ATTRIBUTE_PURE 17338 _3DSTATE_CONSTANT_HS_DWordLength_start(const struct gen_device_info *devinfo) 17339 { 17340 switch (devinfo->gen) { 17341 case 10: return 0; 17342 case 9: return 0; 17343 case 8: return 0; 17344 case 7: 17345 if (devinfo->is_haswell) { 17346 return 0; 17347 } else { 17348 return 0; 17349 } 17350 case 6: return 0; 17351 case 5: return 0; 17352 case 4: 17353 if (devinfo->is_g4x) { 17354 return 0; 17355 } else { 17356 return 0; 17357 } 17358 default: 17359 unreachable("Invalid hardware generation"); 17360 } 17361 } 17362 17363 17364 17365 /* 3DSTATE_CONSTANT_PS */ 17366 17367 17368 #define GEN10_3DSTATE_CONSTANT_PS_length 11 17369 #define GEN9_3DSTATE_CONSTANT_PS_length 11 17370 #define GEN8_3DSTATE_CONSTANT_PS_length 11 17371 #define GEN75_3DSTATE_CONSTANT_PS_length 7 17372 #define GEN7_3DSTATE_CONSTANT_PS_length 7 17373 #define GEN6_3DSTATE_CONSTANT_PS_length 5 17374 17375 static inline uint32_t ATTRIBUTE_PURE 17376 _3DSTATE_CONSTANT_PS_length(const struct gen_device_info *devinfo) 17377 { 17378 switch (devinfo->gen) { 17379 case 10: return 11; 17380 case 9: return 11; 17381 case 8: return 11; 17382 case 7: 17383 if (devinfo->is_haswell) { 17384 return 7; 17385 } else { 17386 return 7; 17387 } 17388 case 6: return 5; 17389 case 5: return 0; 17390 case 4: 17391 if (devinfo->is_g4x) { 17392 return 0; 17393 } else { 17394 return 0; 17395 } 17396 default: 17397 unreachable("Invalid hardware generation"); 17398 } 17399 } 17400 17401 17402 17403 /* 3DSTATE_CONSTANT_PS::3D Command Opcode */ 17404 17405 17406 #define GEN10_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 17407 #define GEN9_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 17408 #define GEN8_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 17409 #define GEN75_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 17410 #define GEN7_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 17411 #define GEN6_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 17412 17413 static inline uint32_t ATTRIBUTE_PURE 17414 _3DSTATE_CONSTANT_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 17415 { 17416 switch (devinfo->gen) { 17417 case 10: return 3; 17418 case 9: return 3; 17419 case 8: return 3; 17420 case 7: 17421 if (devinfo->is_haswell) { 17422 return 3; 17423 } else { 17424 return 3; 17425 } 17426 case 6: return 3; 17427 case 5: return 0; 17428 case 4: 17429 if (devinfo->is_g4x) { 17430 return 0; 17431 } else { 17432 return 0; 17433 } 17434 default: 17435 unreachable("Invalid hardware generation"); 17436 } 17437 } 17438 17439 17440 17441 #define GEN10_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 17442 #define GEN9_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 17443 #define GEN8_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 17444 #define GEN75_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 17445 #define GEN7_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 17446 #define GEN6_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 17447 17448 static inline uint32_t ATTRIBUTE_PURE 17449 _3DSTATE_CONSTANT_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 17450 { 17451 switch (devinfo->gen) { 17452 case 10: return 24; 17453 case 9: return 24; 17454 case 8: return 24; 17455 case 7: 17456 if (devinfo->is_haswell) { 17457 return 24; 17458 } else { 17459 return 24; 17460 } 17461 case 6: return 24; 17462 case 5: return 0; 17463 case 4: 17464 if (devinfo->is_g4x) { 17465 return 0; 17466 } else { 17467 return 0; 17468 } 17469 default: 17470 unreachable("Invalid hardware generation"); 17471 } 17472 } 17473 17474 17475 17476 /* 3DSTATE_CONSTANT_PS::3D Command Sub Opcode */ 17477 17478 17479 #define GEN10_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 17480 #define GEN9_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 17481 #define GEN8_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 17482 #define GEN75_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 17483 #define GEN7_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 17484 #define GEN6_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 17485 17486 static inline uint32_t ATTRIBUTE_PURE 17487 _3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 17488 { 17489 switch (devinfo->gen) { 17490 case 10: return 8; 17491 case 9: return 8; 17492 case 8: return 8; 17493 case 7: 17494 if (devinfo->is_haswell) { 17495 return 8; 17496 } else { 17497 return 8; 17498 } 17499 case 6: return 8; 17500 case 5: return 0; 17501 case 4: 17502 if (devinfo->is_g4x) { 17503 return 0; 17504 } else { 17505 return 0; 17506 } 17507 default: 17508 unreachable("Invalid hardware generation"); 17509 } 17510 } 17511 17512 17513 17514 #define GEN10_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 17515 #define GEN9_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 17516 #define GEN8_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 17517 #define GEN75_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 17518 #define GEN7_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 17519 #define GEN6_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 17520 17521 static inline uint32_t ATTRIBUTE_PURE 17522 _3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 17523 { 17524 switch (devinfo->gen) { 17525 case 10: return 16; 17526 case 9: return 16; 17527 case 8: return 16; 17528 case 7: 17529 if (devinfo->is_haswell) { 17530 return 16; 17531 } else { 17532 return 16; 17533 } 17534 case 6: return 16; 17535 case 5: return 0; 17536 case 4: 17537 if (devinfo->is_g4x) { 17538 return 0; 17539 } else { 17540 return 0; 17541 } 17542 default: 17543 unreachable("Invalid hardware generation"); 17544 } 17545 } 17546 17547 17548 17549 /* 3DSTATE_CONSTANT_PS::Buffer 0 Valid */ 17550 17551 17552 #define GEN6_3DSTATE_CONSTANT_PS_Buffer0Valid_bits 1 17553 17554 static inline uint32_t ATTRIBUTE_PURE 17555 _3DSTATE_CONSTANT_PS_Buffer0Valid_bits(const struct gen_device_info *devinfo) 17556 { 17557 switch (devinfo->gen) { 17558 case 10: return 0; 17559 case 9: return 0; 17560 case 8: return 0; 17561 case 7: 17562 if (devinfo->is_haswell) { 17563 return 0; 17564 } else { 17565 return 0; 17566 } 17567 case 6: return 1; 17568 case 5: return 0; 17569 case 4: 17570 if (devinfo->is_g4x) { 17571 return 0; 17572 } else { 17573 return 0; 17574 } 17575 default: 17576 unreachable("Invalid hardware generation"); 17577 } 17578 } 17579 17580 17581 17582 #define GEN6_3DSTATE_CONSTANT_PS_Buffer0Valid_start 12 17583 17584 static inline uint32_t ATTRIBUTE_PURE 17585 _3DSTATE_CONSTANT_PS_Buffer0Valid_start(const struct gen_device_info *devinfo) 17586 { 17587 switch (devinfo->gen) { 17588 case 10: return 0; 17589 case 9: return 0; 17590 case 8: return 0; 17591 case 7: 17592 if (devinfo->is_haswell) { 17593 return 0; 17594 } else { 17595 return 0; 17596 } 17597 case 6: return 12; 17598 case 5: return 0; 17599 case 4: 17600 if (devinfo->is_g4x) { 17601 return 0; 17602 } else { 17603 return 0; 17604 } 17605 default: 17606 unreachable("Invalid hardware generation"); 17607 } 17608 } 17609 17610 17611 17612 /* 3DSTATE_CONSTANT_PS::Buffer 1 Valid */ 17613 17614 17615 #define GEN6_3DSTATE_CONSTANT_PS_Buffer1Valid_bits 1 17616 17617 static inline uint32_t ATTRIBUTE_PURE 17618 _3DSTATE_CONSTANT_PS_Buffer1Valid_bits(const struct gen_device_info *devinfo) 17619 { 17620 switch (devinfo->gen) { 17621 case 10: return 0; 17622 case 9: return 0; 17623 case 8: return 0; 17624 case 7: 17625 if (devinfo->is_haswell) { 17626 return 0; 17627 } else { 17628 return 0; 17629 } 17630 case 6: return 1; 17631 case 5: return 0; 17632 case 4: 17633 if (devinfo->is_g4x) { 17634 return 0; 17635 } else { 17636 return 0; 17637 } 17638 default: 17639 unreachable("Invalid hardware generation"); 17640 } 17641 } 17642 17643 17644 17645 #define GEN6_3DSTATE_CONSTANT_PS_Buffer1Valid_start 13 17646 17647 static inline uint32_t ATTRIBUTE_PURE 17648 _3DSTATE_CONSTANT_PS_Buffer1Valid_start(const struct gen_device_info *devinfo) 17649 { 17650 switch (devinfo->gen) { 17651 case 10: return 0; 17652 case 9: return 0; 17653 case 8: return 0; 17654 case 7: 17655 if (devinfo->is_haswell) { 17656 return 0; 17657 } else { 17658 return 0; 17659 } 17660 case 6: return 13; 17661 case 5: return 0; 17662 case 4: 17663 if (devinfo->is_g4x) { 17664 return 0; 17665 } else { 17666 return 0; 17667 } 17668 default: 17669 unreachable("Invalid hardware generation"); 17670 } 17671 } 17672 17673 17674 17675 /* 3DSTATE_CONSTANT_PS::Buffer 2 Valid */ 17676 17677 17678 #define GEN6_3DSTATE_CONSTANT_PS_Buffer2Valid_bits 1 17679 17680 static inline uint32_t ATTRIBUTE_PURE 17681 _3DSTATE_CONSTANT_PS_Buffer2Valid_bits(const struct gen_device_info *devinfo) 17682 { 17683 switch (devinfo->gen) { 17684 case 10: return 0; 17685 case 9: return 0; 17686 case 8: return 0; 17687 case 7: 17688 if (devinfo->is_haswell) { 17689 return 0; 17690 } else { 17691 return 0; 17692 } 17693 case 6: return 1; 17694 case 5: return 0; 17695 case 4: 17696 if (devinfo->is_g4x) { 17697 return 0; 17698 } else { 17699 return 0; 17700 } 17701 default: 17702 unreachable("Invalid hardware generation"); 17703 } 17704 } 17705 17706 17707 17708 #define GEN6_3DSTATE_CONSTANT_PS_Buffer2Valid_start 14 17709 17710 static inline uint32_t ATTRIBUTE_PURE 17711 _3DSTATE_CONSTANT_PS_Buffer2Valid_start(const struct gen_device_info *devinfo) 17712 { 17713 switch (devinfo->gen) { 17714 case 10: return 0; 17715 case 9: return 0; 17716 case 8: return 0; 17717 case 7: 17718 if (devinfo->is_haswell) { 17719 return 0; 17720 } else { 17721 return 0; 17722 } 17723 case 6: return 14; 17724 case 5: return 0; 17725 case 4: 17726 if (devinfo->is_g4x) { 17727 return 0; 17728 } else { 17729 return 0; 17730 } 17731 default: 17732 unreachable("Invalid hardware generation"); 17733 } 17734 } 17735 17736 17737 17738 /* 3DSTATE_CONSTANT_PS::Buffer 3 Valid */ 17739 17740 17741 #define GEN6_3DSTATE_CONSTANT_PS_Buffer3Valid_bits 1 17742 17743 static inline uint32_t ATTRIBUTE_PURE 17744 _3DSTATE_CONSTANT_PS_Buffer3Valid_bits(const struct gen_device_info *devinfo) 17745 { 17746 switch (devinfo->gen) { 17747 case 10: return 0; 17748 case 9: return 0; 17749 case 8: return 0; 17750 case 7: 17751 if (devinfo->is_haswell) { 17752 return 0; 17753 } else { 17754 return 0; 17755 } 17756 case 6: return 1; 17757 case 5: return 0; 17758 case 4: 17759 if (devinfo->is_g4x) { 17760 return 0; 17761 } else { 17762 return 0; 17763 } 17764 default: 17765 unreachable("Invalid hardware generation"); 17766 } 17767 } 17768 17769 17770 17771 #define GEN6_3DSTATE_CONSTANT_PS_Buffer3Valid_start 15 17772 17773 static inline uint32_t ATTRIBUTE_PURE 17774 _3DSTATE_CONSTANT_PS_Buffer3Valid_start(const struct gen_device_info *devinfo) 17775 { 17776 switch (devinfo->gen) { 17777 case 10: return 0; 17778 case 9: return 0; 17779 case 8: return 0; 17780 case 7: 17781 if (devinfo->is_haswell) { 17782 return 0; 17783 } else { 17784 return 0; 17785 } 17786 case 6: return 15; 17787 case 5: return 0; 17788 case 4: 17789 if (devinfo->is_g4x) { 17790 return 0; 17791 } else { 17792 return 0; 17793 } 17794 default: 17795 unreachable("Invalid hardware generation"); 17796 } 17797 } 17798 17799 17800 17801 /* 3DSTATE_CONSTANT_PS::Command SubType */ 17802 17803 17804 #define GEN10_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 17805 #define GEN9_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 17806 #define GEN8_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 17807 #define GEN75_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 17808 #define GEN7_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 17809 #define GEN6_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 17810 17811 static inline uint32_t ATTRIBUTE_PURE 17812 _3DSTATE_CONSTANT_PS_CommandSubType_bits(const struct gen_device_info *devinfo) 17813 { 17814 switch (devinfo->gen) { 17815 case 10: return 2; 17816 case 9: return 2; 17817 case 8: return 2; 17818 case 7: 17819 if (devinfo->is_haswell) { 17820 return 2; 17821 } else { 17822 return 2; 17823 } 17824 case 6: return 2; 17825 case 5: return 0; 17826 case 4: 17827 if (devinfo->is_g4x) { 17828 return 0; 17829 } else { 17830 return 0; 17831 } 17832 default: 17833 unreachable("Invalid hardware generation"); 17834 } 17835 } 17836 17837 17838 17839 #define GEN10_3DSTATE_CONSTANT_PS_CommandSubType_start 27 17840 #define GEN9_3DSTATE_CONSTANT_PS_CommandSubType_start 27 17841 #define GEN8_3DSTATE_CONSTANT_PS_CommandSubType_start 27 17842 #define GEN75_3DSTATE_CONSTANT_PS_CommandSubType_start 27 17843 #define GEN7_3DSTATE_CONSTANT_PS_CommandSubType_start 27 17844 #define GEN6_3DSTATE_CONSTANT_PS_CommandSubType_start 27 17845 17846 static inline uint32_t ATTRIBUTE_PURE 17847 _3DSTATE_CONSTANT_PS_CommandSubType_start(const struct gen_device_info *devinfo) 17848 { 17849 switch (devinfo->gen) { 17850 case 10: return 27; 17851 case 9: return 27; 17852 case 8: return 27; 17853 case 7: 17854 if (devinfo->is_haswell) { 17855 return 27; 17856 } else { 17857 return 27; 17858 } 17859 case 6: return 27; 17860 case 5: return 0; 17861 case 4: 17862 if (devinfo->is_g4x) { 17863 return 0; 17864 } else { 17865 return 0; 17866 } 17867 default: 17868 unreachable("Invalid hardware generation"); 17869 } 17870 } 17871 17872 17873 17874 /* 3DSTATE_CONSTANT_PS::Command Type */ 17875 17876 17877 #define GEN10_3DSTATE_CONSTANT_PS_CommandType_bits 3 17878 #define GEN9_3DSTATE_CONSTANT_PS_CommandType_bits 3 17879 #define GEN8_3DSTATE_CONSTANT_PS_CommandType_bits 3 17880 #define GEN75_3DSTATE_CONSTANT_PS_CommandType_bits 3 17881 #define GEN7_3DSTATE_CONSTANT_PS_CommandType_bits 3 17882 #define GEN6_3DSTATE_CONSTANT_PS_CommandType_bits 3 17883 17884 static inline uint32_t ATTRIBUTE_PURE 17885 _3DSTATE_CONSTANT_PS_CommandType_bits(const struct gen_device_info *devinfo) 17886 { 17887 switch (devinfo->gen) { 17888 case 10: return 3; 17889 case 9: return 3; 17890 case 8: return 3; 17891 case 7: 17892 if (devinfo->is_haswell) { 17893 return 3; 17894 } else { 17895 return 3; 17896 } 17897 case 6: return 3; 17898 case 5: return 0; 17899 case 4: 17900 if (devinfo->is_g4x) { 17901 return 0; 17902 } else { 17903 return 0; 17904 } 17905 default: 17906 unreachable("Invalid hardware generation"); 17907 } 17908 } 17909 17910 17911 17912 #define GEN10_3DSTATE_CONSTANT_PS_CommandType_start 29 17913 #define GEN9_3DSTATE_CONSTANT_PS_CommandType_start 29 17914 #define GEN8_3DSTATE_CONSTANT_PS_CommandType_start 29 17915 #define GEN75_3DSTATE_CONSTANT_PS_CommandType_start 29 17916 #define GEN7_3DSTATE_CONSTANT_PS_CommandType_start 29 17917 #define GEN6_3DSTATE_CONSTANT_PS_CommandType_start 29 17918 17919 static inline uint32_t ATTRIBUTE_PURE 17920 _3DSTATE_CONSTANT_PS_CommandType_start(const struct gen_device_info *devinfo) 17921 { 17922 switch (devinfo->gen) { 17923 case 10: return 29; 17924 case 9: return 29; 17925 case 8: return 29; 17926 case 7: 17927 if (devinfo->is_haswell) { 17928 return 29; 17929 } else { 17930 return 29; 17931 } 17932 case 6: return 29; 17933 case 5: return 0; 17934 case 4: 17935 if (devinfo->is_g4x) { 17936 return 0; 17937 } else { 17938 return 0; 17939 } 17940 default: 17941 unreachable("Invalid hardware generation"); 17942 } 17943 } 17944 17945 17946 17947 /* 3DSTATE_CONSTANT_PS::Constant Body */ 17948 17949 17950 #define GEN10_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 17951 #define GEN9_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 17952 #define GEN8_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 17953 #define GEN75_3DSTATE_CONSTANT_PS_ConstantBody_bits 192 17954 #define GEN7_3DSTATE_CONSTANT_PS_ConstantBody_bits 192 17955 17956 static inline uint32_t ATTRIBUTE_PURE 17957 _3DSTATE_CONSTANT_PS_ConstantBody_bits(const struct gen_device_info *devinfo) 17958 { 17959 switch (devinfo->gen) { 17960 case 10: return 320; 17961 case 9: return 320; 17962 case 8: return 320; 17963 case 7: 17964 if (devinfo->is_haswell) { 17965 return 192; 17966 } else { 17967 return 192; 17968 } 17969 case 6: return 0; 17970 case 5: return 0; 17971 case 4: 17972 if (devinfo->is_g4x) { 17973 return 0; 17974 } else { 17975 return 0; 17976 } 17977 default: 17978 unreachable("Invalid hardware generation"); 17979 } 17980 } 17981 17982 17983 17984 #define GEN10_3DSTATE_CONSTANT_PS_ConstantBody_start 32 17985 #define GEN9_3DSTATE_CONSTANT_PS_ConstantBody_start 32 17986 #define GEN8_3DSTATE_CONSTANT_PS_ConstantBody_start 32 17987 #define GEN75_3DSTATE_CONSTANT_PS_ConstantBody_start 32 17988 #define GEN7_3DSTATE_CONSTANT_PS_ConstantBody_start 32 17989 17990 static inline uint32_t ATTRIBUTE_PURE 17991 _3DSTATE_CONSTANT_PS_ConstantBody_start(const struct gen_device_info *devinfo) 17992 { 17993 switch (devinfo->gen) { 17994 case 10: return 32; 17995 case 9: return 32; 17996 case 8: return 32; 17997 case 7: 17998 if (devinfo->is_haswell) { 17999 return 32; 18000 } else { 18001 return 32; 18002 } 18003 case 6: return 0; 18004 case 5: return 0; 18005 case 4: 18006 if (devinfo->is_g4x) { 18007 return 0; 18008 } else { 18009 return 0; 18010 } 18011 default: 18012 unreachable("Invalid hardware generation"); 18013 } 18014 } 18015 18016 18017 18018 /* 3DSTATE_CONSTANT_PS::Constant Buffer Object Control State */ 18019 18020 18021 #define GEN10_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 7 18022 #define GEN9_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 7 18023 #define GEN8_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 7 18024 #define GEN6_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 4 18025 18026 static inline uint32_t ATTRIBUTE_PURE 18027 _3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) 18028 { 18029 switch (devinfo->gen) { 18030 case 10: return 7; 18031 case 9: return 7; 18032 case 8: return 7; 18033 case 7: 18034 if (devinfo->is_haswell) { 18035 return 0; 18036 } else { 18037 return 0; 18038 } 18039 case 6: return 4; 18040 case 5: return 0; 18041 case 4: 18042 if (devinfo->is_g4x) { 18043 return 0; 18044 } else { 18045 return 0; 18046 } 18047 default: 18048 unreachable("Invalid hardware generation"); 18049 } 18050 } 18051 18052 18053 18054 #define GEN10_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 18055 #define GEN9_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 18056 #define GEN8_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 18057 #define GEN6_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 18058 18059 static inline uint32_t ATTRIBUTE_PURE 18060 _3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) 18061 { 18062 switch (devinfo->gen) { 18063 case 10: return 8; 18064 case 9: return 8; 18065 case 8: return 8; 18066 case 7: 18067 if (devinfo->is_haswell) { 18068 return 0; 18069 } else { 18070 return 0; 18071 } 18072 case 6: return 8; 18073 case 5: return 0; 18074 case 4: 18075 if (devinfo->is_g4x) { 18076 return 0; 18077 } else { 18078 return 0; 18079 } 18080 default: 18081 unreachable("Invalid hardware generation"); 18082 } 18083 } 18084 18085 18086 18087 /* 3DSTATE_CONSTANT_PS::DWord Length */ 18088 18089 18090 #define GEN10_3DSTATE_CONSTANT_PS_DWordLength_bits 8 18091 #define GEN9_3DSTATE_CONSTANT_PS_DWordLength_bits 8 18092 #define GEN8_3DSTATE_CONSTANT_PS_DWordLength_bits 8 18093 #define GEN75_3DSTATE_CONSTANT_PS_DWordLength_bits 8 18094 #define GEN7_3DSTATE_CONSTANT_PS_DWordLength_bits 8 18095 #define GEN6_3DSTATE_CONSTANT_PS_DWordLength_bits 8 18096 18097 static inline uint32_t ATTRIBUTE_PURE 18098 _3DSTATE_CONSTANT_PS_DWordLength_bits(const struct gen_device_info *devinfo) 18099 { 18100 switch (devinfo->gen) { 18101 case 10: return 8; 18102 case 9: return 8; 18103 case 8: return 8; 18104 case 7: 18105 if (devinfo->is_haswell) { 18106 return 8; 18107 } else { 18108 return 8; 18109 } 18110 case 6: return 8; 18111 case 5: return 0; 18112 case 4: 18113 if (devinfo->is_g4x) { 18114 return 0; 18115 } else { 18116 return 0; 18117 } 18118 default: 18119 unreachable("Invalid hardware generation"); 18120 } 18121 } 18122 18123 18124 18125 #define GEN10_3DSTATE_CONSTANT_PS_DWordLength_start 0 18126 #define GEN9_3DSTATE_CONSTANT_PS_DWordLength_start 0 18127 #define GEN8_3DSTATE_CONSTANT_PS_DWordLength_start 0 18128 #define GEN75_3DSTATE_CONSTANT_PS_DWordLength_start 0 18129 #define GEN7_3DSTATE_CONSTANT_PS_DWordLength_start 0 18130 #define GEN6_3DSTATE_CONSTANT_PS_DWordLength_start 0 18131 18132 static inline uint32_t ATTRIBUTE_PURE 18133 _3DSTATE_CONSTANT_PS_DWordLength_start(const struct gen_device_info *devinfo) 18134 { 18135 switch (devinfo->gen) { 18136 case 10: return 0; 18137 case 9: return 0; 18138 case 8: return 0; 18139 case 7: 18140 if (devinfo->is_haswell) { 18141 return 0; 18142 } else { 18143 return 0; 18144 } 18145 case 6: return 0; 18146 case 5: return 0; 18147 case 4: 18148 if (devinfo->is_g4x) { 18149 return 0; 18150 } else { 18151 return 0; 18152 } 18153 default: 18154 unreachable("Invalid hardware generation"); 18155 } 18156 } 18157 18158 18159 18160 /* 3DSTATE_CONSTANT_PS::Disable Gather at Set Shader Hint */ 18161 18162 18163 #define GEN10_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits 1 18164 18165 static inline uint32_t ATTRIBUTE_PURE 18166 _3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits(const struct gen_device_info *devinfo) 18167 { 18168 switch (devinfo->gen) { 18169 case 10: return 1; 18170 case 9: return 0; 18171 case 8: return 0; 18172 case 7: 18173 if (devinfo->is_haswell) { 18174 return 0; 18175 } else { 18176 return 0; 18177 } 18178 case 6: return 0; 18179 case 5: return 0; 18180 case 4: 18181 if (devinfo->is_g4x) { 18182 return 0; 18183 } else { 18184 return 0; 18185 } 18186 default: 18187 unreachable("Invalid hardware generation"); 18188 } 18189 } 18190 18191 18192 18193 #define GEN10_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start 15 18194 18195 static inline uint32_t ATTRIBUTE_PURE 18196 _3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start(const struct gen_device_info *devinfo) 18197 { 18198 switch (devinfo->gen) { 18199 case 10: return 15; 18200 case 9: return 0; 18201 case 8: return 0; 18202 case 7: 18203 if (devinfo->is_haswell) { 18204 return 0; 18205 } else { 18206 return 0; 18207 } 18208 case 6: return 0; 18209 case 5: return 0; 18210 case 4: 18211 if (devinfo->is_g4x) { 18212 return 0; 18213 } else { 18214 return 0; 18215 } 18216 default: 18217 unreachable("Invalid hardware generation"); 18218 } 18219 } 18220 18221 18222 18223 /* 3DSTATE_CONSTANT_PS::PS Constant Buffer 0 Read Length */ 18224 18225 18226 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer0ReadLength_bits 5 18227 18228 static inline uint32_t ATTRIBUTE_PURE 18229 _3DSTATE_CONSTANT_PS_PSConstantBuffer0ReadLength_bits(const struct gen_device_info *devinfo) 18230 { 18231 switch (devinfo->gen) { 18232 case 10: return 0; 18233 case 9: return 0; 18234 case 8: return 0; 18235 case 7: 18236 if (devinfo->is_haswell) { 18237 return 0; 18238 } else { 18239 return 0; 18240 } 18241 case 6: return 5; 18242 case 5: return 0; 18243 case 4: 18244 if (devinfo->is_g4x) { 18245 return 0; 18246 } else { 18247 return 0; 18248 } 18249 default: 18250 unreachable("Invalid hardware generation"); 18251 } 18252 } 18253 18254 18255 18256 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer0ReadLength_start 32 18257 18258 static inline uint32_t ATTRIBUTE_PURE 18259 _3DSTATE_CONSTANT_PS_PSConstantBuffer0ReadLength_start(const struct gen_device_info *devinfo) 18260 { 18261 switch (devinfo->gen) { 18262 case 10: return 0; 18263 case 9: return 0; 18264 case 8: return 0; 18265 case 7: 18266 if (devinfo->is_haswell) { 18267 return 0; 18268 } else { 18269 return 0; 18270 } 18271 case 6: return 32; 18272 case 5: return 0; 18273 case 4: 18274 if (devinfo->is_g4x) { 18275 return 0; 18276 } else { 18277 return 0; 18278 } 18279 default: 18280 unreachable("Invalid hardware generation"); 18281 } 18282 } 18283 18284 18285 18286 /* 3DSTATE_CONSTANT_PS::PS Constant Buffer 1 Read Length */ 18287 18288 18289 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer1ReadLength_bits 5 18290 18291 static inline uint32_t ATTRIBUTE_PURE 18292 _3DSTATE_CONSTANT_PS_PSConstantBuffer1ReadLength_bits(const struct gen_device_info *devinfo) 18293 { 18294 switch (devinfo->gen) { 18295 case 10: return 0; 18296 case 9: return 0; 18297 case 8: return 0; 18298 case 7: 18299 if (devinfo->is_haswell) { 18300 return 0; 18301 } else { 18302 return 0; 18303 } 18304 case 6: return 5; 18305 case 5: return 0; 18306 case 4: 18307 if (devinfo->is_g4x) { 18308 return 0; 18309 } else { 18310 return 0; 18311 } 18312 default: 18313 unreachable("Invalid hardware generation"); 18314 } 18315 } 18316 18317 18318 18319 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer1ReadLength_start 64 18320 18321 static inline uint32_t ATTRIBUTE_PURE 18322 _3DSTATE_CONSTANT_PS_PSConstantBuffer1ReadLength_start(const struct gen_device_info *devinfo) 18323 { 18324 switch (devinfo->gen) { 18325 case 10: return 0; 18326 case 9: return 0; 18327 case 8: return 0; 18328 case 7: 18329 if (devinfo->is_haswell) { 18330 return 0; 18331 } else { 18332 return 0; 18333 } 18334 case 6: return 64; 18335 case 5: return 0; 18336 case 4: 18337 if (devinfo->is_g4x) { 18338 return 0; 18339 } else { 18340 return 0; 18341 } 18342 default: 18343 unreachable("Invalid hardware generation"); 18344 } 18345 } 18346 18347 18348 18349 /* 3DSTATE_CONSTANT_PS::PS Constant Buffer 2 Read Length */ 18350 18351 18352 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer2ReadLength_bits 5 18353 18354 static inline uint32_t ATTRIBUTE_PURE 18355 _3DSTATE_CONSTANT_PS_PSConstantBuffer2ReadLength_bits(const struct gen_device_info *devinfo) 18356 { 18357 switch (devinfo->gen) { 18358 case 10: return 0; 18359 case 9: return 0; 18360 case 8: return 0; 18361 case 7: 18362 if (devinfo->is_haswell) { 18363 return 0; 18364 } else { 18365 return 0; 18366 } 18367 case 6: return 5; 18368 case 5: return 0; 18369 case 4: 18370 if (devinfo->is_g4x) { 18371 return 0; 18372 } else { 18373 return 0; 18374 } 18375 default: 18376 unreachable("Invalid hardware generation"); 18377 } 18378 } 18379 18380 18381 18382 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer2ReadLength_start 96 18383 18384 static inline uint32_t ATTRIBUTE_PURE 18385 _3DSTATE_CONSTANT_PS_PSConstantBuffer2ReadLength_start(const struct gen_device_info *devinfo) 18386 { 18387 switch (devinfo->gen) { 18388 case 10: return 0; 18389 case 9: return 0; 18390 case 8: return 0; 18391 case 7: 18392 if (devinfo->is_haswell) { 18393 return 0; 18394 } else { 18395 return 0; 18396 } 18397 case 6: return 96; 18398 case 5: return 0; 18399 case 4: 18400 if (devinfo->is_g4x) { 18401 return 0; 18402 } else { 18403 return 0; 18404 } 18405 default: 18406 unreachable("Invalid hardware generation"); 18407 } 18408 } 18409 18410 18411 18412 /* 3DSTATE_CONSTANT_PS::PS Constant Buffer 3 Read Length */ 18413 18414 18415 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer3ReadLength_bits 5 18416 18417 static inline uint32_t ATTRIBUTE_PURE 18418 _3DSTATE_CONSTANT_PS_PSConstantBuffer3ReadLength_bits(const struct gen_device_info *devinfo) 18419 { 18420 switch (devinfo->gen) { 18421 case 10: return 0; 18422 case 9: return 0; 18423 case 8: return 0; 18424 case 7: 18425 if (devinfo->is_haswell) { 18426 return 0; 18427 } else { 18428 return 0; 18429 } 18430 case 6: return 5; 18431 case 5: return 0; 18432 case 4: 18433 if (devinfo->is_g4x) { 18434 return 0; 18435 } else { 18436 return 0; 18437 } 18438 default: 18439 unreachable("Invalid hardware generation"); 18440 } 18441 } 18442 18443 18444 18445 #define GEN6_3DSTATE_CONSTANT_PS_PSConstantBuffer3ReadLength_start 128 18446 18447 static inline uint32_t ATTRIBUTE_PURE 18448 _3DSTATE_CONSTANT_PS_PSConstantBuffer3ReadLength_start(const struct gen_device_info *devinfo) 18449 { 18450 switch (devinfo->gen) { 18451 case 10: return 0; 18452 case 9: return 0; 18453 case 8: return 0; 18454 case 7: 18455 if (devinfo->is_haswell) { 18456 return 0; 18457 } else { 18458 return 0; 18459 } 18460 case 6: return 128; 18461 case 5: return 0; 18462 case 4: 18463 if (devinfo->is_g4x) { 18464 return 0; 18465 } else { 18466 return 0; 18467 } 18468 default: 18469 unreachable("Invalid hardware generation"); 18470 } 18471 } 18472 18473 18474 18475 /* 3DSTATE_CONSTANT_PS::Pointer to PS Constant Buffer 0 */ 18476 18477 18478 #define GEN6_3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer0_bits 27 18479 18480 static inline uint32_t ATTRIBUTE_PURE 18481 _3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer0_bits(const struct gen_device_info *devinfo) 18482 { 18483 switch (devinfo->gen) { 18484 case 10: return 0; 18485 case 9: return 0; 18486 case 8: return 0; 18487 case 7: 18488 if (devinfo->is_haswell) { 18489 return 0; 18490 } else { 18491 return 0; 18492 } 18493 case 6: return 27; 18494 case 5: return 0; 18495 case 4: 18496 if (devinfo->is_g4x) { 18497 return 0; 18498 } else { 18499 return 0; 18500 } 18501 default: 18502 unreachable("Invalid hardware generation"); 18503 } 18504 } 18505 18506 18507 18508 #define GEN6_3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer0_start 37 18509 18510 static inline uint32_t ATTRIBUTE_PURE 18511 _3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer0_start(const struct gen_device_info *devinfo) 18512 { 18513 switch (devinfo->gen) { 18514 case 10: return 0; 18515 case 9: return 0; 18516 case 8: return 0; 18517 case 7: 18518 if (devinfo->is_haswell) { 18519 return 0; 18520 } else { 18521 return 0; 18522 } 18523 case 6: return 37; 18524 case 5: return 0; 18525 case 4: 18526 if (devinfo->is_g4x) { 18527 return 0; 18528 } else { 18529 return 0; 18530 } 18531 default: 18532 unreachable("Invalid hardware generation"); 18533 } 18534 } 18535 18536 18537 18538 /* 3DSTATE_CONSTANT_PS::Pointer to PS Constant Buffer 1 */ 18539 18540 18541 #define GEN6_3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer1_bits 27 18542 18543 static inline uint32_t ATTRIBUTE_PURE 18544 _3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer1_bits(const struct gen_device_info *devinfo) 18545 { 18546 switch (devinfo->gen) { 18547 case 10: return 0; 18548 case 9: return 0; 18549 case 8: return 0; 18550 case 7: 18551 if (devinfo->is_haswell) { 18552 return 0; 18553 } else { 18554 return 0; 18555 } 18556 case 6: return 27; 18557 case 5: return 0; 18558 case 4: 18559 if (devinfo->is_g4x) { 18560 return 0; 18561 } else { 18562 return 0; 18563 } 18564 default: 18565 unreachable("Invalid hardware generation"); 18566 } 18567 } 18568 18569 18570 18571 #define GEN6_3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer1_start 69 18572 18573 static inline uint32_t ATTRIBUTE_PURE 18574 _3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer1_start(const struct gen_device_info *devinfo) 18575 { 18576 switch (devinfo->gen) { 18577 case 10: return 0; 18578 case 9: return 0; 18579 case 8: return 0; 18580 case 7: 18581 if (devinfo->is_haswell) { 18582 return 0; 18583 } else { 18584 return 0; 18585 } 18586 case 6: return 69; 18587 case 5: return 0; 18588 case 4: 18589 if (devinfo->is_g4x) { 18590 return 0; 18591 } else { 18592 return 0; 18593 } 18594 default: 18595 unreachable("Invalid hardware generation"); 18596 } 18597 } 18598 18599 18600 18601 /* 3DSTATE_CONSTANT_PS::Pointer to PS Constant Buffer 2 */ 18602 18603 18604 #define GEN6_3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer2_bits 27 18605 18606 static inline uint32_t ATTRIBUTE_PURE 18607 _3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer2_bits(const struct gen_device_info *devinfo) 18608 { 18609 switch (devinfo->gen) { 18610 case 10: return 0; 18611 case 9: return 0; 18612 case 8: return 0; 18613 case 7: 18614 if (devinfo->is_haswell) { 18615 return 0; 18616 } else { 18617 return 0; 18618 } 18619 case 6: return 27; 18620 case 5: return 0; 18621 case 4: 18622 if (devinfo->is_g4x) { 18623 return 0; 18624 } else { 18625 return 0; 18626 } 18627 default: 18628 unreachable("Invalid hardware generation"); 18629 } 18630 } 18631 18632 18633 18634 #define GEN6_3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer2_start 101 18635 18636 static inline uint32_t ATTRIBUTE_PURE 18637 _3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer2_start(const struct gen_device_info *devinfo) 18638 { 18639 switch (devinfo->gen) { 18640 case 10: return 0; 18641 case 9: return 0; 18642 case 8: return 0; 18643 case 7: 18644 if (devinfo->is_haswell) { 18645 return 0; 18646 } else { 18647 return 0; 18648 } 18649 case 6: return 101; 18650 case 5: return 0; 18651 case 4: 18652 if (devinfo->is_g4x) { 18653 return 0; 18654 } else { 18655 return 0; 18656 } 18657 default: 18658 unreachable("Invalid hardware generation"); 18659 } 18660 } 18661 18662 18663 18664 /* 3DSTATE_CONSTANT_PS::Pointer to PS Constant Buffer 3 */ 18665 18666 18667 #define GEN6_3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer3_bits 27 18668 18669 static inline uint32_t ATTRIBUTE_PURE 18670 _3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer3_bits(const struct gen_device_info *devinfo) 18671 { 18672 switch (devinfo->gen) { 18673 case 10: return 0; 18674 case 9: return 0; 18675 case 8: return 0; 18676 case 7: 18677 if (devinfo->is_haswell) { 18678 return 0; 18679 } else { 18680 return 0; 18681 } 18682 case 6: return 27; 18683 case 5: return 0; 18684 case 4: 18685 if (devinfo->is_g4x) { 18686 return 0; 18687 } else { 18688 return 0; 18689 } 18690 default: 18691 unreachable("Invalid hardware generation"); 18692 } 18693 } 18694 18695 18696 18697 #define GEN6_3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer3_start 133 18698 18699 static inline uint32_t ATTRIBUTE_PURE 18700 _3DSTATE_CONSTANT_PS_PointertoPSConstantBuffer3_start(const struct gen_device_info *devinfo) 18701 { 18702 switch (devinfo->gen) { 18703 case 10: return 0; 18704 case 9: return 0; 18705 case 8: return 0; 18706 case 7: 18707 if (devinfo->is_haswell) { 18708 return 0; 18709 } else { 18710 return 0; 18711 } 18712 case 6: return 133; 18713 case 5: return 0; 18714 case 4: 18715 if (devinfo->is_g4x) { 18716 return 0; 18717 } else { 18718 return 0; 18719 } 18720 default: 18721 unreachable("Invalid hardware generation"); 18722 } 18723 } 18724 18725 18726 18727 /* 3DSTATE_CONSTANT_VS */ 18728 18729 18730 #define GEN10_3DSTATE_CONSTANT_VS_length 11 18731 #define GEN9_3DSTATE_CONSTANT_VS_length 11 18732 #define GEN8_3DSTATE_CONSTANT_VS_length 11 18733 #define GEN75_3DSTATE_CONSTANT_VS_length 7 18734 #define GEN7_3DSTATE_CONSTANT_VS_length 7 18735 #define GEN6_3DSTATE_CONSTANT_VS_length 5 18736 18737 static inline uint32_t ATTRIBUTE_PURE 18738 _3DSTATE_CONSTANT_VS_length(const struct gen_device_info *devinfo) 18739 { 18740 switch (devinfo->gen) { 18741 case 10: return 11; 18742 case 9: return 11; 18743 case 8: return 11; 18744 case 7: 18745 if (devinfo->is_haswell) { 18746 return 7; 18747 } else { 18748 return 7; 18749 } 18750 case 6: return 5; 18751 case 5: return 0; 18752 case 4: 18753 if (devinfo->is_g4x) { 18754 return 0; 18755 } else { 18756 return 0; 18757 } 18758 default: 18759 unreachable("Invalid hardware generation"); 18760 } 18761 } 18762 18763 18764 18765 /* 3DSTATE_CONSTANT_VS::3D Command Opcode */ 18766 18767 18768 #define GEN10_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 18769 #define GEN9_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 18770 #define GEN8_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 18771 #define GEN75_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 18772 #define GEN7_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 18773 #define GEN6_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 18774 18775 static inline uint32_t ATTRIBUTE_PURE 18776 _3DSTATE_CONSTANT_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 18777 { 18778 switch (devinfo->gen) { 18779 case 10: return 3; 18780 case 9: return 3; 18781 case 8: return 3; 18782 case 7: 18783 if (devinfo->is_haswell) { 18784 return 3; 18785 } else { 18786 return 3; 18787 } 18788 case 6: return 3; 18789 case 5: return 0; 18790 case 4: 18791 if (devinfo->is_g4x) { 18792 return 0; 18793 } else { 18794 return 0; 18795 } 18796 default: 18797 unreachable("Invalid hardware generation"); 18798 } 18799 } 18800 18801 18802 18803 #define GEN10_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 18804 #define GEN9_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 18805 #define GEN8_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 18806 #define GEN75_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 18807 #define GEN7_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 18808 #define GEN6_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 18809 18810 static inline uint32_t ATTRIBUTE_PURE 18811 _3DSTATE_CONSTANT_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 18812 { 18813 switch (devinfo->gen) { 18814 case 10: return 24; 18815 case 9: return 24; 18816 case 8: return 24; 18817 case 7: 18818 if (devinfo->is_haswell) { 18819 return 24; 18820 } else { 18821 return 24; 18822 } 18823 case 6: return 24; 18824 case 5: return 0; 18825 case 4: 18826 if (devinfo->is_g4x) { 18827 return 0; 18828 } else { 18829 return 0; 18830 } 18831 default: 18832 unreachable("Invalid hardware generation"); 18833 } 18834 } 18835 18836 18837 18838 /* 3DSTATE_CONSTANT_VS::3D Command Sub Opcode */ 18839 18840 18841 #define GEN10_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 18842 #define GEN9_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 18843 #define GEN8_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 18844 #define GEN75_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 18845 #define GEN7_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 18846 #define GEN6_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 18847 18848 static inline uint32_t ATTRIBUTE_PURE 18849 _3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 18850 { 18851 switch (devinfo->gen) { 18852 case 10: return 8; 18853 case 9: return 8; 18854 case 8: return 8; 18855 case 7: 18856 if (devinfo->is_haswell) { 18857 return 8; 18858 } else { 18859 return 8; 18860 } 18861 case 6: return 8; 18862 case 5: return 0; 18863 case 4: 18864 if (devinfo->is_g4x) { 18865 return 0; 18866 } else { 18867 return 0; 18868 } 18869 default: 18870 unreachable("Invalid hardware generation"); 18871 } 18872 } 18873 18874 18875 18876 #define GEN10_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 18877 #define GEN9_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 18878 #define GEN8_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 18879 #define GEN75_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 18880 #define GEN7_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 18881 #define GEN6_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 18882 18883 static inline uint32_t ATTRIBUTE_PURE 18884 _3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 18885 { 18886 switch (devinfo->gen) { 18887 case 10: return 16; 18888 case 9: return 16; 18889 case 8: return 16; 18890 case 7: 18891 if (devinfo->is_haswell) { 18892 return 16; 18893 } else { 18894 return 16; 18895 } 18896 case 6: return 16; 18897 case 5: return 0; 18898 case 4: 18899 if (devinfo->is_g4x) { 18900 return 0; 18901 } else { 18902 return 0; 18903 } 18904 default: 18905 unreachable("Invalid hardware generation"); 18906 } 18907 } 18908 18909 18910 18911 /* 3DSTATE_CONSTANT_VS::Buffer 0 Valid */ 18912 18913 18914 #define GEN6_3DSTATE_CONSTANT_VS_Buffer0Valid_bits 1 18915 18916 static inline uint32_t ATTRIBUTE_PURE 18917 _3DSTATE_CONSTANT_VS_Buffer0Valid_bits(const struct gen_device_info *devinfo) 18918 { 18919 switch (devinfo->gen) { 18920 case 10: return 0; 18921 case 9: return 0; 18922 case 8: return 0; 18923 case 7: 18924 if (devinfo->is_haswell) { 18925 return 0; 18926 } else { 18927 return 0; 18928 } 18929 case 6: return 1; 18930 case 5: return 0; 18931 case 4: 18932 if (devinfo->is_g4x) { 18933 return 0; 18934 } else { 18935 return 0; 18936 } 18937 default: 18938 unreachable("Invalid hardware generation"); 18939 } 18940 } 18941 18942 18943 18944 #define GEN6_3DSTATE_CONSTANT_VS_Buffer0Valid_start 12 18945 18946 static inline uint32_t ATTRIBUTE_PURE 18947 _3DSTATE_CONSTANT_VS_Buffer0Valid_start(const struct gen_device_info *devinfo) 18948 { 18949 switch (devinfo->gen) { 18950 case 10: return 0; 18951 case 9: return 0; 18952 case 8: return 0; 18953 case 7: 18954 if (devinfo->is_haswell) { 18955 return 0; 18956 } else { 18957 return 0; 18958 } 18959 case 6: return 12; 18960 case 5: return 0; 18961 case 4: 18962 if (devinfo->is_g4x) { 18963 return 0; 18964 } else { 18965 return 0; 18966 } 18967 default: 18968 unreachable("Invalid hardware generation"); 18969 } 18970 } 18971 18972 18973 18974 /* 3DSTATE_CONSTANT_VS::Buffer 1 Valid */ 18975 18976 18977 #define GEN6_3DSTATE_CONSTANT_VS_Buffer1Valid_bits 1 18978 18979 static inline uint32_t ATTRIBUTE_PURE 18980 _3DSTATE_CONSTANT_VS_Buffer1Valid_bits(const struct gen_device_info *devinfo) 18981 { 18982 switch (devinfo->gen) { 18983 case 10: return 0; 18984 case 9: return 0; 18985 case 8: return 0; 18986 case 7: 18987 if (devinfo->is_haswell) { 18988 return 0; 18989 } else { 18990 return 0; 18991 } 18992 case 6: return 1; 18993 case 5: return 0; 18994 case 4: 18995 if (devinfo->is_g4x) { 18996 return 0; 18997 } else { 18998 return 0; 18999 } 19000 default: 19001 unreachable("Invalid hardware generation"); 19002 } 19003 } 19004 19005 19006 19007 #define GEN6_3DSTATE_CONSTANT_VS_Buffer1Valid_start 13 19008 19009 static inline uint32_t ATTRIBUTE_PURE 19010 _3DSTATE_CONSTANT_VS_Buffer1Valid_start(const struct gen_device_info *devinfo) 19011 { 19012 switch (devinfo->gen) { 19013 case 10: return 0; 19014 case 9: return 0; 19015 case 8: return 0; 19016 case 7: 19017 if (devinfo->is_haswell) { 19018 return 0; 19019 } else { 19020 return 0; 19021 } 19022 case 6: return 13; 19023 case 5: return 0; 19024 case 4: 19025 if (devinfo->is_g4x) { 19026 return 0; 19027 } else { 19028 return 0; 19029 } 19030 default: 19031 unreachable("Invalid hardware generation"); 19032 } 19033 } 19034 19035 19036 19037 /* 3DSTATE_CONSTANT_VS::Buffer 2 Valid */ 19038 19039 19040 #define GEN6_3DSTATE_CONSTANT_VS_Buffer2Valid_bits 1 19041 19042 static inline uint32_t ATTRIBUTE_PURE 19043 _3DSTATE_CONSTANT_VS_Buffer2Valid_bits(const struct gen_device_info *devinfo) 19044 { 19045 switch (devinfo->gen) { 19046 case 10: return 0; 19047 case 9: return 0; 19048 case 8: return 0; 19049 case 7: 19050 if (devinfo->is_haswell) { 19051 return 0; 19052 } else { 19053 return 0; 19054 } 19055 case 6: return 1; 19056 case 5: return 0; 19057 case 4: 19058 if (devinfo->is_g4x) { 19059 return 0; 19060 } else { 19061 return 0; 19062 } 19063 default: 19064 unreachable("Invalid hardware generation"); 19065 } 19066 } 19067 19068 19069 19070 #define GEN6_3DSTATE_CONSTANT_VS_Buffer2Valid_start 14 19071 19072 static inline uint32_t ATTRIBUTE_PURE 19073 _3DSTATE_CONSTANT_VS_Buffer2Valid_start(const struct gen_device_info *devinfo) 19074 { 19075 switch (devinfo->gen) { 19076 case 10: return 0; 19077 case 9: return 0; 19078 case 8: return 0; 19079 case 7: 19080 if (devinfo->is_haswell) { 19081 return 0; 19082 } else { 19083 return 0; 19084 } 19085 case 6: return 14; 19086 case 5: return 0; 19087 case 4: 19088 if (devinfo->is_g4x) { 19089 return 0; 19090 } else { 19091 return 0; 19092 } 19093 default: 19094 unreachable("Invalid hardware generation"); 19095 } 19096 } 19097 19098 19099 19100 /* 3DSTATE_CONSTANT_VS::Buffer 3 Valid */ 19101 19102 19103 #define GEN6_3DSTATE_CONSTANT_VS_Buffer3Valid_bits 1 19104 19105 static inline uint32_t ATTRIBUTE_PURE 19106 _3DSTATE_CONSTANT_VS_Buffer3Valid_bits(const struct gen_device_info *devinfo) 19107 { 19108 switch (devinfo->gen) { 19109 case 10: return 0; 19110 case 9: return 0; 19111 case 8: return 0; 19112 case 7: 19113 if (devinfo->is_haswell) { 19114 return 0; 19115 } else { 19116 return 0; 19117 } 19118 case 6: return 1; 19119 case 5: return 0; 19120 case 4: 19121 if (devinfo->is_g4x) { 19122 return 0; 19123 } else { 19124 return 0; 19125 } 19126 default: 19127 unreachable("Invalid hardware generation"); 19128 } 19129 } 19130 19131 19132 19133 #define GEN6_3DSTATE_CONSTANT_VS_Buffer3Valid_start 15 19134 19135 static inline uint32_t ATTRIBUTE_PURE 19136 _3DSTATE_CONSTANT_VS_Buffer3Valid_start(const struct gen_device_info *devinfo) 19137 { 19138 switch (devinfo->gen) { 19139 case 10: return 0; 19140 case 9: return 0; 19141 case 8: return 0; 19142 case 7: 19143 if (devinfo->is_haswell) { 19144 return 0; 19145 } else { 19146 return 0; 19147 } 19148 case 6: return 15; 19149 case 5: return 0; 19150 case 4: 19151 if (devinfo->is_g4x) { 19152 return 0; 19153 } else { 19154 return 0; 19155 } 19156 default: 19157 unreachable("Invalid hardware generation"); 19158 } 19159 } 19160 19161 19162 19163 /* 3DSTATE_CONSTANT_VS::Command SubType */ 19164 19165 19166 #define GEN10_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 19167 #define GEN9_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 19168 #define GEN8_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 19169 #define GEN75_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 19170 #define GEN7_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 19171 #define GEN6_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 19172 19173 static inline uint32_t ATTRIBUTE_PURE 19174 _3DSTATE_CONSTANT_VS_CommandSubType_bits(const struct gen_device_info *devinfo) 19175 { 19176 switch (devinfo->gen) { 19177 case 10: return 2; 19178 case 9: return 2; 19179 case 8: return 2; 19180 case 7: 19181 if (devinfo->is_haswell) { 19182 return 2; 19183 } else { 19184 return 2; 19185 } 19186 case 6: return 2; 19187 case 5: return 0; 19188 case 4: 19189 if (devinfo->is_g4x) { 19190 return 0; 19191 } else { 19192 return 0; 19193 } 19194 default: 19195 unreachable("Invalid hardware generation"); 19196 } 19197 } 19198 19199 19200 19201 #define GEN10_3DSTATE_CONSTANT_VS_CommandSubType_start 27 19202 #define GEN9_3DSTATE_CONSTANT_VS_CommandSubType_start 27 19203 #define GEN8_3DSTATE_CONSTANT_VS_CommandSubType_start 27 19204 #define GEN75_3DSTATE_CONSTANT_VS_CommandSubType_start 27 19205 #define GEN7_3DSTATE_CONSTANT_VS_CommandSubType_start 27 19206 #define GEN6_3DSTATE_CONSTANT_VS_CommandSubType_start 27 19207 19208 static inline uint32_t ATTRIBUTE_PURE 19209 _3DSTATE_CONSTANT_VS_CommandSubType_start(const struct gen_device_info *devinfo) 19210 { 19211 switch (devinfo->gen) { 19212 case 10: return 27; 19213 case 9: return 27; 19214 case 8: return 27; 19215 case 7: 19216 if (devinfo->is_haswell) { 19217 return 27; 19218 } else { 19219 return 27; 19220 } 19221 case 6: return 27; 19222 case 5: return 0; 19223 case 4: 19224 if (devinfo->is_g4x) { 19225 return 0; 19226 } else { 19227 return 0; 19228 } 19229 default: 19230 unreachable("Invalid hardware generation"); 19231 } 19232 } 19233 19234 19235 19236 /* 3DSTATE_CONSTANT_VS::Command Type */ 19237 19238 19239 #define GEN10_3DSTATE_CONSTANT_VS_CommandType_bits 3 19240 #define GEN9_3DSTATE_CONSTANT_VS_CommandType_bits 3 19241 #define GEN8_3DSTATE_CONSTANT_VS_CommandType_bits 3 19242 #define GEN75_3DSTATE_CONSTANT_VS_CommandType_bits 3 19243 #define GEN7_3DSTATE_CONSTANT_VS_CommandType_bits 3 19244 #define GEN6_3DSTATE_CONSTANT_VS_CommandType_bits 3 19245 19246 static inline uint32_t ATTRIBUTE_PURE 19247 _3DSTATE_CONSTANT_VS_CommandType_bits(const struct gen_device_info *devinfo) 19248 { 19249 switch (devinfo->gen) { 19250 case 10: return 3; 19251 case 9: return 3; 19252 case 8: return 3; 19253 case 7: 19254 if (devinfo->is_haswell) { 19255 return 3; 19256 } else { 19257 return 3; 19258 } 19259 case 6: return 3; 19260 case 5: return 0; 19261 case 4: 19262 if (devinfo->is_g4x) { 19263 return 0; 19264 } else { 19265 return 0; 19266 } 19267 default: 19268 unreachable("Invalid hardware generation"); 19269 } 19270 } 19271 19272 19273 19274 #define GEN10_3DSTATE_CONSTANT_VS_CommandType_start 29 19275 #define GEN9_3DSTATE_CONSTANT_VS_CommandType_start 29 19276 #define GEN8_3DSTATE_CONSTANT_VS_CommandType_start 29 19277 #define GEN75_3DSTATE_CONSTANT_VS_CommandType_start 29 19278 #define GEN7_3DSTATE_CONSTANT_VS_CommandType_start 29 19279 #define GEN6_3DSTATE_CONSTANT_VS_CommandType_start 29 19280 19281 static inline uint32_t ATTRIBUTE_PURE 19282 _3DSTATE_CONSTANT_VS_CommandType_start(const struct gen_device_info *devinfo) 19283 { 19284 switch (devinfo->gen) { 19285 case 10: return 29; 19286 case 9: return 29; 19287 case 8: return 29; 19288 case 7: 19289 if (devinfo->is_haswell) { 19290 return 29; 19291 } else { 19292 return 29; 19293 } 19294 case 6: return 29; 19295 case 5: return 0; 19296 case 4: 19297 if (devinfo->is_g4x) { 19298 return 0; 19299 } else { 19300 return 0; 19301 } 19302 default: 19303 unreachable("Invalid hardware generation"); 19304 } 19305 } 19306 19307 19308 19309 /* 3DSTATE_CONSTANT_VS::Constant Body */ 19310 19311 19312 #define GEN10_3DSTATE_CONSTANT_VS_ConstantBody_bits 320 19313 #define GEN9_3DSTATE_CONSTANT_VS_ConstantBody_bits 320 19314 #define GEN8_3DSTATE_CONSTANT_VS_ConstantBody_bits 320 19315 #define GEN75_3DSTATE_CONSTANT_VS_ConstantBody_bits 192 19316 #define GEN7_3DSTATE_CONSTANT_VS_ConstantBody_bits 192 19317 19318 static inline uint32_t ATTRIBUTE_PURE 19319 _3DSTATE_CONSTANT_VS_ConstantBody_bits(const struct gen_device_info *devinfo) 19320 { 19321 switch (devinfo->gen) { 19322 case 10: return 320; 19323 case 9: return 320; 19324 case 8: return 320; 19325 case 7: 19326 if (devinfo->is_haswell) { 19327 return 192; 19328 } else { 19329 return 192; 19330 } 19331 case 6: return 0; 19332 case 5: return 0; 19333 case 4: 19334 if (devinfo->is_g4x) { 19335 return 0; 19336 } else { 19337 return 0; 19338 } 19339 default: 19340 unreachable("Invalid hardware generation"); 19341 } 19342 } 19343 19344 19345 19346 #define GEN10_3DSTATE_CONSTANT_VS_ConstantBody_start 32 19347 #define GEN9_3DSTATE_CONSTANT_VS_ConstantBody_start 32 19348 #define GEN8_3DSTATE_CONSTANT_VS_ConstantBody_start 32 19349 #define GEN75_3DSTATE_CONSTANT_VS_ConstantBody_start 32 19350 #define GEN7_3DSTATE_CONSTANT_VS_ConstantBody_start 32 19351 19352 static inline uint32_t ATTRIBUTE_PURE 19353 _3DSTATE_CONSTANT_VS_ConstantBody_start(const struct gen_device_info *devinfo) 19354 { 19355 switch (devinfo->gen) { 19356 case 10: return 32; 19357 case 9: return 32; 19358 case 8: return 32; 19359 case 7: 19360 if (devinfo->is_haswell) { 19361 return 32; 19362 } else { 19363 return 32; 19364 } 19365 case 6: return 0; 19366 case 5: return 0; 19367 case 4: 19368 if (devinfo->is_g4x) { 19369 return 0; 19370 } else { 19371 return 0; 19372 } 19373 default: 19374 unreachable("Invalid hardware generation"); 19375 } 19376 } 19377 19378 19379 19380 /* 3DSTATE_CONSTANT_VS::Constant Buffer Object Control State */ 19381 19382 19383 #define GEN10_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_bits 7 19384 #define GEN9_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_bits 7 19385 #define GEN8_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_bits 7 19386 #define GEN6_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_bits 4 19387 19388 static inline uint32_t ATTRIBUTE_PURE 19389 _3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) 19390 { 19391 switch (devinfo->gen) { 19392 case 10: return 7; 19393 case 9: return 7; 19394 case 8: return 7; 19395 case 7: 19396 if (devinfo->is_haswell) { 19397 return 0; 19398 } else { 19399 return 0; 19400 } 19401 case 6: return 4; 19402 case 5: return 0; 19403 case 4: 19404 if (devinfo->is_g4x) { 19405 return 0; 19406 } else { 19407 return 0; 19408 } 19409 default: 19410 unreachable("Invalid hardware generation"); 19411 } 19412 } 19413 19414 19415 19416 #define GEN10_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_start 8 19417 #define GEN9_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_start 8 19418 #define GEN8_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_start 8 19419 #define GEN6_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_start 8 19420 19421 static inline uint32_t ATTRIBUTE_PURE 19422 _3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) 19423 { 19424 switch (devinfo->gen) { 19425 case 10: return 8; 19426 case 9: return 8; 19427 case 8: return 8; 19428 case 7: 19429 if (devinfo->is_haswell) { 19430 return 0; 19431 } else { 19432 return 0; 19433 } 19434 case 6: return 8; 19435 case 5: return 0; 19436 case 4: 19437 if (devinfo->is_g4x) { 19438 return 0; 19439 } else { 19440 return 0; 19441 } 19442 default: 19443 unreachable("Invalid hardware generation"); 19444 } 19445 } 19446 19447 19448 19449 /* 3DSTATE_CONSTANT_VS::DWord Length */ 19450 19451 19452 #define GEN10_3DSTATE_CONSTANT_VS_DWordLength_bits 8 19453 #define GEN9_3DSTATE_CONSTANT_VS_DWordLength_bits 8 19454 #define GEN8_3DSTATE_CONSTANT_VS_DWordLength_bits 8 19455 #define GEN75_3DSTATE_CONSTANT_VS_DWordLength_bits 8 19456 #define GEN7_3DSTATE_CONSTANT_VS_DWordLength_bits 8 19457 #define GEN6_3DSTATE_CONSTANT_VS_DWordLength_bits 8 19458 19459 static inline uint32_t ATTRIBUTE_PURE 19460 _3DSTATE_CONSTANT_VS_DWordLength_bits(const struct gen_device_info *devinfo) 19461 { 19462 switch (devinfo->gen) { 19463 case 10: return 8; 19464 case 9: return 8; 19465 case 8: return 8; 19466 case 7: 19467 if (devinfo->is_haswell) { 19468 return 8; 19469 } else { 19470 return 8; 19471 } 19472 case 6: return 8; 19473 case 5: return 0; 19474 case 4: 19475 if (devinfo->is_g4x) { 19476 return 0; 19477 } else { 19478 return 0; 19479 } 19480 default: 19481 unreachable("Invalid hardware generation"); 19482 } 19483 } 19484 19485 19486 19487 #define GEN10_3DSTATE_CONSTANT_VS_DWordLength_start 0 19488 #define GEN9_3DSTATE_CONSTANT_VS_DWordLength_start 0 19489 #define GEN8_3DSTATE_CONSTANT_VS_DWordLength_start 0 19490 #define GEN75_3DSTATE_CONSTANT_VS_DWordLength_start 0 19491 #define GEN7_3DSTATE_CONSTANT_VS_DWordLength_start 0 19492 #define GEN6_3DSTATE_CONSTANT_VS_DWordLength_start 0 19493 19494 static inline uint32_t ATTRIBUTE_PURE 19495 _3DSTATE_CONSTANT_VS_DWordLength_start(const struct gen_device_info *devinfo) 19496 { 19497 switch (devinfo->gen) { 19498 case 10: return 0; 19499 case 9: return 0; 19500 case 8: return 0; 19501 case 7: 19502 if (devinfo->is_haswell) { 19503 return 0; 19504 } else { 19505 return 0; 19506 } 19507 case 6: return 0; 19508 case 5: return 0; 19509 case 4: 19510 if (devinfo->is_g4x) { 19511 return 0; 19512 } else { 19513 return 0; 19514 } 19515 default: 19516 unreachable("Invalid hardware generation"); 19517 } 19518 } 19519 19520 19521 19522 /* 3DSTATE_CONSTANT_VS::Pointer to VS Constant Buffer 0 */ 19523 19524 19525 #define GEN6_3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer0_bits 27 19526 19527 static inline uint32_t ATTRIBUTE_PURE 19528 _3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer0_bits(const struct gen_device_info *devinfo) 19529 { 19530 switch (devinfo->gen) { 19531 case 10: return 0; 19532 case 9: return 0; 19533 case 8: return 0; 19534 case 7: 19535 if (devinfo->is_haswell) { 19536 return 0; 19537 } else { 19538 return 0; 19539 } 19540 case 6: return 27; 19541 case 5: return 0; 19542 case 4: 19543 if (devinfo->is_g4x) { 19544 return 0; 19545 } else { 19546 return 0; 19547 } 19548 default: 19549 unreachable("Invalid hardware generation"); 19550 } 19551 } 19552 19553 19554 19555 #define GEN6_3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer0_start 37 19556 19557 static inline uint32_t ATTRIBUTE_PURE 19558 _3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer0_start(const struct gen_device_info *devinfo) 19559 { 19560 switch (devinfo->gen) { 19561 case 10: return 0; 19562 case 9: return 0; 19563 case 8: return 0; 19564 case 7: 19565 if (devinfo->is_haswell) { 19566 return 0; 19567 } else { 19568 return 0; 19569 } 19570 case 6: return 37; 19571 case 5: return 0; 19572 case 4: 19573 if (devinfo->is_g4x) { 19574 return 0; 19575 } else { 19576 return 0; 19577 } 19578 default: 19579 unreachable("Invalid hardware generation"); 19580 } 19581 } 19582 19583 19584 19585 /* 3DSTATE_CONSTANT_VS::Pointer to VS Constant Buffer 1 */ 19586 19587 19588 #define GEN6_3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer1_bits 27 19589 19590 static inline uint32_t ATTRIBUTE_PURE 19591 _3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer1_bits(const struct gen_device_info *devinfo) 19592 { 19593 switch (devinfo->gen) { 19594 case 10: return 0; 19595 case 9: return 0; 19596 case 8: return 0; 19597 case 7: 19598 if (devinfo->is_haswell) { 19599 return 0; 19600 } else { 19601 return 0; 19602 } 19603 case 6: return 27; 19604 case 5: return 0; 19605 case 4: 19606 if (devinfo->is_g4x) { 19607 return 0; 19608 } else { 19609 return 0; 19610 } 19611 default: 19612 unreachable("Invalid hardware generation"); 19613 } 19614 } 19615 19616 19617 19618 #define GEN6_3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer1_start 69 19619 19620 static inline uint32_t ATTRIBUTE_PURE 19621 _3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer1_start(const struct gen_device_info *devinfo) 19622 { 19623 switch (devinfo->gen) { 19624 case 10: return 0; 19625 case 9: return 0; 19626 case 8: return 0; 19627 case 7: 19628 if (devinfo->is_haswell) { 19629 return 0; 19630 } else { 19631 return 0; 19632 } 19633 case 6: return 69; 19634 case 5: return 0; 19635 case 4: 19636 if (devinfo->is_g4x) { 19637 return 0; 19638 } else { 19639 return 0; 19640 } 19641 default: 19642 unreachable("Invalid hardware generation"); 19643 } 19644 } 19645 19646 19647 19648 /* 3DSTATE_CONSTANT_VS::Pointer to VS Constant Buffer 2 */ 19649 19650 19651 #define GEN6_3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer2_bits 27 19652 19653 static inline uint32_t ATTRIBUTE_PURE 19654 _3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer2_bits(const struct gen_device_info *devinfo) 19655 { 19656 switch (devinfo->gen) { 19657 case 10: return 0; 19658 case 9: return 0; 19659 case 8: return 0; 19660 case 7: 19661 if (devinfo->is_haswell) { 19662 return 0; 19663 } else { 19664 return 0; 19665 } 19666 case 6: return 27; 19667 case 5: return 0; 19668 case 4: 19669 if (devinfo->is_g4x) { 19670 return 0; 19671 } else { 19672 return 0; 19673 } 19674 default: 19675 unreachable("Invalid hardware generation"); 19676 } 19677 } 19678 19679 19680 19681 #define GEN6_3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer2_start 101 19682 19683 static inline uint32_t ATTRIBUTE_PURE 19684 _3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer2_start(const struct gen_device_info *devinfo) 19685 { 19686 switch (devinfo->gen) { 19687 case 10: return 0; 19688 case 9: return 0; 19689 case 8: return 0; 19690 case 7: 19691 if (devinfo->is_haswell) { 19692 return 0; 19693 } else { 19694 return 0; 19695 } 19696 case 6: return 101; 19697 case 5: return 0; 19698 case 4: 19699 if (devinfo->is_g4x) { 19700 return 0; 19701 } else { 19702 return 0; 19703 } 19704 default: 19705 unreachable("Invalid hardware generation"); 19706 } 19707 } 19708 19709 19710 19711 /* 3DSTATE_CONSTANT_VS::Pointer to VS Constant Buffer 3 */ 19712 19713 19714 #define GEN6_3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer3_bits 27 19715 19716 static inline uint32_t ATTRIBUTE_PURE 19717 _3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer3_bits(const struct gen_device_info *devinfo) 19718 { 19719 switch (devinfo->gen) { 19720 case 10: return 0; 19721 case 9: return 0; 19722 case 8: return 0; 19723 case 7: 19724 if (devinfo->is_haswell) { 19725 return 0; 19726 } else { 19727 return 0; 19728 } 19729 case 6: return 27; 19730 case 5: return 0; 19731 case 4: 19732 if (devinfo->is_g4x) { 19733 return 0; 19734 } else { 19735 return 0; 19736 } 19737 default: 19738 unreachable("Invalid hardware generation"); 19739 } 19740 } 19741 19742 19743 19744 #define GEN6_3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer3_start 133 19745 19746 static inline uint32_t ATTRIBUTE_PURE 19747 _3DSTATE_CONSTANT_VS_PointertoVSConstantBuffer3_start(const struct gen_device_info *devinfo) 19748 { 19749 switch (devinfo->gen) { 19750 case 10: return 0; 19751 case 9: return 0; 19752 case 8: return 0; 19753 case 7: 19754 if (devinfo->is_haswell) { 19755 return 0; 19756 } else { 19757 return 0; 19758 } 19759 case 6: return 133; 19760 case 5: return 0; 19761 case 4: 19762 if (devinfo->is_g4x) { 19763 return 0; 19764 } else { 19765 return 0; 19766 } 19767 default: 19768 unreachable("Invalid hardware generation"); 19769 } 19770 } 19771 19772 19773 19774 /* 3DSTATE_CONSTANT_VS::VS Constant Buffer 0 Read Length */ 19775 19776 19777 #define GEN6_3DSTATE_CONSTANT_VS_VSConstantBuffer0ReadLength_bits 5 19778 19779 static inline uint32_t ATTRIBUTE_PURE 19780 _3DSTATE_CONSTANT_VS_VSConstantBuffer0ReadLength_bits(const struct gen_device_info *devinfo) 19781 { 19782 switch (devinfo->gen) { 19783 case 10: return 0; 19784 case 9: return 0; 19785 case 8: return 0; 19786 case 7: 19787 if (devinfo->is_haswell) { 19788 return 0; 19789 } else { 19790 return 0; 19791 } 19792 case 6: return 5; 19793 case 5: return 0; 19794 case 4: 19795 if (devinfo->is_g4x) { 19796 return 0; 19797 } else { 19798 return 0; 19799 } 19800 default: 19801 unreachable("Invalid hardware generation"); 19802 } 19803 } 19804 19805 19806 19807 #define GEN6_3DSTATE_CONSTANT_VS_VSConstantBuffer0ReadLength_start 32 19808 19809 static inline uint32_t ATTRIBUTE_PURE 19810 _3DSTATE_CONSTANT_VS_VSConstantBuffer0ReadLength_start(const struct gen_device_info *devinfo) 19811 { 19812 switch (devinfo->gen) { 19813 case 10: return 0; 19814 case 9: return 0; 19815 case 8: return 0; 19816 case 7: 19817 if (devinfo->is_haswell) { 19818 return 0; 19819 } else { 19820 return 0; 19821 } 19822 case 6: return 32; 19823 case 5: return 0; 19824 case 4: 19825 if (devinfo->is_g4x) { 19826 return 0; 19827 } else { 19828 return 0; 19829 } 19830 default: 19831 unreachable("Invalid hardware generation"); 19832 } 19833 } 19834 19835 19836 19837 /* 3DSTATE_CONSTANT_VS::VS Constant Buffer 1 Read Length */ 19838 19839 19840 #define GEN6_3DSTATE_CONSTANT_VS_VSConstantBuffer1ReadLength_bits 5 19841 19842 static inline uint32_t ATTRIBUTE_PURE 19843 _3DSTATE_CONSTANT_VS_VSConstantBuffer1ReadLength_bits(const struct gen_device_info *devinfo) 19844 { 19845 switch (devinfo->gen) { 19846 case 10: return 0; 19847 case 9: return 0; 19848 case 8: return 0; 19849 case 7: 19850 if (devinfo->is_haswell) { 19851 return 0; 19852 } else { 19853 return 0; 19854 } 19855 case 6: return 5; 19856 case 5: return 0; 19857 case 4: 19858 if (devinfo->is_g4x) { 19859 return 0; 19860 } else { 19861 return 0; 19862 } 19863 default: 19864 unreachable("Invalid hardware generation"); 19865 } 19866 } 19867 19868 19869 19870 #define GEN6_3DSTATE_CONSTANT_VS_VSConstantBuffer1ReadLength_start 64 19871 19872 static inline uint32_t ATTRIBUTE_PURE 19873 _3DSTATE_CONSTANT_VS_VSConstantBuffer1ReadLength_start(const struct gen_device_info *devinfo) 19874 { 19875 switch (devinfo->gen) { 19876 case 10: return 0; 19877 case 9: return 0; 19878 case 8: return 0; 19879 case 7: 19880 if (devinfo->is_haswell) { 19881 return 0; 19882 } else { 19883 return 0; 19884 } 19885 case 6: return 64; 19886 case 5: return 0; 19887 case 4: 19888 if (devinfo->is_g4x) { 19889 return 0; 19890 } else { 19891 return 0; 19892 } 19893 default: 19894 unreachable("Invalid hardware generation"); 19895 } 19896 } 19897 19898 19899 19900 /* 3DSTATE_CONSTANT_VS::VS Constant Buffer 2 Read Length */ 19901 19902 19903 #define GEN6_3DSTATE_CONSTANT_VS_VSConstantBuffer2ReadLength_bits 5 19904 19905 static inline uint32_t ATTRIBUTE_PURE 19906 _3DSTATE_CONSTANT_VS_VSConstantBuffer2ReadLength_bits(const struct gen_device_info *devinfo) 19907 { 19908 switch (devinfo->gen) { 19909 case 10: return 0; 19910 case 9: return 0; 19911 case 8: return 0; 19912 case 7: 19913 if (devinfo->is_haswell) { 19914 return 0; 19915 } else { 19916 return 0; 19917 } 19918 case 6: return 5; 19919 case 5: return 0; 19920 case 4: 19921 if (devinfo->is_g4x) { 19922 return 0; 19923 } else { 19924 return 0; 19925 } 19926 default: 19927 unreachable("Invalid hardware generation"); 19928 } 19929 } 19930 19931 19932 19933 #define GEN6_3DSTATE_CONSTANT_VS_VSConstantBuffer2ReadLength_start 96 19934 19935 static inline uint32_t ATTRIBUTE_PURE 19936 _3DSTATE_CONSTANT_VS_VSConstantBuffer2ReadLength_start(const struct gen_device_info *devinfo) 19937 { 19938 switch (devinfo->gen) { 19939 case 10: return 0; 19940 case 9: return 0; 19941 case 8: return 0; 19942 case 7: 19943 if (devinfo->is_haswell) { 19944 return 0; 19945 } else { 19946 return 0; 19947 } 19948 case 6: return 96; 19949 case 5: return 0; 19950 case 4: 19951 if (devinfo->is_g4x) { 19952 return 0; 19953 } else { 19954 return 0; 19955 } 19956 default: 19957 unreachable("Invalid hardware generation"); 19958 } 19959 } 19960 19961 19962 19963 /* 3DSTATE_CONSTANT_VS::VS Constant Buffer 3 Read Length */ 19964 19965 19966 #define GEN6_3DSTATE_CONSTANT_VS_VSConstantBuffer3ReadLength_bits 5 19967 19968 static inline uint32_t ATTRIBUTE_PURE 19969 _3DSTATE_CONSTANT_VS_VSConstantBuffer3ReadLength_bits(const struct gen_device_info *devinfo) 19970 { 19971 switch (devinfo->gen) { 19972 case 10: return 0; 19973 case 9: return 0; 19974 case 8: return 0; 19975 case 7: 19976 if (devinfo->is_haswell) { 19977 return 0; 19978 } else { 19979 return 0; 19980 } 19981 case 6: return 5; 19982 case 5: return 0; 19983 case 4: 19984 if (devinfo->is_g4x) { 19985 return 0; 19986 } else { 19987 return 0; 19988 } 19989 default: 19990 unreachable("Invalid hardware generation"); 19991 } 19992 } 19993 19994 19995 19996 #define GEN6_3DSTATE_CONSTANT_VS_VSConstantBuffer3ReadLength_start 128 19997 19998 static inline uint32_t ATTRIBUTE_PURE 19999 _3DSTATE_CONSTANT_VS_VSConstantBuffer3ReadLength_start(const struct gen_device_info *devinfo) 20000 { 20001 switch (devinfo->gen) { 20002 case 10: return 0; 20003 case 9: return 0; 20004 case 8: return 0; 20005 case 7: 20006 if (devinfo->is_haswell) { 20007 return 0; 20008 } else { 20009 return 0; 20010 } 20011 case 6: return 128; 20012 case 5: return 0; 20013 case 4: 20014 if (devinfo->is_g4x) { 20015 return 0; 20016 } else { 20017 return 0; 20018 } 20019 default: 20020 unreachable("Invalid hardware generation"); 20021 } 20022 } 20023 20024 20025 20026 /* 3DSTATE_DEPTH_BUFFER */ 20027 20028 20029 #define GEN10_3DSTATE_DEPTH_BUFFER_length 8 20030 #define GEN9_3DSTATE_DEPTH_BUFFER_length 8 20031 #define GEN8_3DSTATE_DEPTH_BUFFER_length 8 20032 #define GEN75_3DSTATE_DEPTH_BUFFER_length 7 20033 #define GEN7_3DSTATE_DEPTH_BUFFER_length 7 20034 #define GEN6_3DSTATE_DEPTH_BUFFER_length 7 20035 #define GEN5_3DSTATE_DEPTH_BUFFER_length 6 20036 #define GEN45_3DSTATE_DEPTH_BUFFER_length 6 20037 #define GEN4_3DSTATE_DEPTH_BUFFER_length 5 20038 20039 static inline uint32_t ATTRIBUTE_PURE 20040 _3DSTATE_DEPTH_BUFFER_length(const struct gen_device_info *devinfo) 20041 { 20042 switch (devinfo->gen) { 20043 case 10: return 8; 20044 case 9: return 8; 20045 case 8: return 8; 20046 case 7: 20047 if (devinfo->is_haswell) { 20048 return 7; 20049 } else { 20050 return 7; 20051 } 20052 case 6: return 7; 20053 case 5: return 6; 20054 case 4: 20055 if (devinfo->is_g4x) { 20056 return 6; 20057 } else { 20058 return 5; 20059 } 20060 default: 20061 unreachable("Invalid hardware generation"); 20062 } 20063 } 20064 20065 20066 20067 /* 3DSTATE_DEPTH_BUFFER::3D Command Opcode */ 20068 20069 20070 #define GEN10_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 20071 #define GEN9_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 20072 #define GEN8_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 20073 #define GEN75_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 20074 #define GEN7_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 20075 #define GEN6_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 20076 #define GEN5_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 20077 #define GEN45_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 20078 #define GEN4_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 20079 20080 static inline uint32_t ATTRIBUTE_PURE 20081 _3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 20082 { 20083 switch (devinfo->gen) { 20084 case 10: return 3; 20085 case 9: return 3; 20086 case 8: return 3; 20087 case 7: 20088 if (devinfo->is_haswell) { 20089 return 3; 20090 } else { 20091 return 3; 20092 } 20093 case 6: return 3; 20094 case 5: return 3; 20095 case 4: 20096 if (devinfo->is_g4x) { 20097 return 3; 20098 } else { 20099 return 3; 20100 } 20101 default: 20102 unreachable("Invalid hardware generation"); 20103 } 20104 } 20105 20106 20107 20108 #define GEN10_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 20109 #define GEN9_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 20110 #define GEN8_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 20111 #define GEN75_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 20112 #define GEN7_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 20113 #define GEN6_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 20114 #define GEN5_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 20115 #define GEN45_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 20116 #define GEN4_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 20117 20118 static inline uint32_t ATTRIBUTE_PURE 20119 _3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start(const struct gen_device_info *devinfo) 20120 { 20121 switch (devinfo->gen) { 20122 case 10: return 24; 20123 case 9: return 24; 20124 case 8: return 24; 20125 case 7: 20126 if (devinfo->is_haswell) { 20127 return 24; 20128 } else { 20129 return 24; 20130 } 20131 case 6: return 24; 20132 case 5: return 24; 20133 case 4: 20134 if (devinfo->is_g4x) { 20135 return 24; 20136 } else { 20137 return 24; 20138 } 20139 default: 20140 unreachable("Invalid hardware generation"); 20141 } 20142 } 20143 20144 20145 20146 /* 3DSTATE_DEPTH_BUFFER::3D Command Sub Opcode */ 20147 20148 20149 #define GEN10_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 20150 #define GEN9_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 20151 #define GEN8_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 20152 #define GEN75_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 20153 #define GEN7_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 20154 #define GEN6_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 20155 #define GEN5_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 20156 #define GEN45_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 20157 #define GEN4_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 20158 20159 static inline uint32_t ATTRIBUTE_PURE 20160 _3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 20161 { 20162 switch (devinfo->gen) { 20163 case 10: return 8; 20164 case 9: return 8; 20165 case 8: return 8; 20166 case 7: 20167 if (devinfo->is_haswell) { 20168 return 8; 20169 } else { 20170 return 8; 20171 } 20172 case 6: return 8; 20173 case 5: return 8; 20174 case 4: 20175 if (devinfo->is_g4x) { 20176 return 8; 20177 } else { 20178 return 8; 20179 } 20180 default: 20181 unreachable("Invalid hardware generation"); 20182 } 20183 } 20184 20185 20186 20187 #define GEN10_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 20188 #define GEN9_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 20189 #define GEN8_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 20190 #define GEN75_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 20191 #define GEN7_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 20192 #define GEN6_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 20193 #define GEN5_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 20194 #define GEN45_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 20195 #define GEN4_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 20196 20197 static inline uint32_t ATTRIBUTE_PURE 20198 _3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 20199 { 20200 switch (devinfo->gen) { 20201 case 10: return 16; 20202 case 9: return 16; 20203 case 8: return 16; 20204 case 7: 20205 if (devinfo->is_haswell) { 20206 return 16; 20207 } else { 20208 return 16; 20209 } 20210 case 6: return 16; 20211 case 5: return 16; 20212 case 4: 20213 if (devinfo->is_g4x) { 20214 return 16; 20215 } else { 20216 return 16; 20217 } 20218 default: 20219 unreachable("Invalid hardware generation"); 20220 } 20221 } 20222 20223 20224 20225 /* 3DSTATE_DEPTH_BUFFER::Command SubType */ 20226 20227 20228 #define GEN10_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 20229 #define GEN9_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 20230 #define GEN8_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 20231 #define GEN75_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 20232 #define GEN7_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 20233 #define GEN6_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 20234 #define GEN5_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 20235 #define GEN45_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 20236 #define GEN4_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 20237 20238 static inline uint32_t ATTRIBUTE_PURE 20239 _3DSTATE_DEPTH_BUFFER_CommandSubType_bits(const struct gen_device_info *devinfo) 20240 { 20241 switch (devinfo->gen) { 20242 case 10: return 2; 20243 case 9: return 2; 20244 case 8: return 2; 20245 case 7: 20246 if (devinfo->is_haswell) { 20247 return 2; 20248 } else { 20249 return 2; 20250 } 20251 case 6: return 2; 20252 case 5: return 2; 20253 case 4: 20254 if (devinfo->is_g4x) { 20255 return 2; 20256 } else { 20257 return 2; 20258 } 20259 default: 20260 unreachable("Invalid hardware generation"); 20261 } 20262 } 20263 20264 20265 20266 #define GEN10_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 20267 #define GEN9_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 20268 #define GEN8_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 20269 #define GEN75_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 20270 #define GEN7_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 20271 #define GEN6_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 20272 #define GEN5_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 20273 #define GEN45_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 20274 #define GEN4_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 20275 20276 static inline uint32_t ATTRIBUTE_PURE 20277 _3DSTATE_DEPTH_BUFFER_CommandSubType_start(const struct gen_device_info *devinfo) 20278 { 20279 switch (devinfo->gen) { 20280 case 10: return 27; 20281 case 9: return 27; 20282 case 8: return 27; 20283 case 7: 20284 if (devinfo->is_haswell) { 20285 return 27; 20286 } else { 20287 return 27; 20288 } 20289 case 6: return 27; 20290 case 5: return 27; 20291 case 4: 20292 if (devinfo->is_g4x) { 20293 return 27; 20294 } else { 20295 return 27; 20296 } 20297 default: 20298 unreachable("Invalid hardware generation"); 20299 } 20300 } 20301 20302 20303 20304 /* 3DSTATE_DEPTH_BUFFER::Command Type */ 20305 20306 20307 #define GEN10_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 20308 #define GEN9_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 20309 #define GEN8_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 20310 #define GEN75_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 20311 #define GEN7_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 20312 #define GEN6_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 20313 #define GEN5_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 20314 #define GEN45_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 20315 #define GEN4_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 20316 20317 static inline uint32_t ATTRIBUTE_PURE 20318 _3DSTATE_DEPTH_BUFFER_CommandType_bits(const struct gen_device_info *devinfo) 20319 { 20320 switch (devinfo->gen) { 20321 case 10: return 3; 20322 case 9: return 3; 20323 case 8: return 3; 20324 case 7: 20325 if (devinfo->is_haswell) { 20326 return 3; 20327 } else { 20328 return 3; 20329 } 20330 case 6: return 3; 20331 case 5: return 3; 20332 case 4: 20333 if (devinfo->is_g4x) { 20334 return 3; 20335 } else { 20336 return 3; 20337 } 20338 default: 20339 unreachable("Invalid hardware generation"); 20340 } 20341 } 20342 20343 20344 20345 #define GEN10_3DSTATE_DEPTH_BUFFER_CommandType_start 29 20346 #define GEN9_3DSTATE_DEPTH_BUFFER_CommandType_start 29 20347 #define GEN8_3DSTATE_DEPTH_BUFFER_CommandType_start 29 20348 #define GEN75_3DSTATE_DEPTH_BUFFER_CommandType_start 29 20349 #define GEN7_3DSTATE_DEPTH_BUFFER_CommandType_start 29 20350 #define GEN6_3DSTATE_DEPTH_BUFFER_CommandType_start 29 20351 #define GEN5_3DSTATE_DEPTH_BUFFER_CommandType_start 29 20352 #define GEN45_3DSTATE_DEPTH_BUFFER_CommandType_start 29 20353 #define GEN4_3DSTATE_DEPTH_BUFFER_CommandType_start 29 20354 20355 static inline uint32_t ATTRIBUTE_PURE 20356 _3DSTATE_DEPTH_BUFFER_CommandType_start(const struct gen_device_info *devinfo) 20357 { 20358 switch (devinfo->gen) { 20359 case 10: return 29; 20360 case 9: return 29; 20361 case 8: return 29; 20362 case 7: 20363 if (devinfo->is_haswell) { 20364 return 29; 20365 } else { 20366 return 29; 20367 } 20368 case 6: return 29; 20369 case 5: return 29; 20370 case 4: 20371 if (devinfo->is_g4x) { 20372 return 29; 20373 } else { 20374 return 29; 20375 } 20376 default: 20377 unreachable("Invalid hardware generation"); 20378 } 20379 } 20380 20381 20382 20383 /* 3DSTATE_DEPTH_BUFFER::DWord Length */ 20384 20385 20386 #define GEN10_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 20387 #define GEN9_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 20388 #define GEN8_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 20389 #define GEN75_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 20390 #define GEN7_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 20391 #define GEN6_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 20392 #define GEN5_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 20393 #define GEN45_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 20394 #define GEN4_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 20395 20396 static inline uint32_t ATTRIBUTE_PURE 20397 _3DSTATE_DEPTH_BUFFER_DWordLength_bits(const struct gen_device_info *devinfo) 20398 { 20399 switch (devinfo->gen) { 20400 case 10: return 8; 20401 case 9: return 8; 20402 case 8: return 8; 20403 case 7: 20404 if (devinfo->is_haswell) { 20405 return 8; 20406 } else { 20407 return 8; 20408 } 20409 case 6: return 8; 20410 case 5: return 8; 20411 case 4: 20412 if (devinfo->is_g4x) { 20413 return 8; 20414 } else { 20415 return 8; 20416 } 20417 default: 20418 unreachable("Invalid hardware generation"); 20419 } 20420 } 20421 20422 20423 20424 #define GEN10_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 20425 #define GEN9_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 20426 #define GEN8_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 20427 #define GEN75_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 20428 #define GEN7_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 20429 #define GEN6_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 20430 #define GEN5_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 20431 #define GEN45_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 20432 #define GEN4_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 20433 20434 static inline uint32_t ATTRIBUTE_PURE 20435 _3DSTATE_DEPTH_BUFFER_DWordLength_start(const struct gen_device_info *devinfo) 20436 { 20437 switch (devinfo->gen) { 20438 case 10: return 0; 20439 case 9: return 0; 20440 case 8: return 0; 20441 case 7: 20442 if (devinfo->is_haswell) { 20443 return 0; 20444 } else { 20445 return 0; 20446 } 20447 case 6: return 0; 20448 case 5: return 0; 20449 case 4: 20450 if (devinfo->is_g4x) { 20451 return 0; 20452 } else { 20453 return 0; 20454 } 20455 default: 20456 unreachable("Invalid hardware generation"); 20457 } 20458 } 20459 20460 20461 20462 /* 3DSTATE_DEPTH_BUFFER::Depth */ 20463 20464 20465 #define GEN10_3DSTATE_DEPTH_BUFFER_Depth_bits 11 20466 #define GEN9_3DSTATE_DEPTH_BUFFER_Depth_bits 11 20467 #define GEN8_3DSTATE_DEPTH_BUFFER_Depth_bits 11 20468 #define GEN75_3DSTATE_DEPTH_BUFFER_Depth_bits 11 20469 #define GEN7_3DSTATE_DEPTH_BUFFER_Depth_bits 11 20470 #define GEN6_3DSTATE_DEPTH_BUFFER_Depth_bits 11 20471 #define GEN5_3DSTATE_DEPTH_BUFFER_Depth_bits 11 20472 #define GEN45_3DSTATE_DEPTH_BUFFER_Depth_bits 11 20473 #define GEN4_3DSTATE_DEPTH_BUFFER_Depth_bits 11 20474 20475 static inline uint32_t ATTRIBUTE_PURE 20476 _3DSTATE_DEPTH_BUFFER_Depth_bits(const struct gen_device_info *devinfo) 20477 { 20478 switch (devinfo->gen) { 20479 case 10: return 11; 20480 case 9: return 11; 20481 case 8: return 11; 20482 case 7: 20483 if (devinfo->is_haswell) { 20484 return 11; 20485 } else { 20486 return 11; 20487 } 20488 case 6: return 11; 20489 case 5: return 11; 20490 case 4: 20491 if (devinfo->is_g4x) { 20492 return 11; 20493 } else { 20494 return 11; 20495 } 20496 default: 20497 unreachable("Invalid hardware generation"); 20498 } 20499 } 20500 20501 20502 20503 #define GEN10_3DSTATE_DEPTH_BUFFER_Depth_start 181 20504 #define GEN9_3DSTATE_DEPTH_BUFFER_Depth_start 181 20505 #define GEN8_3DSTATE_DEPTH_BUFFER_Depth_start 181 20506 #define GEN75_3DSTATE_DEPTH_BUFFER_Depth_start 149 20507 #define GEN7_3DSTATE_DEPTH_BUFFER_Depth_start 149 20508 #define GEN6_3DSTATE_DEPTH_BUFFER_Depth_start 149 20509 #define GEN5_3DSTATE_DEPTH_BUFFER_Depth_start 149 20510 #define GEN45_3DSTATE_DEPTH_BUFFER_Depth_start 149 20511 #define GEN4_3DSTATE_DEPTH_BUFFER_Depth_start 149 20512 20513 static inline uint32_t ATTRIBUTE_PURE 20514 _3DSTATE_DEPTH_BUFFER_Depth_start(const struct gen_device_info *devinfo) 20515 { 20516 switch (devinfo->gen) { 20517 case 10: return 181; 20518 case 9: return 181; 20519 case 8: return 181; 20520 case 7: 20521 if (devinfo->is_haswell) { 20522 return 149; 20523 } else { 20524 return 149; 20525 } 20526 case 6: return 149; 20527 case 5: return 149; 20528 case 4: 20529 if (devinfo->is_g4x) { 20530 return 149; 20531 } else { 20532 return 149; 20533 } 20534 default: 20535 unreachable("Invalid hardware generation"); 20536 } 20537 } 20538 20539 20540 20541 /* 3DSTATE_DEPTH_BUFFER::Depth Buffer Coordinate Offset Disable */ 20542 20543 20544 #define GEN45_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_bits 1 20545 #define GEN4_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_bits 1 20546 20547 static inline uint32_t ATTRIBUTE_PURE 20548 _3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_bits(const struct gen_device_info *devinfo) 20549 { 20550 switch (devinfo->gen) { 20551 case 10: return 0; 20552 case 9: return 0; 20553 case 8: return 0; 20554 case 7: 20555 if (devinfo->is_haswell) { 20556 return 0; 20557 } else { 20558 return 0; 20559 } 20560 case 6: return 0; 20561 case 5: return 0; 20562 case 4: 20563 if (devinfo->is_g4x) { 20564 return 1; 20565 } else { 20566 return 1; 20567 } 20568 default: 20569 unreachable("Invalid hardware generation"); 20570 } 20571 } 20572 20573 20574 20575 #define GEN45_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_start 57 20576 #define GEN4_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_start 57 20577 20578 static inline uint32_t ATTRIBUTE_PURE 20579 _3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_start(const struct gen_device_info *devinfo) 20580 { 20581 switch (devinfo->gen) { 20582 case 10: return 0; 20583 case 9: return 0; 20584 case 8: return 0; 20585 case 7: 20586 if (devinfo->is_haswell) { 20587 return 0; 20588 } else { 20589 return 0; 20590 } 20591 case 6: return 0; 20592 case 5: return 0; 20593 case 4: 20594 if (devinfo->is_g4x) { 20595 return 57; 20596 } else { 20597 return 57; 20598 } 20599 default: 20600 unreachable("Invalid hardware generation"); 20601 } 20602 } 20603 20604 20605 20606 /* 3DSTATE_DEPTH_BUFFER::Depth Buffer MOCS */ 20607 20608 20609 #define GEN10_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 7 20610 #define GEN9_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 7 20611 #define GEN8_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 7 20612 #define GEN75_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 4 20613 #define GEN7_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 4 20614 #define GEN6_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 5 20615 20616 static inline uint32_t ATTRIBUTE_PURE 20617 _3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits(const struct gen_device_info *devinfo) 20618 { 20619 switch (devinfo->gen) { 20620 case 10: return 7; 20621 case 9: return 7; 20622 case 8: return 7; 20623 case 7: 20624 if (devinfo->is_haswell) { 20625 return 4; 20626 } else { 20627 return 4; 20628 } 20629 case 6: return 5; 20630 case 5: return 0; 20631 case 4: 20632 if (devinfo->is_g4x) { 20633 return 0; 20634 } else { 20635 return 0; 20636 } 20637 default: 20638 unreachable("Invalid hardware generation"); 20639 } 20640 } 20641 20642 20643 20644 #define GEN10_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 160 20645 #define GEN9_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 160 20646 #define GEN8_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 160 20647 #define GEN75_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 128 20648 #define GEN7_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 128 20649 #define GEN6_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 219 20650 20651 static inline uint32_t ATTRIBUTE_PURE 20652 _3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start(const struct gen_device_info *devinfo) 20653 { 20654 switch (devinfo->gen) { 20655 case 10: return 160; 20656 case 9: return 160; 20657 case 8: return 160; 20658 case 7: 20659 if (devinfo->is_haswell) { 20660 return 128; 20661 } else { 20662 return 128; 20663 } 20664 case 6: return 219; 20665 case 5: return 0; 20666 case 4: 20667 if (devinfo->is_g4x) { 20668 return 0; 20669 } else { 20670 return 0; 20671 } 20672 default: 20673 unreachable("Invalid hardware generation"); 20674 } 20675 } 20676 20677 20678 20679 /* 3DSTATE_DEPTH_BUFFER::Depth Buffer Object Control State */ 20680 20681 20682 #define GEN10_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 7 20683 #define GEN9_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 7 20684 #define GEN8_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 7 20685 #define GEN75_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 4 20686 #define GEN7_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 4 20687 #define GEN6_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 5 20688 20689 static inline uint32_t ATTRIBUTE_PURE 20690 _3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits(const struct gen_device_info *devinfo) 20691 { 20692 switch (devinfo->gen) { 20693 case 10: return 7; 20694 case 9: return 7; 20695 case 8: return 7; 20696 case 7: 20697 if (devinfo->is_haswell) { 20698 return 4; 20699 } else { 20700 return 4; 20701 } 20702 case 6: return 5; 20703 case 5: return 0; 20704 case 4: 20705 if (devinfo->is_g4x) { 20706 return 0; 20707 } else { 20708 return 0; 20709 } 20710 default: 20711 unreachable("Invalid hardware generation"); 20712 } 20713 } 20714 20715 20716 20717 #define GEN10_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 160 20718 #define GEN9_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 160 20719 #define GEN8_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 160 20720 #define GEN75_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 128 20721 #define GEN7_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 128 20722 #define GEN6_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 219 20723 20724 static inline uint32_t ATTRIBUTE_PURE 20725 _3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start(const struct gen_device_info *devinfo) 20726 { 20727 switch (devinfo->gen) { 20728 case 10: return 160; 20729 case 9: return 160; 20730 case 8: return 160; 20731 case 7: 20732 if (devinfo->is_haswell) { 20733 return 128; 20734 } else { 20735 return 128; 20736 } 20737 case 6: return 219; 20738 case 5: return 0; 20739 case 4: 20740 if (devinfo->is_g4x) { 20741 return 0; 20742 } else { 20743 return 0; 20744 } 20745 default: 20746 unreachable("Invalid hardware generation"); 20747 } 20748 } 20749 20750 20751 20752 /* 3DSTATE_DEPTH_BUFFER::Depth Coordinate Offset X */ 20753 20754 20755 #define GEN75_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 20756 #define GEN7_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 20757 #define GEN6_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 20758 #define GEN5_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 20759 #define GEN45_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 20760 20761 static inline uint32_t ATTRIBUTE_PURE 20762 _3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits(const struct gen_device_info *devinfo) 20763 { 20764 switch (devinfo->gen) { 20765 case 10: return 0; 20766 case 9: return 0; 20767 case 8: return 0; 20768 case 7: 20769 if (devinfo->is_haswell) { 20770 return 16; 20771 } else { 20772 return 16; 20773 } 20774 case 6: return 16; 20775 case 5: return 16; 20776 case 4: 20777 if (devinfo->is_g4x) { 20778 return 16; 20779 } else { 20780 return 0; 20781 } 20782 default: 20783 unreachable("Invalid hardware generation"); 20784 } 20785 } 20786 20787 20788 20789 #define GEN75_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 20790 #define GEN7_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 20791 #define GEN6_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 20792 #define GEN5_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 20793 #define GEN45_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 20794 20795 static inline uint32_t ATTRIBUTE_PURE 20796 _3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start(const struct gen_device_info *devinfo) 20797 { 20798 switch (devinfo->gen) { 20799 case 10: return 0; 20800 case 9: return 0; 20801 case 8: return 0; 20802 case 7: 20803 if (devinfo->is_haswell) { 20804 return 160; 20805 } else { 20806 return 160; 20807 } 20808 case 6: return 160; 20809 case 5: return 160; 20810 case 4: 20811 if (devinfo->is_g4x) { 20812 return 160; 20813 } else { 20814 return 0; 20815 } 20816 default: 20817 unreachable("Invalid hardware generation"); 20818 } 20819 } 20820 20821 20822 20823 /* 3DSTATE_DEPTH_BUFFER::Depth Coordinate Offset Y */ 20824 20825 20826 #define GEN75_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 20827 #define GEN7_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 20828 #define GEN6_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 20829 #define GEN5_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 20830 #define GEN45_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 20831 20832 static inline uint32_t ATTRIBUTE_PURE 20833 _3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits(const struct gen_device_info *devinfo) 20834 { 20835 switch (devinfo->gen) { 20836 case 10: return 0; 20837 case 9: return 0; 20838 case 8: return 0; 20839 case 7: 20840 if (devinfo->is_haswell) { 20841 return 16; 20842 } else { 20843 return 16; 20844 } 20845 case 6: return 16; 20846 case 5: return 16; 20847 case 4: 20848 if (devinfo->is_g4x) { 20849 return 16; 20850 } else { 20851 return 0; 20852 } 20853 default: 20854 unreachable("Invalid hardware generation"); 20855 } 20856 } 20857 20858 20859 20860 #define GEN75_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 20861 #define GEN7_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 20862 #define GEN6_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 20863 #define GEN5_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 20864 #define GEN45_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 20865 20866 static inline uint32_t ATTRIBUTE_PURE 20867 _3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start(const struct gen_device_info *devinfo) 20868 { 20869 switch (devinfo->gen) { 20870 case 10: return 0; 20871 case 9: return 0; 20872 case 8: return 0; 20873 case 7: 20874 if (devinfo->is_haswell) { 20875 return 176; 20876 } else { 20877 return 176; 20878 } 20879 case 6: return 176; 20880 case 5: return 176; 20881 case 4: 20882 if (devinfo->is_g4x) { 20883 return 176; 20884 } else { 20885 return 0; 20886 } 20887 default: 20888 unreachable("Invalid hardware generation"); 20889 } 20890 } 20891 20892 20893 20894 /* 3DSTATE_DEPTH_BUFFER::Depth Write Enable */ 20895 20896 20897 #define GEN10_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 20898 #define GEN9_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 20899 #define GEN8_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 20900 #define GEN75_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 20901 #define GEN7_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 20902 20903 static inline uint32_t ATTRIBUTE_PURE 20904 _3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits(const struct gen_device_info *devinfo) 20905 { 20906 switch (devinfo->gen) { 20907 case 10: return 1; 20908 case 9: return 1; 20909 case 8: return 1; 20910 case 7: 20911 if (devinfo->is_haswell) { 20912 return 1; 20913 } else { 20914 return 1; 20915 } 20916 case 6: return 0; 20917 case 5: return 0; 20918 case 4: 20919 if (devinfo->is_g4x) { 20920 return 0; 20921 } else { 20922 return 0; 20923 } 20924 default: 20925 unreachable("Invalid hardware generation"); 20926 } 20927 } 20928 20929 20930 20931 #define GEN10_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 20932 #define GEN9_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 20933 #define GEN8_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 20934 #define GEN75_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 20935 #define GEN7_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 20936 20937 static inline uint32_t ATTRIBUTE_PURE 20938 _3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start(const struct gen_device_info *devinfo) 20939 { 20940 switch (devinfo->gen) { 20941 case 10: return 60; 20942 case 9: return 60; 20943 case 8: return 60; 20944 case 7: 20945 if (devinfo->is_haswell) { 20946 return 60; 20947 } else { 20948 return 60; 20949 } 20950 case 6: return 0; 20951 case 5: return 0; 20952 case 4: 20953 if (devinfo->is_g4x) { 20954 return 0; 20955 } else { 20956 return 0; 20957 } 20958 default: 20959 unreachable("Invalid hardware generation"); 20960 } 20961 } 20962 20963 20964 20965 /* 3DSTATE_DEPTH_BUFFER::Height */ 20966 20967 20968 #define GEN10_3DSTATE_DEPTH_BUFFER_Height_bits 14 20969 #define GEN9_3DSTATE_DEPTH_BUFFER_Height_bits 14 20970 #define GEN8_3DSTATE_DEPTH_BUFFER_Height_bits 14 20971 #define GEN75_3DSTATE_DEPTH_BUFFER_Height_bits 14 20972 #define GEN7_3DSTATE_DEPTH_BUFFER_Height_bits 14 20973 #define GEN6_3DSTATE_DEPTH_BUFFER_Height_bits 13 20974 #define GEN5_3DSTATE_DEPTH_BUFFER_Height_bits 13 20975 #define GEN45_3DSTATE_DEPTH_BUFFER_Height_bits 13 20976 #define GEN4_3DSTATE_DEPTH_BUFFER_Height_bits 13 20977 20978 static inline uint32_t ATTRIBUTE_PURE 20979 _3DSTATE_DEPTH_BUFFER_Height_bits(const struct gen_device_info *devinfo) 20980 { 20981 switch (devinfo->gen) { 20982 case 10: return 14; 20983 case 9: return 14; 20984 case 8: return 14; 20985 case 7: 20986 if (devinfo->is_haswell) { 20987 return 14; 20988 } else { 20989 return 14; 20990 } 20991 case 6: return 13; 20992 case 5: return 13; 20993 case 4: 20994 if (devinfo->is_g4x) { 20995 return 13; 20996 } else { 20997 return 13; 20998 } 20999 default: 21000 unreachable("Invalid hardware generation"); 21001 } 21002 } 21003 21004 21005 21006 #define GEN10_3DSTATE_DEPTH_BUFFER_Height_start 146 21007 #define GEN9_3DSTATE_DEPTH_BUFFER_Height_start 146 21008 #define GEN8_3DSTATE_DEPTH_BUFFER_Height_start 146 21009 #define GEN75_3DSTATE_DEPTH_BUFFER_Height_start 114 21010 #define GEN7_3DSTATE_DEPTH_BUFFER_Height_start 114 21011 #define GEN6_3DSTATE_DEPTH_BUFFER_Height_start 115 21012 #define GEN5_3DSTATE_DEPTH_BUFFER_Height_start 115 21013 #define GEN45_3DSTATE_DEPTH_BUFFER_Height_start 115 21014 #define GEN4_3DSTATE_DEPTH_BUFFER_Height_start 115 21015 21016 static inline uint32_t ATTRIBUTE_PURE 21017 _3DSTATE_DEPTH_BUFFER_Height_start(const struct gen_device_info *devinfo) 21018 { 21019 switch (devinfo->gen) { 21020 case 10: return 146; 21021 case 9: return 146; 21022 case 8: return 146; 21023 case 7: 21024 if (devinfo->is_haswell) { 21025 return 114; 21026 } else { 21027 return 114; 21028 } 21029 case 6: return 115; 21030 case 5: return 115; 21031 case 4: 21032 if (devinfo->is_g4x) { 21033 return 115; 21034 } else { 21035 return 115; 21036 } 21037 default: 21038 unreachable("Invalid hardware generation"); 21039 } 21040 } 21041 21042 21043 21044 /* 3DSTATE_DEPTH_BUFFER::Hierarchical Depth Buffer Enable */ 21045 21046 21047 #define GEN10_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 21048 #define GEN9_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 21049 #define GEN8_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 21050 #define GEN75_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 21051 #define GEN7_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 21052 #define GEN6_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 21053 #define GEN5_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 21054 21055 static inline uint32_t ATTRIBUTE_PURE 21056 _3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits(const struct gen_device_info *devinfo) 21057 { 21058 switch (devinfo->gen) { 21059 case 10: return 1; 21060 case 9: return 1; 21061 case 8: return 1; 21062 case 7: 21063 if (devinfo->is_haswell) { 21064 return 1; 21065 } else { 21066 return 1; 21067 } 21068 case 6: return 1; 21069 case 5: return 1; 21070 case 4: 21071 if (devinfo->is_g4x) { 21072 return 0; 21073 } else { 21074 return 0; 21075 } 21076 default: 21077 unreachable("Invalid hardware generation"); 21078 } 21079 } 21080 21081 21082 21083 #define GEN10_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 21084 #define GEN9_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 21085 #define GEN8_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 21086 #define GEN75_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 21087 #define GEN7_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 21088 #define GEN6_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 21089 #define GEN5_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 21090 21091 static inline uint32_t ATTRIBUTE_PURE 21092 _3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start(const struct gen_device_info *devinfo) 21093 { 21094 switch (devinfo->gen) { 21095 case 10: return 54; 21096 case 9: return 54; 21097 case 8: return 54; 21098 case 7: 21099 if (devinfo->is_haswell) { 21100 return 54; 21101 } else { 21102 return 54; 21103 } 21104 case 6: return 54; 21105 case 5: return 54; 21106 case 4: 21107 if (devinfo->is_g4x) { 21108 return 0; 21109 } else { 21110 return 0; 21111 } 21112 default: 21113 unreachable("Invalid hardware generation"); 21114 } 21115 } 21116 21117 21118 21119 /* 3DSTATE_DEPTH_BUFFER::LOD */ 21120 21121 21122 #define GEN10_3DSTATE_DEPTH_BUFFER_LOD_bits 4 21123 #define GEN9_3DSTATE_DEPTH_BUFFER_LOD_bits 4 21124 #define GEN8_3DSTATE_DEPTH_BUFFER_LOD_bits 4 21125 #define GEN75_3DSTATE_DEPTH_BUFFER_LOD_bits 4 21126 #define GEN7_3DSTATE_DEPTH_BUFFER_LOD_bits 4 21127 #define GEN6_3DSTATE_DEPTH_BUFFER_LOD_bits 4 21128 #define GEN5_3DSTATE_DEPTH_BUFFER_LOD_bits 4 21129 #define GEN45_3DSTATE_DEPTH_BUFFER_LOD_bits 4 21130 #define GEN4_3DSTATE_DEPTH_BUFFER_LOD_bits 4 21131 21132 static inline uint32_t ATTRIBUTE_PURE 21133 _3DSTATE_DEPTH_BUFFER_LOD_bits(const struct gen_device_info *devinfo) 21134 { 21135 switch (devinfo->gen) { 21136 case 10: return 4; 21137 case 9: return 4; 21138 case 8: return 4; 21139 case 7: 21140 if (devinfo->is_haswell) { 21141 return 4; 21142 } else { 21143 return 4; 21144 } 21145 case 6: return 4; 21146 case 5: return 4; 21147 case 4: 21148 if (devinfo->is_g4x) { 21149 return 4; 21150 } else { 21151 return 4; 21152 } 21153 default: 21154 unreachable("Invalid hardware generation"); 21155 } 21156 } 21157 21158 21159 21160 #define GEN10_3DSTATE_DEPTH_BUFFER_LOD_start 128 21161 #define GEN9_3DSTATE_DEPTH_BUFFER_LOD_start 128 21162 #define GEN8_3DSTATE_DEPTH_BUFFER_LOD_start 128 21163 #define GEN75_3DSTATE_DEPTH_BUFFER_LOD_start 96 21164 #define GEN7_3DSTATE_DEPTH_BUFFER_LOD_start 96 21165 #define GEN6_3DSTATE_DEPTH_BUFFER_LOD_start 98 21166 #define GEN5_3DSTATE_DEPTH_BUFFER_LOD_start 98 21167 #define GEN45_3DSTATE_DEPTH_BUFFER_LOD_start 98 21168 #define GEN4_3DSTATE_DEPTH_BUFFER_LOD_start 98 21169 21170 static inline uint32_t ATTRIBUTE_PURE 21171 _3DSTATE_DEPTH_BUFFER_LOD_start(const struct gen_device_info *devinfo) 21172 { 21173 switch (devinfo->gen) { 21174 case 10: return 128; 21175 case 9: return 128; 21176 case 8: return 128; 21177 case 7: 21178 if (devinfo->is_haswell) { 21179 return 96; 21180 } else { 21181 return 96; 21182 } 21183 case 6: return 98; 21184 case 5: return 98; 21185 case 4: 21186 if (devinfo->is_g4x) { 21187 return 98; 21188 } else { 21189 return 98; 21190 } 21191 default: 21192 unreachable("Invalid hardware generation"); 21193 } 21194 } 21195 21196 21197 21198 /* 3DSTATE_DEPTH_BUFFER::MIP Map Layout Mode */ 21199 21200 21201 #define GEN6_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits 1 21202 #define GEN5_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits 1 21203 #define GEN45_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits 1 21204 #define GEN4_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits 1 21205 21206 static inline uint32_t ATTRIBUTE_PURE 21207 _3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits(const struct gen_device_info *devinfo) 21208 { 21209 switch (devinfo->gen) { 21210 case 10: return 0; 21211 case 9: return 0; 21212 case 8: return 0; 21213 case 7: 21214 if (devinfo->is_haswell) { 21215 return 0; 21216 } else { 21217 return 0; 21218 } 21219 case 6: return 1; 21220 case 5: return 1; 21221 case 4: 21222 if (devinfo->is_g4x) { 21223 return 1; 21224 } else { 21225 return 1; 21226 } 21227 default: 21228 unreachable("Invalid hardware generation"); 21229 } 21230 } 21231 21232 21233 21234 #define GEN6_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start 97 21235 #define GEN5_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start 97 21236 #define GEN45_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start 97 21237 #define GEN4_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start 97 21238 21239 static inline uint32_t ATTRIBUTE_PURE 21240 _3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start(const struct gen_device_info *devinfo) 21241 { 21242 switch (devinfo->gen) { 21243 case 10: return 0; 21244 case 9: return 0; 21245 case 8: return 0; 21246 case 7: 21247 if (devinfo->is_haswell) { 21248 return 0; 21249 } else { 21250 return 0; 21251 } 21252 case 6: return 97; 21253 case 5: return 97; 21254 case 4: 21255 if (devinfo->is_g4x) { 21256 return 97; 21257 } else { 21258 return 97; 21259 } 21260 default: 21261 unreachable("Invalid hardware generation"); 21262 } 21263 } 21264 21265 21266 21267 /* 3DSTATE_DEPTH_BUFFER::Minimum Array Element */ 21268 21269 21270 #define GEN10_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 21271 #define GEN9_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 21272 #define GEN8_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 21273 #define GEN75_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 21274 #define GEN7_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 21275 #define GEN6_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 21276 #define GEN5_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 21277 #define GEN45_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 21278 #define GEN4_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 21279 21280 static inline uint32_t ATTRIBUTE_PURE 21281 _3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits(const struct gen_device_info *devinfo) 21282 { 21283 switch (devinfo->gen) { 21284 case 10: return 11; 21285 case 9: return 11; 21286 case 8: return 11; 21287 case 7: 21288 if (devinfo->is_haswell) { 21289 return 11; 21290 } else { 21291 return 11; 21292 } 21293 case 6: return 11; 21294 case 5: return 11; 21295 case 4: 21296 if (devinfo->is_g4x) { 21297 return 11; 21298 } else { 21299 return 11; 21300 } 21301 default: 21302 unreachable("Invalid hardware generation"); 21303 } 21304 } 21305 21306 21307 21308 #define GEN10_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 170 21309 #define GEN9_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 170 21310 #define GEN8_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 170 21311 #define GEN75_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 21312 #define GEN7_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 21313 #define GEN6_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 21314 #define GEN5_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 21315 #define GEN45_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 21316 #define GEN4_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 21317 21318 static inline uint32_t ATTRIBUTE_PURE 21319 _3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start(const struct gen_device_info *devinfo) 21320 { 21321 switch (devinfo->gen) { 21322 case 10: return 170; 21323 case 9: return 170; 21324 case 8: return 170; 21325 case 7: 21326 if (devinfo->is_haswell) { 21327 return 138; 21328 } else { 21329 return 138; 21330 } 21331 case 6: return 138; 21332 case 5: return 138; 21333 case 4: 21334 if (devinfo->is_g4x) { 21335 return 138; 21336 } else { 21337 return 138; 21338 } 21339 default: 21340 unreachable("Invalid hardware generation"); 21341 } 21342 } 21343 21344 21345 21346 /* 3DSTATE_DEPTH_BUFFER::Mip Tail Start LOD */ 21347 21348 21349 #define GEN10_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_bits 4 21350 #define GEN9_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_bits 4 21351 21352 static inline uint32_t ATTRIBUTE_PURE 21353 _3DSTATE_DEPTH_BUFFER_MipTailStartLOD_bits(const struct gen_device_info *devinfo) 21354 { 21355 switch (devinfo->gen) { 21356 case 10: return 4; 21357 case 9: return 4; 21358 case 8: return 0; 21359 case 7: 21360 if (devinfo->is_haswell) { 21361 return 0; 21362 } else { 21363 return 0; 21364 } 21365 case 6: return 0; 21366 case 5: return 0; 21367 case 4: 21368 if (devinfo->is_g4x) { 21369 return 0; 21370 } else { 21371 return 0; 21372 } 21373 default: 21374 unreachable("Invalid hardware generation"); 21375 } 21376 } 21377 21378 21379 21380 #define GEN10_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_start 218 21381 #define GEN9_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_start 218 21382 21383 static inline uint32_t ATTRIBUTE_PURE 21384 _3DSTATE_DEPTH_BUFFER_MipTailStartLOD_start(const struct gen_device_info *devinfo) 21385 { 21386 switch (devinfo->gen) { 21387 case 10: return 218; 21388 case 9: return 218; 21389 case 8: return 0; 21390 case 7: 21391 if (devinfo->is_haswell) { 21392 return 0; 21393 } else { 21394 return 0; 21395 } 21396 case 6: return 0; 21397 case 5: return 0; 21398 case 4: 21399 if (devinfo->is_g4x) { 21400 return 0; 21401 } else { 21402 return 0; 21403 } 21404 default: 21405 unreachable("Invalid hardware generation"); 21406 } 21407 } 21408 21409 21410 21411 /* 3DSTATE_DEPTH_BUFFER::Render Target View Extent */ 21412 21413 21414 #define GEN10_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 21415 #define GEN9_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 21416 #define GEN8_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 21417 #define GEN75_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 21418 #define GEN7_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 21419 #define GEN6_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 9 21420 #define GEN5_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 9 21421 #define GEN45_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 9 21422 #define GEN4_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 9 21423 21424 static inline uint32_t ATTRIBUTE_PURE 21425 _3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits(const struct gen_device_info *devinfo) 21426 { 21427 switch (devinfo->gen) { 21428 case 10: return 11; 21429 case 9: return 11; 21430 case 8: return 11; 21431 case 7: 21432 if (devinfo->is_haswell) { 21433 return 11; 21434 } else { 21435 return 11; 21436 } 21437 case 6: return 9; 21438 case 5: return 9; 21439 case 4: 21440 if (devinfo->is_g4x) { 21441 return 9; 21442 } else { 21443 return 9; 21444 } 21445 default: 21446 unreachable("Invalid hardware generation"); 21447 } 21448 } 21449 21450 21451 21452 #define GEN10_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 245 21453 #define GEN9_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 245 21454 #define GEN8_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 245 21455 #define GEN75_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 213 21456 #define GEN7_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 213 21457 #define GEN6_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 129 21458 #define GEN5_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 129 21459 #define GEN45_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 129 21460 #define GEN4_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 129 21461 21462 static inline uint32_t ATTRIBUTE_PURE 21463 _3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start(const struct gen_device_info *devinfo) 21464 { 21465 switch (devinfo->gen) { 21466 case 10: return 245; 21467 case 9: return 245; 21468 case 8: return 245; 21469 case 7: 21470 if (devinfo->is_haswell) { 21471 return 213; 21472 } else { 21473 return 213; 21474 } 21475 case 6: return 129; 21476 case 5: return 129; 21477 case 4: 21478 if (devinfo->is_g4x) { 21479 return 129; 21480 } else { 21481 return 129; 21482 } 21483 default: 21484 unreachable("Invalid hardware generation"); 21485 } 21486 } 21487 21488 21489 21490 /* 3DSTATE_DEPTH_BUFFER::Separate Stencil Buffer Enable */ 21491 21492 21493 #define GEN6_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_bits 1 21494 #define GEN5_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_bits 1 21495 21496 static inline uint32_t ATTRIBUTE_PURE 21497 _3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_bits(const struct gen_device_info *devinfo) 21498 { 21499 switch (devinfo->gen) { 21500 case 10: return 0; 21501 case 9: return 0; 21502 case 8: return 0; 21503 case 7: 21504 if (devinfo->is_haswell) { 21505 return 0; 21506 } else { 21507 return 0; 21508 } 21509 case 6: return 1; 21510 case 5: return 1; 21511 case 4: 21512 if (devinfo->is_g4x) { 21513 return 0; 21514 } else { 21515 return 0; 21516 } 21517 default: 21518 unreachable("Invalid hardware generation"); 21519 } 21520 } 21521 21522 21523 21524 #define GEN6_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_start 53 21525 #define GEN5_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_start 53 21526 21527 static inline uint32_t ATTRIBUTE_PURE 21528 _3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_start(const struct gen_device_info *devinfo) 21529 { 21530 switch (devinfo->gen) { 21531 case 10: return 0; 21532 case 9: return 0; 21533 case 8: return 0; 21534 case 7: 21535 if (devinfo->is_haswell) { 21536 return 0; 21537 } else { 21538 return 0; 21539 } 21540 case 6: return 53; 21541 case 5: return 53; 21542 case 4: 21543 if (devinfo->is_g4x) { 21544 return 0; 21545 } else { 21546 return 0; 21547 } 21548 default: 21549 unreachable("Invalid hardware generation"); 21550 } 21551 } 21552 21553 21554 21555 /* 3DSTATE_DEPTH_BUFFER::Software Tiled Rendering Mode */ 21556 21557 21558 #define GEN6_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits 2 21559 #define GEN5_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits 2 21560 #define GEN45_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits 2 21561 #define GEN4_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits 2 21562 21563 static inline uint32_t ATTRIBUTE_PURE 21564 _3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits(const struct gen_device_info *devinfo) 21565 { 21566 switch (devinfo->gen) { 21567 case 10: return 0; 21568 case 9: return 0; 21569 case 8: return 0; 21570 case 7: 21571 if (devinfo->is_haswell) { 21572 return 0; 21573 } else { 21574 return 0; 21575 } 21576 case 6: return 2; 21577 case 5: return 2; 21578 case 4: 21579 if (devinfo->is_g4x) { 21580 return 2; 21581 } else { 21582 return 2; 21583 } 21584 default: 21585 unreachable("Invalid hardware generation"); 21586 } 21587 } 21588 21589 21590 21591 #define GEN6_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start 55 21592 #define GEN5_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start 55 21593 #define GEN45_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start 55 21594 #define GEN4_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start 55 21595 21596 static inline uint32_t ATTRIBUTE_PURE 21597 _3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start(const struct gen_device_info *devinfo) 21598 { 21599 switch (devinfo->gen) { 21600 case 10: return 0; 21601 case 9: return 0; 21602 case 8: return 0; 21603 case 7: 21604 if (devinfo->is_haswell) { 21605 return 0; 21606 } else { 21607 return 0; 21608 } 21609 case 6: return 55; 21610 case 5: return 55; 21611 case 4: 21612 if (devinfo->is_g4x) { 21613 return 55; 21614 } else { 21615 return 55; 21616 } 21617 default: 21618 unreachable("Invalid hardware generation"); 21619 } 21620 } 21621 21622 21623 21624 /* 3DSTATE_DEPTH_BUFFER::Stencil Write Enable */ 21625 21626 21627 #define GEN10_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 21628 #define GEN9_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 21629 #define GEN8_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 21630 #define GEN75_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 21631 #define GEN7_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 21632 21633 static inline uint32_t ATTRIBUTE_PURE 21634 _3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits(const struct gen_device_info *devinfo) 21635 { 21636 switch (devinfo->gen) { 21637 case 10: return 1; 21638 case 9: return 1; 21639 case 8: return 1; 21640 case 7: 21641 if (devinfo->is_haswell) { 21642 return 1; 21643 } else { 21644 return 1; 21645 } 21646 case 6: return 0; 21647 case 5: return 0; 21648 case 4: 21649 if (devinfo->is_g4x) { 21650 return 0; 21651 } else { 21652 return 0; 21653 } 21654 default: 21655 unreachable("Invalid hardware generation"); 21656 } 21657 } 21658 21659 21660 21661 #define GEN10_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 21662 #define GEN9_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 21663 #define GEN8_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 21664 #define GEN75_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 21665 #define GEN7_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 21666 21667 static inline uint32_t ATTRIBUTE_PURE 21668 _3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start(const struct gen_device_info *devinfo) 21669 { 21670 switch (devinfo->gen) { 21671 case 10: return 59; 21672 case 9: return 59; 21673 case 8: return 59; 21674 case 7: 21675 if (devinfo->is_haswell) { 21676 return 59; 21677 } else { 21678 return 59; 21679 } 21680 case 6: return 0; 21681 case 5: return 0; 21682 case 4: 21683 if (devinfo->is_g4x) { 21684 return 0; 21685 } else { 21686 return 0; 21687 } 21688 default: 21689 unreachable("Invalid hardware generation"); 21690 } 21691 } 21692 21693 21694 21695 /* 3DSTATE_DEPTH_BUFFER::Surface Base Address */ 21696 21697 21698 #define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 21699 #define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 21700 #define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 21701 #define GEN75_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 21702 #define GEN7_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 21703 #define GEN6_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 21704 #define GEN5_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 21705 #define GEN45_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 21706 #define GEN4_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 21707 21708 static inline uint32_t ATTRIBUTE_PURE 21709 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits(const struct gen_device_info *devinfo) 21710 { 21711 switch (devinfo->gen) { 21712 case 10: return 64; 21713 case 9: return 64; 21714 case 8: return 64; 21715 case 7: 21716 if (devinfo->is_haswell) { 21717 return 32; 21718 } else { 21719 return 32; 21720 } 21721 case 6: return 32; 21722 case 5: return 32; 21723 case 4: 21724 if (devinfo->is_g4x) { 21725 return 32; 21726 } else { 21727 return 32; 21728 } 21729 default: 21730 unreachable("Invalid hardware generation"); 21731 } 21732 } 21733 21734 21735 21736 #define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 21737 #define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 21738 #define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 21739 #define GEN75_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 21740 #define GEN7_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 21741 #define GEN6_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 21742 #define GEN5_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 21743 #define GEN45_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 21744 #define GEN4_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 21745 21746 static inline uint32_t ATTRIBUTE_PURE 21747 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(const struct gen_device_info *devinfo) 21748 { 21749 switch (devinfo->gen) { 21750 case 10: return 64; 21751 case 9: return 64; 21752 case 8: return 64; 21753 case 7: 21754 if (devinfo->is_haswell) { 21755 return 64; 21756 } else { 21757 return 64; 21758 } 21759 case 6: return 64; 21760 case 5: return 64; 21761 case 4: 21762 if (devinfo->is_g4x) { 21763 return 64; 21764 } else { 21765 return 64; 21766 } 21767 default: 21768 unreachable("Invalid hardware generation"); 21769 } 21770 } 21771 21772 21773 21774 /* 3DSTATE_DEPTH_BUFFER::Surface Format */ 21775 21776 21777 #define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 21778 #define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 21779 #define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 21780 #define GEN75_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 21781 #define GEN7_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 21782 #define GEN6_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 21783 #define GEN5_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 21784 #define GEN45_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 21785 #define GEN4_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 21786 21787 static inline uint32_t ATTRIBUTE_PURE 21788 _3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits(const struct gen_device_info *devinfo) 21789 { 21790 switch (devinfo->gen) { 21791 case 10: return 3; 21792 case 9: return 3; 21793 case 8: return 3; 21794 case 7: 21795 if (devinfo->is_haswell) { 21796 return 3; 21797 } else { 21798 return 3; 21799 } 21800 case 6: return 3; 21801 case 5: return 3; 21802 case 4: 21803 if (devinfo->is_g4x) { 21804 return 3; 21805 } else { 21806 return 3; 21807 } 21808 default: 21809 unreachable("Invalid hardware generation"); 21810 } 21811 } 21812 21813 21814 21815 #define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 21816 #define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 21817 #define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 21818 #define GEN75_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 21819 #define GEN7_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 21820 #define GEN6_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 21821 #define GEN5_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 21822 #define GEN45_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 21823 #define GEN4_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 21824 21825 static inline uint32_t ATTRIBUTE_PURE 21826 _3DSTATE_DEPTH_BUFFER_SurfaceFormat_start(const struct gen_device_info *devinfo) 21827 { 21828 switch (devinfo->gen) { 21829 case 10: return 50; 21830 case 9: return 50; 21831 case 8: return 50; 21832 case 7: 21833 if (devinfo->is_haswell) { 21834 return 50; 21835 } else { 21836 return 50; 21837 } 21838 case 6: return 50; 21839 case 5: return 50; 21840 case 4: 21841 if (devinfo->is_g4x) { 21842 return 50; 21843 } else { 21844 return 50; 21845 } 21846 default: 21847 unreachable("Invalid hardware generation"); 21848 } 21849 } 21850 21851 21852 21853 /* 3DSTATE_DEPTH_BUFFER::Surface Pitch */ 21854 21855 21856 #define GEN10_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 21857 #define GEN9_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 21858 #define GEN8_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 21859 #define GEN75_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 21860 #define GEN7_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 21861 #define GEN6_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 17 21862 #define GEN5_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 17 21863 #define GEN45_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 17 21864 #define GEN4_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 17 21865 21866 static inline uint32_t ATTRIBUTE_PURE 21867 _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(const struct gen_device_info *devinfo) 21868 { 21869 switch (devinfo->gen) { 21870 case 10: return 18; 21871 case 9: return 18; 21872 case 8: return 18; 21873 case 7: 21874 if (devinfo->is_haswell) { 21875 return 18; 21876 } else { 21877 return 18; 21878 } 21879 case 6: return 17; 21880 case 5: return 17; 21881 case 4: 21882 if (devinfo->is_g4x) { 21883 return 17; 21884 } else { 21885 return 17; 21886 } 21887 default: 21888 unreachable("Invalid hardware generation"); 21889 } 21890 } 21891 21892 21893 21894 #define GEN10_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 21895 #define GEN9_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 21896 #define GEN8_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 21897 #define GEN75_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 21898 #define GEN7_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 21899 #define GEN6_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 21900 #define GEN5_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 21901 #define GEN45_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 21902 #define GEN4_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 21903 21904 static inline uint32_t ATTRIBUTE_PURE 21905 _3DSTATE_DEPTH_BUFFER_SurfacePitch_start(const struct gen_device_info *devinfo) 21906 { 21907 switch (devinfo->gen) { 21908 case 10: return 32; 21909 case 9: return 32; 21910 case 8: return 32; 21911 case 7: 21912 if (devinfo->is_haswell) { 21913 return 32; 21914 } else { 21915 return 32; 21916 } 21917 case 6: return 32; 21918 case 5: return 32; 21919 case 4: 21920 if (devinfo->is_g4x) { 21921 return 32; 21922 } else { 21923 return 32; 21924 } 21925 default: 21926 unreachable("Invalid hardware generation"); 21927 } 21928 } 21929 21930 21931 21932 /* 3DSTATE_DEPTH_BUFFER::Surface QPitch */ 21933 21934 21935 #define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits 15 21936 #define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits 15 21937 #define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits 15 21938 21939 static inline uint32_t ATTRIBUTE_PURE 21940 _3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits(const struct gen_device_info *devinfo) 21941 { 21942 switch (devinfo->gen) { 21943 case 10: return 15; 21944 case 9: return 15; 21945 case 8: return 15; 21946 case 7: 21947 if (devinfo->is_haswell) { 21948 return 0; 21949 } else { 21950 return 0; 21951 } 21952 case 6: return 0; 21953 case 5: return 0; 21954 case 4: 21955 if (devinfo->is_g4x) { 21956 return 0; 21957 } else { 21958 return 0; 21959 } 21960 default: 21961 unreachable("Invalid hardware generation"); 21962 } 21963 } 21964 21965 21966 21967 #define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start 224 21968 #define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start 224 21969 #define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start 224 21970 21971 static inline uint32_t ATTRIBUTE_PURE 21972 _3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start(const struct gen_device_info *devinfo) 21973 { 21974 switch (devinfo->gen) { 21975 case 10: return 224; 21976 case 9: return 224; 21977 case 8: return 224; 21978 case 7: 21979 if (devinfo->is_haswell) { 21980 return 0; 21981 } else { 21982 return 0; 21983 } 21984 case 6: return 0; 21985 case 5: return 0; 21986 case 4: 21987 if (devinfo->is_g4x) { 21988 return 0; 21989 } else { 21990 return 0; 21991 } 21992 default: 21993 unreachable("Invalid hardware generation"); 21994 } 21995 } 21996 21997 21998 21999 /* 3DSTATE_DEPTH_BUFFER::Surface Type */ 22000 22001 22002 #define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 22003 #define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 22004 #define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 22005 #define GEN75_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 22006 #define GEN7_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 22007 #define GEN6_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 22008 #define GEN5_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 22009 #define GEN45_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 22010 #define GEN4_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 22011 22012 static inline uint32_t ATTRIBUTE_PURE 22013 _3DSTATE_DEPTH_BUFFER_SurfaceType_bits(const struct gen_device_info *devinfo) 22014 { 22015 switch (devinfo->gen) { 22016 case 10: return 3; 22017 case 9: return 3; 22018 case 8: return 3; 22019 case 7: 22020 if (devinfo->is_haswell) { 22021 return 3; 22022 } else { 22023 return 3; 22024 } 22025 case 6: return 3; 22026 case 5: return 3; 22027 case 4: 22028 if (devinfo->is_g4x) { 22029 return 3; 22030 } else { 22031 return 3; 22032 } 22033 default: 22034 unreachable("Invalid hardware generation"); 22035 } 22036 } 22037 22038 22039 22040 #define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 22041 #define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 22042 #define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 22043 #define GEN75_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 22044 #define GEN7_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 22045 #define GEN6_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 22046 #define GEN5_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 22047 #define GEN45_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 22048 #define GEN4_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 22049 22050 static inline uint32_t ATTRIBUTE_PURE 22051 _3DSTATE_DEPTH_BUFFER_SurfaceType_start(const struct gen_device_info *devinfo) 22052 { 22053 switch (devinfo->gen) { 22054 case 10: return 61; 22055 case 9: return 61; 22056 case 8: return 61; 22057 case 7: 22058 if (devinfo->is_haswell) { 22059 return 61; 22060 } else { 22061 return 61; 22062 } 22063 case 6: return 61; 22064 case 5: return 61; 22065 case 4: 22066 if (devinfo->is_g4x) { 22067 return 61; 22068 } else { 22069 return 61; 22070 } 22071 default: 22072 unreachable("Invalid hardware generation"); 22073 } 22074 } 22075 22076 22077 22078 /* 3DSTATE_DEPTH_BUFFER::Tile Walk */ 22079 22080 22081 #define GEN6_3DSTATE_DEPTH_BUFFER_TileWalk_bits 1 22082 #define GEN5_3DSTATE_DEPTH_BUFFER_TileWalk_bits 1 22083 #define GEN45_3DSTATE_DEPTH_BUFFER_TileWalk_bits 1 22084 #define GEN4_3DSTATE_DEPTH_BUFFER_TileWalk_bits 1 22085 22086 static inline uint32_t ATTRIBUTE_PURE 22087 _3DSTATE_DEPTH_BUFFER_TileWalk_bits(const struct gen_device_info *devinfo) 22088 { 22089 switch (devinfo->gen) { 22090 case 10: return 0; 22091 case 9: return 0; 22092 case 8: return 0; 22093 case 7: 22094 if (devinfo->is_haswell) { 22095 return 0; 22096 } else { 22097 return 0; 22098 } 22099 case 6: return 1; 22100 case 5: return 1; 22101 case 4: 22102 if (devinfo->is_g4x) { 22103 return 1; 22104 } else { 22105 return 1; 22106 } 22107 default: 22108 unreachable("Invalid hardware generation"); 22109 } 22110 } 22111 22112 22113 22114 #define GEN6_3DSTATE_DEPTH_BUFFER_TileWalk_start 58 22115 #define GEN5_3DSTATE_DEPTH_BUFFER_TileWalk_start 58 22116 #define GEN45_3DSTATE_DEPTH_BUFFER_TileWalk_start 58 22117 #define GEN4_3DSTATE_DEPTH_BUFFER_TileWalk_start 58 22118 22119 static inline uint32_t ATTRIBUTE_PURE 22120 _3DSTATE_DEPTH_BUFFER_TileWalk_start(const struct gen_device_info *devinfo) 22121 { 22122 switch (devinfo->gen) { 22123 case 10: return 0; 22124 case 9: return 0; 22125 case 8: return 0; 22126 case 7: 22127 if (devinfo->is_haswell) { 22128 return 0; 22129 } else { 22130 return 0; 22131 } 22132 case 6: return 58; 22133 case 5: return 58; 22134 case 4: 22135 if (devinfo->is_g4x) { 22136 return 58; 22137 } else { 22138 return 58; 22139 } 22140 default: 22141 unreachable("Invalid hardware generation"); 22142 } 22143 } 22144 22145 22146 22147 /* 3DSTATE_DEPTH_BUFFER::Tiled Resource Mode */ 22148 22149 22150 #define GEN10_3DSTATE_DEPTH_BUFFER_TiledResourceMode_bits 2 22151 #define GEN9_3DSTATE_DEPTH_BUFFER_TiledResourceMode_bits 2 22152 22153 static inline uint32_t ATTRIBUTE_PURE 22154 _3DSTATE_DEPTH_BUFFER_TiledResourceMode_bits(const struct gen_device_info *devinfo) 22155 { 22156 switch (devinfo->gen) { 22157 case 10: return 2; 22158 case 9: return 2; 22159 case 8: return 0; 22160 case 7: 22161 if (devinfo->is_haswell) { 22162 return 0; 22163 } else { 22164 return 0; 22165 } 22166 case 6: return 0; 22167 case 5: return 0; 22168 case 4: 22169 if (devinfo->is_g4x) { 22170 return 0; 22171 } else { 22172 return 0; 22173 } 22174 default: 22175 unreachable("Invalid hardware generation"); 22176 } 22177 } 22178 22179 22180 22181 #define GEN10_3DSTATE_DEPTH_BUFFER_TiledResourceMode_start 222 22182 #define GEN9_3DSTATE_DEPTH_BUFFER_TiledResourceMode_start 222 22183 22184 static inline uint32_t ATTRIBUTE_PURE 22185 _3DSTATE_DEPTH_BUFFER_TiledResourceMode_start(const struct gen_device_info *devinfo) 22186 { 22187 switch (devinfo->gen) { 22188 case 10: return 222; 22189 case 9: return 222; 22190 case 8: return 0; 22191 case 7: 22192 if (devinfo->is_haswell) { 22193 return 0; 22194 } else { 22195 return 0; 22196 } 22197 case 6: return 0; 22198 case 5: return 0; 22199 case 4: 22200 if (devinfo->is_g4x) { 22201 return 0; 22202 } else { 22203 return 0; 22204 } 22205 default: 22206 unreachable("Invalid hardware generation"); 22207 } 22208 } 22209 22210 22211 22212 /* 3DSTATE_DEPTH_BUFFER::Tiled Surface */ 22213 22214 22215 #define GEN6_3DSTATE_DEPTH_BUFFER_TiledSurface_bits 1 22216 #define GEN5_3DSTATE_DEPTH_BUFFER_TiledSurface_bits 1 22217 #define GEN45_3DSTATE_DEPTH_BUFFER_TiledSurface_bits 1 22218 #define GEN4_3DSTATE_DEPTH_BUFFER_TiledSurface_bits 1 22219 22220 static inline uint32_t ATTRIBUTE_PURE 22221 _3DSTATE_DEPTH_BUFFER_TiledSurface_bits(const struct gen_device_info *devinfo) 22222 { 22223 switch (devinfo->gen) { 22224 case 10: return 0; 22225 case 9: return 0; 22226 case 8: return 0; 22227 case 7: 22228 if (devinfo->is_haswell) { 22229 return 0; 22230 } else { 22231 return 0; 22232 } 22233 case 6: return 1; 22234 case 5: return 1; 22235 case 4: 22236 if (devinfo->is_g4x) { 22237 return 1; 22238 } else { 22239 return 1; 22240 } 22241 default: 22242 unreachable("Invalid hardware generation"); 22243 } 22244 } 22245 22246 22247 22248 #define GEN6_3DSTATE_DEPTH_BUFFER_TiledSurface_start 59 22249 #define GEN5_3DSTATE_DEPTH_BUFFER_TiledSurface_start 59 22250 #define GEN45_3DSTATE_DEPTH_BUFFER_TiledSurface_start 59 22251 #define GEN4_3DSTATE_DEPTH_BUFFER_TiledSurface_start 59 22252 22253 static inline uint32_t ATTRIBUTE_PURE 22254 _3DSTATE_DEPTH_BUFFER_TiledSurface_start(const struct gen_device_info *devinfo) 22255 { 22256 switch (devinfo->gen) { 22257 case 10: return 0; 22258 case 9: return 0; 22259 case 8: return 0; 22260 case 7: 22261 if (devinfo->is_haswell) { 22262 return 0; 22263 } else { 22264 return 0; 22265 } 22266 case 6: return 59; 22267 case 5: return 59; 22268 case 4: 22269 if (devinfo->is_g4x) { 22270 return 59; 22271 } else { 22272 return 59; 22273 } 22274 default: 22275 unreachable("Invalid hardware generation"); 22276 } 22277 } 22278 22279 22280 22281 /* 3DSTATE_DEPTH_BUFFER::Width */ 22282 22283 22284 #define GEN10_3DSTATE_DEPTH_BUFFER_Width_bits 14 22285 #define GEN9_3DSTATE_DEPTH_BUFFER_Width_bits 14 22286 #define GEN8_3DSTATE_DEPTH_BUFFER_Width_bits 14 22287 #define GEN75_3DSTATE_DEPTH_BUFFER_Width_bits 14 22288 #define GEN7_3DSTATE_DEPTH_BUFFER_Width_bits 14 22289 #define GEN6_3DSTATE_DEPTH_BUFFER_Width_bits 13 22290 #define GEN5_3DSTATE_DEPTH_BUFFER_Width_bits 13 22291 #define GEN45_3DSTATE_DEPTH_BUFFER_Width_bits 13 22292 #define GEN4_3DSTATE_DEPTH_BUFFER_Width_bits 13 22293 22294 static inline uint32_t ATTRIBUTE_PURE 22295 _3DSTATE_DEPTH_BUFFER_Width_bits(const struct gen_device_info *devinfo) 22296 { 22297 switch (devinfo->gen) { 22298 case 10: return 14; 22299 case 9: return 14; 22300 case 8: return 14; 22301 case 7: 22302 if (devinfo->is_haswell) { 22303 return 14; 22304 } else { 22305 return 14; 22306 } 22307 case 6: return 13; 22308 case 5: return 13; 22309 case 4: 22310 if (devinfo->is_g4x) { 22311 return 13; 22312 } else { 22313 return 13; 22314 } 22315 default: 22316 unreachable("Invalid hardware generation"); 22317 } 22318 } 22319 22320 22321 22322 #define GEN10_3DSTATE_DEPTH_BUFFER_Width_start 132 22323 #define GEN9_3DSTATE_DEPTH_BUFFER_Width_start 132 22324 #define GEN8_3DSTATE_DEPTH_BUFFER_Width_start 132 22325 #define GEN75_3DSTATE_DEPTH_BUFFER_Width_start 100 22326 #define GEN7_3DSTATE_DEPTH_BUFFER_Width_start 100 22327 #define GEN6_3DSTATE_DEPTH_BUFFER_Width_start 102 22328 #define GEN5_3DSTATE_DEPTH_BUFFER_Width_start 102 22329 #define GEN45_3DSTATE_DEPTH_BUFFER_Width_start 102 22330 #define GEN4_3DSTATE_DEPTH_BUFFER_Width_start 102 22331 22332 static inline uint32_t ATTRIBUTE_PURE 22333 _3DSTATE_DEPTH_BUFFER_Width_start(const struct gen_device_info *devinfo) 22334 { 22335 switch (devinfo->gen) { 22336 case 10: return 132; 22337 case 9: return 132; 22338 case 8: return 132; 22339 case 7: 22340 if (devinfo->is_haswell) { 22341 return 100; 22342 } else { 22343 return 100; 22344 } 22345 case 6: return 102; 22346 case 5: return 102; 22347 case 4: 22348 if (devinfo->is_g4x) { 22349 return 102; 22350 } else { 22351 return 102; 22352 } 22353 default: 22354 unreachable("Invalid hardware generation"); 22355 } 22356 } 22357 22358 22359 22360 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */ 22361 22362 22363 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_length 2 22364 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_length 2 22365 22366 static inline uint32_t ATTRIBUTE_PURE 22367 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_length(const struct gen_device_info *devinfo) 22368 { 22369 switch (devinfo->gen) { 22370 case 10: return 0; 22371 case 9: return 0; 22372 case 8: return 0; 22373 case 7: 22374 if (devinfo->is_haswell) { 22375 return 2; 22376 } else { 22377 return 2; 22378 } 22379 case 6: return 0; 22380 case 5: return 0; 22381 case 4: 22382 if (devinfo->is_g4x) { 22383 return 0; 22384 } else { 22385 return 0; 22386 } 22387 default: 22388 unreachable("Invalid hardware generation"); 22389 } 22390 } 22391 22392 22393 22394 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::3D Command Opcode */ 22395 22396 22397 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_bits 3 22398 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_bits 3 22399 22400 static inline uint32_t ATTRIBUTE_PURE 22401 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 22402 { 22403 switch (devinfo->gen) { 22404 case 10: return 0; 22405 case 9: return 0; 22406 case 8: return 0; 22407 case 7: 22408 if (devinfo->is_haswell) { 22409 return 3; 22410 } else { 22411 return 3; 22412 } 22413 case 6: return 0; 22414 case 5: return 0; 22415 case 4: 22416 if (devinfo->is_g4x) { 22417 return 0; 22418 } else { 22419 return 0; 22420 } 22421 default: 22422 unreachable("Invalid hardware generation"); 22423 } 22424 } 22425 22426 22427 22428 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_start 24 22429 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_start 24 22430 22431 static inline uint32_t ATTRIBUTE_PURE 22432 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 22433 { 22434 switch (devinfo->gen) { 22435 case 10: return 0; 22436 case 9: return 0; 22437 case 8: return 0; 22438 case 7: 22439 if (devinfo->is_haswell) { 22440 return 24; 22441 } else { 22442 return 24; 22443 } 22444 case 6: return 0; 22445 case 5: return 0; 22446 case 4: 22447 if (devinfo->is_g4x) { 22448 return 0; 22449 } else { 22450 return 0; 22451 } 22452 default: 22453 unreachable("Invalid hardware generation"); 22454 } 22455 } 22456 22457 22458 22459 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::3D Command Sub Opcode */ 22460 22461 22462 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_bits 8 22463 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_bits 8 22464 22465 static inline uint32_t ATTRIBUTE_PURE 22466 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 22467 { 22468 switch (devinfo->gen) { 22469 case 10: return 0; 22470 case 9: return 0; 22471 case 8: return 0; 22472 case 7: 22473 if (devinfo->is_haswell) { 22474 return 8; 22475 } else { 22476 return 8; 22477 } 22478 case 6: return 0; 22479 case 5: return 0; 22480 case 4: 22481 if (devinfo->is_g4x) { 22482 return 0; 22483 } else { 22484 return 0; 22485 } 22486 default: 22487 unreachable("Invalid hardware generation"); 22488 } 22489 } 22490 22491 22492 22493 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_start 16 22494 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_start 16 22495 22496 static inline uint32_t ATTRIBUTE_PURE 22497 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 22498 { 22499 switch (devinfo->gen) { 22500 case 10: return 0; 22501 case 9: return 0; 22502 case 8: return 0; 22503 case 7: 22504 if (devinfo->is_haswell) { 22505 return 16; 22506 } else { 22507 return 16; 22508 } 22509 case 6: return 0; 22510 case 5: return 0; 22511 case 4: 22512 if (devinfo->is_g4x) { 22513 return 0; 22514 } else { 22515 return 0; 22516 } 22517 default: 22518 unreachable("Invalid hardware generation"); 22519 } 22520 } 22521 22522 22523 22524 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::Command SubType */ 22525 22526 22527 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_bits 2 22528 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_bits 2 22529 22530 static inline uint32_t ATTRIBUTE_PURE 22531 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) 22532 { 22533 switch (devinfo->gen) { 22534 case 10: return 0; 22535 case 9: return 0; 22536 case 8: return 0; 22537 case 7: 22538 if (devinfo->is_haswell) { 22539 return 2; 22540 } else { 22541 return 2; 22542 } 22543 case 6: return 0; 22544 case 5: return 0; 22545 case 4: 22546 if (devinfo->is_g4x) { 22547 return 0; 22548 } else { 22549 return 0; 22550 } 22551 default: 22552 unreachable("Invalid hardware generation"); 22553 } 22554 } 22555 22556 22557 22558 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_start 27 22559 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_start 27 22560 22561 static inline uint32_t ATTRIBUTE_PURE 22562 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) 22563 { 22564 switch (devinfo->gen) { 22565 case 10: return 0; 22566 case 9: return 0; 22567 case 8: return 0; 22568 case 7: 22569 if (devinfo->is_haswell) { 22570 return 27; 22571 } else { 22572 return 27; 22573 } 22574 case 6: return 0; 22575 case 5: return 0; 22576 case 4: 22577 if (devinfo->is_g4x) { 22578 return 0; 22579 } else { 22580 return 0; 22581 } 22582 default: 22583 unreachable("Invalid hardware generation"); 22584 } 22585 } 22586 22587 22588 22589 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::Command Type */ 22590 22591 22592 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_bits 3 22593 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_bits 3 22594 22595 static inline uint32_t ATTRIBUTE_PURE 22596 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) 22597 { 22598 switch (devinfo->gen) { 22599 case 10: return 0; 22600 case 9: return 0; 22601 case 8: return 0; 22602 case 7: 22603 if (devinfo->is_haswell) { 22604 return 3; 22605 } else { 22606 return 3; 22607 } 22608 case 6: return 0; 22609 case 5: return 0; 22610 case 4: 22611 if (devinfo->is_g4x) { 22612 return 0; 22613 } else { 22614 return 0; 22615 } 22616 default: 22617 unreachable("Invalid hardware generation"); 22618 } 22619 } 22620 22621 22622 22623 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_start 29 22624 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_start 29 22625 22626 static inline uint32_t ATTRIBUTE_PURE 22627 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) 22628 { 22629 switch (devinfo->gen) { 22630 case 10: return 0; 22631 case 9: return 0; 22632 case 8: return 0; 22633 case 7: 22634 if (devinfo->is_haswell) { 22635 return 29; 22636 } else { 22637 return 29; 22638 } 22639 case 6: return 0; 22640 case 5: return 0; 22641 case 4: 22642 if (devinfo->is_g4x) { 22643 return 0; 22644 } else { 22645 return 0; 22646 } 22647 default: 22648 unreachable("Invalid hardware generation"); 22649 } 22650 } 22651 22652 22653 22654 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::DWord Length */ 22655 22656 22657 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_bits 8 22658 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_bits 8 22659 22660 static inline uint32_t ATTRIBUTE_PURE 22661 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) 22662 { 22663 switch (devinfo->gen) { 22664 case 10: return 0; 22665 case 9: return 0; 22666 case 8: return 0; 22667 case 7: 22668 if (devinfo->is_haswell) { 22669 return 8; 22670 } else { 22671 return 8; 22672 } 22673 case 6: return 0; 22674 case 5: return 0; 22675 case 4: 22676 if (devinfo->is_g4x) { 22677 return 0; 22678 } else { 22679 return 0; 22680 } 22681 default: 22682 unreachable("Invalid hardware generation"); 22683 } 22684 } 22685 22686 22687 22688 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_start 0 22689 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_start 0 22690 22691 static inline uint32_t ATTRIBUTE_PURE 22692 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) 22693 { 22694 switch (devinfo->gen) { 22695 case 10: return 0; 22696 case 9: return 0; 22697 case 8: return 0; 22698 case 7: 22699 if (devinfo->is_haswell) { 22700 return 0; 22701 } else { 22702 return 0; 22703 } 22704 case 6: return 0; 22705 case 5: return 0; 22706 case 4: 22707 if (devinfo->is_g4x) { 22708 return 0; 22709 } else { 22710 return 0; 22711 } 22712 default: 22713 unreachable("Invalid hardware generation"); 22714 } 22715 } 22716 22717 22718 22719 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::Pointer to DEPTH_STENCIL_STATE */ 22720 22721 22722 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits 26 22723 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits 26 22724 22725 static inline uint32_t ATTRIBUTE_PURE 22726 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits(const struct gen_device_info *devinfo) 22727 { 22728 switch (devinfo->gen) { 22729 case 10: return 0; 22730 case 9: return 0; 22731 case 8: return 0; 22732 case 7: 22733 if (devinfo->is_haswell) { 22734 return 26; 22735 } else { 22736 return 26; 22737 } 22738 case 6: return 0; 22739 case 5: return 0; 22740 case 4: 22741 if (devinfo->is_g4x) { 22742 return 0; 22743 } else { 22744 return 0; 22745 } 22746 default: 22747 unreachable("Invalid hardware generation"); 22748 } 22749 } 22750 22751 22752 22753 #define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start 38 22754 #define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start 38 22755 22756 static inline uint32_t ATTRIBUTE_PURE 22757 _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start(const struct gen_device_info *devinfo) 22758 { 22759 switch (devinfo->gen) { 22760 case 10: return 0; 22761 case 9: return 0; 22762 case 8: return 0; 22763 case 7: 22764 if (devinfo->is_haswell) { 22765 return 38; 22766 } else { 22767 return 38; 22768 } 22769 case 6: return 0; 22770 case 5: return 0; 22771 case 4: 22772 if (devinfo->is_g4x) { 22773 return 0; 22774 } else { 22775 return 0; 22776 } 22777 default: 22778 unreachable("Invalid hardware generation"); 22779 } 22780 } 22781 22782 22783 22784 /* 3DSTATE_DRAWING_RECTANGLE */ 22785 22786 22787 #define GEN10_3DSTATE_DRAWING_RECTANGLE_length 4 22788 #define GEN9_3DSTATE_DRAWING_RECTANGLE_length 4 22789 #define GEN8_3DSTATE_DRAWING_RECTANGLE_length 4 22790 #define GEN75_3DSTATE_DRAWING_RECTANGLE_length 4 22791 #define GEN7_3DSTATE_DRAWING_RECTANGLE_length 4 22792 #define GEN6_3DSTATE_DRAWING_RECTANGLE_length 4 22793 #define GEN5_3DSTATE_DRAWING_RECTANGLE_length 4 22794 #define GEN45_3DSTATE_DRAWING_RECTANGLE_length 4 22795 #define GEN4_3DSTATE_DRAWING_RECTANGLE_length 4 22796 22797 static inline uint32_t ATTRIBUTE_PURE 22798 _3DSTATE_DRAWING_RECTANGLE_length(const struct gen_device_info *devinfo) 22799 { 22800 switch (devinfo->gen) { 22801 case 10: return 4; 22802 case 9: return 4; 22803 case 8: return 4; 22804 case 7: 22805 if (devinfo->is_haswell) { 22806 return 4; 22807 } else { 22808 return 4; 22809 } 22810 case 6: return 4; 22811 case 5: return 4; 22812 case 4: 22813 if (devinfo->is_g4x) { 22814 return 4; 22815 } else { 22816 return 4; 22817 } 22818 default: 22819 unreachable("Invalid hardware generation"); 22820 } 22821 } 22822 22823 22824 22825 /* 3DSTATE_DRAWING_RECTANGLE::3D Command Opcode */ 22826 22827 22828 #define GEN10_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 22829 #define GEN9_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 22830 #define GEN8_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 22831 #define GEN75_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 22832 #define GEN7_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 22833 #define GEN6_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 22834 #define GEN5_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 22835 #define GEN45_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 22836 #define GEN4_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 22837 22838 static inline uint32_t ATTRIBUTE_PURE 22839 _3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 22840 { 22841 switch (devinfo->gen) { 22842 case 10: return 3; 22843 case 9: return 3; 22844 case 8: return 3; 22845 case 7: 22846 if (devinfo->is_haswell) { 22847 return 3; 22848 } else { 22849 return 3; 22850 } 22851 case 6: return 3; 22852 case 5: return 3; 22853 case 4: 22854 if (devinfo->is_g4x) { 22855 return 3; 22856 } else { 22857 return 3; 22858 } 22859 default: 22860 unreachable("Invalid hardware generation"); 22861 } 22862 } 22863 22864 22865 22866 #define GEN10_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 22867 #define GEN9_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 22868 #define GEN8_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 22869 #define GEN75_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 22870 #define GEN7_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 22871 #define GEN6_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 22872 #define GEN5_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 22873 #define GEN45_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 22874 #define GEN4_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 22875 22876 static inline uint32_t ATTRIBUTE_PURE 22877 _3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start(const struct gen_device_info *devinfo) 22878 { 22879 switch (devinfo->gen) { 22880 case 10: return 24; 22881 case 9: return 24; 22882 case 8: return 24; 22883 case 7: 22884 if (devinfo->is_haswell) { 22885 return 24; 22886 } else { 22887 return 24; 22888 } 22889 case 6: return 24; 22890 case 5: return 24; 22891 case 4: 22892 if (devinfo->is_g4x) { 22893 return 24; 22894 } else { 22895 return 24; 22896 } 22897 default: 22898 unreachable("Invalid hardware generation"); 22899 } 22900 } 22901 22902 22903 22904 /* 3DSTATE_DRAWING_RECTANGLE::3D Command Sub Opcode */ 22905 22906 22907 #define GEN10_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 22908 #define GEN9_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 22909 #define GEN8_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 22910 #define GEN75_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 22911 #define GEN7_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 22912 #define GEN6_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 22913 #define GEN5_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 22914 #define GEN45_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 22915 #define GEN4_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 22916 22917 static inline uint32_t ATTRIBUTE_PURE 22918 _3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 22919 { 22920 switch (devinfo->gen) { 22921 case 10: return 8; 22922 case 9: return 8; 22923 case 8: return 8; 22924 case 7: 22925 if (devinfo->is_haswell) { 22926 return 8; 22927 } else { 22928 return 8; 22929 } 22930 case 6: return 8; 22931 case 5: return 8; 22932 case 4: 22933 if (devinfo->is_g4x) { 22934 return 8; 22935 } else { 22936 return 8; 22937 } 22938 default: 22939 unreachable("Invalid hardware generation"); 22940 } 22941 } 22942 22943 22944 22945 #define GEN10_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 22946 #define GEN9_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 22947 #define GEN8_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 22948 #define GEN75_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 22949 #define GEN7_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 22950 #define GEN6_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 22951 #define GEN5_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 22952 #define GEN45_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 22953 #define GEN4_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 22954 22955 static inline uint32_t ATTRIBUTE_PURE 22956 _3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 22957 { 22958 switch (devinfo->gen) { 22959 case 10: return 16; 22960 case 9: return 16; 22961 case 8: return 16; 22962 case 7: 22963 if (devinfo->is_haswell) { 22964 return 16; 22965 } else { 22966 return 16; 22967 } 22968 case 6: return 16; 22969 case 5: return 16; 22970 case 4: 22971 if (devinfo->is_g4x) { 22972 return 16; 22973 } else { 22974 return 16; 22975 } 22976 default: 22977 unreachable("Invalid hardware generation"); 22978 } 22979 } 22980 22981 22982 22983 /* 3DSTATE_DRAWING_RECTANGLE::Clipped Drawing Rectangle X Max */ 22984 22985 22986 #define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 22987 #define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 22988 #define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 22989 #define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 22990 #define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 22991 #define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 22992 #define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 22993 #define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 22994 #define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 22995 22996 static inline uint32_t ATTRIBUTE_PURE 22997 _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits(const struct gen_device_info *devinfo) 22998 { 22999 switch (devinfo->gen) { 23000 case 10: return 16; 23001 case 9: return 16; 23002 case 8: return 16; 23003 case 7: 23004 if (devinfo->is_haswell) { 23005 return 16; 23006 } else { 23007 return 16; 23008 } 23009 case 6: return 16; 23010 case 5: return 16; 23011 case 4: 23012 if (devinfo->is_g4x) { 23013 return 16; 23014 } else { 23015 return 16; 23016 } 23017 default: 23018 unreachable("Invalid hardware generation"); 23019 } 23020 } 23021 23022 23023 23024 #define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 23025 #define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 23026 #define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 23027 #define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 23028 #define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 23029 #define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 23030 #define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 23031 #define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 23032 #define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 23033 23034 static inline uint32_t ATTRIBUTE_PURE 23035 _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start(const struct gen_device_info *devinfo) 23036 { 23037 switch (devinfo->gen) { 23038 case 10: return 64; 23039 case 9: return 64; 23040 case 8: return 64; 23041 case 7: 23042 if (devinfo->is_haswell) { 23043 return 64; 23044 } else { 23045 return 64; 23046 } 23047 case 6: return 64; 23048 case 5: return 64; 23049 case 4: 23050 if (devinfo->is_g4x) { 23051 return 64; 23052 } else { 23053 return 64; 23054 } 23055 default: 23056 unreachable("Invalid hardware generation"); 23057 } 23058 } 23059 23060 23061 23062 /* 3DSTATE_DRAWING_RECTANGLE::Clipped Drawing Rectangle X Min */ 23063 23064 23065 #define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 23066 #define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 23067 #define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 23068 #define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 23069 #define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 23070 #define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 23071 #define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 23072 #define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 23073 #define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 23074 23075 static inline uint32_t ATTRIBUTE_PURE 23076 _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits(const struct gen_device_info *devinfo) 23077 { 23078 switch (devinfo->gen) { 23079 case 10: return 16; 23080 case 9: return 16; 23081 case 8: return 16; 23082 case 7: 23083 if (devinfo->is_haswell) { 23084 return 16; 23085 } else { 23086 return 16; 23087 } 23088 case 6: return 16; 23089 case 5: return 16; 23090 case 4: 23091 if (devinfo->is_g4x) { 23092 return 16; 23093 } else { 23094 return 16; 23095 } 23096 default: 23097 unreachable("Invalid hardware generation"); 23098 } 23099 } 23100 23101 23102 23103 #define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 23104 #define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 23105 #define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 23106 #define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 23107 #define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 23108 #define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 23109 #define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 23110 #define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 23111 #define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 23112 23113 static inline uint32_t ATTRIBUTE_PURE 23114 _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start(const struct gen_device_info *devinfo) 23115 { 23116 switch (devinfo->gen) { 23117 case 10: return 32; 23118 case 9: return 32; 23119 case 8: return 32; 23120 case 7: 23121 if (devinfo->is_haswell) { 23122 return 32; 23123 } else { 23124 return 32; 23125 } 23126 case 6: return 32; 23127 case 5: return 32; 23128 case 4: 23129 if (devinfo->is_g4x) { 23130 return 32; 23131 } else { 23132 return 32; 23133 } 23134 default: 23135 unreachable("Invalid hardware generation"); 23136 } 23137 } 23138 23139 23140 23141 /* 3DSTATE_DRAWING_RECTANGLE::Clipped Drawing Rectangle Y Max */ 23142 23143 23144 #define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 23145 #define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 23146 #define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 23147 #define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 23148 #define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 23149 #define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 23150 #define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 23151 #define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 23152 #define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 23153 23154 static inline uint32_t ATTRIBUTE_PURE 23155 _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits(const struct gen_device_info *devinfo) 23156 { 23157 switch (devinfo->gen) { 23158 case 10: return 16; 23159 case 9: return 16; 23160 case 8: return 16; 23161 case 7: 23162 if (devinfo->is_haswell) { 23163 return 16; 23164 } else { 23165 return 16; 23166 } 23167 case 6: return 16; 23168 case 5: return 16; 23169 case 4: 23170 if (devinfo->is_g4x) { 23171 return 16; 23172 } else { 23173 return 16; 23174 } 23175 default: 23176 unreachable("Invalid hardware generation"); 23177 } 23178 } 23179 23180 23181 23182 #define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 23183 #define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 23184 #define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 23185 #define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 23186 #define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 23187 #define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 23188 #define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 23189 #define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 23190 #define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 23191 23192 static inline uint32_t ATTRIBUTE_PURE 23193 _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start(const struct gen_device_info *devinfo) 23194 { 23195 switch (devinfo->gen) { 23196 case 10: return 80; 23197 case 9: return 80; 23198 case 8: return 80; 23199 case 7: 23200 if (devinfo->is_haswell) { 23201 return 80; 23202 } else { 23203 return 80; 23204 } 23205 case 6: return 80; 23206 case 5: return 80; 23207 case 4: 23208 if (devinfo->is_g4x) { 23209 return 80; 23210 } else { 23211 return 80; 23212 } 23213 default: 23214 unreachable("Invalid hardware generation"); 23215 } 23216 } 23217 23218 23219 23220 /* 3DSTATE_DRAWING_RECTANGLE::Clipped Drawing Rectangle Y Min */ 23221 23222 23223 #define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 23224 #define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 23225 #define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 23226 #define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 23227 #define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 23228 #define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 23229 #define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 23230 #define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 23231 #define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 23232 23233 static inline uint32_t ATTRIBUTE_PURE 23234 _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits(const struct gen_device_info *devinfo) 23235 { 23236 switch (devinfo->gen) { 23237 case 10: return 16; 23238 case 9: return 16; 23239 case 8: return 16; 23240 case 7: 23241 if (devinfo->is_haswell) { 23242 return 16; 23243 } else { 23244 return 16; 23245 } 23246 case 6: return 16; 23247 case 5: return 16; 23248 case 4: 23249 if (devinfo->is_g4x) { 23250 return 16; 23251 } else { 23252 return 16; 23253 } 23254 default: 23255 unreachable("Invalid hardware generation"); 23256 } 23257 } 23258 23259 23260 23261 #define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 23262 #define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 23263 #define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 23264 #define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 23265 #define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 23266 #define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 23267 #define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 23268 #define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 23269 #define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 23270 23271 static inline uint32_t ATTRIBUTE_PURE 23272 _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start(const struct gen_device_info *devinfo) 23273 { 23274 switch (devinfo->gen) { 23275 case 10: return 48; 23276 case 9: return 48; 23277 case 8: return 48; 23278 case 7: 23279 if (devinfo->is_haswell) { 23280 return 48; 23281 } else { 23282 return 48; 23283 } 23284 case 6: return 48; 23285 case 5: return 48; 23286 case 4: 23287 if (devinfo->is_g4x) { 23288 return 48; 23289 } else { 23290 return 48; 23291 } 23292 default: 23293 unreachable("Invalid hardware generation"); 23294 } 23295 } 23296 23297 23298 23299 /* 3DSTATE_DRAWING_RECTANGLE::Command SubType */ 23300 23301 23302 #define GEN10_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 23303 #define GEN9_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 23304 #define GEN8_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 23305 #define GEN75_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 23306 #define GEN7_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 23307 #define GEN6_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 23308 #define GEN5_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 23309 #define GEN45_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 23310 #define GEN4_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 23311 23312 static inline uint32_t ATTRIBUTE_PURE 23313 _3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits(const struct gen_device_info *devinfo) 23314 { 23315 switch (devinfo->gen) { 23316 case 10: return 2; 23317 case 9: return 2; 23318 case 8: return 2; 23319 case 7: 23320 if (devinfo->is_haswell) { 23321 return 2; 23322 } else { 23323 return 2; 23324 } 23325 case 6: return 2; 23326 case 5: return 2; 23327 case 4: 23328 if (devinfo->is_g4x) { 23329 return 2; 23330 } else { 23331 return 2; 23332 } 23333 default: 23334 unreachable("Invalid hardware generation"); 23335 } 23336 } 23337 23338 23339 23340 #define GEN10_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 23341 #define GEN9_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 23342 #define GEN8_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 23343 #define GEN75_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 23344 #define GEN7_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 23345 #define GEN6_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 23346 #define GEN5_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 23347 #define GEN45_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 23348 #define GEN4_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 23349 23350 static inline uint32_t ATTRIBUTE_PURE 23351 _3DSTATE_DRAWING_RECTANGLE_CommandSubType_start(const struct gen_device_info *devinfo) 23352 { 23353 switch (devinfo->gen) { 23354 case 10: return 27; 23355 case 9: return 27; 23356 case 8: return 27; 23357 case 7: 23358 if (devinfo->is_haswell) { 23359 return 27; 23360 } else { 23361 return 27; 23362 } 23363 case 6: return 27; 23364 case 5: return 27; 23365 case 4: 23366 if (devinfo->is_g4x) { 23367 return 27; 23368 } else { 23369 return 27; 23370 } 23371 default: 23372 unreachable("Invalid hardware generation"); 23373 } 23374 } 23375 23376 23377 23378 /* 3DSTATE_DRAWING_RECTANGLE::Command Type */ 23379 23380 23381 #define GEN10_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 23382 #define GEN9_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 23383 #define GEN8_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 23384 #define GEN75_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 23385 #define GEN7_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 23386 #define GEN6_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 23387 #define GEN5_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 23388 #define GEN45_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 23389 #define GEN4_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 23390 23391 static inline uint32_t ATTRIBUTE_PURE 23392 _3DSTATE_DRAWING_RECTANGLE_CommandType_bits(const struct gen_device_info *devinfo) 23393 { 23394 switch (devinfo->gen) { 23395 case 10: return 3; 23396 case 9: return 3; 23397 case 8: return 3; 23398 case 7: 23399 if (devinfo->is_haswell) { 23400 return 3; 23401 } else { 23402 return 3; 23403 } 23404 case 6: return 3; 23405 case 5: return 3; 23406 case 4: 23407 if (devinfo->is_g4x) { 23408 return 3; 23409 } else { 23410 return 3; 23411 } 23412 default: 23413 unreachable("Invalid hardware generation"); 23414 } 23415 } 23416 23417 23418 23419 #define GEN10_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 23420 #define GEN9_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 23421 #define GEN8_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 23422 #define GEN75_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 23423 #define GEN7_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 23424 #define GEN6_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 23425 #define GEN5_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 23426 #define GEN45_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 23427 #define GEN4_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 23428 23429 static inline uint32_t ATTRIBUTE_PURE 23430 _3DSTATE_DRAWING_RECTANGLE_CommandType_start(const struct gen_device_info *devinfo) 23431 { 23432 switch (devinfo->gen) { 23433 case 10: return 29; 23434 case 9: return 29; 23435 case 8: return 29; 23436 case 7: 23437 if (devinfo->is_haswell) { 23438 return 29; 23439 } else { 23440 return 29; 23441 } 23442 case 6: return 29; 23443 case 5: return 29; 23444 case 4: 23445 if (devinfo->is_g4x) { 23446 return 29; 23447 } else { 23448 return 29; 23449 } 23450 default: 23451 unreachable("Invalid hardware generation"); 23452 } 23453 } 23454 23455 23456 23457 /* 3DSTATE_DRAWING_RECTANGLE::Core Mode Select */ 23458 23459 23460 #define GEN10_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 23461 #define GEN9_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 23462 #define GEN8_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 23463 #define GEN75_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 23464 23465 static inline uint32_t ATTRIBUTE_PURE 23466 _3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits(const struct gen_device_info *devinfo) 23467 { 23468 switch (devinfo->gen) { 23469 case 10: return 2; 23470 case 9: return 2; 23471 case 8: return 2; 23472 case 7: 23473 if (devinfo->is_haswell) { 23474 return 2; 23475 } else { 23476 return 0; 23477 } 23478 case 6: return 0; 23479 case 5: return 0; 23480 case 4: 23481 if (devinfo->is_g4x) { 23482 return 0; 23483 } else { 23484 return 0; 23485 } 23486 default: 23487 unreachable("Invalid hardware generation"); 23488 } 23489 } 23490 23491 23492 23493 #define GEN10_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 23494 #define GEN9_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 23495 #define GEN8_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 23496 #define GEN75_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 23497 23498 static inline uint32_t ATTRIBUTE_PURE 23499 _3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start(const struct gen_device_info *devinfo) 23500 { 23501 switch (devinfo->gen) { 23502 case 10: return 14; 23503 case 9: return 14; 23504 case 8: return 14; 23505 case 7: 23506 if (devinfo->is_haswell) { 23507 return 14; 23508 } else { 23509 return 0; 23510 } 23511 case 6: return 0; 23512 case 5: return 0; 23513 case 4: 23514 if (devinfo->is_g4x) { 23515 return 0; 23516 } else { 23517 return 0; 23518 } 23519 default: 23520 unreachable("Invalid hardware generation"); 23521 } 23522 } 23523 23524 23525 23526 /* 3DSTATE_DRAWING_RECTANGLE::DWord Length */ 23527 23528 23529 #define GEN10_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 23530 #define GEN9_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 23531 #define GEN8_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 23532 #define GEN75_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 23533 #define GEN7_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 23534 #define GEN6_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 23535 #define GEN5_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 23536 #define GEN45_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 23537 #define GEN4_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 23538 23539 static inline uint32_t ATTRIBUTE_PURE 23540 _3DSTATE_DRAWING_RECTANGLE_DWordLength_bits(const struct gen_device_info *devinfo) 23541 { 23542 switch (devinfo->gen) { 23543 case 10: return 8; 23544 case 9: return 8; 23545 case 8: return 8; 23546 case 7: 23547 if (devinfo->is_haswell) { 23548 return 8; 23549 } else { 23550 return 8; 23551 } 23552 case 6: return 8; 23553 case 5: return 8; 23554 case 4: 23555 if (devinfo->is_g4x) { 23556 return 8; 23557 } else { 23558 return 8; 23559 } 23560 default: 23561 unreachable("Invalid hardware generation"); 23562 } 23563 } 23564 23565 23566 23567 #define GEN10_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 23568 #define GEN9_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 23569 #define GEN8_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 23570 #define GEN75_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 23571 #define GEN7_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 23572 #define GEN6_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 23573 #define GEN5_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 23574 #define GEN45_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 23575 #define GEN4_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 23576 23577 static inline uint32_t ATTRIBUTE_PURE 23578 _3DSTATE_DRAWING_RECTANGLE_DWordLength_start(const struct gen_device_info *devinfo) 23579 { 23580 switch (devinfo->gen) { 23581 case 10: return 0; 23582 case 9: return 0; 23583 case 8: return 0; 23584 case 7: 23585 if (devinfo->is_haswell) { 23586 return 0; 23587 } else { 23588 return 0; 23589 } 23590 case 6: return 0; 23591 case 5: return 0; 23592 case 4: 23593 if (devinfo->is_g4x) { 23594 return 0; 23595 } else { 23596 return 0; 23597 } 23598 default: 23599 unreachable("Invalid hardware generation"); 23600 } 23601 } 23602 23603 23604 23605 /* 3DSTATE_DRAWING_RECTANGLE::Drawing Rectangle Origin X */ 23606 23607 23608 #define GEN10_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 23609 #define GEN9_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 23610 #define GEN8_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 23611 #define GEN75_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 23612 #define GEN7_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 23613 #define GEN6_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 23614 #define GEN5_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 23615 #define GEN45_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 23616 #define GEN4_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 23617 23618 static inline uint32_t ATTRIBUTE_PURE 23619 _3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits(const struct gen_device_info *devinfo) 23620 { 23621 switch (devinfo->gen) { 23622 case 10: return 16; 23623 case 9: return 16; 23624 case 8: return 16; 23625 case 7: 23626 if (devinfo->is_haswell) { 23627 return 16; 23628 } else { 23629 return 16; 23630 } 23631 case 6: return 16; 23632 case 5: return 16; 23633 case 4: 23634 if (devinfo->is_g4x) { 23635 return 16; 23636 } else { 23637 return 16; 23638 } 23639 default: 23640 unreachable("Invalid hardware generation"); 23641 } 23642 } 23643 23644 23645 23646 #define GEN10_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 23647 #define GEN9_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 23648 #define GEN8_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 23649 #define GEN75_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 23650 #define GEN7_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 23651 #define GEN6_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 23652 #define GEN5_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 23653 #define GEN45_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 23654 #define GEN4_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 23655 23656 static inline uint32_t ATTRIBUTE_PURE 23657 _3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start(const struct gen_device_info *devinfo) 23658 { 23659 switch (devinfo->gen) { 23660 case 10: return 96; 23661 case 9: return 96; 23662 case 8: return 96; 23663 case 7: 23664 if (devinfo->is_haswell) { 23665 return 96; 23666 } else { 23667 return 96; 23668 } 23669 case 6: return 96; 23670 case 5: return 96; 23671 case 4: 23672 if (devinfo->is_g4x) { 23673 return 96; 23674 } else { 23675 return 96; 23676 } 23677 default: 23678 unreachable("Invalid hardware generation"); 23679 } 23680 } 23681 23682 23683 23684 /* 3DSTATE_DRAWING_RECTANGLE::Drawing Rectangle Origin Y */ 23685 23686 23687 #define GEN10_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 23688 #define GEN9_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 23689 #define GEN8_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 23690 #define GEN75_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 23691 #define GEN7_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 23692 #define GEN6_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 23693 #define GEN5_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 23694 #define GEN45_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 23695 #define GEN4_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 23696 23697 static inline uint32_t ATTRIBUTE_PURE 23698 _3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits(const struct gen_device_info *devinfo) 23699 { 23700 switch (devinfo->gen) { 23701 case 10: return 16; 23702 case 9: return 16; 23703 case 8: return 16; 23704 case 7: 23705 if (devinfo->is_haswell) { 23706 return 16; 23707 } else { 23708 return 16; 23709 } 23710 case 6: return 16; 23711 case 5: return 16; 23712 case 4: 23713 if (devinfo->is_g4x) { 23714 return 16; 23715 } else { 23716 return 16; 23717 } 23718 default: 23719 unreachable("Invalid hardware generation"); 23720 } 23721 } 23722 23723 23724 23725 #define GEN10_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 23726 #define GEN9_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 23727 #define GEN8_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 23728 #define GEN75_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 23729 #define GEN7_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 23730 #define GEN6_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 23731 #define GEN5_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 23732 #define GEN45_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 23733 #define GEN4_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 23734 23735 static inline uint32_t ATTRIBUTE_PURE 23736 _3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start(const struct gen_device_info *devinfo) 23737 { 23738 switch (devinfo->gen) { 23739 case 10: return 112; 23740 case 9: return 112; 23741 case 8: return 112; 23742 case 7: 23743 if (devinfo->is_haswell) { 23744 return 112; 23745 } else { 23746 return 112; 23747 } 23748 case 6: return 112; 23749 case 5: return 112; 23750 case 4: 23751 if (devinfo->is_g4x) { 23752 return 112; 23753 } else { 23754 return 112; 23755 } 23756 default: 23757 unreachable("Invalid hardware generation"); 23758 } 23759 } 23760 23761 23762 23763 /* 3DSTATE_DS */ 23764 23765 23766 #define GEN10_3DSTATE_DS_length 11 23767 #define GEN9_3DSTATE_DS_length 11 23768 #define GEN8_3DSTATE_DS_length 9 23769 #define GEN75_3DSTATE_DS_length 6 23770 #define GEN7_3DSTATE_DS_length 6 23771 23772 static inline uint32_t ATTRIBUTE_PURE 23773 _3DSTATE_DS_length(const struct gen_device_info *devinfo) 23774 { 23775 switch (devinfo->gen) { 23776 case 10: return 11; 23777 case 9: return 11; 23778 case 8: return 9; 23779 case 7: 23780 if (devinfo->is_haswell) { 23781 return 6; 23782 } else { 23783 return 6; 23784 } 23785 case 6: return 0; 23786 case 5: return 0; 23787 case 4: 23788 if (devinfo->is_g4x) { 23789 return 0; 23790 } else { 23791 return 0; 23792 } 23793 default: 23794 unreachable("Invalid hardware generation"); 23795 } 23796 } 23797 23798 23799 23800 /* 3DSTATE_DS::3D Command Opcode */ 23801 23802 23803 #define GEN10_3DSTATE_DS_3DCommandOpcode_bits 3 23804 #define GEN9_3DSTATE_DS_3DCommandOpcode_bits 3 23805 #define GEN8_3DSTATE_DS_3DCommandOpcode_bits 3 23806 #define GEN75_3DSTATE_DS_3DCommandOpcode_bits 3 23807 #define GEN7_3DSTATE_DS_3DCommandOpcode_bits 3 23808 23809 static inline uint32_t ATTRIBUTE_PURE 23810 _3DSTATE_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 23811 { 23812 switch (devinfo->gen) { 23813 case 10: return 3; 23814 case 9: return 3; 23815 case 8: return 3; 23816 case 7: 23817 if (devinfo->is_haswell) { 23818 return 3; 23819 } else { 23820 return 3; 23821 } 23822 case 6: return 0; 23823 case 5: return 0; 23824 case 4: 23825 if (devinfo->is_g4x) { 23826 return 0; 23827 } else { 23828 return 0; 23829 } 23830 default: 23831 unreachable("Invalid hardware generation"); 23832 } 23833 } 23834 23835 23836 23837 #define GEN10_3DSTATE_DS_3DCommandOpcode_start 24 23838 #define GEN9_3DSTATE_DS_3DCommandOpcode_start 24 23839 #define GEN8_3DSTATE_DS_3DCommandOpcode_start 24 23840 #define GEN75_3DSTATE_DS_3DCommandOpcode_start 24 23841 #define GEN7_3DSTATE_DS_3DCommandOpcode_start 24 23842 23843 static inline uint32_t ATTRIBUTE_PURE 23844 _3DSTATE_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 23845 { 23846 switch (devinfo->gen) { 23847 case 10: return 24; 23848 case 9: return 24; 23849 case 8: return 24; 23850 case 7: 23851 if (devinfo->is_haswell) { 23852 return 24; 23853 } else { 23854 return 24; 23855 } 23856 case 6: return 0; 23857 case 5: return 0; 23858 case 4: 23859 if (devinfo->is_g4x) { 23860 return 0; 23861 } else { 23862 return 0; 23863 } 23864 default: 23865 unreachable("Invalid hardware generation"); 23866 } 23867 } 23868 23869 23870 23871 /* 3DSTATE_DS::3D Command Sub Opcode */ 23872 23873 23874 #define GEN10_3DSTATE_DS_3DCommandSubOpcode_bits 8 23875 #define GEN9_3DSTATE_DS_3DCommandSubOpcode_bits 8 23876 #define GEN8_3DSTATE_DS_3DCommandSubOpcode_bits 8 23877 #define GEN75_3DSTATE_DS_3DCommandSubOpcode_bits 8 23878 #define GEN7_3DSTATE_DS_3DCommandSubOpcode_bits 8 23879 23880 static inline uint32_t ATTRIBUTE_PURE 23881 _3DSTATE_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 23882 { 23883 switch (devinfo->gen) { 23884 case 10: return 8; 23885 case 9: return 8; 23886 case 8: return 8; 23887 case 7: 23888 if (devinfo->is_haswell) { 23889 return 8; 23890 } else { 23891 return 8; 23892 } 23893 case 6: return 0; 23894 case 5: return 0; 23895 case 4: 23896 if (devinfo->is_g4x) { 23897 return 0; 23898 } else { 23899 return 0; 23900 } 23901 default: 23902 unreachable("Invalid hardware generation"); 23903 } 23904 } 23905 23906 23907 23908 #define GEN10_3DSTATE_DS_3DCommandSubOpcode_start 16 23909 #define GEN9_3DSTATE_DS_3DCommandSubOpcode_start 16 23910 #define GEN8_3DSTATE_DS_3DCommandSubOpcode_start 16 23911 #define GEN75_3DSTATE_DS_3DCommandSubOpcode_start 16 23912 #define GEN7_3DSTATE_DS_3DCommandSubOpcode_start 16 23913 23914 static inline uint32_t ATTRIBUTE_PURE 23915 _3DSTATE_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 23916 { 23917 switch (devinfo->gen) { 23918 case 10: return 16; 23919 case 9: return 16; 23920 case 8: return 16; 23921 case 7: 23922 if (devinfo->is_haswell) { 23923 return 16; 23924 } else { 23925 return 16; 23926 } 23927 case 6: return 0; 23928 case 5: return 0; 23929 case 4: 23930 if (devinfo->is_g4x) { 23931 return 0; 23932 } else { 23933 return 0; 23934 } 23935 default: 23936 unreachable("Invalid hardware generation"); 23937 } 23938 } 23939 23940 23941 23942 /* 3DSTATE_DS::Accesses UAV */ 23943 23944 23945 #define GEN10_3DSTATE_DS_AccessesUAV_bits 1 23946 #define GEN9_3DSTATE_DS_AccessesUAV_bits 1 23947 #define GEN8_3DSTATE_DS_AccessesUAV_bits 1 23948 #define GEN75_3DSTATE_DS_AccessesUAV_bits 1 23949 23950 static inline uint32_t ATTRIBUTE_PURE 23951 _3DSTATE_DS_AccessesUAV_bits(const struct gen_device_info *devinfo) 23952 { 23953 switch (devinfo->gen) { 23954 case 10: return 1; 23955 case 9: return 1; 23956 case 8: return 1; 23957 case 7: 23958 if (devinfo->is_haswell) { 23959 return 1; 23960 } else { 23961 return 0; 23962 } 23963 case 6: return 0; 23964 case 5: return 0; 23965 case 4: 23966 if (devinfo->is_g4x) { 23967 return 0; 23968 } else { 23969 return 0; 23970 } 23971 default: 23972 unreachable("Invalid hardware generation"); 23973 } 23974 } 23975 23976 23977 23978 #define GEN10_3DSTATE_DS_AccessesUAV_start 110 23979 #define GEN9_3DSTATE_DS_AccessesUAV_start 110 23980 #define GEN8_3DSTATE_DS_AccessesUAV_start 110 23981 #define GEN75_3DSTATE_DS_AccessesUAV_start 78 23982 23983 static inline uint32_t ATTRIBUTE_PURE 23984 _3DSTATE_DS_AccessesUAV_start(const struct gen_device_info *devinfo) 23985 { 23986 switch (devinfo->gen) { 23987 case 10: return 110; 23988 case 9: return 110; 23989 case 8: return 110; 23990 case 7: 23991 if (devinfo->is_haswell) { 23992 return 78; 23993 } else { 23994 return 0; 23995 } 23996 case 6: return 0; 23997 case 5: return 0; 23998 case 4: 23999 if (devinfo->is_g4x) { 24000 return 0; 24001 } else { 24002 return 0; 24003 } 24004 default: 24005 unreachable("Invalid hardware generation"); 24006 } 24007 } 24008 24009 24010 24011 /* 3DSTATE_DS::Binding Table Entry Count */ 24012 24013 24014 #define GEN10_3DSTATE_DS_BindingTableEntryCount_bits 8 24015 #define GEN9_3DSTATE_DS_BindingTableEntryCount_bits 8 24016 #define GEN8_3DSTATE_DS_BindingTableEntryCount_bits 8 24017 #define GEN75_3DSTATE_DS_BindingTableEntryCount_bits 8 24018 #define GEN7_3DSTATE_DS_BindingTableEntryCount_bits 8 24019 24020 static inline uint32_t ATTRIBUTE_PURE 24021 _3DSTATE_DS_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) 24022 { 24023 switch (devinfo->gen) { 24024 case 10: return 8; 24025 case 9: return 8; 24026 case 8: return 8; 24027 case 7: 24028 if (devinfo->is_haswell) { 24029 return 8; 24030 } else { 24031 return 8; 24032 } 24033 case 6: return 0; 24034 case 5: return 0; 24035 case 4: 24036 if (devinfo->is_g4x) { 24037 return 0; 24038 } else { 24039 return 0; 24040 } 24041 default: 24042 unreachable("Invalid hardware generation"); 24043 } 24044 } 24045 24046 24047 24048 #define GEN10_3DSTATE_DS_BindingTableEntryCount_start 114 24049 #define GEN9_3DSTATE_DS_BindingTableEntryCount_start 114 24050 #define GEN8_3DSTATE_DS_BindingTableEntryCount_start 114 24051 #define GEN75_3DSTATE_DS_BindingTableEntryCount_start 82 24052 #define GEN7_3DSTATE_DS_BindingTableEntryCount_start 82 24053 24054 static inline uint32_t ATTRIBUTE_PURE 24055 _3DSTATE_DS_BindingTableEntryCount_start(const struct gen_device_info *devinfo) 24056 { 24057 switch (devinfo->gen) { 24058 case 10: return 114; 24059 case 9: return 114; 24060 case 8: return 114; 24061 case 7: 24062 if (devinfo->is_haswell) { 24063 return 82; 24064 } else { 24065 return 82; 24066 } 24067 case 6: return 0; 24068 case 5: return 0; 24069 case 4: 24070 if (devinfo->is_g4x) { 24071 return 0; 24072 } else { 24073 return 0; 24074 } 24075 default: 24076 unreachable("Invalid hardware generation"); 24077 } 24078 } 24079 24080 24081 24082 /* 3DSTATE_DS::Cache Disable */ 24083 24084 24085 #define GEN10_3DSTATE_DS_CacheDisable_bits 1 24086 #define GEN9_3DSTATE_DS_CacheDisable_bits 1 24087 #define GEN8_3DSTATE_DS_CacheDisable_bits 1 24088 24089 static inline uint32_t ATTRIBUTE_PURE 24090 _3DSTATE_DS_CacheDisable_bits(const struct gen_device_info *devinfo) 24091 { 24092 switch (devinfo->gen) { 24093 case 10: return 1; 24094 case 9: return 1; 24095 case 8: return 1; 24096 case 7: 24097 if (devinfo->is_haswell) { 24098 return 0; 24099 } else { 24100 return 0; 24101 } 24102 case 6: return 0; 24103 case 5: return 0; 24104 case 4: 24105 if (devinfo->is_g4x) { 24106 return 0; 24107 } else { 24108 return 0; 24109 } 24110 default: 24111 unreachable("Invalid hardware generation"); 24112 } 24113 } 24114 24115 24116 24117 #define GEN10_3DSTATE_DS_CacheDisable_start 225 24118 #define GEN9_3DSTATE_DS_CacheDisable_start 225 24119 #define GEN8_3DSTATE_DS_CacheDisable_start 225 24120 24121 static inline uint32_t ATTRIBUTE_PURE 24122 _3DSTATE_DS_CacheDisable_start(const struct gen_device_info *devinfo) 24123 { 24124 switch (devinfo->gen) { 24125 case 10: return 225; 24126 case 9: return 225; 24127 case 8: return 225; 24128 case 7: 24129 if (devinfo->is_haswell) { 24130 return 0; 24131 } else { 24132 return 0; 24133 } 24134 case 6: return 0; 24135 case 5: return 0; 24136 case 4: 24137 if (devinfo->is_g4x) { 24138 return 0; 24139 } else { 24140 return 0; 24141 } 24142 default: 24143 unreachable("Invalid hardware generation"); 24144 } 24145 } 24146 24147 24148 24149 /* 3DSTATE_DS::Command SubType */ 24150 24151 24152 #define GEN10_3DSTATE_DS_CommandSubType_bits 2 24153 #define GEN9_3DSTATE_DS_CommandSubType_bits 2 24154 #define GEN8_3DSTATE_DS_CommandSubType_bits 2 24155 #define GEN75_3DSTATE_DS_CommandSubType_bits 2 24156 #define GEN7_3DSTATE_DS_CommandSubType_bits 2 24157 24158 static inline uint32_t ATTRIBUTE_PURE 24159 _3DSTATE_DS_CommandSubType_bits(const struct gen_device_info *devinfo) 24160 { 24161 switch (devinfo->gen) { 24162 case 10: return 2; 24163 case 9: return 2; 24164 case 8: return 2; 24165 case 7: 24166 if (devinfo->is_haswell) { 24167 return 2; 24168 } else { 24169 return 2; 24170 } 24171 case 6: return 0; 24172 case 5: return 0; 24173 case 4: 24174 if (devinfo->is_g4x) { 24175 return 0; 24176 } else { 24177 return 0; 24178 } 24179 default: 24180 unreachable("Invalid hardware generation"); 24181 } 24182 } 24183 24184 24185 24186 #define GEN10_3DSTATE_DS_CommandSubType_start 27 24187 #define GEN9_3DSTATE_DS_CommandSubType_start 27 24188 #define GEN8_3DSTATE_DS_CommandSubType_start 27 24189 #define GEN75_3DSTATE_DS_CommandSubType_start 27 24190 #define GEN7_3DSTATE_DS_CommandSubType_start 27 24191 24192 static inline uint32_t ATTRIBUTE_PURE 24193 _3DSTATE_DS_CommandSubType_start(const struct gen_device_info *devinfo) 24194 { 24195 switch (devinfo->gen) { 24196 case 10: return 27; 24197 case 9: return 27; 24198 case 8: return 27; 24199 case 7: 24200 if (devinfo->is_haswell) { 24201 return 27; 24202 } else { 24203 return 27; 24204 } 24205 case 6: return 0; 24206 case 5: return 0; 24207 case 4: 24208 if (devinfo->is_g4x) { 24209 return 0; 24210 } else { 24211 return 0; 24212 } 24213 default: 24214 unreachable("Invalid hardware generation"); 24215 } 24216 } 24217 24218 24219 24220 /* 3DSTATE_DS::Command Type */ 24221 24222 24223 #define GEN10_3DSTATE_DS_CommandType_bits 3 24224 #define GEN9_3DSTATE_DS_CommandType_bits 3 24225 #define GEN8_3DSTATE_DS_CommandType_bits 3 24226 #define GEN75_3DSTATE_DS_CommandType_bits 3 24227 #define GEN7_3DSTATE_DS_CommandType_bits 3 24228 24229 static inline uint32_t ATTRIBUTE_PURE 24230 _3DSTATE_DS_CommandType_bits(const struct gen_device_info *devinfo) 24231 { 24232 switch (devinfo->gen) { 24233 case 10: return 3; 24234 case 9: return 3; 24235 case 8: return 3; 24236 case 7: 24237 if (devinfo->is_haswell) { 24238 return 3; 24239 } else { 24240 return 3; 24241 } 24242 case 6: return 0; 24243 case 5: return 0; 24244 case 4: 24245 if (devinfo->is_g4x) { 24246 return 0; 24247 } else { 24248 return 0; 24249 } 24250 default: 24251 unreachable("Invalid hardware generation"); 24252 } 24253 } 24254 24255 24256 24257 #define GEN10_3DSTATE_DS_CommandType_start 29 24258 #define GEN9_3DSTATE_DS_CommandType_start 29 24259 #define GEN8_3DSTATE_DS_CommandType_start 29 24260 #define GEN75_3DSTATE_DS_CommandType_start 29 24261 #define GEN7_3DSTATE_DS_CommandType_start 29 24262 24263 static inline uint32_t ATTRIBUTE_PURE 24264 _3DSTATE_DS_CommandType_start(const struct gen_device_info *devinfo) 24265 { 24266 switch (devinfo->gen) { 24267 case 10: return 29; 24268 case 9: return 29; 24269 case 8: return 29; 24270 case 7: 24271 if (devinfo->is_haswell) { 24272 return 29; 24273 } else { 24274 return 29; 24275 } 24276 case 6: return 0; 24277 case 5: return 0; 24278 case 4: 24279 if (devinfo->is_g4x) { 24280 return 0; 24281 } else { 24282 return 0; 24283 } 24284 default: 24285 unreachable("Invalid hardware generation"); 24286 } 24287 } 24288 24289 24290 24291 /* 3DSTATE_DS::Compute W Coordinate Enable */ 24292 24293 24294 #define GEN10_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 24295 #define GEN9_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 24296 #define GEN8_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 24297 #define GEN75_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 24298 #define GEN7_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 24299 24300 static inline uint32_t ATTRIBUTE_PURE 24301 _3DSTATE_DS_ComputeWCoordinateEnable_bits(const struct gen_device_info *devinfo) 24302 { 24303 switch (devinfo->gen) { 24304 case 10: return 1; 24305 case 9: return 1; 24306 case 8: return 1; 24307 case 7: 24308 if (devinfo->is_haswell) { 24309 return 1; 24310 } else { 24311 return 1; 24312 } 24313 case 6: return 0; 24314 case 5: return 0; 24315 case 4: 24316 if (devinfo->is_g4x) { 24317 return 0; 24318 } else { 24319 return 0; 24320 } 24321 default: 24322 unreachable("Invalid hardware generation"); 24323 } 24324 } 24325 24326 24327 24328 #define GEN10_3DSTATE_DS_ComputeWCoordinateEnable_start 226 24329 #define GEN9_3DSTATE_DS_ComputeWCoordinateEnable_start 226 24330 #define GEN8_3DSTATE_DS_ComputeWCoordinateEnable_start 226 24331 #define GEN75_3DSTATE_DS_ComputeWCoordinateEnable_start 162 24332 #define GEN7_3DSTATE_DS_ComputeWCoordinateEnable_start 162 24333 24334 static inline uint32_t ATTRIBUTE_PURE 24335 _3DSTATE_DS_ComputeWCoordinateEnable_start(const struct gen_device_info *devinfo) 24336 { 24337 switch (devinfo->gen) { 24338 case 10: return 226; 24339 case 9: return 226; 24340 case 8: return 226; 24341 case 7: 24342 if (devinfo->is_haswell) { 24343 return 162; 24344 } else { 24345 return 162; 24346 } 24347 case 6: return 0; 24348 case 5: return 0; 24349 case 4: 24350 if (devinfo->is_g4x) { 24351 return 0; 24352 } else { 24353 return 0; 24354 } 24355 default: 24356 unreachable("Invalid hardware generation"); 24357 } 24358 } 24359 24360 24361 24362 /* 3DSTATE_DS::DS Cache Disable */ 24363 24364 24365 #define GEN75_3DSTATE_DS_DSCacheDisable_bits 1 24366 #define GEN7_3DSTATE_DS_DSCacheDisable_bits 1 24367 24368 static inline uint32_t ATTRIBUTE_PURE 24369 _3DSTATE_DS_DSCacheDisable_bits(const struct gen_device_info *devinfo) 24370 { 24371 switch (devinfo->gen) { 24372 case 10: return 0; 24373 case 9: return 0; 24374 case 8: return 0; 24375 case 7: 24376 if (devinfo->is_haswell) { 24377 return 1; 24378 } else { 24379 return 1; 24380 } 24381 case 6: return 0; 24382 case 5: return 0; 24383 case 4: 24384 if (devinfo->is_g4x) { 24385 return 0; 24386 } else { 24387 return 0; 24388 } 24389 default: 24390 unreachable("Invalid hardware generation"); 24391 } 24392 } 24393 24394 24395 24396 #define GEN75_3DSTATE_DS_DSCacheDisable_start 161 24397 #define GEN7_3DSTATE_DS_DSCacheDisable_start 161 24398 24399 static inline uint32_t ATTRIBUTE_PURE 24400 _3DSTATE_DS_DSCacheDisable_start(const struct gen_device_info *devinfo) 24401 { 24402 switch (devinfo->gen) { 24403 case 10: return 0; 24404 case 9: return 0; 24405 case 8: return 0; 24406 case 7: 24407 if (devinfo->is_haswell) { 24408 return 161; 24409 } else { 24410 return 161; 24411 } 24412 case 6: return 0; 24413 case 5: return 0; 24414 case 4: 24415 if (devinfo->is_g4x) { 24416 return 0; 24417 } else { 24418 return 0; 24419 } 24420 default: 24421 unreachable("Invalid hardware generation"); 24422 } 24423 } 24424 24425 24426 24427 /* 3DSTATE_DS::DUAL_PATCH Kernel Start Pointer */ 24428 24429 24430 #define GEN10_3DSTATE_DS_DUAL_PATCHKernelStartPointer_bits 58 24431 #define GEN9_3DSTATE_DS_DUAL_PATCHKernelStartPointer_bits 58 24432 24433 static inline uint32_t ATTRIBUTE_PURE 24434 _3DSTATE_DS_DUAL_PATCHKernelStartPointer_bits(const struct gen_device_info *devinfo) 24435 { 24436 switch (devinfo->gen) { 24437 case 10: return 58; 24438 case 9: return 58; 24439 case 8: return 0; 24440 case 7: 24441 if (devinfo->is_haswell) { 24442 return 0; 24443 } else { 24444 return 0; 24445 } 24446 case 6: return 0; 24447 case 5: return 0; 24448 case 4: 24449 if (devinfo->is_g4x) { 24450 return 0; 24451 } else { 24452 return 0; 24453 } 24454 default: 24455 unreachable("Invalid hardware generation"); 24456 } 24457 } 24458 24459 24460 24461 #define GEN10_3DSTATE_DS_DUAL_PATCHKernelStartPointer_start 294 24462 #define GEN9_3DSTATE_DS_DUAL_PATCHKernelStartPointer_start 294 24463 24464 static inline uint32_t ATTRIBUTE_PURE 24465 _3DSTATE_DS_DUAL_PATCHKernelStartPointer_start(const struct gen_device_info *devinfo) 24466 { 24467 switch (devinfo->gen) { 24468 case 10: return 294; 24469 case 9: return 294; 24470 case 8: return 0; 24471 case 7: 24472 if (devinfo->is_haswell) { 24473 return 0; 24474 } else { 24475 return 0; 24476 } 24477 case 6: return 0; 24478 case 5: return 0; 24479 case 4: 24480 if (devinfo->is_g4x) { 24481 return 0; 24482 } else { 24483 return 0; 24484 } 24485 default: 24486 unreachable("Invalid hardware generation"); 24487 } 24488 } 24489 24490 24491 24492 /* 3DSTATE_DS::DWord Length */ 24493 24494 24495 #define GEN10_3DSTATE_DS_DWordLength_bits 8 24496 #define GEN9_3DSTATE_DS_DWordLength_bits 8 24497 #define GEN8_3DSTATE_DS_DWordLength_bits 8 24498 #define GEN75_3DSTATE_DS_DWordLength_bits 8 24499 #define GEN7_3DSTATE_DS_DWordLength_bits 8 24500 24501 static inline uint32_t ATTRIBUTE_PURE 24502 _3DSTATE_DS_DWordLength_bits(const struct gen_device_info *devinfo) 24503 { 24504 switch (devinfo->gen) { 24505 case 10: return 8; 24506 case 9: return 8; 24507 case 8: return 8; 24508 case 7: 24509 if (devinfo->is_haswell) { 24510 return 8; 24511 } else { 24512 return 8; 24513 } 24514 case 6: return 0; 24515 case 5: return 0; 24516 case 4: 24517 if (devinfo->is_g4x) { 24518 return 0; 24519 } else { 24520 return 0; 24521 } 24522 default: 24523 unreachable("Invalid hardware generation"); 24524 } 24525 } 24526 24527 24528 24529 #define GEN10_3DSTATE_DS_DWordLength_start 0 24530 #define GEN9_3DSTATE_DS_DWordLength_start 0 24531 #define GEN8_3DSTATE_DS_DWordLength_start 0 24532 #define GEN75_3DSTATE_DS_DWordLength_start 0 24533 #define GEN7_3DSTATE_DS_DWordLength_start 0 24534 24535 static inline uint32_t ATTRIBUTE_PURE 24536 _3DSTATE_DS_DWordLength_start(const struct gen_device_info *devinfo) 24537 { 24538 switch (devinfo->gen) { 24539 case 10: return 0; 24540 case 9: return 0; 24541 case 8: return 0; 24542 case 7: 24543 if (devinfo->is_haswell) { 24544 return 0; 24545 } else { 24546 return 0; 24547 } 24548 case 6: return 0; 24549 case 5: return 0; 24550 case 4: 24551 if (devinfo->is_g4x) { 24552 return 0; 24553 } else { 24554 return 0; 24555 } 24556 default: 24557 unreachable("Invalid hardware generation"); 24558 } 24559 } 24560 24561 24562 24563 /* 3DSTATE_DS::Dispatch GRF Start Register For URB Data */ 24564 24565 24566 #define GEN10_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 24567 #define GEN9_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 24568 #define GEN8_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 24569 #define GEN75_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 24570 #define GEN7_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 24571 24572 static inline uint32_t ATTRIBUTE_PURE 24573 _3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits(const struct gen_device_info *devinfo) 24574 { 24575 switch (devinfo->gen) { 24576 case 10: return 5; 24577 case 9: return 5; 24578 case 8: return 5; 24579 case 7: 24580 if (devinfo->is_haswell) { 24581 return 5; 24582 } else { 24583 return 5; 24584 } 24585 case 6: return 0; 24586 case 5: return 0; 24587 case 4: 24588 if (devinfo->is_g4x) { 24589 return 0; 24590 } else { 24591 return 0; 24592 } 24593 default: 24594 unreachable("Invalid hardware generation"); 24595 } 24596 } 24597 24598 24599 24600 #define GEN10_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 212 24601 #define GEN9_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 212 24602 #define GEN8_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 212 24603 #define GEN75_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 148 24604 #define GEN7_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 148 24605 24606 static inline uint32_t ATTRIBUTE_PURE 24607 _3DSTATE_DS_DispatchGRFStartRegisterForURBData_start(const struct gen_device_info *devinfo) 24608 { 24609 switch (devinfo->gen) { 24610 case 10: return 212; 24611 case 9: return 212; 24612 case 8: return 212; 24613 case 7: 24614 if (devinfo->is_haswell) { 24615 return 148; 24616 } else { 24617 return 148; 24618 } 24619 case 6: return 0; 24620 case 5: return 0; 24621 case 4: 24622 if (devinfo->is_g4x) { 24623 return 0; 24624 } else { 24625 return 0; 24626 } 24627 default: 24628 unreachable("Invalid hardware generation"); 24629 } 24630 } 24631 24632 24633 24634 /* 3DSTATE_DS::Dispatch Mode */ 24635 24636 24637 #define GEN10_3DSTATE_DS_DispatchMode_bits 2 24638 #define GEN9_3DSTATE_DS_DispatchMode_bits 2 24639 #define GEN8_3DSTATE_DS_DispatchMode_bits 1 24640 24641 static inline uint32_t ATTRIBUTE_PURE 24642 _3DSTATE_DS_DispatchMode_bits(const struct gen_device_info *devinfo) 24643 { 24644 switch (devinfo->gen) { 24645 case 10: return 2; 24646 case 9: return 2; 24647 case 8: return 1; 24648 case 7: 24649 if (devinfo->is_haswell) { 24650 return 0; 24651 } else { 24652 return 0; 24653 } 24654 case 6: return 0; 24655 case 5: return 0; 24656 case 4: 24657 if (devinfo->is_g4x) { 24658 return 0; 24659 } else { 24660 return 0; 24661 } 24662 default: 24663 unreachable("Invalid hardware generation"); 24664 } 24665 } 24666 24667 24668 24669 #define GEN10_3DSTATE_DS_DispatchMode_start 227 24670 #define GEN9_3DSTATE_DS_DispatchMode_start 227 24671 #define GEN8_3DSTATE_DS_DispatchMode_start 227 24672 24673 static inline uint32_t ATTRIBUTE_PURE 24674 _3DSTATE_DS_DispatchMode_start(const struct gen_device_info *devinfo) 24675 { 24676 switch (devinfo->gen) { 24677 case 10: return 227; 24678 case 9: return 227; 24679 case 8: return 227; 24680 case 7: 24681 if (devinfo->is_haswell) { 24682 return 0; 24683 } else { 24684 return 0; 24685 } 24686 case 6: return 0; 24687 case 5: return 0; 24688 case 4: 24689 if (devinfo->is_g4x) { 24690 return 0; 24691 } else { 24692 return 0; 24693 } 24694 default: 24695 unreachable("Invalid hardware generation"); 24696 } 24697 } 24698 24699 24700 24701 /* 3DSTATE_DS::Enable */ 24702 24703 24704 #define GEN10_3DSTATE_DS_Enable_bits 1 24705 #define GEN9_3DSTATE_DS_Enable_bits 1 24706 #define GEN8_3DSTATE_DS_Enable_bits 1 24707 #define GEN75_3DSTATE_DS_Enable_bits 1 24708 #define GEN7_3DSTATE_DS_Enable_bits 1 24709 24710 static inline uint32_t ATTRIBUTE_PURE 24711 _3DSTATE_DS_Enable_bits(const struct gen_device_info *devinfo) 24712 { 24713 switch (devinfo->gen) { 24714 case 10: return 1; 24715 case 9: return 1; 24716 case 8: return 1; 24717 case 7: 24718 if (devinfo->is_haswell) { 24719 return 1; 24720 } else { 24721 return 1; 24722 } 24723 case 6: return 0; 24724 case 5: return 0; 24725 case 4: 24726 if (devinfo->is_g4x) { 24727 return 0; 24728 } else { 24729 return 0; 24730 } 24731 default: 24732 unreachable("Invalid hardware generation"); 24733 } 24734 } 24735 24736 24737 24738 #define GEN10_3DSTATE_DS_Enable_start 224 24739 #define GEN9_3DSTATE_DS_Enable_start 224 24740 #define GEN8_3DSTATE_DS_Enable_start 224 24741 #define GEN75_3DSTATE_DS_Enable_start 160 24742 #define GEN7_3DSTATE_DS_Enable_start 160 24743 24744 static inline uint32_t ATTRIBUTE_PURE 24745 _3DSTATE_DS_Enable_start(const struct gen_device_info *devinfo) 24746 { 24747 switch (devinfo->gen) { 24748 case 10: return 224; 24749 case 9: return 224; 24750 case 8: return 224; 24751 case 7: 24752 if (devinfo->is_haswell) { 24753 return 160; 24754 } else { 24755 return 160; 24756 } 24757 case 6: return 0; 24758 case 5: return 0; 24759 case 4: 24760 if (devinfo->is_g4x) { 24761 return 0; 24762 } else { 24763 return 0; 24764 } 24765 default: 24766 unreachable("Invalid hardware generation"); 24767 } 24768 } 24769 24770 24771 24772 /* 3DSTATE_DS::Floating Point Mode */ 24773 24774 24775 #define GEN10_3DSTATE_DS_FloatingPointMode_bits 1 24776 #define GEN9_3DSTATE_DS_FloatingPointMode_bits 1 24777 #define GEN8_3DSTATE_DS_FloatingPointMode_bits 1 24778 #define GEN75_3DSTATE_DS_FloatingPointMode_bits 1 24779 #define GEN7_3DSTATE_DS_FloatingPointMode_bits 1 24780 24781 static inline uint32_t ATTRIBUTE_PURE 24782 _3DSTATE_DS_FloatingPointMode_bits(const struct gen_device_info *devinfo) 24783 { 24784 switch (devinfo->gen) { 24785 case 10: return 1; 24786 case 9: return 1; 24787 case 8: return 1; 24788 case 7: 24789 if (devinfo->is_haswell) { 24790 return 1; 24791 } else { 24792 return 1; 24793 } 24794 case 6: return 0; 24795 case 5: return 0; 24796 case 4: 24797 if (devinfo->is_g4x) { 24798 return 0; 24799 } else { 24800 return 0; 24801 } 24802 default: 24803 unreachable("Invalid hardware generation"); 24804 } 24805 } 24806 24807 24808 24809 #define GEN10_3DSTATE_DS_FloatingPointMode_start 112 24810 #define GEN9_3DSTATE_DS_FloatingPointMode_start 112 24811 #define GEN8_3DSTATE_DS_FloatingPointMode_start 112 24812 #define GEN75_3DSTATE_DS_FloatingPointMode_start 80 24813 #define GEN7_3DSTATE_DS_FloatingPointMode_start 80 24814 24815 static inline uint32_t ATTRIBUTE_PURE 24816 _3DSTATE_DS_FloatingPointMode_start(const struct gen_device_info *devinfo) 24817 { 24818 switch (devinfo->gen) { 24819 case 10: return 112; 24820 case 9: return 112; 24821 case 8: return 112; 24822 case 7: 24823 if (devinfo->is_haswell) { 24824 return 80; 24825 } else { 24826 return 80; 24827 } 24828 case 6: return 0; 24829 case 5: return 0; 24830 case 4: 24831 if (devinfo->is_g4x) { 24832 return 0; 24833 } else { 24834 return 0; 24835 } 24836 default: 24837 unreachable("Invalid hardware generation"); 24838 } 24839 } 24840 24841 24842 24843 /* 3DSTATE_DS::Illegal Opcode Exception Enable */ 24844 24845 24846 #define GEN10_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 24847 #define GEN9_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 24848 #define GEN8_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 24849 #define GEN75_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 24850 #define GEN7_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 24851 24852 static inline uint32_t ATTRIBUTE_PURE 24853 _3DSTATE_DS_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) 24854 { 24855 switch (devinfo->gen) { 24856 case 10: return 1; 24857 case 9: return 1; 24858 case 8: return 1; 24859 case 7: 24860 if (devinfo->is_haswell) { 24861 return 1; 24862 } else { 24863 return 1; 24864 } 24865 case 6: return 0; 24866 case 5: return 0; 24867 case 4: 24868 if (devinfo->is_g4x) { 24869 return 0; 24870 } else { 24871 return 0; 24872 } 24873 default: 24874 unreachable("Invalid hardware generation"); 24875 } 24876 } 24877 24878 24879 24880 #define GEN10_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 109 24881 #define GEN9_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 109 24882 #define GEN8_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 109 24883 #define GEN75_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 77 24884 #define GEN7_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 77 24885 24886 static inline uint32_t ATTRIBUTE_PURE 24887 _3DSTATE_DS_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) 24888 { 24889 switch (devinfo->gen) { 24890 case 10: return 109; 24891 case 9: return 109; 24892 case 8: return 109; 24893 case 7: 24894 if (devinfo->is_haswell) { 24895 return 77; 24896 } else { 24897 return 77; 24898 } 24899 case 6: return 0; 24900 case 5: return 0; 24901 case 4: 24902 if (devinfo->is_g4x) { 24903 return 0; 24904 } else { 24905 return 0; 24906 } 24907 default: 24908 unreachable("Invalid hardware generation"); 24909 } 24910 } 24911 24912 24913 24914 /* 3DSTATE_DS::Kernel Start Pointer */ 24915 24916 24917 #define GEN10_3DSTATE_DS_KernelStartPointer_bits 58 24918 #define GEN9_3DSTATE_DS_KernelStartPointer_bits 58 24919 #define GEN8_3DSTATE_DS_KernelStartPointer_bits 58 24920 #define GEN75_3DSTATE_DS_KernelStartPointer_bits 26 24921 #define GEN7_3DSTATE_DS_KernelStartPointer_bits 26 24922 24923 static inline uint32_t ATTRIBUTE_PURE 24924 _3DSTATE_DS_KernelStartPointer_bits(const struct gen_device_info *devinfo) 24925 { 24926 switch (devinfo->gen) { 24927 case 10: return 58; 24928 case 9: return 58; 24929 case 8: return 58; 24930 case 7: 24931 if (devinfo->is_haswell) { 24932 return 26; 24933 } else { 24934 return 26; 24935 } 24936 case 6: return 0; 24937 case 5: return 0; 24938 case 4: 24939 if (devinfo->is_g4x) { 24940 return 0; 24941 } else { 24942 return 0; 24943 } 24944 default: 24945 unreachable("Invalid hardware generation"); 24946 } 24947 } 24948 24949 24950 24951 #define GEN10_3DSTATE_DS_KernelStartPointer_start 38 24952 #define GEN9_3DSTATE_DS_KernelStartPointer_start 38 24953 #define GEN8_3DSTATE_DS_KernelStartPointer_start 38 24954 #define GEN75_3DSTATE_DS_KernelStartPointer_start 38 24955 #define GEN7_3DSTATE_DS_KernelStartPointer_start 38 24956 24957 static inline uint32_t ATTRIBUTE_PURE 24958 _3DSTATE_DS_KernelStartPointer_start(const struct gen_device_info *devinfo) 24959 { 24960 switch (devinfo->gen) { 24961 case 10: return 38; 24962 case 9: return 38; 24963 case 8: return 38; 24964 case 7: 24965 if (devinfo->is_haswell) { 24966 return 38; 24967 } else { 24968 return 38; 24969 } 24970 case 6: return 0; 24971 case 5: return 0; 24972 case 4: 24973 if (devinfo->is_g4x) { 24974 return 0; 24975 } else { 24976 return 0; 24977 } 24978 default: 24979 unreachable("Invalid hardware generation"); 24980 } 24981 } 24982 24983 24984 24985 /* 3DSTATE_DS::Maximum Number of Threads */ 24986 24987 24988 #define GEN10_3DSTATE_DS_MaximumNumberofThreads_bits 10 24989 #define GEN9_3DSTATE_DS_MaximumNumberofThreads_bits 9 24990 #define GEN8_3DSTATE_DS_MaximumNumberofThreads_bits 9 24991 #define GEN75_3DSTATE_DS_MaximumNumberofThreads_bits 9 24992 #define GEN7_3DSTATE_DS_MaximumNumberofThreads_bits 7 24993 24994 static inline uint32_t ATTRIBUTE_PURE 24995 _3DSTATE_DS_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) 24996 { 24997 switch (devinfo->gen) { 24998 case 10: return 10; 24999 case 9: return 9; 25000 case 8: return 9; 25001 case 7: 25002 if (devinfo->is_haswell) { 25003 return 9; 25004 } else { 25005 return 7; 25006 } 25007 case 6: return 0; 25008 case 5: return 0; 25009 case 4: 25010 if (devinfo->is_g4x) { 25011 return 0; 25012 } else { 25013 return 0; 25014 } 25015 default: 25016 unreachable("Invalid hardware generation"); 25017 } 25018 } 25019 25020 25021 25022 #define GEN10_3DSTATE_DS_MaximumNumberofThreads_start 245 25023 #define GEN9_3DSTATE_DS_MaximumNumberofThreads_start 245 25024 #define GEN8_3DSTATE_DS_MaximumNumberofThreads_start 245 25025 #define GEN75_3DSTATE_DS_MaximumNumberofThreads_start 181 25026 #define GEN7_3DSTATE_DS_MaximumNumberofThreads_start 185 25027 25028 static inline uint32_t ATTRIBUTE_PURE 25029 _3DSTATE_DS_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) 25030 { 25031 switch (devinfo->gen) { 25032 case 10: return 245; 25033 case 9: return 245; 25034 case 8: return 245; 25035 case 7: 25036 if (devinfo->is_haswell) { 25037 return 181; 25038 } else { 25039 return 185; 25040 } 25041 case 6: return 0; 25042 case 5: return 0; 25043 case 4: 25044 if (devinfo->is_g4x) { 25045 return 0; 25046 } else { 25047 return 0; 25048 } 25049 default: 25050 unreachable("Invalid hardware generation"); 25051 } 25052 } 25053 25054 25055 25056 /* 3DSTATE_DS::Patch URB Entry Read Length */ 25057 25058 25059 #define GEN10_3DSTATE_DS_PatchURBEntryReadLength_bits 7 25060 #define GEN9_3DSTATE_DS_PatchURBEntryReadLength_bits 7 25061 #define GEN8_3DSTATE_DS_PatchURBEntryReadLength_bits 7 25062 #define GEN75_3DSTATE_DS_PatchURBEntryReadLength_bits 7 25063 #define GEN7_3DSTATE_DS_PatchURBEntryReadLength_bits 7 25064 25065 static inline uint32_t ATTRIBUTE_PURE 25066 _3DSTATE_DS_PatchURBEntryReadLength_bits(const struct gen_device_info *devinfo) 25067 { 25068 switch (devinfo->gen) { 25069 case 10: return 7; 25070 case 9: return 7; 25071 case 8: return 7; 25072 case 7: 25073 if (devinfo->is_haswell) { 25074 return 7; 25075 } else { 25076 return 7; 25077 } 25078 case 6: return 0; 25079 case 5: return 0; 25080 case 4: 25081 if (devinfo->is_g4x) { 25082 return 0; 25083 } else { 25084 return 0; 25085 } 25086 default: 25087 unreachable("Invalid hardware generation"); 25088 } 25089 } 25090 25091 25092 25093 #define GEN10_3DSTATE_DS_PatchURBEntryReadLength_start 203 25094 #define GEN9_3DSTATE_DS_PatchURBEntryReadLength_start 203 25095 #define GEN8_3DSTATE_DS_PatchURBEntryReadLength_start 203 25096 #define GEN75_3DSTATE_DS_PatchURBEntryReadLength_start 139 25097 #define GEN7_3DSTATE_DS_PatchURBEntryReadLength_start 139 25098 25099 static inline uint32_t ATTRIBUTE_PURE 25100 _3DSTATE_DS_PatchURBEntryReadLength_start(const struct gen_device_info *devinfo) 25101 { 25102 switch (devinfo->gen) { 25103 case 10: return 203; 25104 case 9: return 203; 25105 case 8: return 203; 25106 case 7: 25107 if (devinfo->is_haswell) { 25108 return 139; 25109 } else { 25110 return 139; 25111 } 25112 case 6: return 0; 25113 case 5: return 0; 25114 case 4: 25115 if (devinfo->is_g4x) { 25116 return 0; 25117 } else { 25118 return 0; 25119 } 25120 default: 25121 unreachable("Invalid hardware generation"); 25122 } 25123 } 25124 25125 25126 25127 /* 3DSTATE_DS::Patch URB Entry Read Offset */ 25128 25129 25130 #define GEN10_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 25131 #define GEN9_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 25132 #define GEN8_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 25133 #define GEN75_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 25134 #define GEN7_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 25135 25136 static inline uint32_t ATTRIBUTE_PURE 25137 _3DSTATE_DS_PatchURBEntryReadOffset_bits(const struct gen_device_info *devinfo) 25138 { 25139 switch (devinfo->gen) { 25140 case 10: return 6; 25141 case 9: return 6; 25142 case 8: return 6; 25143 case 7: 25144 if (devinfo->is_haswell) { 25145 return 6; 25146 } else { 25147 return 6; 25148 } 25149 case 6: return 0; 25150 case 5: return 0; 25151 case 4: 25152 if (devinfo->is_g4x) { 25153 return 0; 25154 } else { 25155 return 0; 25156 } 25157 default: 25158 unreachable("Invalid hardware generation"); 25159 } 25160 } 25161 25162 25163 25164 #define GEN10_3DSTATE_DS_PatchURBEntryReadOffset_start 196 25165 #define GEN9_3DSTATE_DS_PatchURBEntryReadOffset_start 196 25166 #define GEN8_3DSTATE_DS_PatchURBEntryReadOffset_start 196 25167 #define GEN75_3DSTATE_DS_PatchURBEntryReadOffset_start 132 25168 #define GEN7_3DSTATE_DS_PatchURBEntryReadOffset_start 132 25169 25170 static inline uint32_t ATTRIBUTE_PURE 25171 _3DSTATE_DS_PatchURBEntryReadOffset_start(const struct gen_device_info *devinfo) 25172 { 25173 switch (devinfo->gen) { 25174 case 10: return 196; 25175 case 9: return 196; 25176 case 8: return 196; 25177 case 7: 25178 if (devinfo->is_haswell) { 25179 return 132; 25180 } else { 25181 return 132; 25182 } 25183 case 6: return 0; 25184 case 5: return 0; 25185 case 4: 25186 if (devinfo->is_g4x) { 25187 return 0; 25188 } else { 25189 return 0; 25190 } 25191 default: 25192 unreachable("Invalid hardware generation"); 25193 } 25194 } 25195 25196 25197 25198 /* 3DSTATE_DS::Per-Thread Scratch Space */ 25199 25200 25201 #define GEN10_3DSTATE_DS_PerThreadScratchSpace_bits 4 25202 #define GEN9_3DSTATE_DS_PerThreadScratchSpace_bits 4 25203 #define GEN8_3DSTATE_DS_PerThreadScratchSpace_bits 4 25204 #define GEN75_3DSTATE_DS_PerThreadScratchSpace_bits 4 25205 #define GEN7_3DSTATE_DS_PerThreadScratchSpace_bits 4 25206 25207 static inline uint32_t ATTRIBUTE_PURE 25208 _3DSTATE_DS_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) 25209 { 25210 switch (devinfo->gen) { 25211 case 10: return 4; 25212 case 9: return 4; 25213 case 8: return 4; 25214 case 7: 25215 if (devinfo->is_haswell) { 25216 return 4; 25217 } else { 25218 return 4; 25219 } 25220 case 6: return 0; 25221 case 5: return 0; 25222 case 4: 25223 if (devinfo->is_g4x) { 25224 return 0; 25225 } else { 25226 return 0; 25227 } 25228 default: 25229 unreachable("Invalid hardware generation"); 25230 } 25231 } 25232 25233 25234 25235 #define GEN10_3DSTATE_DS_PerThreadScratchSpace_start 128 25236 #define GEN9_3DSTATE_DS_PerThreadScratchSpace_start 128 25237 #define GEN8_3DSTATE_DS_PerThreadScratchSpace_start 128 25238 #define GEN75_3DSTATE_DS_PerThreadScratchSpace_start 96 25239 #define GEN7_3DSTATE_DS_PerThreadScratchSpace_start 96 25240 25241 static inline uint32_t ATTRIBUTE_PURE 25242 _3DSTATE_DS_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) 25243 { 25244 switch (devinfo->gen) { 25245 case 10: return 128; 25246 case 9: return 128; 25247 case 8: return 128; 25248 case 7: 25249 if (devinfo->is_haswell) { 25250 return 96; 25251 } else { 25252 return 96; 25253 } 25254 case 6: return 0; 25255 case 5: return 0; 25256 case 4: 25257 if (devinfo->is_g4x) { 25258 return 0; 25259 } else { 25260 return 0; 25261 } 25262 default: 25263 unreachable("Invalid hardware generation"); 25264 } 25265 } 25266 25267 25268 25269 /* 3DSTATE_DS::Sampler Count */ 25270 25271 25272 #define GEN10_3DSTATE_DS_SamplerCount_bits 3 25273 #define GEN9_3DSTATE_DS_SamplerCount_bits 3 25274 #define GEN8_3DSTATE_DS_SamplerCount_bits 3 25275 #define GEN75_3DSTATE_DS_SamplerCount_bits 3 25276 #define GEN7_3DSTATE_DS_SamplerCount_bits 3 25277 25278 static inline uint32_t ATTRIBUTE_PURE 25279 _3DSTATE_DS_SamplerCount_bits(const struct gen_device_info *devinfo) 25280 { 25281 switch (devinfo->gen) { 25282 case 10: return 3; 25283 case 9: return 3; 25284 case 8: return 3; 25285 case 7: 25286 if (devinfo->is_haswell) { 25287 return 3; 25288 } else { 25289 return 3; 25290 } 25291 case 6: return 0; 25292 case 5: return 0; 25293 case 4: 25294 if (devinfo->is_g4x) { 25295 return 0; 25296 } else { 25297 return 0; 25298 } 25299 default: 25300 unreachable("Invalid hardware generation"); 25301 } 25302 } 25303 25304 25305 25306 #define GEN10_3DSTATE_DS_SamplerCount_start 123 25307 #define GEN9_3DSTATE_DS_SamplerCount_start 123 25308 #define GEN8_3DSTATE_DS_SamplerCount_start 123 25309 #define GEN75_3DSTATE_DS_SamplerCount_start 91 25310 #define GEN7_3DSTATE_DS_SamplerCount_start 91 25311 25312 static inline uint32_t ATTRIBUTE_PURE 25313 _3DSTATE_DS_SamplerCount_start(const struct gen_device_info *devinfo) 25314 { 25315 switch (devinfo->gen) { 25316 case 10: return 123; 25317 case 9: return 123; 25318 case 8: return 123; 25319 case 7: 25320 if (devinfo->is_haswell) { 25321 return 91; 25322 } else { 25323 return 91; 25324 } 25325 case 6: return 0; 25326 case 5: return 0; 25327 case 4: 25328 if (devinfo->is_g4x) { 25329 return 0; 25330 } else { 25331 return 0; 25332 } 25333 default: 25334 unreachable("Invalid hardware generation"); 25335 } 25336 } 25337 25338 25339 25340 /* 3DSTATE_DS::Scratch Space Base Pointer */ 25341 25342 25343 #define GEN10_3DSTATE_DS_ScratchSpaceBasePointer_bits 54 25344 #define GEN9_3DSTATE_DS_ScratchSpaceBasePointer_bits 54 25345 #define GEN8_3DSTATE_DS_ScratchSpaceBasePointer_bits 54 25346 #define GEN75_3DSTATE_DS_ScratchSpaceBasePointer_bits 22 25347 #define GEN7_3DSTATE_DS_ScratchSpaceBasePointer_bits 22 25348 25349 static inline uint32_t ATTRIBUTE_PURE 25350 _3DSTATE_DS_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) 25351 { 25352 switch (devinfo->gen) { 25353 case 10: return 54; 25354 case 9: return 54; 25355 case 8: return 54; 25356 case 7: 25357 if (devinfo->is_haswell) { 25358 return 22; 25359 } else { 25360 return 22; 25361 } 25362 case 6: return 0; 25363 case 5: return 0; 25364 case 4: 25365 if (devinfo->is_g4x) { 25366 return 0; 25367 } else { 25368 return 0; 25369 } 25370 default: 25371 unreachable("Invalid hardware generation"); 25372 } 25373 } 25374 25375 25376 25377 #define GEN10_3DSTATE_DS_ScratchSpaceBasePointer_start 138 25378 #define GEN9_3DSTATE_DS_ScratchSpaceBasePointer_start 138 25379 #define GEN8_3DSTATE_DS_ScratchSpaceBasePointer_start 138 25380 #define GEN75_3DSTATE_DS_ScratchSpaceBasePointer_start 106 25381 #define GEN7_3DSTATE_DS_ScratchSpaceBasePointer_start 106 25382 25383 static inline uint32_t ATTRIBUTE_PURE 25384 _3DSTATE_DS_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) 25385 { 25386 switch (devinfo->gen) { 25387 case 10: return 138; 25388 case 9: return 138; 25389 case 8: return 138; 25390 case 7: 25391 if (devinfo->is_haswell) { 25392 return 106; 25393 } else { 25394 return 106; 25395 } 25396 case 6: return 0; 25397 case 5: return 0; 25398 case 4: 25399 if (devinfo->is_g4x) { 25400 return 0; 25401 } else { 25402 return 0; 25403 } 25404 default: 25405 unreachable("Invalid hardware generation"); 25406 } 25407 } 25408 25409 25410 25411 /* 3DSTATE_DS::Single Domain Point Dispatch */ 25412 25413 25414 #define GEN8_3DSTATE_DS_SingleDomainPointDispatch_bits 1 25415 #define GEN75_3DSTATE_DS_SingleDomainPointDispatch_bits 1 25416 #define GEN7_3DSTATE_DS_SingleDomainPointDispatch_bits 1 25417 25418 static inline uint32_t ATTRIBUTE_PURE 25419 _3DSTATE_DS_SingleDomainPointDispatch_bits(const struct gen_device_info *devinfo) 25420 { 25421 switch (devinfo->gen) { 25422 case 10: return 0; 25423 case 9: return 0; 25424 case 8: return 1; 25425 case 7: 25426 if (devinfo->is_haswell) { 25427 return 1; 25428 } else { 25429 return 1; 25430 } 25431 case 6: return 0; 25432 case 5: return 0; 25433 case 4: 25434 if (devinfo->is_g4x) { 25435 return 0; 25436 } else { 25437 return 0; 25438 } 25439 default: 25440 unreachable("Invalid hardware generation"); 25441 } 25442 } 25443 25444 25445 25446 #define GEN8_3DSTATE_DS_SingleDomainPointDispatch_start 127 25447 #define GEN75_3DSTATE_DS_SingleDomainPointDispatch_start 95 25448 #define GEN7_3DSTATE_DS_SingleDomainPointDispatch_start 95 25449 25450 static inline uint32_t ATTRIBUTE_PURE 25451 _3DSTATE_DS_SingleDomainPointDispatch_start(const struct gen_device_info *devinfo) 25452 { 25453 switch (devinfo->gen) { 25454 case 10: return 0; 25455 case 9: return 0; 25456 case 8: return 127; 25457 case 7: 25458 if (devinfo->is_haswell) { 25459 return 95; 25460 } else { 25461 return 95; 25462 } 25463 case 6: return 0; 25464 case 5: return 0; 25465 case 4: 25466 if (devinfo->is_g4x) { 25467 return 0; 25468 } else { 25469 return 0; 25470 } 25471 default: 25472 unreachable("Invalid hardware generation"); 25473 } 25474 } 25475 25476 25477 25478 /* 3DSTATE_DS::Software Exception Enable */ 25479 25480 25481 #define GEN10_3DSTATE_DS_SoftwareExceptionEnable_bits 1 25482 #define GEN9_3DSTATE_DS_SoftwareExceptionEnable_bits 1 25483 #define GEN8_3DSTATE_DS_SoftwareExceptionEnable_bits 1 25484 #define GEN75_3DSTATE_DS_SoftwareExceptionEnable_bits 1 25485 #define GEN7_3DSTATE_DS_SoftwareExceptionEnable_bits 1 25486 25487 static inline uint32_t ATTRIBUTE_PURE 25488 _3DSTATE_DS_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) 25489 { 25490 switch (devinfo->gen) { 25491 case 10: return 1; 25492 case 9: return 1; 25493 case 8: return 1; 25494 case 7: 25495 if (devinfo->is_haswell) { 25496 return 1; 25497 } else { 25498 return 1; 25499 } 25500 case 6: return 0; 25501 case 5: return 0; 25502 case 4: 25503 if (devinfo->is_g4x) { 25504 return 0; 25505 } else { 25506 return 0; 25507 } 25508 default: 25509 unreachable("Invalid hardware generation"); 25510 } 25511 } 25512 25513 25514 25515 #define GEN10_3DSTATE_DS_SoftwareExceptionEnable_start 103 25516 #define GEN9_3DSTATE_DS_SoftwareExceptionEnable_start 103 25517 #define GEN8_3DSTATE_DS_SoftwareExceptionEnable_start 103 25518 #define GEN75_3DSTATE_DS_SoftwareExceptionEnable_start 71 25519 #define GEN7_3DSTATE_DS_SoftwareExceptionEnable_start 71 25520 25521 static inline uint32_t ATTRIBUTE_PURE 25522 _3DSTATE_DS_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) 25523 { 25524 switch (devinfo->gen) { 25525 case 10: return 103; 25526 case 9: return 103; 25527 case 8: return 103; 25528 case 7: 25529 if (devinfo->is_haswell) { 25530 return 71; 25531 } else { 25532 return 71; 25533 } 25534 case 6: return 0; 25535 case 5: return 0; 25536 case 4: 25537 if (devinfo->is_g4x) { 25538 return 0; 25539 } else { 25540 return 0; 25541 } 25542 default: 25543 unreachable("Invalid hardware generation"); 25544 } 25545 } 25546 25547 25548 25549 /* 3DSTATE_DS::Statistics Enable */ 25550 25551 25552 #define GEN10_3DSTATE_DS_StatisticsEnable_bits 1 25553 #define GEN9_3DSTATE_DS_StatisticsEnable_bits 1 25554 #define GEN8_3DSTATE_DS_StatisticsEnable_bits 1 25555 #define GEN75_3DSTATE_DS_StatisticsEnable_bits 1 25556 #define GEN7_3DSTATE_DS_StatisticsEnable_bits 1 25557 25558 static inline uint32_t ATTRIBUTE_PURE 25559 _3DSTATE_DS_StatisticsEnable_bits(const struct gen_device_info *devinfo) 25560 { 25561 switch (devinfo->gen) { 25562 case 10: return 1; 25563 case 9: return 1; 25564 case 8: return 1; 25565 case 7: 25566 if (devinfo->is_haswell) { 25567 return 1; 25568 } else { 25569 return 1; 25570 } 25571 case 6: return 0; 25572 case 5: return 0; 25573 case 4: 25574 if (devinfo->is_g4x) { 25575 return 0; 25576 } else { 25577 return 0; 25578 } 25579 default: 25580 unreachable("Invalid hardware generation"); 25581 } 25582 } 25583 25584 25585 25586 #define GEN10_3DSTATE_DS_StatisticsEnable_start 234 25587 #define GEN9_3DSTATE_DS_StatisticsEnable_start 234 25588 #define GEN8_3DSTATE_DS_StatisticsEnable_start 234 25589 #define GEN75_3DSTATE_DS_StatisticsEnable_start 170 25590 #define GEN7_3DSTATE_DS_StatisticsEnable_start 170 25591 25592 static inline uint32_t ATTRIBUTE_PURE 25593 _3DSTATE_DS_StatisticsEnable_start(const struct gen_device_info *devinfo) 25594 { 25595 switch (devinfo->gen) { 25596 case 10: return 234; 25597 case 9: return 234; 25598 case 8: return 234; 25599 case 7: 25600 if (devinfo->is_haswell) { 25601 return 170; 25602 } else { 25603 return 170; 25604 } 25605 case 6: return 0; 25606 case 5: return 0; 25607 case 4: 25608 if (devinfo->is_g4x) { 25609 return 0; 25610 } else { 25611 return 0; 25612 } 25613 default: 25614 unreachable("Invalid hardware generation"); 25615 } 25616 } 25617 25618 25619 25620 /* 3DSTATE_DS::Thread Dispatch Priority */ 25621 25622 25623 #define GEN10_3DSTATE_DS_ThreadDispatchPriority_bits 1 25624 #define GEN9_3DSTATE_DS_ThreadDispatchPriority_bits 1 25625 #define GEN8_3DSTATE_DS_ThreadDispatchPriority_bits 1 25626 #define GEN75_3DSTATE_DS_ThreadDispatchPriority_bits 1 25627 25628 static inline uint32_t ATTRIBUTE_PURE 25629 _3DSTATE_DS_ThreadDispatchPriority_bits(const struct gen_device_info *devinfo) 25630 { 25631 switch (devinfo->gen) { 25632 case 10: return 1; 25633 case 9: return 1; 25634 case 8: return 1; 25635 case 7: 25636 if (devinfo->is_haswell) { 25637 return 1; 25638 } else { 25639 return 0; 25640 } 25641 case 6: return 0; 25642 case 5: return 0; 25643 case 4: 25644 if (devinfo->is_g4x) { 25645 return 0; 25646 } else { 25647 return 0; 25648 } 25649 default: 25650 unreachable("Invalid hardware generation"); 25651 } 25652 } 25653 25654 25655 25656 #define GEN10_3DSTATE_DS_ThreadDispatchPriority_start 113 25657 #define GEN9_3DSTATE_DS_ThreadDispatchPriority_start 113 25658 #define GEN8_3DSTATE_DS_ThreadDispatchPriority_start 113 25659 #define GEN75_3DSTATE_DS_ThreadDispatchPriority_start 81 25660 25661 static inline uint32_t ATTRIBUTE_PURE 25662 _3DSTATE_DS_ThreadDispatchPriority_start(const struct gen_device_info *devinfo) 25663 { 25664 switch (devinfo->gen) { 25665 case 10: return 113; 25666 case 9: return 113; 25667 case 8: return 113; 25668 case 7: 25669 if (devinfo->is_haswell) { 25670 return 81; 25671 } else { 25672 return 0; 25673 } 25674 case 6: return 0; 25675 case 5: return 0; 25676 case 4: 25677 if (devinfo->is_g4x) { 25678 return 0; 25679 } else { 25680 return 0; 25681 } 25682 default: 25683 unreachable("Invalid hardware generation"); 25684 } 25685 } 25686 25687 25688 25689 /* 3DSTATE_DS::User Clip Distance Clip Test Enable Bitmask */ 25690 25691 25692 #define GEN10_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits 8 25693 #define GEN9_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits 8 25694 #define GEN8_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits 8 25695 25696 static inline uint32_t ATTRIBUTE_PURE 25697 _3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits(const struct gen_device_info *devinfo) 25698 { 25699 switch (devinfo->gen) { 25700 case 10: return 8; 25701 case 9: return 8; 25702 case 8: return 8; 25703 case 7: 25704 if (devinfo->is_haswell) { 25705 return 0; 25706 } else { 25707 return 0; 25708 } 25709 case 6: return 0; 25710 case 5: return 0; 25711 case 4: 25712 if (devinfo->is_g4x) { 25713 return 0; 25714 } else { 25715 return 0; 25716 } 25717 default: 25718 unreachable("Invalid hardware generation"); 25719 } 25720 } 25721 25722 25723 25724 #define GEN10_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start 264 25725 #define GEN9_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start 264 25726 #define GEN8_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start 264 25727 25728 static inline uint32_t ATTRIBUTE_PURE 25729 _3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start(const struct gen_device_info *devinfo) 25730 { 25731 switch (devinfo->gen) { 25732 case 10: return 264; 25733 case 9: return 264; 25734 case 8: return 264; 25735 case 7: 25736 if (devinfo->is_haswell) { 25737 return 0; 25738 } else { 25739 return 0; 25740 } 25741 case 6: return 0; 25742 case 5: return 0; 25743 case 4: 25744 if (devinfo->is_g4x) { 25745 return 0; 25746 } else { 25747 return 0; 25748 } 25749 default: 25750 unreachable("Invalid hardware generation"); 25751 } 25752 } 25753 25754 25755 25756 /* 3DSTATE_DS::User Clip Distance Cull Test Enable Bitmask */ 25757 25758 25759 #define GEN10_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits 8 25760 #define GEN9_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits 8 25761 #define GEN8_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits 8 25762 25763 static inline uint32_t ATTRIBUTE_PURE 25764 _3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits(const struct gen_device_info *devinfo) 25765 { 25766 switch (devinfo->gen) { 25767 case 10: return 8; 25768 case 9: return 8; 25769 case 8: return 8; 25770 case 7: 25771 if (devinfo->is_haswell) { 25772 return 0; 25773 } else { 25774 return 0; 25775 } 25776 case 6: return 0; 25777 case 5: return 0; 25778 case 4: 25779 if (devinfo->is_g4x) { 25780 return 0; 25781 } else { 25782 return 0; 25783 } 25784 default: 25785 unreachable("Invalid hardware generation"); 25786 } 25787 } 25788 25789 25790 25791 #define GEN10_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start 256 25792 #define GEN9_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start 256 25793 #define GEN8_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start 256 25794 25795 static inline uint32_t ATTRIBUTE_PURE 25796 _3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start(const struct gen_device_info *devinfo) 25797 { 25798 switch (devinfo->gen) { 25799 case 10: return 256; 25800 case 9: return 256; 25801 case 8: return 256; 25802 case 7: 25803 if (devinfo->is_haswell) { 25804 return 0; 25805 } else { 25806 return 0; 25807 } 25808 case 6: return 0; 25809 case 5: return 0; 25810 case 4: 25811 if (devinfo->is_g4x) { 25812 return 0; 25813 } else { 25814 return 0; 25815 } 25816 default: 25817 unreachable("Invalid hardware generation"); 25818 } 25819 } 25820 25821 25822 25823 /* 3DSTATE_DS::Vector Mask Enable */ 25824 25825 25826 #define GEN10_3DSTATE_DS_VectorMaskEnable_bits 1 25827 #define GEN9_3DSTATE_DS_VectorMaskEnable_bits 1 25828 #define GEN8_3DSTATE_DS_VectorMaskEnable_bits 1 25829 #define GEN75_3DSTATE_DS_VectorMaskEnable_bits 1 25830 #define GEN7_3DSTATE_DS_VectorMaskEnable_bits 1 25831 25832 static inline uint32_t ATTRIBUTE_PURE 25833 _3DSTATE_DS_VectorMaskEnable_bits(const struct gen_device_info *devinfo) 25834 { 25835 switch (devinfo->gen) { 25836 case 10: return 1; 25837 case 9: return 1; 25838 case 8: return 1; 25839 case 7: 25840 if (devinfo->is_haswell) { 25841 return 1; 25842 } else { 25843 return 1; 25844 } 25845 case 6: return 0; 25846 case 5: return 0; 25847 case 4: 25848 if (devinfo->is_g4x) { 25849 return 0; 25850 } else { 25851 return 0; 25852 } 25853 default: 25854 unreachable("Invalid hardware generation"); 25855 } 25856 } 25857 25858 25859 25860 #define GEN10_3DSTATE_DS_VectorMaskEnable_start 126 25861 #define GEN9_3DSTATE_DS_VectorMaskEnable_start 126 25862 #define GEN8_3DSTATE_DS_VectorMaskEnable_start 126 25863 #define GEN75_3DSTATE_DS_VectorMaskEnable_start 94 25864 #define GEN7_3DSTATE_DS_VectorMaskEnable_start 94 25865 25866 static inline uint32_t ATTRIBUTE_PURE 25867 _3DSTATE_DS_VectorMaskEnable_start(const struct gen_device_info *devinfo) 25868 { 25869 switch (devinfo->gen) { 25870 case 10: return 126; 25871 case 9: return 126; 25872 case 8: return 126; 25873 case 7: 25874 if (devinfo->is_haswell) { 25875 return 94; 25876 } else { 25877 return 94; 25878 } 25879 case 6: return 0; 25880 case 5: return 0; 25881 case 4: 25882 if (devinfo->is_g4x) { 25883 return 0; 25884 } else { 25885 return 0; 25886 } 25887 default: 25888 unreachable("Invalid hardware generation"); 25889 } 25890 } 25891 25892 25893 25894 /* 3DSTATE_DS::Vertex URB Entry Output Length */ 25895 25896 25897 #define GEN10_3DSTATE_DS_VertexURBEntryOutputLength_bits 5 25898 #define GEN9_3DSTATE_DS_VertexURBEntryOutputLength_bits 5 25899 #define GEN8_3DSTATE_DS_VertexURBEntryOutputLength_bits 5 25900 25901 static inline uint32_t ATTRIBUTE_PURE 25902 _3DSTATE_DS_VertexURBEntryOutputLength_bits(const struct gen_device_info *devinfo) 25903 { 25904 switch (devinfo->gen) { 25905 case 10: return 5; 25906 case 9: return 5; 25907 case 8: return 5; 25908 case 7: 25909 if (devinfo->is_haswell) { 25910 return 0; 25911 } else { 25912 return 0; 25913 } 25914 case 6: return 0; 25915 case 5: return 0; 25916 case 4: 25917 if (devinfo->is_g4x) { 25918 return 0; 25919 } else { 25920 return 0; 25921 } 25922 default: 25923 unreachable("Invalid hardware generation"); 25924 } 25925 } 25926 25927 25928 25929 #define GEN10_3DSTATE_DS_VertexURBEntryOutputLength_start 272 25930 #define GEN9_3DSTATE_DS_VertexURBEntryOutputLength_start 272 25931 #define GEN8_3DSTATE_DS_VertexURBEntryOutputLength_start 272 25932 25933 static inline uint32_t ATTRIBUTE_PURE 25934 _3DSTATE_DS_VertexURBEntryOutputLength_start(const struct gen_device_info *devinfo) 25935 { 25936 switch (devinfo->gen) { 25937 case 10: return 272; 25938 case 9: return 272; 25939 case 8: return 272; 25940 case 7: 25941 if (devinfo->is_haswell) { 25942 return 0; 25943 } else { 25944 return 0; 25945 } 25946 case 6: return 0; 25947 case 5: return 0; 25948 case 4: 25949 if (devinfo->is_g4x) { 25950 return 0; 25951 } else { 25952 return 0; 25953 } 25954 default: 25955 unreachable("Invalid hardware generation"); 25956 } 25957 } 25958 25959 25960 25961 /* 3DSTATE_DS::Vertex URB Entry Output Read Offset */ 25962 25963 25964 #define GEN10_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits 6 25965 #define GEN9_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits 6 25966 #define GEN8_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits 6 25967 25968 static inline uint32_t ATTRIBUTE_PURE 25969 _3DSTATE_DS_VertexURBEntryOutputReadOffset_bits(const struct gen_device_info *devinfo) 25970 { 25971 switch (devinfo->gen) { 25972 case 10: return 6; 25973 case 9: return 6; 25974 case 8: return 6; 25975 case 7: 25976 if (devinfo->is_haswell) { 25977 return 0; 25978 } else { 25979 return 0; 25980 } 25981 case 6: return 0; 25982 case 5: return 0; 25983 case 4: 25984 if (devinfo->is_g4x) { 25985 return 0; 25986 } else { 25987 return 0; 25988 } 25989 default: 25990 unreachable("Invalid hardware generation"); 25991 } 25992 } 25993 25994 25995 25996 #define GEN10_3DSTATE_DS_VertexURBEntryOutputReadOffset_start 277 25997 #define GEN9_3DSTATE_DS_VertexURBEntryOutputReadOffset_start 277 25998 #define GEN8_3DSTATE_DS_VertexURBEntryOutputReadOffset_start 277 25999 26000 static inline uint32_t ATTRIBUTE_PURE 26001 _3DSTATE_DS_VertexURBEntryOutputReadOffset_start(const struct gen_device_info *devinfo) 26002 { 26003 switch (devinfo->gen) { 26004 case 10: return 277; 26005 case 9: return 277; 26006 case 8: return 277; 26007 case 7: 26008 if (devinfo->is_haswell) { 26009 return 0; 26010 } else { 26011 return 0; 26012 } 26013 case 6: return 0; 26014 case 5: return 0; 26015 case 4: 26016 if (devinfo->is_g4x) { 26017 return 0; 26018 } else { 26019 return 0; 26020 } 26021 default: 26022 unreachable("Invalid hardware generation"); 26023 } 26024 } 26025 26026 26027 26028 /* 3DSTATE_GATHER_CONSTANT_DS */ 26029 26030 26031 26032 26033 26034 /* 3DSTATE_GATHER_CONSTANT_DS::3D Command Opcode */ 26035 26036 26037 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 26038 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 26039 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 26040 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 26041 26042 static inline uint32_t ATTRIBUTE_PURE 26043 _3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 26044 { 26045 switch (devinfo->gen) { 26046 case 10: return 3; 26047 case 9: return 3; 26048 case 8: return 3; 26049 case 7: 26050 if (devinfo->is_haswell) { 26051 return 3; 26052 } else { 26053 return 0; 26054 } 26055 case 6: return 0; 26056 case 5: return 0; 26057 case 4: 26058 if (devinfo->is_g4x) { 26059 return 0; 26060 } else { 26061 return 0; 26062 } 26063 default: 26064 unreachable("Invalid hardware generation"); 26065 } 26066 } 26067 26068 26069 26070 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 26071 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 26072 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 26073 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 26074 26075 static inline uint32_t ATTRIBUTE_PURE 26076 _3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 26077 { 26078 switch (devinfo->gen) { 26079 case 10: return 24; 26080 case 9: return 24; 26081 case 8: return 24; 26082 case 7: 26083 if (devinfo->is_haswell) { 26084 return 24; 26085 } else { 26086 return 0; 26087 } 26088 case 6: return 0; 26089 case 5: return 0; 26090 case 4: 26091 if (devinfo->is_g4x) { 26092 return 0; 26093 } else { 26094 return 0; 26095 } 26096 default: 26097 unreachable("Invalid hardware generation"); 26098 } 26099 } 26100 26101 26102 26103 /* 3DSTATE_GATHER_CONSTANT_DS::3D Command Sub Opcode */ 26104 26105 26106 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 26107 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 26108 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 26109 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 26110 26111 static inline uint32_t ATTRIBUTE_PURE 26112 _3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 26113 { 26114 switch (devinfo->gen) { 26115 case 10: return 8; 26116 case 9: return 8; 26117 case 8: return 8; 26118 case 7: 26119 if (devinfo->is_haswell) { 26120 return 8; 26121 } else { 26122 return 0; 26123 } 26124 case 6: return 0; 26125 case 5: return 0; 26126 case 4: 26127 if (devinfo->is_g4x) { 26128 return 0; 26129 } else { 26130 return 0; 26131 } 26132 default: 26133 unreachable("Invalid hardware generation"); 26134 } 26135 } 26136 26137 26138 26139 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 26140 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 26141 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 26142 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 26143 26144 static inline uint32_t ATTRIBUTE_PURE 26145 _3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 26146 { 26147 switch (devinfo->gen) { 26148 case 10: return 16; 26149 case 9: return 16; 26150 case 8: return 16; 26151 case 7: 26152 if (devinfo->is_haswell) { 26153 return 16; 26154 } else { 26155 return 0; 26156 } 26157 case 6: return 0; 26158 case 5: return 0; 26159 case 4: 26160 if (devinfo->is_g4x) { 26161 return 0; 26162 } else { 26163 return 0; 26164 } 26165 default: 26166 unreachable("Invalid hardware generation"); 26167 } 26168 } 26169 26170 26171 26172 /* 3DSTATE_GATHER_CONSTANT_DS::Command SubType */ 26173 26174 26175 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 26176 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 26177 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 26178 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 26179 26180 static inline uint32_t ATTRIBUTE_PURE 26181 _3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits(const struct gen_device_info *devinfo) 26182 { 26183 switch (devinfo->gen) { 26184 case 10: return 2; 26185 case 9: return 2; 26186 case 8: return 2; 26187 case 7: 26188 if (devinfo->is_haswell) { 26189 return 2; 26190 } else { 26191 return 0; 26192 } 26193 case 6: return 0; 26194 case 5: return 0; 26195 case 4: 26196 if (devinfo->is_g4x) { 26197 return 0; 26198 } else { 26199 return 0; 26200 } 26201 default: 26202 unreachable("Invalid hardware generation"); 26203 } 26204 } 26205 26206 26207 26208 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 26209 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 26210 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 26211 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 26212 26213 static inline uint32_t ATTRIBUTE_PURE 26214 _3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start(const struct gen_device_info *devinfo) 26215 { 26216 switch (devinfo->gen) { 26217 case 10: return 27; 26218 case 9: return 27; 26219 case 8: return 27; 26220 case 7: 26221 if (devinfo->is_haswell) { 26222 return 27; 26223 } else { 26224 return 0; 26225 } 26226 case 6: return 0; 26227 case 5: return 0; 26228 case 4: 26229 if (devinfo->is_g4x) { 26230 return 0; 26231 } else { 26232 return 0; 26233 } 26234 default: 26235 unreachable("Invalid hardware generation"); 26236 } 26237 } 26238 26239 26240 26241 /* 3DSTATE_GATHER_CONSTANT_DS::Command Type */ 26242 26243 26244 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 26245 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 26246 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 26247 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 26248 26249 static inline uint32_t ATTRIBUTE_PURE 26250 _3DSTATE_GATHER_CONSTANT_DS_CommandType_bits(const struct gen_device_info *devinfo) 26251 { 26252 switch (devinfo->gen) { 26253 case 10: return 3; 26254 case 9: return 3; 26255 case 8: return 3; 26256 case 7: 26257 if (devinfo->is_haswell) { 26258 return 3; 26259 } else { 26260 return 0; 26261 } 26262 case 6: return 0; 26263 case 5: return 0; 26264 case 4: 26265 if (devinfo->is_g4x) { 26266 return 0; 26267 } else { 26268 return 0; 26269 } 26270 default: 26271 unreachable("Invalid hardware generation"); 26272 } 26273 } 26274 26275 26276 26277 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 26278 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 26279 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 26280 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 26281 26282 static inline uint32_t ATTRIBUTE_PURE 26283 _3DSTATE_GATHER_CONSTANT_DS_CommandType_start(const struct gen_device_info *devinfo) 26284 { 26285 switch (devinfo->gen) { 26286 case 10: return 29; 26287 case 9: return 29; 26288 case 8: return 29; 26289 case 7: 26290 if (devinfo->is_haswell) { 26291 return 29; 26292 } else { 26293 return 0; 26294 } 26295 case 6: return 0; 26296 case 5: return 0; 26297 case 4: 26298 if (devinfo->is_g4x) { 26299 return 0; 26300 } else { 26301 return 0; 26302 } 26303 default: 26304 unreachable("Invalid hardware generation"); 26305 } 26306 } 26307 26308 26309 26310 /* 3DSTATE_GATHER_CONSTANT_DS::Constant Buffer Binding Table Block */ 26311 26312 26313 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 26314 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 26315 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 26316 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 26317 26318 static inline uint32_t ATTRIBUTE_PURE 26319 _3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits(const struct gen_device_info *devinfo) 26320 { 26321 switch (devinfo->gen) { 26322 case 10: return 4; 26323 case 9: return 4; 26324 case 8: return 4; 26325 case 7: 26326 if (devinfo->is_haswell) { 26327 return 4; 26328 } else { 26329 return 0; 26330 } 26331 case 6: return 0; 26332 case 5: return 0; 26333 case 4: 26334 if (devinfo->is_g4x) { 26335 return 0; 26336 } else { 26337 return 0; 26338 } 26339 default: 26340 unreachable("Invalid hardware generation"); 26341 } 26342 } 26343 26344 26345 26346 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 26347 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 26348 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 26349 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 26350 26351 static inline uint32_t ATTRIBUTE_PURE 26352 _3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start(const struct gen_device_info *devinfo) 26353 { 26354 switch (devinfo->gen) { 26355 case 10: return 44; 26356 case 9: return 44; 26357 case 8: return 44; 26358 case 7: 26359 if (devinfo->is_haswell) { 26360 return 44; 26361 } else { 26362 return 0; 26363 } 26364 case 6: return 0; 26365 case 5: return 0; 26366 case 4: 26367 if (devinfo->is_g4x) { 26368 return 0; 26369 } else { 26370 return 0; 26371 } 26372 default: 26373 unreachable("Invalid hardware generation"); 26374 } 26375 } 26376 26377 26378 26379 /* 3DSTATE_GATHER_CONSTANT_DS::Constant Buffer Dx9 Generate Stall */ 26380 26381 26382 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits 1 26383 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits 1 26384 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits 1 26385 26386 static inline uint32_t ATTRIBUTE_PURE 26387 _3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits(const struct gen_device_info *devinfo) 26388 { 26389 switch (devinfo->gen) { 26390 case 10: return 1; 26391 case 9: return 1; 26392 case 8: return 1; 26393 case 7: 26394 if (devinfo->is_haswell) { 26395 return 0; 26396 } else { 26397 return 0; 26398 } 26399 case 6: return 0; 26400 case 5: return 0; 26401 case 4: 26402 if (devinfo->is_g4x) { 26403 return 0; 26404 } else { 26405 return 0; 26406 } 26407 default: 26408 unreachable("Invalid hardware generation"); 26409 } 26410 } 26411 26412 26413 26414 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start 69 26415 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start 69 26416 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start 69 26417 26418 static inline uint32_t ATTRIBUTE_PURE 26419 _3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start(const struct gen_device_info *devinfo) 26420 { 26421 switch (devinfo->gen) { 26422 case 10: return 69; 26423 case 9: return 69; 26424 case 8: return 69; 26425 case 7: 26426 if (devinfo->is_haswell) { 26427 return 0; 26428 } else { 26429 return 0; 26430 } 26431 case 6: return 0; 26432 case 5: return 0; 26433 case 4: 26434 if (devinfo->is_g4x) { 26435 return 0; 26436 } else { 26437 return 0; 26438 } 26439 default: 26440 unreachable("Invalid hardware generation"); 26441 } 26442 } 26443 26444 26445 26446 /* 3DSTATE_GATHER_CONSTANT_DS::Constant Buffer Valid */ 26447 26448 26449 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 26450 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 26451 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 26452 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 26453 26454 static inline uint32_t ATTRIBUTE_PURE 26455 _3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits(const struct gen_device_info *devinfo) 26456 { 26457 switch (devinfo->gen) { 26458 case 10: return 16; 26459 case 9: return 16; 26460 case 8: return 16; 26461 case 7: 26462 if (devinfo->is_haswell) { 26463 return 16; 26464 } else { 26465 return 0; 26466 } 26467 case 6: return 0; 26468 case 5: return 0; 26469 case 4: 26470 if (devinfo->is_g4x) { 26471 return 0; 26472 } else { 26473 return 0; 26474 } 26475 default: 26476 unreachable("Invalid hardware generation"); 26477 } 26478 } 26479 26480 26481 26482 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 26483 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 26484 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 26485 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 26486 26487 static inline uint32_t ATTRIBUTE_PURE 26488 _3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start(const struct gen_device_info *devinfo) 26489 { 26490 switch (devinfo->gen) { 26491 case 10: return 48; 26492 case 9: return 48; 26493 case 8: return 48; 26494 case 7: 26495 if (devinfo->is_haswell) { 26496 return 48; 26497 } else { 26498 return 0; 26499 } 26500 case 6: return 0; 26501 case 5: return 0; 26502 case 4: 26503 if (devinfo->is_g4x) { 26504 return 0; 26505 } else { 26506 return 0; 26507 } 26508 default: 26509 unreachable("Invalid hardware generation"); 26510 } 26511 } 26512 26513 26514 26515 /* 3DSTATE_GATHER_CONSTANT_DS::DWord Length */ 26516 26517 26518 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 26519 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 26520 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 26521 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 26522 26523 static inline uint32_t ATTRIBUTE_PURE 26524 _3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits(const struct gen_device_info *devinfo) 26525 { 26526 switch (devinfo->gen) { 26527 case 10: return 8; 26528 case 9: return 8; 26529 case 8: return 8; 26530 case 7: 26531 if (devinfo->is_haswell) { 26532 return 8; 26533 } else { 26534 return 0; 26535 } 26536 case 6: return 0; 26537 case 5: return 0; 26538 case 4: 26539 if (devinfo->is_g4x) { 26540 return 0; 26541 } else { 26542 return 0; 26543 } 26544 default: 26545 unreachable("Invalid hardware generation"); 26546 } 26547 } 26548 26549 26550 26551 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 26552 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 26553 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 26554 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 26555 26556 static inline uint32_t ATTRIBUTE_PURE 26557 _3DSTATE_GATHER_CONSTANT_DS_DWordLength_start(const struct gen_device_info *devinfo) 26558 { 26559 switch (devinfo->gen) { 26560 case 10: return 0; 26561 case 9: return 0; 26562 case 8: return 0; 26563 case 7: 26564 if (devinfo->is_haswell) { 26565 return 0; 26566 } else { 26567 return 0; 26568 } 26569 case 6: return 0; 26570 case 5: return 0; 26571 case 4: 26572 if (devinfo->is_g4x) { 26573 return 0; 26574 } else { 26575 return 0; 26576 } 26577 default: 26578 unreachable("Invalid hardware generation"); 26579 } 26580 } 26581 26582 26583 26584 /* 3DSTATE_GATHER_CONSTANT_DS::Entry_0 */ 26585 26586 26587 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_Entry_0_bits 16 26588 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_Entry_0_bits 16 26589 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_Entry_0_bits 16 26590 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_Entry_0_bits 16 26591 26592 static inline uint32_t ATTRIBUTE_PURE 26593 _3DSTATE_GATHER_CONSTANT_DS_Entry_0_bits(const struct gen_device_info *devinfo) 26594 { 26595 switch (devinfo->gen) { 26596 case 10: return 16; 26597 case 9: return 16; 26598 case 8: return 16; 26599 case 7: 26600 if (devinfo->is_haswell) { 26601 return 16; 26602 } else { 26603 return 0; 26604 } 26605 case 6: return 0; 26606 case 5: return 0; 26607 case 4: 26608 if (devinfo->is_g4x) { 26609 return 0; 26610 } else { 26611 return 0; 26612 } 26613 default: 26614 unreachable("Invalid hardware generation"); 26615 } 26616 } 26617 26618 26619 26620 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_Entry_0_start 0 26621 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_Entry_0_start 0 26622 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_Entry_0_start 0 26623 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_Entry_0_start 0 26624 26625 static inline uint32_t ATTRIBUTE_PURE 26626 _3DSTATE_GATHER_CONSTANT_DS_Entry_0_start(const struct gen_device_info *devinfo) 26627 { 26628 switch (devinfo->gen) { 26629 case 10: return 0; 26630 case 9: return 0; 26631 case 8: return 0; 26632 case 7: 26633 if (devinfo->is_haswell) { 26634 return 0; 26635 } else { 26636 return 0; 26637 } 26638 case 6: return 0; 26639 case 5: return 0; 26640 case 4: 26641 if (devinfo->is_g4x) { 26642 return 0; 26643 } else { 26644 return 0; 26645 } 26646 default: 26647 unreachable("Invalid hardware generation"); 26648 } 26649 } 26650 26651 26652 26653 /* 3DSTATE_GATHER_CONSTANT_DS::Entry_1 */ 26654 26655 26656 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_Entry_1_bits 16 26657 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_Entry_1_bits 16 26658 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_Entry_1_bits 16 26659 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_Entry_1_bits 16 26660 26661 static inline uint32_t ATTRIBUTE_PURE 26662 _3DSTATE_GATHER_CONSTANT_DS_Entry_1_bits(const struct gen_device_info *devinfo) 26663 { 26664 switch (devinfo->gen) { 26665 case 10: return 16; 26666 case 9: return 16; 26667 case 8: return 16; 26668 case 7: 26669 if (devinfo->is_haswell) { 26670 return 16; 26671 } else { 26672 return 0; 26673 } 26674 case 6: return 0; 26675 case 5: return 0; 26676 case 4: 26677 if (devinfo->is_g4x) { 26678 return 0; 26679 } else { 26680 return 0; 26681 } 26682 default: 26683 unreachable("Invalid hardware generation"); 26684 } 26685 } 26686 26687 26688 26689 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_Entry_1_start 16 26690 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_Entry_1_start 16 26691 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_Entry_1_start 16 26692 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_Entry_1_start 16 26693 26694 static inline uint32_t ATTRIBUTE_PURE 26695 _3DSTATE_GATHER_CONSTANT_DS_Entry_1_start(const struct gen_device_info *devinfo) 26696 { 26697 switch (devinfo->gen) { 26698 case 10: return 16; 26699 case 9: return 16; 26700 case 8: return 16; 26701 case 7: 26702 if (devinfo->is_haswell) { 26703 return 16; 26704 } else { 26705 return 0; 26706 } 26707 case 6: return 0; 26708 case 5: return 0; 26709 case 4: 26710 if (devinfo->is_g4x) { 26711 return 0; 26712 } else { 26713 return 0; 26714 } 26715 default: 26716 unreachable("Invalid hardware generation"); 26717 } 26718 } 26719 26720 26721 26722 /* 3DSTATE_GATHER_CONSTANT_DS::Gather Buffer Offset */ 26723 26724 26725 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 26726 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 26727 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 26728 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 26729 26730 static inline uint32_t ATTRIBUTE_PURE 26731 _3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits(const struct gen_device_info *devinfo) 26732 { 26733 switch (devinfo->gen) { 26734 case 10: return 17; 26735 case 9: return 17; 26736 case 8: return 17; 26737 case 7: 26738 if (devinfo->is_haswell) { 26739 return 17; 26740 } else { 26741 return 0; 26742 } 26743 case 6: return 0; 26744 case 5: return 0; 26745 case 4: 26746 if (devinfo->is_g4x) { 26747 return 0; 26748 } else { 26749 return 0; 26750 } 26751 default: 26752 unreachable("Invalid hardware generation"); 26753 } 26754 } 26755 26756 26757 26758 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 26759 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 26760 #define GEN8_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 26761 #define GEN75_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 26762 26763 static inline uint32_t ATTRIBUTE_PURE 26764 _3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start(const struct gen_device_info *devinfo) 26765 { 26766 switch (devinfo->gen) { 26767 case 10: return 70; 26768 case 9: return 70; 26769 case 8: return 70; 26770 case 7: 26771 if (devinfo->is_haswell) { 26772 return 70; 26773 } else { 26774 return 0; 26775 } 26776 case 6: return 0; 26777 case 5: return 0; 26778 case 4: 26779 if (devinfo->is_g4x) { 26780 return 0; 26781 } else { 26782 return 0; 26783 } 26784 default: 26785 unreachable("Invalid hardware generation"); 26786 } 26787 } 26788 26789 26790 26791 /* 3DSTATE_GATHER_CONSTANT_DS::On-Die Table */ 26792 26793 26794 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_bits 1 26795 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_bits 1 26796 26797 static inline uint32_t ATTRIBUTE_PURE 26798 _3DSTATE_GATHER_CONSTANT_DS_OnDieTable_bits(const struct gen_device_info *devinfo) 26799 { 26800 switch (devinfo->gen) { 26801 case 10: return 1; 26802 case 9: return 1; 26803 case 8: return 0; 26804 case 7: 26805 if (devinfo->is_haswell) { 26806 return 0; 26807 } else { 26808 return 0; 26809 } 26810 case 6: return 0; 26811 case 5: return 0; 26812 case 4: 26813 if (devinfo->is_g4x) { 26814 return 0; 26815 } else { 26816 return 0; 26817 } 26818 default: 26819 unreachable("Invalid hardware generation"); 26820 } 26821 } 26822 26823 26824 26825 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_start 67 26826 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_start 67 26827 26828 static inline uint32_t ATTRIBUTE_PURE 26829 _3DSTATE_GATHER_CONSTANT_DS_OnDieTable_start(const struct gen_device_info *devinfo) 26830 { 26831 switch (devinfo->gen) { 26832 case 10: return 67; 26833 case 9: return 67; 26834 case 8: return 0; 26835 case 7: 26836 if (devinfo->is_haswell) { 26837 return 0; 26838 } else { 26839 return 0; 26840 } 26841 case 6: return 0; 26842 case 5: return 0; 26843 case 4: 26844 if (devinfo->is_g4x) { 26845 return 0; 26846 } else { 26847 return 0; 26848 } 26849 default: 26850 unreachable("Invalid hardware generation"); 26851 } 26852 } 26853 26854 26855 26856 /* 3DSTATE_GATHER_CONSTANT_DS::Update Gather Table Only */ 26857 26858 26859 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_bits 1 26860 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_bits 1 26861 26862 static inline uint32_t ATTRIBUTE_PURE 26863 _3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_bits(const struct gen_device_info *devinfo) 26864 { 26865 switch (devinfo->gen) { 26866 case 10: return 1; 26867 case 9: return 1; 26868 case 8: return 0; 26869 case 7: 26870 if (devinfo->is_haswell) { 26871 return 0; 26872 } else { 26873 return 0; 26874 } 26875 case 6: return 0; 26876 case 5: return 0; 26877 case 4: 26878 if (devinfo->is_g4x) { 26879 return 0; 26880 } else { 26881 return 0; 26882 } 26883 default: 26884 unreachable("Invalid hardware generation"); 26885 } 26886 } 26887 26888 26889 26890 #define GEN10_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_start 33 26891 #define GEN9_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_start 33 26892 26893 static inline uint32_t ATTRIBUTE_PURE 26894 _3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_start(const struct gen_device_info *devinfo) 26895 { 26896 switch (devinfo->gen) { 26897 case 10: return 33; 26898 case 9: return 33; 26899 case 8: return 0; 26900 case 7: 26901 if (devinfo->is_haswell) { 26902 return 0; 26903 } else { 26904 return 0; 26905 } 26906 case 6: return 0; 26907 case 5: return 0; 26908 case 4: 26909 if (devinfo->is_g4x) { 26910 return 0; 26911 } else { 26912 return 0; 26913 } 26914 default: 26915 unreachable("Invalid hardware generation"); 26916 } 26917 } 26918 26919 26920 26921 /* 3DSTATE_GATHER_CONSTANT_GS */ 26922 26923 26924 26925 26926 26927 /* 3DSTATE_GATHER_CONSTANT_GS::3D Command Opcode */ 26928 26929 26930 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 26931 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 26932 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 26933 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 26934 26935 static inline uint32_t ATTRIBUTE_PURE 26936 _3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 26937 { 26938 switch (devinfo->gen) { 26939 case 10: return 3; 26940 case 9: return 3; 26941 case 8: return 3; 26942 case 7: 26943 if (devinfo->is_haswell) { 26944 return 3; 26945 } else { 26946 return 0; 26947 } 26948 case 6: return 0; 26949 case 5: return 0; 26950 case 4: 26951 if (devinfo->is_g4x) { 26952 return 0; 26953 } else { 26954 return 0; 26955 } 26956 default: 26957 unreachable("Invalid hardware generation"); 26958 } 26959 } 26960 26961 26962 26963 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 26964 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 26965 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 26966 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 26967 26968 static inline uint32_t ATTRIBUTE_PURE 26969 _3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 26970 { 26971 switch (devinfo->gen) { 26972 case 10: return 24; 26973 case 9: return 24; 26974 case 8: return 24; 26975 case 7: 26976 if (devinfo->is_haswell) { 26977 return 24; 26978 } else { 26979 return 0; 26980 } 26981 case 6: return 0; 26982 case 5: return 0; 26983 case 4: 26984 if (devinfo->is_g4x) { 26985 return 0; 26986 } else { 26987 return 0; 26988 } 26989 default: 26990 unreachable("Invalid hardware generation"); 26991 } 26992 } 26993 26994 26995 26996 /* 3DSTATE_GATHER_CONSTANT_GS::3D Command Sub Opcode */ 26997 26998 26999 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 27000 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 27001 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 27002 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 27003 27004 static inline uint32_t ATTRIBUTE_PURE 27005 _3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 27006 { 27007 switch (devinfo->gen) { 27008 case 10: return 8; 27009 case 9: return 8; 27010 case 8: return 8; 27011 case 7: 27012 if (devinfo->is_haswell) { 27013 return 8; 27014 } else { 27015 return 0; 27016 } 27017 case 6: return 0; 27018 case 5: return 0; 27019 case 4: 27020 if (devinfo->is_g4x) { 27021 return 0; 27022 } else { 27023 return 0; 27024 } 27025 default: 27026 unreachable("Invalid hardware generation"); 27027 } 27028 } 27029 27030 27031 27032 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 27033 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 27034 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 27035 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 27036 27037 static inline uint32_t ATTRIBUTE_PURE 27038 _3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 27039 { 27040 switch (devinfo->gen) { 27041 case 10: return 16; 27042 case 9: return 16; 27043 case 8: return 16; 27044 case 7: 27045 if (devinfo->is_haswell) { 27046 return 16; 27047 } else { 27048 return 0; 27049 } 27050 case 6: return 0; 27051 case 5: return 0; 27052 case 4: 27053 if (devinfo->is_g4x) { 27054 return 0; 27055 } else { 27056 return 0; 27057 } 27058 default: 27059 unreachable("Invalid hardware generation"); 27060 } 27061 } 27062 27063 27064 27065 /* 3DSTATE_GATHER_CONSTANT_GS::Command SubType */ 27066 27067 27068 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 27069 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 27070 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 27071 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 27072 27073 static inline uint32_t ATTRIBUTE_PURE 27074 _3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits(const struct gen_device_info *devinfo) 27075 { 27076 switch (devinfo->gen) { 27077 case 10: return 2; 27078 case 9: return 2; 27079 case 8: return 2; 27080 case 7: 27081 if (devinfo->is_haswell) { 27082 return 2; 27083 } else { 27084 return 0; 27085 } 27086 case 6: return 0; 27087 case 5: return 0; 27088 case 4: 27089 if (devinfo->is_g4x) { 27090 return 0; 27091 } else { 27092 return 0; 27093 } 27094 default: 27095 unreachable("Invalid hardware generation"); 27096 } 27097 } 27098 27099 27100 27101 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 27102 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 27103 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 27104 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 27105 27106 static inline uint32_t ATTRIBUTE_PURE 27107 _3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start(const struct gen_device_info *devinfo) 27108 { 27109 switch (devinfo->gen) { 27110 case 10: return 27; 27111 case 9: return 27; 27112 case 8: return 27; 27113 case 7: 27114 if (devinfo->is_haswell) { 27115 return 27; 27116 } else { 27117 return 0; 27118 } 27119 case 6: return 0; 27120 case 5: return 0; 27121 case 4: 27122 if (devinfo->is_g4x) { 27123 return 0; 27124 } else { 27125 return 0; 27126 } 27127 default: 27128 unreachable("Invalid hardware generation"); 27129 } 27130 } 27131 27132 27133 27134 /* 3DSTATE_GATHER_CONSTANT_GS::Command Type */ 27135 27136 27137 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 27138 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 27139 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 27140 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 27141 27142 static inline uint32_t ATTRIBUTE_PURE 27143 _3DSTATE_GATHER_CONSTANT_GS_CommandType_bits(const struct gen_device_info *devinfo) 27144 { 27145 switch (devinfo->gen) { 27146 case 10: return 3; 27147 case 9: return 3; 27148 case 8: return 3; 27149 case 7: 27150 if (devinfo->is_haswell) { 27151 return 3; 27152 } else { 27153 return 0; 27154 } 27155 case 6: return 0; 27156 case 5: return 0; 27157 case 4: 27158 if (devinfo->is_g4x) { 27159 return 0; 27160 } else { 27161 return 0; 27162 } 27163 default: 27164 unreachable("Invalid hardware generation"); 27165 } 27166 } 27167 27168 27169 27170 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 27171 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 27172 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 27173 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 27174 27175 static inline uint32_t ATTRIBUTE_PURE 27176 _3DSTATE_GATHER_CONSTANT_GS_CommandType_start(const struct gen_device_info *devinfo) 27177 { 27178 switch (devinfo->gen) { 27179 case 10: return 29; 27180 case 9: return 29; 27181 case 8: return 29; 27182 case 7: 27183 if (devinfo->is_haswell) { 27184 return 29; 27185 } else { 27186 return 0; 27187 } 27188 case 6: return 0; 27189 case 5: return 0; 27190 case 4: 27191 if (devinfo->is_g4x) { 27192 return 0; 27193 } else { 27194 return 0; 27195 } 27196 default: 27197 unreachable("Invalid hardware generation"); 27198 } 27199 } 27200 27201 27202 27203 /* 3DSTATE_GATHER_CONSTANT_GS::Constant Buffer Binding Table Block */ 27204 27205 27206 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 27207 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 27208 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 27209 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 27210 27211 static inline uint32_t ATTRIBUTE_PURE 27212 _3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits(const struct gen_device_info *devinfo) 27213 { 27214 switch (devinfo->gen) { 27215 case 10: return 4; 27216 case 9: return 4; 27217 case 8: return 4; 27218 case 7: 27219 if (devinfo->is_haswell) { 27220 return 4; 27221 } else { 27222 return 0; 27223 } 27224 case 6: return 0; 27225 case 5: return 0; 27226 case 4: 27227 if (devinfo->is_g4x) { 27228 return 0; 27229 } else { 27230 return 0; 27231 } 27232 default: 27233 unreachable("Invalid hardware generation"); 27234 } 27235 } 27236 27237 27238 27239 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 27240 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 27241 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 27242 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 27243 27244 static inline uint32_t ATTRIBUTE_PURE 27245 _3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start(const struct gen_device_info *devinfo) 27246 { 27247 switch (devinfo->gen) { 27248 case 10: return 44; 27249 case 9: return 44; 27250 case 8: return 44; 27251 case 7: 27252 if (devinfo->is_haswell) { 27253 return 44; 27254 } else { 27255 return 0; 27256 } 27257 case 6: return 0; 27258 case 5: return 0; 27259 case 4: 27260 if (devinfo->is_g4x) { 27261 return 0; 27262 } else { 27263 return 0; 27264 } 27265 default: 27266 unreachable("Invalid hardware generation"); 27267 } 27268 } 27269 27270 27271 27272 /* 3DSTATE_GATHER_CONSTANT_GS::Constant Buffer Dx9 Generate Stall */ 27273 27274 27275 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits 1 27276 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits 1 27277 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits 1 27278 27279 static inline uint32_t ATTRIBUTE_PURE 27280 _3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits(const struct gen_device_info *devinfo) 27281 { 27282 switch (devinfo->gen) { 27283 case 10: return 1; 27284 case 9: return 1; 27285 case 8: return 1; 27286 case 7: 27287 if (devinfo->is_haswell) { 27288 return 0; 27289 } else { 27290 return 0; 27291 } 27292 case 6: return 0; 27293 case 5: return 0; 27294 case 4: 27295 if (devinfo->is_g4x) { 27296 return 0; 27297 } else { 27298 return 0; 27299 } 27300 default: 27301 unreachable("Invalid hardware generation"); 27302 } 27303 } 27304 27305 27306 27307 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start 69 27308 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start 69 27309 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start 69 27310 27311 static inline uint32_t ATTRIBUTE_PURE 27312 _3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start(const struct gen_device_info *devinfo) 27313 { 27314 switch (devinfo->gen) { 27315 case 10: return 69; 27316 case 9: return 69; 27317 case 8: return 69; 27318 case 7: 27319 if (devinfo->is_haswell) { 27320 return 0; 27321 } else { 27322 return 0; 27323 } 27324 case 6: return 0; 27325 case 5: return 0; 27326 case 4: 27327 if (devinfo->is_g4x) { 27328 return 0; 27329 } else { 27330 return 0; 27331 } 27332 default: 27333 unreachable("Invalid hardware generation"); 27334 } 27335 } 27336 27337 27338 27339 /* 3DSTATE_GATHER_CONSTANT_GS::Constant Buffer Valid */ 27340 27341 27342 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 27343 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 27344 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 27345 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 27346 27347 static inline uint32_t ATTRIBUTE_PURE 27348 _3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits(const struct gen_device_info *devinfo) 27349 { 27350 switch (devinfo->gen) { 27351 case 10: return 16; 27352 case 9: return 16; 27353 case 8: return 16; 27354 case 7: 27355 if (devinfo->is_haswell) { 27356 return 16; 27357 } else { 27358 return 0; 27359 } 27360 case 6: return 0; 27361 case 5: return 0; 27362 case 4: 27363 if (devinfo->is_g4x) { 27364 return 0; 27365 } else { 27366 return 0; 27367 } 27368 default: 27369 unreachable("Invalid hardware generation"); 27370 } 27371 } 27372 27373 27374 27375 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 27376 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 27377 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 27378 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 27379 27380 static inline uint32_t ATTRIBUTE_PURE 27381 _3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start(const struct gen_device_info *devinfo) 27382 { 27383 switch (devinfo->gen) { 27384 case 10: return 48; 27385 case 9: return 48; 27386 case 8: return 48; 27387 case 7: 27388 if (devinfo->is_haswell) { 27389 return 48; 27390 } else { 27391 return 0; 27392 } 27393 case 6: return 0; 27394 case 5: return 0; 27395 case 4: 27396 if (devinfo->is_g4x) { 27397 return 0; 27398 } else { 27399 return 0; 27400 } 27401 default: 27402 unreachable("Invalid hardware generation"); 27403 } 27404 } 27405 27406 27407 27408 /* 3DSTATE_GATHER_CONSTANT_GS::DWord Length */ 27409 27410 27411 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 27412 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 27413 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 27414 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 27415 27416 static inline uint32_t ATTRIBUTE_PURE 27417 _3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits(const struct gen_device_info *devinfo) 27418 { 27419 switch (devinfo->gen) { 27420 case 10: return 8; 27421 case 9: return 8; 27422 case 8: return 8; 27423 case 7: 27424 if (devinfo->is_haswell) { 27425 return 8; 27426 } else { 27427 return 0; 27428 } 27429 case 6: return 0; 27430 case 5: return 0; 27431 case 4: 27432 if (devinfo->is_g4x) { 27433 return 0; 27434 } else { 27435 return 0; 27436 } 27437 default: 27438 unreachable("Invalid hardware generation"); 27439 } 27440 } 27441 27442 27443 27444 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 27445 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 27446 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 27447 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 27448 27449 static inline uint32_t ATTRIBUTE_PURE 27450 _3DSTATE_GATHER_CONSTANT_GS_DWordLength_start(const struct gen_device_info *devinfo) 27451 { 27452 switch (devinfo->gen) { 27453 case 10: return 0; 27454 case 9: return 0; 27455 case 8: return 0; 27456 case 7: 27457 if (devinfo->is_haswell) { 27458 return 0; 27459 } else { 27460 return 0; 27461 } 27462 case 6: return 0; 27463 case 5: return 0; 27464 case 4: 27465 if (devinfo->is_g4x) { 27466 return 0; 27467 } else { 27468 return 0; 27469 } 27470 default: 27471 unreachable("Invalid hardware generation"); 27472 } 27473 } 27474 27475 27476 27477 /* 3DSTATE_GATHER_CONSTANT_GS::Entry_0 */ 27478 27479 27480 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_Entry_0_bits 16 27481 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_Entry_0_bits 16 27482 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_Entry_0_bits 16 27483 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_Entry_0_bits 16 27484 27485 static inline uint32_t ATTRIBUTE_PURE 27486 _3DSTATE_GATHER_CONSTANT_GS_Entry_0_bits(const struct gen_device_info *devinfo) 27487 { 27488 switch (devinfo->gen) { 27489 case 10: return 16; 27490 case 9: return 16; 27491 case 8: return 16; 27492 case 7: 27493 if (devinfo->is_haswell) { 27494 return 16; 27495 } else { 27496 return 0; 27497 } 27498 case 6: return 0; 27499 case 5: return 0; 27500 case 4: 27501 if (devinfo->is_g4x) { 27502 return 0; 27503 } else { 27504 return 0; 27505 } 27506 default: 27507 unreachable("Invalid hardware generation"); 27508 } 27509 } 27510 27511 27512 27513 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_Entry_0_start 0 27514 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_Entry_0_start 0 27515 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_Entry_0_start 0 27516 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_Entry_0_start 0 27517 27518 static inline uint32_t ATTRIBUTE_PURE 27519 _3DSTATE_GATHER_CONSTANT_GS_Entry_0_start(const struct gen_device_info *devinfo) 27520 { 27521 switch (devinfo->gen) { 27522 case 10: return 0; 27523 case 9: return 0; 27524 case 8: return 0; 27525 case 7: 27526 if (devinfo->is_haswell) { 27527 return 0; 27528 } else { 27529 return 0; 27530 } 27531 case 6: return 0; 27532 case 5: return 0; 27533 case 4: 27534 if (devinfo->is_g4x) { 27535 return 0; 27536 } else { 27537 return 0; 27538 } 27539 default: 27540 unreachable("Invalid hardware generation"); 27541 } 27542 } 27543 27544 27545 27546 /* 3DSTATE_GATHER_CONSTANT_GS::Entry_1 */ 27547 27548 27549 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_Entry_1_bits 16 27550 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_Entry_1_bits 16 27551 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_Entry_1_bits 16 27552 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_Entry_1_bits 16 27553 27554 static inline uint32_t ATTRIBUTE_PURE 27555 _3DSTATE_GATHER_CONSTANT_GS_Entry_1_bits(const struct gen_device_info *devinfo) 27556 { 27557 switch (devinfo->gen) { 27558 case 10: return 16; 27559 case 9: return 16; 27560 case 8: return 16; 27561 case 7: 27562 if (devinfo->is_haswell) { 27563 return 16; 27564 } else { 27565 return 0; 27566 } 27567 case 6: return 0; 27568 case 5: return 0; 27569 case 4: 27570 if (devinfo->is_g4x) { 27571 return 0; 27572 } else { 27573 return 0; 27574 } 27575 default: 27576 unreachable("Invalid hardware generation"); 27577 } 27578 } 27579 27580 27581 27582 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_Entry_1_start 16 27583 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_Entry_1_start 16 27584 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_Entry_1_start 16 27585 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_Entry_1_start 16 27586 27587 static inline uint32_t ATTRIBUTE_PURE 27588 _3DSTATE_GATHER_CONSTANT_GS_Entry_1_start(const struct gen_device_info *devinfo) 27589 { 27590 switch (devinfo->gen) { 27591 case 10: return 16; 27592 case 9: return 16; 27593 case 8: return 16; 27594 case 7: 27595 if (devinfo->is_haswell) { 27596 return 16; 27597 } else { 27598 return 0; 27599 } 27600 case 6: return 0; 27601 case 5: return 0; 27602 case 4: 27603 if (devinfo->is_g4x) { 27604 return 0; 27605 } else { 27606 return 0; 27607 } 27608 default: 27609 unreachable("Invalid hardware generation"); 27610 } 27611 } 27612 27613 27614 27615 /* 3DSTATE_GATHER_CONSTANT_GS::Gather Buffer Offset */ 27616 27617 27618 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 27619 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 27620 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 27621 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 27622 27623 static inline uint32_t ATTRIBUTE_PURE 27624 _3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits(const struct gen_device_info *devinfo) 27625 { 27626 switch (devinfo->gen) { 27627 case 10: return 17; 27628 case 9: return 17; 27629 case 8: return 17; 27630 case 7: 27631 if (devinfo->is_haswell) { 27632 return 17; 27633 } else { 27634 return 0; 27635 } 27636 case 6: return 0; 27637 case 5: return 0; 27638 case 4: 27639 if (devinfo->is_g4x) { 27640 return 0; 27641 } else { 27642 return 0; 27643 } 27644 default: 27645 unreachable("Invalid hardware generation"); 27646 } 27647 } 27648 27649 27650 27651 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 27652 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 27653 #define GEN8_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 27654 #define GEN75_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 27655 27656 static inline uint32_t ATTRIBUTE_PURE 27657 _3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start(const struct gen_device_info *devinfo) 27658 { 27659 switch (devinfo->gen) { 27660 case 10: return 70; 27661 case 9: return 70; 27662 case 8: return 70; 27663 case 7: 27664 if (devinfo->is_haswell) { 27665 return 70; 27666 } else { 27667 return 0; 27668 } 27669 case 6: return 0; 27670 case 5: return 0; 27671 case 4: 27672 if (devinfo->is_g4x) { 27673 return 0; 27674 } else { 27675 return 0; 27676 } 27677 default: 27678 unreachable("Invalid hardware generation"); 27679 } 27680 } 27681 27682 27683 27684 /* 3DSTATE_GATHER_CONSTANT_GS::On-Die Table */ 27685 27686 27687 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_bits 1 27688 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_bits 1 27689 27690 static inline uint32_t ATTRIBUTE_PURE 27691 _3DSTATE_GATHER_CONSTANT_GS_OnDieTable_bits(const struct gen_device_info *devinfo) 27692 { 27693 switch (devinfo->gen) { 27694 case 10: return 1; 27695 case 9: return 1; 27696 case 8: return 0; 27697 case 7: 27698 if (devinfo->is_haswell) { 27699 return 0; 27700 } else { 27701 return 0; 27702 } 27703 case 6: return 0; 27704 case 5: return 0; 27705 case 4: 27706 if (devinfo->is_g4x) { 27707 return 0; 27708 } else { 27709 return 0; 27710 } 27711 default: 27712 unreachable("Invalid hardware generation"); 27713 } 27714 } 27715 27716 27717 27718 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_start 67 27719 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_start 67 27720 27721 static inline uint32_t ATTRIBUTE_PURE 27722 _3DSTATE_GATHER_CONSTANT_GS_OnDieTable_start(const struct gen_device_info *devinfo) 27723 { 27724 switch (devinfo->gen) { 27725 case 10: return 67; 27726 case 9: return 67; 27727 case 8: return 0; 27728 case 7: 27729 if (devinfo->is_haswell) { 27730 return 0; 27731 } else { 27732 return 0; 27733 } 27734 case 6: return 0; 27735 case 5: return 0; 27736 case 4: 27737 if (devinfo->is_g4x) { 27738 return 0; 27739 } else { 27740 return 0; 27741 } 27742 default: 27743 unreachable("Invalid hardware generation"); 27744 } 27745 } 27746 27747 27748 27749 /* 3DSTATE_GATHER_CONSTANT_GS::Update Gather Table Only */ 27750 27751 27752 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_bits 1 27753 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_bits 1 27754 27755 static inline uint32_t ATTRIBUTE_PURE 27756 _3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_bits(const struct gen_device_info *devinfo) 27757 { 27758 switch (devinfo->gen) { 27759 case 10: return 1; 27760 case 9: return 1; 27761 case 8: return 0; 27762 case 7: 27763 if (devinfo->is_haswell) { 27764 return 0; 27765 } else { 27766 return 0; 27767 } 27768 case 6: return 0; 27769 case 5: return 0; 27770 case 4: 27771 if (devinfo->is_g4x) { 27772 return 0; 27773 } else { 27774 return 0; 27775 } 27776 default: 27777 unreachable("Invalid hardware generation"); 27778 } 27779 } 27780 27781 27782 27783 #define GEN10_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_start 33 27784 #define GEN9_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_start 33 27785 27786 static inline uint32_t ATTRIBUTE_PURE 27787 _3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_start(const struct gen_device_info *devinfo) 27788 { 27789 switch (devinfo->gen) { 27790 case 10: return 33; 27791 case 9: return 33; 27792 case 8: return 0; 27793 case 7: 27794 if (devinfo->is_haswell) { 27795 return 0; 27796 } else { 27797 return 0; 27798 } 27799 case 6: return 0; 27800 case 5: return 0; 27801 case 4: 27802 if (devinfo->is_g4x) { 27803 return 0; 27804 } else { 27805 return 0; 27806 } 27807 default: 27808 unreachable("Invalid hardware generation"); 27809 } 27810 } 27811 27812 27813 27814 /* 3DSTATE_GATHER_CONSTANT_HS */ 27815 27816 27817 27818 27819 27820 /* 3DSTATE_GATHER_CONSTANT_HS::3D Command Opcode */ 27821 27822 27823 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 27824 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 27825 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 27826 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 27827 27828 static inline uint32_t ATTRIBUTE_PURE 27829 _3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 27830 { 27831 switch (devinfo->gen) { 27832 case 10: return 3; 27833 case 9: return 3; 27834 case 8: return 3; 27835 case 7: 27836 if (devinfo->is_haswell) { 27837 return 3; 27838 } else { 27839 return 0; 27840 } 27841 case 6: return 0; 27842 case 5: return 0; 27843 case 4: 27844 if (devinfo->is_g4x) { 27845 return 0; 27846 } else { 27847 return 0; 27848 } 27849 default: 27850 unreachable("Invalid hardware generation"); 27851 } 27852 } 27853 27854 27855 27856 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 27857 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 27858 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 27859 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 27860 27861 static inline uint32_t ATTRIBUTE_PURE 27862 _3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 27863 { 27864 switch (devinfo->gen) { 27865 case 10: return 24; 27866 case 9: return 24; 27867 case 8: return 24; 27868 case 7: 27869 if (devinfo->is_haswell) { 27870 return 24; 27871 } else { 27872 return 0; 27873 } 27874 case 6: return 0; 27875 case 5: return 0; 27876 case 4: 27877 if (devinfo->is_g4x) { 27878 return 0; 27879 } else { 27880 return 0; 27881 } 27882 default: 27883 unreachable("Invalid hardware generation"); 27884 } 27885 } 27886 27887 27888 27889 /* 3DSTATE_GATHER_CONSTANT_HS::3D Command Sub Opcode */ 27890 27891 27892 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 27893 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 27894 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 27895 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 27896 27897 static inline uint32_t ATTRIBUTE_PURE 27898 _3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 27899 { 27900 switch (devinfo->gen) { 27901 case 10: return 8; 27902 case 9: return 8; 27903 case 8: return 8; 27904 case 7: 27905 if (devinfo->is_haswell) { 27906 return 8; 27907 } else { 27908 return 0; 27909 } 27910 case 6: return 0; 27911 case 5: return 0; 27912 case 4: 27913 if (devinfo->is_g4x) { 27914 return 0; 27915 } else { 27916 return 0; 27917 } 27918 default: 27919 unreachable("Invalid hardware generation"); 27920 } 27921 } 27922 27923 27924 27925 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 27926 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 27927 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 27928 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 27929 27930 static inline uint32_t ATTRIBUTE_PURE 27931 _3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 27932 { 27933 switch (devinfo->gen) { 27934 case 10: return 16; 27935 case 9: return 16; 27936 case 8: return 16; 27937 case 7: 27938 if (devinfo->is_haswell) { 27939 return 16; 27940 } else { 27941 return 0; 27942 } 27943 case 6: return 0; 27944 case 5: return 0; 27945 case 4: 27946 if (devinfo->is_g4x) { 27947 return 0; 27948 } else { 27949 return 0; 27950 } 27951 default: 27952 unreachable("Invalid hardware generation"); 27953 } 27954 } 27955 27956 27957 27958 /* 3DSTATE_GATHER_CONSTANT_HS::Command SubType */ 27959 27960 27961 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 27962 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 27963 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 27964 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 27965 27966 static inline uint32_t ATTRIBUTE_PURE 27967 _3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits(const struct gen_device_info *devinfo) 27968 { 27969 switch (devinfo->gen) { 27970 case 10: return 2; 27971 case 9: return 2; 27972 case 8: return 2; 27973 case 7: 27974 if (devinfo->is_haswell) { 27975 return 2; 27976 } else { 27977 return 0; 27978 } 27979 case 6: return 0; 27980 case 5: return 0; 27981 case 4: 27982 if (devinfo->is_g4x) { 27983 return 0; 27984 } else { 27985 return 0; 27986 } 27987 default: 27988 unreachable("Invalid hardware generation"); 27989 } 27990 } 27991 27992 27993 27994 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 27995 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 27996 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 27997 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 27998 27999 static inline uint32_t ATTRIBUTE_PURE 28000 _3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start(const struct gen_device_info *devinfo) 28001 { 28002 switch (devinfo->gen) { 28003 case 10: return 27; 28004 case 9: return 27; 28005 case 8: return 27; 28006 case 7: 28007 if (devinfo->is_haswell) { 28008 return 27; 28009 } else { 28010 return 0; 28011 } 28012 case 6: return 0; 28013 case 5: return 0; 28014 case 4: 28015 if (devinfo->is_g4x) { 28016 return 0; 28017 } else { 28018 return 0; 28019 } 28020 default: 28021 unreachable("Invalid hardware generation"); 28022 } 28023 } 28024 28025 28026 28027 /* 3DSTATE_GATHER_CONSTANT_HS::Command Type */ 28028 28029 28030 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 28031 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 28032 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 28033 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 28034 28035 static inline uint32_t ATTRIBUTE_PURE 28036 _3DSTATE_GATHER_CONSTANT_HS_CommandType_bits(const struct gen_device_info *devinfo) 28037 { 28038 switch (devinfo->gen) { 28039 case 10: return 3; 28040 case 9: return 3; 28041 case 8: return 3; 28042 case 7: 28043 if (devinfo->is_haswell) { 28044 return 3; 28045 } else { 28046 return 0; 28047 } 28048 case 6: return 0; 28049 case 5: return 0; 28050 case 4: 28051 if (devinfo->is_g4x) { 28052 return 0; 28053 } else { 28054 return 0; 28055 } 28056 default: 28057 unreachable("Invalid hardware generation"); 28058 } 28059 } 28060 28061 28062 28063 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 28064 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 28065 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 28066 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 28067 28068 static inline uint32_t ATTRIBUTE_PURE 28069 _3DSTATE_GATHER_CONSTANT_HS_CommandType_start(const struct gen_device_info *devinfo) 28070 { 28071 switch (devinfo->gen) { 28072 case 10: return 29; 28073 case 9: return 29; 28074 case 8: return 29; 28075 case 7: 28076 if (devinfo->is_haswell) { 28077 return 29; 28078 } else { 28079 return 0; 28080 } 28081 case 6: return 0; 28082 case 5: return 0; 28083 case 4: 28084 if (devinfo->is_g4x) { 28085 return 0; 28086 } else { 28087 return 0; 28088 } 28089 default: 28090 unreachable("Invalid hardware generation"); 28091 } 28092 } 28093 28094 28095 28096 /* 3DSTATE_GATHER_CONSTANT_HS::Constant Buffer Binding Table Block */ 28097 28098 28099 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 28100 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 28101 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 28102 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 28103 28104 static inline uint32_t ATTRIBUTE_PURE 28105 _3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits(const struct gen_device_info *devinfo) 28106 { 28107 switch (devinfo->gen) { 28108 case 10: return 4; 28109 case 9: return 4; 28110 case 8: return 4; 28111 case 7: 28112 if (devinfo->is_haswell) { 28113 return 4; 28114 } else { 28115 return 0; 28116 } 28117 case 6: return 0; 28118 case 5: return 0; 28119 case 4: 28120 if (devinfo->is_g4x) { 28121 return 0; 28122 } else { 28123 return 0; 28124 } 28125 default: 28126 unreachable("Invalid hardware generation"); 28127 } 28128 } 28129 28130 28131 28132 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 28133 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 28134 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 28135 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 28136 28137 static inline uint32_t ATTRIBUTE_PURE 28138 _3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start(const struct gen_device_info *devinfo) 28139 { 28140 switch (devinfo->gen) { 28141 case 10: return 44; 28142 case 9: return 44; 28143 case 8: return 44; 28144 case 7: 28145 if (devinfo->is_haswell) { 28146 return 44; 28147 } else { 28148 return 0; 28149 } 28150 case 6: return 0; 28151 case 5: return 0; 28152 case 4: 28153 if (devinfo->is_g4x) { 28154 return 0; 28155 } else { 28156 return 0; 28157 } 28158 default: 28159 unreachable("Invalid hardware generation"); 28160 } 28161 } 28162 28163 28164 28165 /* 3DSTATE_GATHER_CONSTANT_HS::Constant Buffer Dx9 Generate Stall */ 28166 28167 28168 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits 1 28169 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits 1 28170 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits 1 28171 28172 static inline uint32_t ATTRIBUTE_PURE 28173 _3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits(const struct gen_device_info *devinfo) 28174 { 28175 switch (devinfo->gen) { 28176 case 10: return 1; 28177 case 9: return 1; 28178 case 8: return 1; 28179 case 7: 28180 if (devinfo->is_haswell) { 28181 return 0; 28182 } else { 28183 return 0; 28184 } 28185 case 6: return 0; 28186 case 5: return 0; 28187 case 4: 28188 if (devinfo->is_g4x) { 28189 return 0; 28190 } else { 28191 return 0; 28192 } 28193 default: 28194 unreachable("Invalid hardware generation"); 28195 } 28196 } 28197 28198 28199 28200 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start 69 28201 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start 69 28202 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start 69 28203 28204 static inline uint32_t ATTRIBUTE_PURE 28205 _3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start(const struct gen_device_info *devinfo) 28206 { 28207 switch (devinfo->gen) { 28208 case 10: return 69; 28209 case 9: return 69; 28210 case 8: return 69; 28211 case 7: 28212 if (devinfo->is_haswell) { 28213 return 0; 28214 } else { 28215 return 0; 28216 } 28217 case 6: return 0; 28218 case 5: return 0; 28219 case 4: 28220 if (devinfo->is_g4x) { 28221 return 0; 28222 } else { 28223 return 0; 28224 } 28225 default: 28226 unreachable("Invalid hardware generation"); 28227 } 28228 } 28229 28230 28231 28232 /* 3DSTATE_GATHER_CONSTANT_HS::Constant Buffer Valid */ 28233 28234 28235 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 28236 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 28237 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 28238 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 28239 28240 static inline uint32_t ATTRIBUTE_PURE 28241 _3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits(const struct gen_device_info *devinfo) 28242 { 28243 switch (devinfo->gen) { 28244 case 10: return 16; 28245 case 9: return 16; 28246 case 8: return 16; 28247 case 7: 28248 if (devinfo->is_haswell) { 28249 return 16; 28250 } else { 28251 return 0; 28252 } 28253 case 6: return 0; 28254 case 5: return 0; 28255 case 4: 28256 if (devinfo->is_g4x) { 28257 return 0; 28258 } else { 28259 return 0; 28260 } 28261 default: 28262 unreachable("Invalid hardware generation"); 28263 } 28264 } 28265 28266 28267 28268 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 28269 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 28270 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 28271 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 28272 28273 static inline uint32_t ATTRIBUTE_PURE 28274 _3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start(const struct gen_device_info *devinfo) 28275 { 28276 switch (devinfo->gen) { 28277 case 10: return 48; 28278 case 9: return 48; 28279 case 8: return 48; 28280 case 7: 28281 if (devinfo->is_haswell) { 28282 return 48; 28283 } else { 28284 return 0; 28285 } 28286 case 6: return 0; 28287 case 5: return 0; 28288 case 4: 28289 if (devinfo->is_g4x) { 28290 return 0; 28291 } else { 28292 return 0; 28293 } 28294 default: 28295 unreachable("Invalid hardware generation"); 28296 } 28297 } 28298 28299 28300 28301 /* 3DSTATE_GATHER_CONSTANT_HS::DWord Length */ 28302 28303 28304 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 28305 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 28306 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 28307 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 28308 28309 static inline uint32_t ATTRIBUTE_PURE 28310 _3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits(const struct gen_device_info *devinfo) 28311 { 28312 switch (devinfo->gen) { 28313 case 10: return 8; 28314 case 9: return 8; 28315 case 8: return 8; 28316 case 7: 28317 if (devinfo->is_haswell) { 28318 return 8; 28319 } else { 28320 return 0; 28321 } 28322 case 6: return 0; 28323 case 5: return 0; 28324 case 4: 28325 if (devinfo->is_g4x) { 28326 return 0; 28327 } else { 28328 return 0; 28329 } 28330 default: 28331 unreachable("Invalid hardware generation"); 28332 } 28333 } 28334 28335 28336 28337 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 28338 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 28339 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 28340 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 28341 28342 static inline uint32_t ATTRIBUTE_PURE 28343 _3DSTATE_GATHER_CONSTANT_HS_DWordLength_start(const struct gen_device_info *devinfo) 28344 { 28345 switch (devinfo->gen) { 28346 case 10: return 0; 28347 case 9: return 0; 28348 case 8: return 0; 28349 case 7: 28350 if (devinfo->is_haswell) { 28351 return 0; 28352 } else { 28353 return 0; 28354 } 28355 case 6: return 0; 28356 case 5: return 0; 28357 case 4: 28358 if (devinfo->is_g4x) { 28359 return 0; 28360 } else { 28361 return 0; 28362 } 28363 default: 28364 unreachable("Invalid hardware generation"); 28365 } 28366 } 28367 28368 28369 28370 /* 3DSTATE_GATHER_CONSTANT_HS::Entry_0 */ 28371 28372 28373 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_Entry_0_bits 16 28374 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_Entry_0_bits 16 28375 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_Entry_0_bits 16 28376 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_Entry_0_bits 16 28377 28378 static inline uint32_t ATTRIBUTE_PURE 28379 _3DSTATE_GATHER_CONSTANT_HS_Entry_0_bits(const struct gen_device_info *devinfo) 28380 { 28381 switch (devinfo->gen) { 28382 case 10: return 16; 28383 case 9: return 16; 28384 case 8: return 16; 28385 case 7: 28386 if (devinfo->is_haswell) { 28387 return 16; 28388 } else { 28389 return 0; 28390 } 28391 case 6: return 0; 28392 case 5: return 0; 28393 case 4: 28394 if (devinfo->is_g4x) { 28395 return 0; 28396 } else { 28397 return 0; 28398 } 28399 default: 28400 unreachable("Invalid hardware generation"); 28401 } 28402 } 28403 28404 28405 28406 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_Entry_0_start 0 28407 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_Entry_0_start 0 28408 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_Entry_0_start 0 28409 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_Entry_0_start 0 28410 28411 static inline uint32_t ATTRIBUTE_PURE 28412 _3DSTATE_GATHER_CONSTANT_HS_Entry_0_start(const struct gen_device_info *devinfo) 28413 { 28414 switch (devinfo->gen) { 28415 case 10: return 0; 28416 case 9: return 0; 28417 case 8: return 0; 28418 case 7: 28419 if (devinfo->is_haswell) { 28420 return 0; 28421 } else { 28422 return 0; 28423 } 28424 case 6: return 0; 28425 case 5: return 0; 28426 case 4: 28427 if (devinfo->is_g4x) { 28428 return 0; 28429 } else { 28430 return 0; 28431 } 28432 default: 28433 unreachable("Invalid hardware generation"); 28434 } 28435 } 28436 28437 28438 28439 /* 3DSTATE_GATHER_CONSTANT_HS::Entry_1 */ 28440 28441 28442 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_Entry_1_bits 16 28443 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_Entry_1_bits 16 28444 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_Entry_1_bits 16 28445 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_Entry_1_bits 16 28446 28447 static inline uint32_t ATTRIBUTE_PURE 28448 _3DSTATE_GATHER_CONSTANT_HS_Entry_1_bits(const struct gen_device_info *devinfo) 28449 { 28450 switch (devinfo->gen) { 28451 case 10: return 16; 28452 case 9: return 16; 28453 case 8: return 16; 28454 case 7: 28455 if (devinfo->is_haswell) { 28456 return 16; 28457 } else { 28458 return 0; 28459 } 28460 case 6: return 0; 28461 case 5: return 0; 28462 case 4: 28463 if (devinfo->is_g4x) { 28464 return 0; 28465 } else { 28466 return 0; 28467 } 28468 default: 28469 unreachable("Invalid hardware generation"); 28470 } 28471 } 28472 28473 28474 28475 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_Entry_1_start 16 28476 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_Entry_1_start 16 28477 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_Entry_1_start 16 28478 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_Entry_1_start 16 28479 28480 static inline uint32_t ATTRIBUTE_PURE 28481 _3DSTATE_GATHER_CONSTANT_HS_Entry_1_start(const struct gen_device_info *devinfo) 28482 { 28483 switch (devinfo->gen) { 28484 case 10: return 16; 28485 case 9: return 16; 28486 case 8: return 16; 28487 case 7: 28488 if (devinfo->is_haswell) { 28489 return 16; 28490 } else { 28491 return 0; 28492 } 28493 case 6: return 0; 28494 case 5: return 0; 28495 case 4: 28496 if (devinfo->is_g4x) { 28497 return 0; 28498 } else { 28499 return 0; 28500 } 28501 default: 28502 unreachable("Invalid hardware generation"); 28503 } 28504 } 28505 28506 28507 28508 /* 3DSTATE_GATHER_CONSTANT_HS::Gather Buffer Offset */ 28509 28510 28511 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 28512 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 28513 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 28514 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 28515 28516 static inline uint32_t ATTRIBUTE_PURE 28517 _3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits(const struct gen_device_info *devinfo) 28518 { 28519 switch (devinfo->gen) { 28520 case 10: return 17; 28521 case 9: return 17; 28522 case 8: return 17; 28523 case 7: 28524 if (devinfo->is_haswell) { 28525 return 17; 28526 } else { 28527 return 0; 28528 } 28529 case 6: return 0; 28530 case 5: return 0; 28531 case 4: 28532 if (devinfo->is_g4x) { 28533 return 0; 28534 } else { 28535 return 0; 28536 } 28537 default: 28538 unreachable("Invalid hardware generation"); 28539 } 28540 } 28541 28542 28543 28544 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 28545 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 28546 #define GEN8_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 28547 #define GEN75_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 28548 28549 static inline uint32_t ATTRIBUTE_PURE 28550 _3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start(const struct gen_device_info *devinfo) 28551 { 28552 switch (devinfo->gen) { 28553 case 10: return 70; 28554 case 9: return 70; 28555 case 8: return 70; 28556 case 7: 28557 if (devinfo->is_haswell) { 28558 return 70; 28559 } else { 28560 return 0; 28561 } 28562 case 6: return 0; 28563 case 5: return 0; 28564 case 4: 28565 if (devinfo->is_g4x) { 28566 return 0; 28567 } else { 28568 return 0; 28569 } 28570 default: 28571 unreachable("Invalid hardware generation"); 28572 } 28573 } 28574 28575 28576 28577 /* 3DSTATE_GATHER_CONSTANT_HS::On-Die Table */ 28578 28579 28580 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_bits 1 28581 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_bits 1 28582 28583 static inline uint32_t ATTRIBUTE_PURE 28584 _3DSTATE_GATHER_CONSTANT_HS_OnDieTable_bits(const struct gen_device_info *devinfo) 28585 { 28586 switch (devinfo->gen) { 28587 case 10: return 1; 28588 case 9: return 1; 28589 case 8: return 0; 28590 case 7: 28591 if (devinfo->is_haswell) { 28592 return 0; 28593 } else { 28594 return 0; 28595 } 28596 case 6: return 0; 28597 case 5: return 0; 28598 case 4: 28599 if (devinfo->is_g4x) { 28600 return 0; 28601 } else { 28602 return 0; 28603 } 28604 default: 28605 unreachable("Invalid hardware generation"); 28606 } 28607 } 28608 28609 28610 28611 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_start 67 28612 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_start 67 28613 28614 static inline uint32_t ATTRIBUTE_PURE 28615 _3DSTATE_GATHER_CONSTANT_HS_OnDieTable_start(const struct gen_device_info *devinfo) 28616 { 28617 switch (devinfo->gen) { 28618 case 10: return 67; 28619 case 9: return 67; 28620 case 8: return 0; 28621 case 7: 28622 if (devinfo->is_haswell) { 28623 return 0; 28624 } else { 28625 return 0; 28626 } 28627 case 6: return 0; 28628 case 5: return 0; 28629 case 4: 28630 if (devinfo->is_g4x) { 28631 return 0; 28632 } else { 28633 return 0; 28634 } 28635 default: 28636 unreachable("Invalid hardware generation"); 28637 } 28638 } 28639 28640 28641 28642 /* 3DSTATE_GATHER_CONSTANT_HS::Update Gather Table Only */ 28643 28644 28645 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_bits 1 28646 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_bits 1 28647 28648 static inline uint32_t ATTRIBUTE_PURE 28649 _3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_bits(const struct gen_device_info *devinfo) 28650 { 28651 switch (devinfo->gen) { 28652 case 10: return 1; 28653 case 9: return 1; 28654 case 8: return 0; 28655 case 7: 28656 if (devinfo->is_haswell) { 28657 return 0; 28658 } else { 28659 return 0; 28660 } 28661 case 6: return 0; 28662 case 5: return 0; 28663 case 4: 28664 if (devinfo->is_g4x) { 28665 return 0; 28666 } else { 28667 return 0; 28668 } 28669 default: 28670 unreachable("Invalid hardware generation"); 28671 } 28672 } 28673 28674 28675 28676 #define GEN10_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_start 33 28677 #define GEN9_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_start 33 28678 28679 static inline uint32_t ATTRIBUTE_PURE 28680 _3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_start(const struct gen_device_info *devinfo) 28681 { 28682 switch (devinfo->gen) { 28683 case 10: return 33; 28684 case 9: return 33; 28685 case 8: return 0; 28686 case 7: 28687 if (devinfo->is_haswell) { 28688 return 0; 28689 } else { 28690 return 0; 28691 } 28692 case 6: return 0; 28693 case 5: return 0; 28694 case 4: 28695 if (devinfo->is_g4x) { 28696 return 0; 28697 } else { 28698 return 0; 28699 } 28700 default: 28701 unreachable("Invalid hardware generation"); 28702 } 28703 } 28704 28705 28706 28707 /* 3DSTATE_GATHER_CONSTANT_PS */ 28708 28709 28710 28711 28712 28713 /* 3DSTATE_GATHER_CONSTANT_PS::3D Command Opcode */ 28714 28715 28716 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 28717 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 28718 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 28719 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 28720 28721 static inline uint32_t ATTRIBUTE_PURE 28722 _3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 28723 { 28724 switch (devinfo->gen) { 28725 case 10: return 3; 28726 case 9: return 3; 28727 case 8: return 3; 28728 case 7: 28729 if (devinfo->is_haswell) { 28730 return 3; 28731 } else { 28732 return 0; 28733 } 28734 case 6: return 0; 28735 case 5: return 0; 28736 case 4: 28737 if (devinfo->is_g4x) { 28738 return 0; 28739 } else { 28740 return 0; 28741 } 28742 default: 28743 unreachable("Invalid hardware generation"); 28744 } 28745 } 28746 28747 28748 28749 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 28750 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 28751 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 28752 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 28753 28754 static inline uint32_t ATTRIBUTE_PURE 28755 _3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 28756 { 28757 switch (devinfo->gen) { 28758 case 10: return 24; 28759 case 9: return 24; 28760 case 8: return 24; 28761 case 7: 28762 if (devinfo->is_haswell) { 28763 return 24; 28764 } else { 28765 return 0; 28766 } 28767 case 6: return 0; 28768 case 5: return 0; 28769 case 4: 28770 if (devinfo->is_g4x) { 28771 return 0; 28772 } else { 28773 return 0; 28774 } 28775 default: 28776 unreachable("Invalid hardware generation"); 28777 } 28778 } 28779 28780 28781 28782 /* 3DSTATE_GATHER_CONSTANT_PS::3D Command Sub Opcode */ 28783 28784 28785 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 28786 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 28787 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 28788 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 28789 28790 static inline uint32_t ATTRIBUTE_PURE 28791 _3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 28792 { 28793 switch (devinfo->gen) { 28794 case 10: return 8; 28795 case 9: return 8; 28796 case 8: return 8; 28797 case 7: 28798 if (devinfo->is_haswell) { 28799 return 8; 28800 } else { 28801 return 0; 28802 } 28803 case 6: return 0; 28804 case 5: return 0; 28805 case 4: 28806 if (devinfo->is_g4x) { 28807 return 0; 28808 } else { 28809 return 0; 28810 } 28811 default: 28812 unreachable("Invalid hardware generation"); 28813 } 28814 } 28815 28816 28817 28818 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 28819 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 28820 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 28821 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 28822 28823 static inline uint32_t ATTRIBUTE_PURE 28824 _3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 28825 { 28826 switch (devinfo->gen) { 28827 case 10: return 16; 28828 case 9: return 16; 28829 case 8: return 16; 28830 case 7: 28831 if (devinfo->is_haswell) { 28832 return 16; 28833 } else { 28834 return 0; 28835 } 28836 case 6: return 0; 28837 case 5: return 0; 28838 case 4: 28839 if (devinfo->is_g4x) { 28840 return 0; 28841 } else { 28842 return 0; 28843 } 28844 default: 28845 unreachable("Invalid hardware generation"); 28846 } 28847 } 28848 28849 28850 28851 /* 3DSTATE_GATHER_CONSTANT_PS::Command SubType */ 28852 28853 28854 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 28855 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 28856 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 28857 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 28858 28859 static inline uint32_t ATTRIBUTE_PURE 28860 _3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits(const struct gen_device_info *devinfo) 28861 { 28862 switch (devinfo->gen) { 28863 case 10: return 2; 28864 case 9: return 2; 28865 case 8: return 2; 28866 case 7: 28867 if (devinfo->is_haswell) { 28868 return 2; 28869 } else { 28870 return 0; 28871 } 28872 case 6: return 0; 28873 case 5: return 0; 28874 case 4: 28875 if (devinfo->is_g4x) { 28876 return 0; 28877 } else { 28878 return 0; 28879 } 28880 default: 28881 unreachable("Invalid hardware generation"); 28882 } 28883 } 28884 28885 28886 28887 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 28888 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 28889 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 28890 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 28891 28892 static inline uint32_t ATTRIBUTE_PURE 28893 _3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start(const struct gen_device_info *devinfo) 28894 { 28895 switch (devinfo->gen) { 28896 case 10: return 27; 28897 case 9: return 27; 28898 case 8: return 27; 28899 case 7: 28900 if (devinfo->is_haswell) { 28901 return 27; 28902 } else { 28903 return 0; 28904 } 28905 case 6: return 0; 28906 case 5: return 0; 28907 case 4: 28908 if (devinfo->is_g4x) { 28909 return 0; 28910 } else { 28911 return 0; 28912 } 28913 default: 28914 unreachable("Invalid hardware generation"); 28915 } 28916 } 28917 28918 28919 28920 /* 3DSTATE_GATHER_CONSTANT_PS::Command Type */ 28921 28922 28923 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 28924 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 28925 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 28926 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 28927 28928 static inline uint32_t ATTRIBUTE_PURE 28929 _3DSTATE_GATHER_CONSTANT_PS_CommandType_bits(const struct gen_device_info *devinfo) 28930 { 28931 switch (devinfo->gen) { 28932 case 10: return 3; 28933 case 9: return 3; 28934 case 8: return 3; 28935 case 7: 28936 if (devinfo->is_haswell) { 28937 return 3; 28938 } else { 28939 return 0; 28940 } 28941 case 6: return 0; 28942 case 5: return 0; 28943 case 4: 28944 if (devinfo->is_g4x) { 28945 return 0; 28946 } else { 28947 return 0; 28948 } 28949 default: 28950 unreachable("Invalid hardware generation"); 28951 } 28952 } 28953 28954 28955 28956 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 28957 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 28958 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 28959 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 28960 28961 static inline uint32_t ATTRIBUTE_PURE 28962 _3DSTATE_GATHER_CONSTANT_PS_CommandType_start(const struct gen_device_info *devinfo) 28963 { 28964 switch (devinfo->gen) { 28965 case 10: return 29; 28966 case 9: return 29; 28967 case 8: return 29; 28968 case 7: 28969 if (devinfo->is_haswell) { 28970 return 29; 28971 } else { 28972 return 0; 28973 } 28974 case 6: return 0; 28975 case 5: return 0; 28976 case 4: 28977 if (devinfo->is_g4x) { 28978 return 0; 28979 } else { 28980 return 0; 28981 } 28982 default: 28983 unreachable("Invalid hardware generation"); 28984 } 28985 } 28986 28987 28988 28989 /* 3DSTATE_GATHER_CONSTANT_PS::Constant Buffer Binding Table Block */ 28990 28991 28992 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 28993 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 28994 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 28995 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 28996 28997 static inline uint32_t ATTRIBUTE_PURE 28998 _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits(const struct gen_device_info *devinfo) 28999 { 29000 switch (devinfo->gen) { 29001 case 10: return 4; 29002 case 9: return 4; 29003 case 8: return 4; 29004 case 7: 29005 if (devinfo->is_haswell) { 29006 return 4; 29007 } else { 29008 return 0; 29009 } 29010 case 6: return 0; 29011 case 5: return 0; 29012 case 4: 29013 if (devinfo->is_g4x) { 29014 return 0; 29015 } else { 29016 return 0; 29017 } 29018 default: 29019 unreachable("Invalid hardware generation"); 29020 } 29021 } 29022 29023 29024 29025 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 29026 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 29027 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 29028 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 29029 29030 static inline uint32_t ATTRIBUTE_PURE 29031 _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start(const struct gen_device_info *devinfo) 29032 { 29033 switch (devinfo->gen) { 29034 case 10: return 44; 29035 case 9: return 44; 29036 case 8: return 44; 29037 case 7: 29038 if (devinfo->is_haswell) { 29039 return 44; 29040 } else { 29041 return 0; 29042 } 29043 case 6: return 0; 29044 case 5: return 0; 29045 case 4: 29046 if (devinfo->is_g4x) { 29047 return 0; 29048 } else { 29049 return 0; 29050 } 29051 default: 29052 unreachable("Invalid hardware generation"); 29053 } 29054 } 29055 29056 29057 29058 /* 3DSTATE_GATHER_CONSTANT_PS::Constant Buffer Dx9 Enable */ 29059 29060 29061 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 29062 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 29063 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 29064 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 29065 29066 static inline uint32_t ATTRIBUTE_PURE 29067 _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits(const struct gen_device_info *devinfo) 29068 { 29069 switch (devinfo->gen) { 29070 case 10: return 1; 29071 case 9: return 1; 29072 case 8: return 1; 29073 case 7: 29074 if (devinfo->is_haswell) { 29075 return 1; 29076 } else { 29077 return 0; 29078 } 29079 case 6: return 0; 29080 case 5: return 0; 29081 case 4: 29082 if (devinfo->is_g4x) { 29083 return 0; 29084 } else { 29085 return 0; 29086 } 29087 default: 29088 unreachable("Invalid hardware generation"); 29089 } 29090 } 29091 29092 29093 29094 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 29095 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 29096 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 29097 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 29098 29099 static inline uint32_t ATTRIBUTE_PURE 29100 _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start(const struct gen_device_info *devinfo) 29101 { 29102 switch (devinfo->gen) { 29103 case 10: return 68; 29104 case 9: return 68; 29105 case 8: return 68; 29106 case 7: 29107 if (devinfo->is_haswell) { 29108 return 68; 29109 } else { 29110 return 0; 29111 } 29112 case 6: return 0; 29113 case 5: return 0; 29114 case 4: 29115 if (devinfo->is_g4x) { 29116 return 0; 29117 } else { 29118 return 0; 29119 } 29120 default: 29121 unreachable("Invalid hardware generation"); 29122 } 29123 } 29124 29125 29126 29127 /* 3DSTATE_GATHER_CONSTANT_PS::Constant Buffer Dx9 Generate Stall */ 29128 29129 29130 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits 1 29131 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits 1 29132 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits 1 29133 29134 static inline uint32_t ATTRIBUTE_PURE 29135 _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits(const struct gen_device_info *devinfo) 29136 { 29137 switch (devinfo->gen) { 29138 case 10: return 1; 29139 case 9: return 1; 29140 case 8: return 1; 29141 case 7: 29142 if (devinfo->is_haswell) { 29143 return 0; 29144 } else { 29145 return 0; 29146 } 29147 case 6: return 0; 29148 case 5: return 0; 29149 case 4: 29150 if (devinfo->is_g4x) { 29151 return 0; 29152 } else { 29153 return 0; 29154 } 29155 default: 29156 unreachable("Invalid hardware generation"); 29157 } 29158 } 29159 29160 29161 29162 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start 69 29163 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start 69 29164 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start 69 29165 29166 static inline uint32_t ATTRIBUTE_PURE 29167 _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start(const struct gen_device_info *devinfo) 29168 { 29169 switch (devinfo->gen) { 29170 case 10: return 69; 29171 case 9: return 69; 29172 case 8: return 69; 29173 case 7: 29174 if (devinfo->is_haswell) { 29175 return 0; 29176 } else { 29177 return 0; 29178 } 29179 case 6: return 0; 29180 case 5: return 0; 29181 case 4: 29182 if (devinfo->is_g4x) { 29183 return 0; 29184 } else { 29185 return 0; 29186 } 29187 default: 29188 unreachable("Invalid hardware generation"); 29189 } 29190 } 29191 29192 29193 29194 /* 3DSTATE_GATHER_CONSTANT_PS::Constant Buffer Valid */ 29195 29196 29197 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 29198 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 29199 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 29200 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 29201 29202 static inline uint32_t ATTRIBUTE_PURE 29203 _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits(const struct gen_device_info *devinfo) 29204 { 29205 switch (devinfo->gen) { 29206 case 10: return 16; 29207 case 9: return 16; 29208 case 8: return 16; 29209 case 7: 29210 if (devinfo->is_haswell) { 29211 return 16; 29212 } else { 29213 return 0; 29214 } 29215 case 6: return 0; 29216 case 5: return 0; 29217 case 4: 29218 if (devinfo->is_g4x) { 29219 return 0; 29220 } else { 29221 return 0; 29222 } 29223 default: 29224 unreachable("Invalid hardware generation"); 29225 } 29226 } 29227 29228 29229 29230 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 29231 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 29232 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 29233 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 29234 29235 static inline uint32_t ATTRIBUTE_PURE 29236 _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start(const struct gen_device_info *devinfo) 29237 { 29238 switch (devinfo->gen) { 29239 case 10: return 48; 29240 case 9: return 48; 29241 case 8: return 48; 29242 case 7: 29243 if (devinfo->is_haswell) { 29244 return 48; 29245 } else { 29246 return 0; 29247 } 29248 case 6: return 0; 29249 case 5: return 0; 29250 case 4: 29251 if (devinfo->is_g4x) { 29252 return 0; 29253 } else { 29254 return 0; 29255 } 29256 default: 29257 unreachable("Invalid hardware generation"); 29258 } 29259 } 29260 29261 29262 29263 /* 3DSTATE_GATHER_CONSTANT_PS::DWord Length */ 29264 29265 29266 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 29267 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 29268 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 29269 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 29270 29271 static inline uint32_t ATTRIBUTE_PURE 29272 _3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits(const struct gen_device_info *devinfo) 29273 { 29274 switch (devinfo->gen) { 29275 case 10: return 8; 29276 case 9: return 8; 29277 case 8: return 8; 29278 case 7: 29279 if (devinfo->is_haswell) { 29280 return 8; 29281 } else { 29282 return 0; 29283 } 29284 case 6: return 0; 29285 case 5: return 0; 29286 case 4: 29287 if (devinfo->is_g4x) { 29288 return 0; 29289 } else { 29290 return 0; 29291 } 29292 default: 29293 unreachable("Invalid hardware generation"); 29294 } 29295 } 29296 29297 29298 29299 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 29300 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 29301 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 29302 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 29303 29304 static inline uint32_t ATTRIBUTE_PURE 29305 _3DSTATE_GATHER_CONSTANT_PS_DWordLength_start(const struct gen_device_info *devinfo) 29306 { 29307 switch (devinfo->gen) { 29308 case 10: return 0; 29309 case 9: return 0; 29310 case 8: return 0; 29311 case 7: 29312 if (devinfo->is_haswell) { 29313 return 0; 29314 } else { 29315 return 0; 29316 } 29317 case 6: return 0; 29318 case 5: return 0; 29319 case 4: 29320 if (devinfo->is_g4x) { 29321 return 0; 29322 } else { 29323 return 0; 29324 } 29325 default: 29326 unreachable("Invalid hardware generation"); 29327 } 29328 } 29329 29330 29331 29332 /* 3DSTATE_GATHER_CONSTANT_PS::DX9 On-Die Register Read Enable */ 29333 29334 29335 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_bits 1 29336 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_bits 1 29337 29338 static inline uint32_t ATTRIBUTE_PURE 29339 _3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_bits(const struct gen_device_info *devinfo) 29340 { 29341 switch (devinfo->gen) { 29342 case 10: return 1; 29343 case 9: return 1; 29344 case 8: return 0; 29345 case 7: 29346 if (devinfo->is_haswell) { 29347 return 0; 29348 } else { 29349 return 0; 29350 } 29351 case 6: return 0; 29352 case 5: return 0; 29353 case 4: 29354 if (devinfo->is_g4x) { 29355 return 0; 29356 } else { 29357 return 0; 29358 } 29359 default: 29360 unreachable("Invalid hardware generation"); 29361 } 29362 } 29363 29364 29365 29366 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_start 32 29367 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_start 32 29368 29369 static inline uint32_t ATTRIBUTE_PURE 29370 _3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_start(const struct gen_device_info *devinfo) 29371 { 29372 switch (devinfo->gen) { 29373 case 10: return 32; 29374 case 9: return 32; 29375 case 8: return 0; 29376 case 7: 29377 if (devinfo->is_haswell) { 29378 return 0; 29379 } else { 29380 return 0; 29381 } 29382 case 6: return 0; 29383 case 5: return 0; 29384 case 4: 29385 if (devinfo->is_g4x) { 29386 return 0; 29387 } else { 29388 return 0; 29389 } 29390 default: 29391 unreachable("Invalid hardware generation"); 29392 } 29393 } 29394 29395 29396 29397 /* 3DSTATE_GATHER_CONSTANT_PS::Entry_0 */ 29398 29399 29400 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_Entry_0_bits 16 29401 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_Entry_0_bits 16 29402 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_Entry_0_bits 16 29403 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_Entry_0_bits 16 29404 29405 static inline uint32_t ATTRIBUTE_PURE 29406 _3DSTATE_GATHER_CONSTANT_PS_Entry_0_bits(const struct gen_device_info *devinfo) 29407 { 29408 switch (devinfo->gen) { 29409 case 10: return 16; 29410 case 9: return 16; 29411 case 8: return 16; 29412 case 7: 29413 if (devinfo->is_haswell) { 29414 return 16; 29415 } else { 29416 return 0; 29417 } 29418 case 6: return 0; 29419 case 5: return 0; 29420 case 4: 29421 if (devinfo->is_g4x) { 29422 return 0; 29423 } else { 29424 return 0; 29425 } 29426 default: 29427 unreachable("Invalid hardware generation"); 29428 } 29429 } 29430 29431 29432 29433 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_Entry_0_start 0 29434 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_Entry_0_start 0 29435 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_Entry_0_start 0 29436 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_Entry_0_start 0 29437 29438 static inline uint32_t ATTRIBUTE_PURE 29439 _3DSTATE_GATHER_CONSTANT_PS_Entry_0_start(const struct gen_device_info *devinfo) 29440 { 29441 switch (devinfo->gen) { 29442 case 10: return 0; 29443 case 9: return 0; 29444 case 8: return 0; 29445 case 7: 29446 if (devinfo->is_haswell) { 29447 return 0; 29448 } else { 29449 return 0; 29450 } 29451 case 6: return 0; 29452 case 5: return 0; 29453 case 4: 29454 if (devinfo->is_g4x) { 29455 return 0; 29456 } else { 29457 return 0; 29458 } 29459 default: 29460 unreachable("Invalid hardware generation"); 29461 } 29462 } 29463 29464 29465 29466 /* 3DSTATE_GATHER_CONSTANT_PS::Entry_1 */ 29467 29468 29469 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_Entry_1_bits 16 29470 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_Entry_1_bits 16 29471 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_Entry_1_bits 16 29472 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_Entry_1_bits 16 29473 29474 static inline uint32_t ATTRIBUTE_PURE 29475 _3DSTATE_GATHER_CONSTANT_PS_Entry_1_bits(const struct gen_device_info *devinfo) 29476 { 29477 switch (devinfo->gen) { 29478 case 10: return 16; 29479 case 9: return 16; 29480 case 8: return 16; 29481 case 7: 29482 if (devinfo->is_haswell) { 29483 return 16; 29484 } else { 29485 return 0; 29486 } 29487 case 6: return 0; 29488 case 5: return 0; 29489 case 4: 29490 if (devinfo->is_g4x) { 29491 return 0; 29492 } else { 29493 return 0; 29494 } 29495 default: 29496 unreachable("Invalid hardware generation"); 29497 } 29498 } 29499 29500 29501 29502 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_Entry_1_start 16 29503 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_Entry_1_start 16 29504 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_Entry_1_start 16 29505 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_Entry_1_start 16 29506 29507 static inline uint32_t ATTRIBUTE_PURE 29508 _3DSTATE_GATHER_CONSTANT_PS_Entry_1_start(const struct gen_device_info *devinfo) 29509 { 29510 switch (devinfo->gen) { 29511 case 10: return 16; 29512 case 9: return 16; 29513 case 8: return 16; 29514 case 7: 29515 if (devinfo->is_haswell) { 29516 return 16; 29517 } else { 29518 return 0; 29519 } 29520 case 6: return 0; 29521 case 5: return 0; 29522 case 4: 29523 if (devinfo->is_g4x) { 29524 return 0; 29525 } else { 29526 return 0; 29527 } 29528 default: 29529 unreachable("Invalid hardware generation"); 29530 } 29531 } 29532 29533 29534 29535 /* 3DSTATE_GATHER_CONSTANT_PS::Gather Buffer Offset */ 29536 29537 29538 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 29539 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 29540 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 29541 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 29542 29543 static inline uint32_t ATTRIBUTE_PURE 29544 _3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits(const struct gen_device_info *devinfo) 29545 { 29546 switch (devinfo->gen) { 29547 case 10: return 17; 29548 case 9: return 17; 29549 case 8: return 17; 29550 case 7: 29551 if (devinfo->is_haswell) { 29552 return 17; 29553 } else { 29554 return 0; 29555 } 29556 case 6: return 0; 29557 case 5: return 0; 29558 case 4: 29559 if (devinfo->is_g4x) { 29560 return 0; 29561 } else { 29562 return 0; 29563 } 29564 default: 29565 unreachable("Invalid hardware generation"); 29566 } 29567 } 29568 29569 29570 29571 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 29572 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 29573 #define GEN8_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 29574 #define GEN75_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 29575 29576 static inline uint32_t ATTRIBUTE_PURE 29577 _3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start(const struct gen_device_info *devinfo) 29578 { 29579 switch (devinfo->gen) { 29580 case 10: return 70; 29581 case 9: return 70; 29582 case 8: return 70; 29583 case 7: 29584 if (devinfo->is_haswell) { 29585 return 70; 29586 } else { 29587 return 0; 29588 } 29589 case 6: return 0; 29590 case 5: return 0; 29591 case 4: 29592 if (devinfo->is_g4x) { 29593 return 0; 29594 } else { 29595 return 0; 29596 } 29597 default: 29598 unreachable("Invalid hardware generation"); 29599 } 29600 } 29601 29602 29603 29604 /* 3DSTATE_GATHER_CONSTANT_PS::On-Die Table */ 29605 29606 29607 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_bits 1 29608 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_bits 1 29609 29610 static inline uint32_t ATTRIBUTE_PURE 29611 _3DSTATE_GATHER_CONSTANT_PS_OnDieTable_bits(const struct gen_device_info *devinfo) 29612 { 29613 switch (devinfo->gen) { 29614 case 10: return 1; 29615 case 9: return 1; 29616 case 8: return 0; 29617 case 7: 29618 if (devinfo->is_haswell) { 29619 return 0; 29620 } else { 29621 return 0; 29622 } 29623 case 6: return 0; 29624 case 5: return 0; 29625 case 4: 29626 if (devinfo->is_g4x) { 29627 return 0; 29628 } else { 29629 return 0; 29630 } 29631 default: 29632 unreachable("Invalid hardware generation"); 29633 } 29634 } 29635 29636 29637 29638 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_start 67 29639 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_start 67 29640 29641 static inline uint32_t ATTRIBUTE_PURE 29642 _3DSTATE_GATHER_CONSTANT_PS_OnDieTable_start(const struct gen_device_info *devinfo) 29643 { 29644 switch (devinfo->gen) { 29645 case 10: return 67; 29646 case 9: return 67; 29647 case 8: return 0; 29648 case 7: 29649 if (devinfo->is_haswell) { 29650 return 0; 29651 } else { 29652 return 0; 29653 } 29654 case 6: return 0; 29655 case 5: return 0; 29656 case 4: 29657 if (devinfo->is_g4x) { 29658 return 0; 29659 } else { 29660 return 0; 29661 } 29662 default: 29663 unreachable("Invalid hardware generation"); 29664 } 29665 } 29666 29667 29668 29669 /* 3DSTATE_GATHER_CONSTANT_PS::Update Gather Table Only */ 29670 29671 29672 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_bits 1 29673 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_bits 1 29674 29675 static inline uint32_t ATTRIBUTE_PURE 29676 _3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_bits(const struct gen_device_info *devinfo) 29677 { 29678 switch (devinfo->gen) { 29679 case 10: return 1; 29680 case 9: return 1; 29681 case 8: return 0; 29682 case 7: 29683 if (devinfo->is_haswell) { 29684 return 0; 29685 } else { 29686 return 0; 29687 } 29688 case 6: return 0; 29689 case 5: return 0; 29690 case 4: 29691 if (devinfo->is_g4x) { 29692 return 0; 29693 } else { 29694 return 0; 29695 } 29696 default: 29697 unreachable("Invalid hardware generation"); 29698 } 29699 } 29700 29701 29702 29703 #define GEN10_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_start 33 29704 #define GEN9_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_start 33 29705 29706 static inline uint32_t ATTRIBUTE_PURE 29707 _3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_start(const struct gen_device_info *devinfo) 29708 { 29709 switch (devinfo->gen) { 29710 case 10: return 33; 29711 case 9: return 33; 29712 case 8: return 0; 29713 case 7: 29714 if (devinfo->is_haswell) { 29715 return 0; 29716 } else { 29717 return 0; 29718 } 29719 case 6: return 0; 29720 case 5: return 0; 29721 case 4: 29722 if (devinfo->is_g4x) { 29723 return 0; 29724 } else { 29725 return 0; 29726 } 29727 default: 29728 unreachable("Invalid hardware generation"); 29729 } 29730 } 29731 29732 29733 29734 /* 3DSTATE_GATHER_CONSTANT_VS */ 29735 29736 29737 29738 29739 29740 /* 3DSTATE_GATHER_CONSTANT_VS::3D Command Opcode */ 29741 29742 29743 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 29744 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 29745 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 29746 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 29747 29748 static inline uint32_t ATTRIBUTE_PURE 29749 _3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 29750 { 29751 switch (devinfo->gen) { 29752 case 10: return 3; 29753 case 9: return 3; 29754 case 8: return 3; 29755 case 7: 29756 if (devinfo->is_haswell) { 29757 return 3; 29758 } else { 29759 return 0; 29760 } 29761 case 6: return 0; 29762 case 5: return 0; 29763 case 4: 29764 if (devinfo->is_g4x) { 29765 return 0; 29766 } else { 29767 return 0; 29768 } 29769 default: 29770 unreachable("Invalid hardware generation"); 29771 } 29772 } 29773 29774 29775 29776 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 29777 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 29778 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 29779 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 29780 29781 static inline uint32_t ATTRIBUTE_PURE 29782 _3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 29783 { 29784 switch (devinfo->gen) { 29785 case 10: return 24; 29786 case 9: return 24; 29787 case 8: return 24; 29788 case 7: 29789 if (devinfo->is_haswell) { 29790 return 24; 29791 } else { 29792 return 0; 29793 } 29794 case 6: return 0; 29795 case 5: return 0; 29796 case 4: 29797 if (devinfo->is_g4x) { 29798 return 0; 29799 } else { 29800 return 0; 29801 } 29802 default: 29803 unreachable("Invalid hardware generation"); 29804 } 29805 } 29806 29807 29808 29809 /* 3DSTATE_GATHER_CONSTANT_VS::3D Command Sub Opcode */ 29810 29811 29812 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 29813 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 29814 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 29815 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 29816 29817 static inline uint32_t ATTRIBUTE_PURE 29818 _3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 29819 { 29820 switch (devinfo->gen) { 29821 case 10: return 8; 29822 case 9: return 8; 29823 case 8: return 8; 29824 case 7: 29825 if (devinfo->is_haswell) { 29826 return 8; 29827 } else { 29828 return 0; 29829 } 29830 case 6: return 0; 29831 case 5: return 0; 29832 case 4: 29833 if (devinfo->is_g4x) { 29834 return 0; 29835 } else { 29836 return 0; 29837 } 29838 default: 29839 unreachable("Invalid hardware generation"); 29840 } 29841 } 29842 29843 29844 29845 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 29846 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 29847 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 29848 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 29849 29850 static inline uint32_t ATTRIBUTE_PURE 29851 _3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 29852 { 29853 switch (devinfo->gen) { 29854 case 10: return 16; 29855 case 9: return 16; 29856 case 8: return 16; 29857 case 7: 29858 if (devinfo->is_haswell) { 29859 return 16; 29860 } else { 29861 return 0; 29862 } 29863 case 6: return 0; 29864 case 5: return 0; 29865 case 4: 29866 if (devinfo->is_g4x) { 29867 return 0; 29868 } else { 29869 return 0; 29870 } 29871 default: 29872 unreachable("Invalid hardware generation"); 29873 } 29874 } 29875 29876 29877 29878 /* 3DSTATE_GATHER_CONSTANT_VS::Command SubType */ 29879 29880 29881 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 29882 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 29883 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 29884 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 29885 29886 static inline uint32_t ATTRIBUTE_PURE 29887 _3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits(const struct gen_device_info *devinfo) 29888 { 29889 switch (devinfo->gen) { 29890 case 10: return 2; 29891 case 9: return 2; 29892 case 8: return 2; 29893 case 7: 29894 if (devinfo->is_haswell) { 29895 return 2; 29896 } else { 29897 return 0; 29898 } 29899 case 6: return 0; 29900 case 5: return 0; 29901 case 4: 29902 if (devinfo->is_g4x) { 29903 return 0; 29904 } else { 29905 return 0; 29906 } 29907 default: 29908 unreachable("Invalid hardware generation"); 29909 } 29910 } 29911 29912 29913 29914 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 29915 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 29916 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 29917 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 29918 29919 static inline uint32_t ATTRIBUTE_PURE 29920 _3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start(const struct gen_device_info *devinfo) 29921 { 29922 switch (devinfo->gen) { 29923 case 10: return 27; 29924 case 9: return 27; 29925 case 8: return 27; 29926 case 7: 29927 if (devinfo->is_haswell) { 29928 return 27; 29929 } else { 29930 return 0; 29931 } 29932 case 6: return 0; 29933 case 5: return 0; 29934 case 4: 29935 if (devinfo->is_g4x) { 29936 return 0; 29937 } else { 29938 return 0; 29939 } 29940 default: 29941 unreachable("Invalid hardware generation"); 29942 } 29943 } 29944 29945 29946 29947 /* 3DSTATE_GATHER_CONSTANT_VS::Command Type */ 29948 29949 29950 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 29951 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 29952 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 29953 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 29954 29955 static inline uint32_t ATTRIBUTE_PURE 29956 _3DSTATE_GATHER_CONSTANT_VS_CommandType_bits(const struct gen_device_info *devinfo) 29957 { 29958 switch (devinfo->gen) { 29959 case 10: return 3; 29960 case 9: return 3; 29961 case 8: return 3; 29962 case 7: 29963 if (devinfo->is_haswell) { 29964 return 3; 29965 } else { 29966 return 0; 29967 } 29968 case 6: return 0; 29969 case 5: return 0; 29970 case 4: 29971 if (devinfo->is_g4x) { 29972 return 0; 29973 } else { 29974 return 0; 29975 } 29976 default: 29977 unreachable("Invalid hardware generation"); 29978 } 29979 } 29980 29981 29982 29983 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 29984 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 29985 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 29986 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 29987 29988 static inline uint32_t ATTRIBUTE_PURE 29989 _3DSTATE_GATHER_CONSTANT_VS_CommandType_start(const struct gen_device_info *devinfo) 29990 { 29991 switch (devinfo->gen) { 29992 case 10: return 29; 29993 case 9: return 29; 29994 case 8: return 29; 29995 case 7: 29996 if (devinfo->is_haswell) { 29997 return 29; 29998 } else { 29999 return 0; 30000 } 30001 case 6: return 0; 30002 case 5: return 0; 30003 case 4: 30004 if (devinfo->is_g4x) { 30005 return 0; 30006 } else { 30007 return 0; 30008 } 30009 default: 30010 unreachable("Invalid hardware generation"); 30011 } 30012 } 30013 30014 30015 30016 /* 3DSTATE_GATHER_CONSTANT_VS::Constant Buffer Binding Table Block */ 30017 30018 30019 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 30020 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 30021 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 30022 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 30023 30024 static inline uint32_t ATTRIBUTE_PURE 30025 _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits(const struct gen_device_info *devinfo) 30026 { 30027 switch (devinfo->gen) { 30028 case 10: return 4; 30029 case 9: return 4; 30030 case 8: return 4; 30031 case 7: 30032 if (devinfo->is_haswell) { 30033 return 4; 30034 } else { 30035 return 0; 30036 } 30037 case 6: return 0; 30038 case 5: return 0; 30039 case 4: 30040 if (devinfo->is_g4x) { 30041 return 0; 30042 } else { 30043 return 0; 30044 } 30045 default: 30046 unreachable("Invalid hardware generation"); 30047 } 30048 } 30049 30050 30051 30052 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 30053 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 30054 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 30055 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 30056 30057 static inline uint32_t ATTRIBUTE_PURE 30058 _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start(const struct gen_device_info *devinfo) 30059 { 30060 switch (devinfo->gen) { 30061 case 10: return 44; 30062 case 9: return 44; 30063 case 8: return 44; 30064 case 7: 30065 if (devinfo->is_haswell) { 30066 return 44; 30067 } else { 30068 return 0; 30069 } 30070 case 6: return 0; 30071 case 5: return 0; 30072 case 4: 30073 if (devinfo->is_g4x) { 30074 return 0; 30075 } else { 30076 return 0; 30077 } 30078 default: 30079 unreachable("Invalid hardware generation"); 30080 } 30081 } 30082 30083 30084 30085 /* 3DSTATE_GATHER_CONSTANT_VS::Constant Buffer Dx9 Enable */ 30086 30087 30088 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 30089 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 30090 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 30091 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 30092 30093 static inline uint32_t ATTRIBUTE_PURE 30094 _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits(const struct gen_device_info *devinfo) 30095 { 30096 switch (devinfo->gen) { 30097 case 10: return 1; 30098 case 9: return 1; 30099 case 8: return 1; 30100 case 7: 30101 if (devinfo->is_haswell) { 30102 return 1; 30103 } else { 30104 return 0; 30105 } 30106 case 6: return 0; 30107 case 5: return 0; 30108 case 4: 30109 if (devinfo->is_g4x) { 30110 return 0; 30111 } else { 30112 return 0; 30113 } 30114 default: 30115 unreachable("Invalid hardware generation"); 30116 } 30117 } 30118 30119 30120 30121 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 30122 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 30123 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 30124 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 30125 30126 static inline uint32_t ATTRIBUTE_PURE 30127 _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start(const struct gen_device_info *devinfo) 30128 { 30129 switch (devinfo->gen) { 30130 case 10: return 68; 30131 case 9: return 68; 30132 case 8: return 68; 30133 case 7: 30134 if (devinfo->is_haswell) { 30135 return 68; 30136 } else { 30137 return 0; 30138 } 30139 case 6: return 0; 30140 case 5: return 0; 30141 case 4: 30142 if (devinfo->is_g4x) { 30143 return 0; 30144 } else { 30145 return 0; 30146 } 30147 default: 30148 unreachable("Invalid hardware generation"); 30149 } 30150 } 30151 30152 30153 30154 /* 3DSTATE_GATHER_CONSTANT_VS::Constant Buffer Dx9 Generate Stall */ 30155 30156 30157 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits 1 30158 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits 1 30159 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits 1 30160 30161 static inline uint32_t ATTRIBUTE_PURE 30162 _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits(const struct gen_device_info *devinfo) 30163 { 30164 switch (devinfo->gen) { 30165 case 10: return 1; 30166 case 9: return 1; 30167 case 8: return 1; 30168 case 7: 30169 if (devinfo->is_haswell) { 30170 return 0; 30171 } else { 30172 return 0; 30173 } 30174 case 6: return 0; 30175 case 5: return 0; 30176 case 4: 30177 if (devinfo->is_g4x) { 30178 return 0; 30179 } else { 30180 return 0; 30181 } 30182 default: 30183 unreachable("Invalid hardware generation"); 30184 } 30185 } 30186 30187 30188 30189 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start 69 30190 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start 69 30191 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start 69 30192 30193 static inline uint32_t ATTRIBUTE_PURE 30194 _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start(const struct gen_device_info *devinfo) 30195 { 30196 switch (devinfo->gen) { 30197 case 10: return 69; 30198 case 9: return 69; 30199 case 8: return 69; 30200 case 7: 30201 if (devinfo->is_haswell) { 30202 return 0; 30203 } else { 30204 return 0; 30205 } 30206 case 6: return 0; 30207 case 5: return 0; 30208 case 4: 30209 if (devinfo->is_g4x) { 30210 return 0; 30211 } else { 30212 return 0; 30213 } 30214 default: 30215 unreachable("Invalid hardware generation"); 30216 } 30217 } 30218 30219 30220 30221 /* 3DSTATE_GATHER_CONSTANT_VS::Constant Buffer Valid */ 30222 30223 30224 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 30225 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 30226 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 30227 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 30228 30229 static inline uint32_t ATTRIBUTE_PURE 30230 _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits(const struct gen_device_info *devinfo) 30231 { 30232 switch (devinfo->gen) { 30233 case 10: return 16; 30234 case 9: return 16; 30235 case 8: return 16; 30236 case 7: 30237 if (devinfo->is_haswell) { 30238 return 16; 30239 } else { 30240 return 0; 30241 } 30242 case 6: return 0; 30243 case 5: return 0; 30244 case 4: 30245 if (devinfo->is_g4x) { 30246 return 0; 30247 } else { 30248 return 0; 30249 } 30250 default: 30251 unreachable("Invalid hardware generation"); 30252 } 30253 } 30254 30255 30256 30257 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 30258 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 30259 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 30260 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 30261 30262 static inline uint32_t ATTRIBUTE_PURE 30263 _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start(const struct gen_device_info *devinfo) 30264 { 30265 switch (devinfo->gen) { 30266 case 10: return 48; 30267 case 9: return 48; 30268 case 8: return 48; 30269 case 7: 30270 if (devinfo->is_haswell) { 30271 return 48; 30272 } else { 30273 return 0; 30274 } 30275 case 6: return 0; 30276 case 5: return 0; 30277 case 4: 30278 if (devinfo->is_g4x) { 30279 return 0; 30280 } else { 30281 return 0; 30282 } 30283 default: 30284 unreachable("Invalid hardware generation"); 30285 } 30286 } 30287 30288 30289 30290 /* 3DSTATE_GATHER_CONSTANT_VS::DWord Length */ 30291 30292 30293 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 30294 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 30295 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 30296 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 30297 30298 static inline uint32_t ATTRIBUTE_PURE 30299 _3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits(const struct gen_device_info *devinfo) 30300 { 30301 switch (devinfo->gen) { 30302 case 10: return 8; 30303 case 9: return 8; 30304 case 8: return 8; 30305 case 7: 30306 if (devinfo->is_haswell) { 30307 return 8; 30308 } else { 30309 return 0; 30310 } 30311 case 6: return 0; 30312 case 5: return 0; 30313 case 4: 30314 if (devinfo->is_g4x) { 30315 return 0; 30316 } else { 30317 return 0; 30318 } 30319 default: 30320 unreachable("Invalid hardware generation"); 30321 } 30322 } 30323 30324 30325 30326 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 30327 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 30328 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 30329 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 30330 30331 static inline uint32_t ATTRIBUTE_PURE 30332 _3DSTATE_GATHER_CONSTANT_VS_DWordLength_start(const struct gen_device_info *devinfo) 30333 { 30334 switch (devinfo->gen) { 30335 case 10: return 0; 30336 case 9: return 0; 30337 case 8: return 0; 30338 case 7: 30339 if (devinfo->is_haswell) { 30340 return 0; 30341 } else { 30342 return 0; 30343 } 30344 case 6: return 0; 30345 case 5: return 0; 30346 case 4: 30347 if (devinfo->is_g4x) { 30348 return 0; 30349 } else { 30350 return 0; 30351 } 30352 default: 30353 unreachable("Invalid hardware generation"); 30354 } 30355 } 30356 30357 30358 30359 /* 3DSTATE_GATHER_CONSTANT_VS::DX9 On-Die Register Read Enable */ 30360 30361 30362 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_bits 1 30363 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_bits 1 30364 30365 static inline uint32_t ATTRIBUTE_PURE 30366 _3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_bits(const struct gen_device_info *devinfo) 30367 { 30368 switch (devinfo->gen) { 30369 case 10: return 1; 30370 case 9: return 1; 30371 case 8: return 0; 30372 case 7: 30373 if (devinfo->is_haswell) { 30374 return 0; 30375 } else { 30376 return 0; 30377 } 30378 case 6: return 0; 30379 case 5: return 0; 30380 case 4: 30381 if (devinfo->is_g4x) { 30382 return 0; 30383 } else { 30384 return 0; 30385 } 30386 default: 30387 unreachable("Invalid hardware generation"); 30388 } 30389 } 30390 30391 30392 30393 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_start 32 30394 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_start 32 30395 30396 static inline uint32_t ATTRIBUTE_PURE 30397 _3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_start(const struct gen_device_info *devinfo) 30398 { 30399 switch (devinfo->gen) { 30400 case 10: return 32; 30401 case 9: return 32; 30402 case 8: return 0; 30403 case 7: 30404 if (devinfo->is_haswell) { 30405 return 0; 30406 } else { 30407 return 0; 30408 } 30409 case 6: return 0; 30410 case 5: return 0; 30411 case 4: 30412 if (devinfo->is_g4x) { 30413 return 0; 30414 } else { 30415 return 0; 30416 } 30417 default: 30418 unreachable("Invalid hardware generation"); 30419 } 30420 } 30421 30422 30423 30424 /* 3DSTATE_GATHER_CONSTANT_VS::Entry_0 */ 30425 30426 30427 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_Entry_0_bits 16 30428 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_Entry_0_bits 16 30429 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_Entry_0_bits 16 30430 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_Entry_0_bits 16 30431 30432 static inline uint32_t ATTRIBUTE_PURE 30433 _3DSTATE_GATHER_CONSTANT_VS_Entry_0_bits(const struct gen_device_info *devinfo) 30434 { 30435 switch (devinfo->gen) { 30436 case 10: return 16; 30437 case 9: return 16; 30438 case 8: return 16; 30439 case 7: 30440 if (devinfo->is_haswell) { 30441 return 16; 30442 } else { 30443 return 0; 30444 } 30445 case 6: return 0; 30446 case 5: return 0; 30447 case 4: 30448 if (devinfo->is_g4x) { 30449 return 0; 30450 } else { 30451 return 0; 30452 } 30453 default: 30454 unreachable("Invalid hardware generation"); 30455 } 30456 } 30457 30458 30459 30460 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_Entry_0_start 0 30461 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_Entry_0_start 0 30462 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_Entry_0_start 0 30463 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_Entry_0_start 0 30464 30465 static inline uint32_t ATTRIBUTE_PURE 30466 _3DSTATE_GATHER_CONSTANT_VS_Entry_0_start(const struct gen_device_info *devinfo) 30467 { 30468 switch (devinfo->gen) { 30469 case 10: return 0; 30470 case 9: return 0; 30471 case 8: return 0; 30472 case 7: 30473 if (devinfo->is_haswell) { 30474 return 0; 30475 } else { 30476 return 0; 30477 } 30478 case 6: return 0; 30479 case 5: return 0; 30480 case 4: 30481 if (devinfo->is_g4x) { 30482 return 0; 30483 } else { 30484 return 0; 30485 } 30486 default: 30487 unreachable("Invalid hardware generation"); 30488 } 30489 } 30490 30491 30492 30493 /* 3DSTATE_GATHER_CONSTANT_VS::Entry_1 */ 30494 30495 30496 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_Entry_1_bits 16 30497 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_Entry_1_bits 16 30498 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_Entry_1_bits 16 30499 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_Entry_1_bits 16 30500 30501 static inline uint32_t ATTRIBUTE_PURE 30502 _3DSTATE_GATHER_CONSTANT_VS_Entry_1_bits(const struct gen_device_info *devinfo) 30503 { 30504 switch (devinfo->gen) { 30505 case 10: return 16; 30506 case 9: return 16; 30507 case 8: return 16; 30508 case 7: 30509 if (devinfo->is_haswell) { 30510 return 16; 30511 } else { 30512 return 0; 30513 } 30514 case 6: return 0; 30515 case 5: return 0; 30516 case 4: 30517 if (devinfo->is_g4x) { 30518 return 0; 30519 } else { 30520 return 0; 30521 } 30522 default: 30523 unreachable("Invalid hardware generation"); 30524 } 30525 } 30526 30527 30528 30529 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_Entry_1_start 16 30530 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_Entry_1_start 16 30531 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_Entry_1_start 16 30532 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_Entry_1_start 16 30533 30534 static inline uint32_t ATTRIBUTE_PURE 30535 _3DSTATE_GATHER_CONSTANT_VS_Entry_1_start(const struct gen_device_info *devinfo) 30536 { 30537 switch (devinfo->gen) { 30538 case 10: return 16; 30539 case 9: return 16; 30540 case 8: return 16; 30541 case 7: 30542 if (devinfo->is_haswell) { 30543 return 16; 30544 } else { 30545 return 0; 30546 } 30547 case 6: return 0; 30548 case 5: return 0; 30549 case 4: 30550 if (devinfo->is_g4x) { 30551 return 0; 30552 } else { 30553 return 0; 30554 } 30555 default: 30556 unreachable("Invalid hardware generation"); 30557 } 30558 } 30559 30560 30561 30562 /* 3DSTATE_GATHER_CONSTANT_VS::Gather Buffer Offset */ 30563 30564 30565 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 30566 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 30567 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 30568 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 30569 30570 static inline uint32_t ATTRIBUTE_PURE 30571 _3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits(const struct gen_device_info *devinfo) 30572 { 30573 switch (devinfo->gen) { 30574 case 10: return 17; 30575 case 9: return 17; 30576 case 8: return 17; 30577 case 7: 30578 if (devinfo->is_haswell) { 30579 return 17; 30580 } else { 30581 return 0; 30582 } 30583 case 6: return 0; 30584 case 5: return 0; 30585 case 4: 30586 if (devinfo->is_g4x) { 30587 return 0; 30588 } else { 30589 return 0; 30590 } 30591 default: 30592 unreachable("Invalid hardware generation"); 30593 } 30594 } 30595 30596 30597 30598 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 30599 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 30600 #define GEN8_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 30601 #define GEN75_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 30602 30603 static inline uint32_t ATTRIBUTE_PURE 30604 _3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start(const struct gen_device_info *devinfo) 30605 { 30606 switch (devinfo->gen) { 30607 case 10: return 70; 30608 case 9: return 70; 30609 case 8: return 70; 30610 case 7: 30611 if (devinfo->is_haswell) { 30612 return 70; 30613 } else { 30614 return 0; 30615 } 30616 case 6: return 0; 30617 case 5: return 0; 30618 case 4: 30619 if (devinfo->is_g4x) { 30620 return 0; 30621 } else { 30622 return 0; 30623 } 30624 default: 30625 unreachable("Invalid hardware generation"); 30626 } 30627 } 30628 30629 30630 30631 /* 3DSTATE_GATHER_CONSTANT_VS::On-Die Table */ 30632 30633 30634 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_bits 1 30635 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_bits 1 30636 30637 static inline uint32_t ATTRIBUTE_PURE 30638 _3DSTATE_GATHER_CONSTANT_VS_OnDieTable_bits(const struct gen_device_info *devinfo) 30639 { 30640 switch (devinfo->gen) { 30641 case 10: return 1; 30642 case 9: return 1; 30643 case 8: return 0; 30644 case 7: 30645 if (devinfo->is_haswell) { 30646 return 0; 30647 } else { 30648 return 0; 30649 } 30650 case 6: return 0; 30651 case 5: return 0; 30652 case 4: 30653 if (devinfo->is_g4x) { 30654 return 0; 30655 } else { 30656 return 0; 30657 } 30658 default: 30659 unreachable("Invalid hardware generation"); 30660 } 30661 } 30662 30663 30664 30665 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_start 67 30666 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_start 67 30667 30668 static inline uint32_t ATTRIBUTE_PURE 30669 _3DSTATE_GATHER_CONSTANT_VS_OnDieTable_start(const struct gen_device_info *devinfo) 30670 { 30671 switch (devinfo->gen) { 30672 case 10: return 67; 30673 case 9: return 67; 30674 case 8: return 0; 30675 case 7: 30676 if (devinfo->is_haswell) { 30677 return 0; 30678 } else { 30679 return 0; 30680 } 30681 case 6: return 0; 30682 case 5: return 0; 30683 case 4: 30684 if (devinfo->is_g4x) { 30685 return 0; 30686 } else { 30687 return 0; 30688 } 30689 default: 30690 unreachable("Invalid hardware generation"); 30691 } 30692 } 30693 30694 30695 30696 /* 3DSTATE_GATHER_CONSTANT_VS::Update Gather Table Only */ 30697 30698 30699 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_bits 1 30700 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_bits 1 30701 30702 static inline uint32_t ATTRIBUTE_PURE 30703 _3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_bits(const struct gen_device_info *devinfo) 30704 { 30705 switch (devinfo->gen) { 30706 case 10: return 1; 30707 case 9: return 1; 30708 case 8: return 0; 30709 case 7: 30710 if (devinfo->is_haswell) { 30711 return 0; 30712 } else { 30713 return 0; 30714 } 30715 case 6: return 0; 30716 case 5: return 0; 30717 case 4: 30718 if (devinfo->is_g4x) { 30719 return 0; 30720 } else { 30721 return 0; 30722 } 30723 default: 30724 unreachable("Invalid hardware generation"); 30725 } 30726 } 30727 30728 30729 30730 #define GEN10_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_start 33 30731 #define GEN9_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_start 33 30732 30733 static inline uint32_t ATTRIBUTE_PURE 30734 _3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_start(const struct gen_device_info *devinfo) 30735 { 30736 switch (devinfo->gen) { 30737 case 10: return 33; 30738 case 9: return 33; 30739 case 8: return 0; 30740 case 7: 30741 if (devinfo->is_haswell) { 30742 return 0; 30743 } else { 30744 return 0; 30745 } 30746 case 6: return 0; 30747 case 5: return 0; 30748 case 4: 30749 if (devinfo->is_g4x) { 30750 return 0; 30751 } else { 30752 return 0; 30753 } 30754 default: 30755 unreachable("Invalid hardware generation"); 30756 } 30757 } 30758 30759 30760 30761 /* 3DSTATE_GATHER_POOL_ALLOC */ 30762 30763 30764 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_length 4 30765 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_length 4 30766 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_length 4 30767 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_length 3 30768 30769 static inline uint32_t ATTRIBUTE_PURE 30770 _3DSTATE_GATHER_POOL_ALLOC_length(const struct gen_device_info *devinfo) 30771 { 30772 switch (devinfo->gen) { 30773 case 10: return 4; 30774 case 9: return 4; 30775 case 8: return 4; 30776 case 7: 30777 if (devinfo->is_haswell) { 30778 return 3; 30779 } else { 30780 return 0; 30781 } 30782 case 6: return 0; 30783 case 5: return 0; 30784 case 4: 30785 if (devinfo->is_g4x) { 30786 return 0; 30787 } else { 30788 return 0; 30789 } 30790 default: 30791 unreachable("Invalid hardware generation"); 30792 } 30793 } 30794 30795 30796 30797 /* 3DSTATE_GATHER_POOL_ALLOC::3D Command Opcode */ 30798 30799 30800 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 30801 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 30802 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 30803 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 30804 30805 static inline uint32_t ATTRIBUTE_PURE 30806 _3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 30807 { 30808 switch (devinfo->gen) { 30809 case 10: return 3; 30810 case 9: return 3; 30811 case 8: return 3; 30812 case 7: 30813 if (devinfo->is_haswell) { 30814 return 3; 30815 } else { 30816 return 0; 30817 } 30818 case 6: return 0; 30819 case 5: return 0; 30820 case 4: 30821 if (devinfo->is_g4x) { 30822 return 0; 30823 } else { 30824 return 0; 30825 } 30826 default: 30827 unreachable("Invalid hardware generation"); 30828 } 30829 } 30830 30831 30832 30833 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 30834 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 30835 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 30836 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 30837 30838 static inline uint32_t ATTRIBUTE_PURE 30839 _3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start(const struct gen_device_info *devinfo) 30840 { 30841 switch (devinfo->gen) { 30842 case 10: return 24; 30843 case 9: return 24; 30844 case 8: return 24; 30845 case 7: 30846 if (devinfo->is_haswell) { 30847 return 24; 30848 } else { 30849 return 0; 30850 } 30851 case 6: return 0; 30852 case 5: return 0; 30853 case 4: 30854 if (devinfo->is_g4x) { 30855 return 0; 30856 } else { 30857 return 0; 30858 } 30859 default: 30860 unreachable("Invalid hardware generation"); 30861 } 30862 } 30863 30864 30865 30866 /* 3DSTATE_GATHER_POOL_ALLOC::3D Command Sub Opcode */ 30867 30868 30869 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 30870 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 30871 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 30872 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 30873 30874 static inline uint32_t ATTRIBUTE_PURE 30875 _3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 30876 { 30877 switch (devinfo->gen) { 30878 case 10: return 8; 30879 case 9: return 8; 30880 case 8: return 8; 30881 case 7: 30882 if (devinfo->is_haswell) { 30883 return 8; 30884 } else { 30885 return 0; 30886 } 30887 case 6: return 0; 30888 case 5: return 0; 30889 case 4: 30890 if (devinfo->is_g4x) { 30891 return 0; 30892 } else { 30893 return 0; 30894 } 30895 default: 30896 unreachable("Invalid hardware generation"); 30897 } 30898 } 30899 30900 30901 30902 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 30903 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 30904 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 30905 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 30906 30907 static inline uint32_t ATTRIBUTE_PURE 30908 _3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 30909 { 30910 switch (devinfo->gen) { 30911 case 10: return 16; 30912 case 9: return 16; 30913 case 8: return 16; 30914 case 7: 30915 if (devinfo->is_haswell) { 30916 return 16; 30917 } else { 30918 return 0; 30919 } 30920 case 6: return 0; 30921 case 5: return 0; 30922 case 4: 30923 if (devinfo->is_g4x) { 30924 return 0; 30925 } else { 30926 return 0; 30927 } 30928 default: 30929 unreachable("Invalid hardware generation"); 30930 } 30931 } 30932 30933 30934 30935 /* 3DSTATE_GATHER_POOL_ALLOC::Command SubType */ 30936 30937 30938 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 30939 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 30940 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 30941 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 30942 30943 static inline uint32_t ATTRIBUTE_PURE 30944 _3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits(const struct gen_device_info *devinfo) 30945 { 30946 switch (devinfo->gen) { 30947 case 10: return 2; 30948 case 9: return 2; 30949 case 8: return 2; 30950 case 7: 30951 if (devinfo->is_haswell) { 30952 return 2; 30953 } else { 30954 return 0; 30955 } 30956 case 6: return 0; 30957 case 5: return 0; 30958 case 4: 30959 if (devinfo->is_g4x) { 30960 return 0; 30961 } else { 30962 return 0; 30963 } 30964 default: 30965 unreachable("Invalid hardware generation"); 30966 } 30967 } 30968 30969 30970 30971 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 30972 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 30973 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 30974 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 30975 30976 static inline uint32_t ATTRIBUTE_PURE 30977 _3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start(const struct gen_device_info *devinfo) 30978 { 30979 switch (devinfo->gen) { 30980 case 10: return 27; 30981 case 9: return 27; 30982 case 8: return 27; 30983 case 7: 30984 if (devinfo->is_haswell) { 30985 return 27; 30986 } else { 30987 return 0; 30988 } 30989 case 6: return 0; 30990 case 5: return 0; 30991 case 4: 30992 if (devinfo->is_g4x) { 30993 return 0; 30994 } else { 30995 return 0; 30996 } 30997 default: 30998 unreachable("Invalid hardware generation"); 30999 } 31000 } 31001 31002 31003 31004 /* 3DSTATE_GATHER_POOL_ALLOC::Command Type */ 31005 31006 31007 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 31008 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 31009 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 31010 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 31011 31012 static inline uint32_t ATTRIBUTE_PURE 31013 _3DSTATE_GATHER_POOL_ALLOC_CommandType_bits(const struct gen_device_info *devinfo) 31014 { 31015 switch (devinfo->gen) { 31016 case 10: return 3; 31017 case 9: return 3; 31018 case 8: return 3; 31019 case 7: 31020 if (devinfo->is_haswell) { 31021 return 3; 31022 } else { 31023 return 0; 31024 } 31025 case 6: return 0; 31026 case 5: return 0; 31027 case 4: 31028 if (devinfo->is_g4x) { 31029 return 0; 31030 } else { 31031 return 0; 31032 } 31033 default: 31034 unreachable("Invalid hardware generation"); 31035 } 31036 } 31037 31038 31039 31040 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 31041 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 31042 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 31043 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 31044 31045 static inline uint32_t ATTRIBUTE_PURE 31046 _3DSTATE_GATHER_POOL_ALLOC_CommandType_start(const struct gen_device_info *devinfo) 31047 { 31048 switch (devinfo->gen) { 31049 case 10: return 29; 31050 case 9: return 29; 31051 case 8: return 29; 31052 case 7: 31053 if (devinfo->is_haswell) { 31054 return 29; 31055 } else { 31056 return 0; 31057 } 31058 case 6: return 0; 31059 case 5: return 0; 31060 case 4: 31061 if (devinfo->is_g4x) { 31062 return 0; 31063 } else { 31064 return 0; 31065 } 31066 default: 31067 unreachable("Invalid hardware generation"); 31068 } 31069 } 31070 31071 31072 31073 /* 3DSTATE_GATHER_POOL_ALLOC::DWord Length */ 31074 31075 31076 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 31077 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 31078 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 31079 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 31080 31081 static inline uint32_t ATTRIBUTE_PURE 31082 _3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits(const struct gen_device_info *devinfo) 31083 { 31084 switch (devinfo->gen) { 31085 case 10: return 8; 31086 case 9: return 8; 31087 case 8: return 8; 31088 case 7: 31089 if (devinfo->is_haswell) { 31090 return 8; 31091 } else { 31092 return 0; 31093 } 31094 case 6: return 0; 31095 case 5: return 0; 31096 case 4: 31097 if (devinfo->is_g4x) { 31098 return 0; 31099 } else { 31100 return 0; 31101 } 31102 default: 31103 unreachable("Invalid hardware generation"); 31104 } 31105 } 31106 31107 31108 31109 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 31110 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 31111 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 31112 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 31113 31114 static inline uint32_t ATTRIBUTE_PURE 31115 _3DSTATE_GATHER_POOL_ALLOC_DWordLength_start(const struct gen_device_info *devinfo) 31116 { 31117 switch (devinfo->gen) { 31118 case 10: return 0; 31119 case 9: return 0; 31120 case 8: return 0; 31121 case 7: 31122 if (devinfo->is_haswell) { 31123 return 0; 31124 } else { 31125 return 0; 31126 } 31127 case 6: return 0; 31128 case 5: return 0; 31129 case 4: 31130 if (devinfo->is_g4x) { 31131 return 0; 31132 } else { 31133 return 0; 31134 } 31135 default: 31136 unreachable("Invalid hardware generation"); 31137 } 31138 } 31139 31140 31141 31142 /* 3DSTATE_GATHER_POOL_ALLOC::Gather Pool Base Address */ 31143 31144 31145 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 52 31146 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 52 31147 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 52 31148 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 20 31149 31150 static inline uint32_t ATTRIBUTE_PURE 31151 _3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits(const struct gen_device_info *devinfo) 31152 { 31153 switch (devinfo->gen) { 31154 case 10: return 52; 31155 case 9: return 52; 31156 case 8: return 52; 31157 case 7: 31158 if (devinfo->is_haswell) { 31159 return 20; 31160 } else { 31161 return 0; 31162 } 31163 case 6: return 0; 31164 case 5: return 0; 31165 case 4: 31166 if (devinfo->is_g4x) { 31167 return 0; 31168 } else { 31169 return 0; 31170 } 31171 default: 31172 unreachable("Invalid hardware generation"); 31173 } 31174 } 31175 31176 31177 31178 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 31179 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 31180 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 31181 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 31182 31183 static inline uint32_t ATTRIBUTE_PURE 31184 _3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start(const struct gen_device_info *devinfo) 31185 { 31186 switch (devinfo->gen) { 31187 case 10: return 44; 31188 case 9: return 44; 31189 case 8: return 44; 31190 case 7: 31191 if (devinfo->is_haswell) { 31192 return 44; 31193 } else { 31194 return 0; 31195 } 31196 case 6: return 0; 31197 case 5: return 0; 31198 case 4: 31199 if (devinfo->is_g4x) { 31200 return 0; 31201 } else { 31202 return 0; 31203 } 31204 default: 31205 unreachable("Invalid hardware generation"); 31206 } 31207 } 31208 31209 31210 31211 /* 3DSTATE_GATHER_POOL_ALLOC::Gather Pool Buffer Size */ 31212 31213 31214 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits 20 31215 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits 20 31216 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits 20 31217 31218 static inline uint32_t ATTRIBUTE_PURE 31219 _3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits(const struct gen_device_info *devinfo) 31220 { 31221 switch (devinfo->gen) { 31222 case 10: return 20; 31223 case 9: return 20; 31224 case 8: return 20; 31225 case 7: 31226 if (devinfo->is_haswell) { 31227 return 0; 31228 } else { 31229 return 0; 31230 } 31231 case 6: return 0; 31232 case 5: return 0; 31233 case 4: 31234 if (devinfo->is_g4x) { 31235 return 0; 31236 } else { 31237 return 0; 31238 } 31239 default: 31240 unreachable("Invalid hardware generation"); 31241 } 31242 } 31243 31244 31245 31246 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start 108 31247 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start 108 31248 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start 108 31249 31250 static inline uint32_t ATTRIBUTE_PURE 31251 _3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start(const struct gen_device_info *devinfo) 31252 { 31253 switch (devinfo->gen) { 31254 case 10: return 108; 31255 case 9: return 108; 31256 case 8: return 108; 31257 case 7: 31258 if (devinfo->is_haswell) { 31259 return 0; 31260 } else { 31261 return 0; 31262 } 31263 case 6: return 0; 31264 case 5: return 0; 31265 case 4: 31266 if (devinfo->is_g4x) { 31267 return 0; 31268 } else { 31269 return 0; 31270 } 31271 default: 31272 unreachable("Invalid hardware generation"); 31273 } 31274 } 31275 31276 31277 31278 /* 3DSTATE_GATHER_POOL_ALLOC::Gather Pool Enable */ 31279 31280 31281 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 31282 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 31283 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 31284 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 31285 31286 static inline uint32_t ATTRIBUTE_PURE 31287 _3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits(const struct gen_device_info *devinfo) 31288 { 31289 switch (devinfo->gen) { 31290 case 10: return 1; 31291 case 9: return 1; 31292 case 8: return 1; 31293 case 7: 31294 if (devinfo->is_haswell) { 31295 return 1; 31296 } else { 31297 return 0; 31298 } 31299 case 6: return 0; 31300 case 5: return 0; 31301 case 4: 31302 if (devinfo->is_g4x) { 31303 return 0; 31304 } else { 31305 return 0; 31306 } 31307 default: 31308 unreachable("Invalid hardware generation"); 31309 } 31310 } 31311 31312 31313 31314 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 31315 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 31316 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 31317 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 31318 31319 static inline uint32_t ATTRIBUTE_PURE 31320 _3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start(const struct gen_device_info *devinfo) 31321 { 31322 switch (devinfo->gen) { 31323 case 10: return 43; 31324 case 9: return 43; 31325 case 8: return 43; 31326 case 7: 31327 if (devinfo->is_haswell) { 31328 return 43; 31329 } else { 31330 return 0; 31331 } 31332 case 6: return 0; 31333 case 5: return 0; 31334 case 4: 31335 if (devinfo->is_g4x) { 31336 return 0; 31337 } else { 31338 return 0; 31339 } 31340 default: 31341 unreachable("Invalid hardware generation"); 31342 } 31343 } 31344 31345 31346 31347 /* 3DSTATE_GATHER_POOL_ALLOC::Gather Pool Upper Bound */ 31348 31349 31350 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_bits 20 31351 31352 static inline uint32_t ATTRIBUTE_PURE 31353 _3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_bits(const struct gen_device_info *devinfo) 31354 { 31355 switch (devinfo->gen) { 31356 case 10: return 0; 31357 case 9: return 0; 31358 case 8: return 0; 31359 case 7: 31360 if (devinfo->is_haswell) { 31361 return 20; 31362 } else { 31363 return 0; 31364 } 31365 case 6: return 0; 31366 case 5: return 0; 31367 case 4: 31368 if (devinfo->is_g4x) { 31369 return 0; 31370 } else { 31371 return 0; 31372 } 31373 default: 31374 unreachable("Invalid hardware generation"); 31375 } 31376 } 31377 31378 31379 31380 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_start 76 31381 31382 static inline uint32_t ATTRIBUTE_PURE 31383 _3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_start(const struct gen_device_info *devinfo) 31384 { 31385 switch (devinfo->gen) { 31386 case 10: return 0; 31387 case 9: return 0; 31388 case 8: return 0; 31389 case 7: 31390 if (devinfo->is_haswell) { 31391 return 76; 31392 } else { 31393 return 0; 31394 } 31395 case 6: return 0; 31396 case 5: return 0; 31397 case 4: 31398 if (devinfo->is_g4x) { 31399 return 0; 31400 } else { 31401 return 0; 31402 } 31403 default: 31404 unreachable("Invalid hardware generation"); 31405 } 31406 } 31407 31408 31409 31410 /* 3DSTATE_GATHER_POOL_ALLOC::Memory Object Control State */ 31411 31412 31413 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_bits 7 31414 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_bits 7 31415 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_bits 7 31416 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_bits 4 31417 31418 static inline uint32_t ATTRIBUTE_PURE 31419 _3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_bits(const struct gen_device_info *devinfo) 31420 { 31421 switch (devinfo->gen) { 31422 case 10: return 7; 31423 case 9: return 7; 31424 case 8: return 7; 31425 case 7: 31426 if (devinfo->is_haswell) { 31427 return 4; 31428 } else { 31429 return 0; 31430 } 31431 case 6: return 0; 31432 case 5: return 0; 31433 case 4: 31434 if (devinfo->is_g4x) { 31435 return 0; 31436 } else { 31437 return 0; 31438 } 31439 default: 31440 unreachable("Invalid hardware generation"); 31441 } 31442 } 31443 31444 31445 31446 #define GEN10_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_start 32 31447 #define GEN9_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_start 32 31448 #define GEN8_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_start 32 31449 #define GEN75_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_start 32 31450 31451 static inline uint32_t ATTRIBUTE_PURE 31452 _3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_start(const struct gen_device_info *devinfo) 31453 { 31454 switch (devinfo->gen) { 31455 case 10: return 32; 31456 case 9: return 32; 31457 case 8: return 32; 31458 case 7: 31459 if (devinfo->is_haswell) { 31460 return 32; 31461 } else { 31462 return 0; 31463 } 31464 case 6: return 0; 31465 case 5: return 0; 31466 case 4: 31467 if (devinfo->is_g4x) { 31468 return 0; 31469 } else { 31470 return 0; 31471 } 31472 default: 31473 unreachable("Invalid hardware generation"); 31474 } 31475 } 31476 31477 31478 31479 /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP */ 31480 31481 31482 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_length 2 31483 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_length 2 31484 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_length 2 31485 31486 static inline uint32_t ATTRIBUTE_PURE 31487 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_length(const struct gen_device_info *devinfo) 31488 { 31489 switch (devinfo->gen) { 31490 case 10: return 0; 31491 case 9: return 0; 31492 case 8: return 0; 31493 case 7: 31494 if (devinfo->is_haswell) { 31495 return 0; 31496 } else { 31497 return 0; 31498 } 31499 case 6: return 0; 31500 case 5: return 2; 31501 case 4: 31502 if (devinfo->is_g4x) { 31503 return 2; 31504 } else { 31505 return 2; 31506 } 31507 default: 31508 unreachable("Invalid hardware generation"); 31509 } 31510 } 31511 31512 31513 31514 /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::3D Command Opcode */ 31515 31516 31517 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_bits 3 31518 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_bits 3 31519 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_bits 3 31520 31521 static inline uint32_t ATTRIBUTE_PURE 31522 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 31523 { 31524 switch (devinfo->gen) { 31525 case 10: return 0; 31526 case 9: return 0; 31527 case 8: return 0; 31528 case 7: 31529 if (devinfo->is_haswell) { 31530 return 0; 31531 } else { 31532 return 0; 31533 } 31534 case 6: return 0; 31535 case 5: return 3; 31536 case 4: 31537 if (devinfo->is_g4x) { 31538 return 3; 31539 } else { 31540 return 3; 31541 } 31542 default: 31543 unreachable("Invalid hardware generation"); 31544 } 31545 } 31546 31547 31548 31549 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_start 24 31550 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_start 24 31551 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_start 24 31552 31553 static inline uint32_t ATTRIBUTE_PURE 31554 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_start(const struct gen_device_info *devinfo) 31555 { 31556 switch (devinfo->gen) { 31557 case 10: return 0; 31558 case 9: return 0; 31559 case 8: return 0; 31560 case 7: 31561 if (devinfo->is_haswell) { 31562 return 0; 31563 } else { 31564 return 0; 31565 } 31566 case 6: return 0; 31567 case 5: return 24; 31568 case 4: 31569 if (devinfo->is_g4x) { 31570 return 24; 31571 } else { 31572 return 24; 31573 } 31574 default: 31575 unreachable("Invalid hardware generation"); 31576 } 31577 } 31578 31579 31580 31581 /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::3D Command Sub Opcode */ 31582 31583 31584 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_bits 8 31585 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_bits 8 31586 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_bits 8 31587 31588 static inline uint32_t ATTRIBUTE_PURE 31589 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 31590 { 31591 switch (devinfo->gen) { 31592 case 10: return 0; 31593 case 9: return 0; 31594 case 8: return 0; 31595 case 7: 31596 if (devinfo->is_haswell) { 31597 return 0; 31598 } else { 31599 return 0; 31600 } 31601 case 6: return 0; 31602 case 5: return 8; 31603 case 4: 31604 if (devinfo->is_g4x) { 31605 return 8; 31606 } else { 31607 return 8; 31608 } 31609 default: 31610 unreachable("Invalid hardware generation"); 31611 } 31612 } 31613 31614 31615 31616 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_start 16 31617 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_start 16 31618 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_start 16 31619 31620 static inline uint32_t ATTRIBUTE_PURE 31621 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 31622 { 31623 switch (devinfo->gen) { 31624 case 10: return 0; 31625 case 9: return 0; 31626 case 8: return 0; 31627 case 7: 31628 if (devinfo->is_haswell) { 31629 return 0; 31630 } else { 31631 return 0; 31632 } 31633 case 6: return 0; 31634 case 5: return 16; 31635 case 4: 31636 if (devinfo->is_g4x) { 31637 return 16; 31638 } else { 31639 return 16; 31640 } 31641 default: 31642 unreachable("Invalid hardware generation"); 31643 } 31644 } 31645 31646 31647 31648 /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::Command SubType */ 31649 31650 31651 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_bits 2 31652 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_bits 2 31653 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_bits 2 31654 31655 static inline uint32_t ATTRIBUTE_PURE 31656 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_bits(const struct gen_device_info *devinfo) 31657 { 31658 switch (devinfo->gen) { 31659 case 10: return 0; 31660 case 9: return 0; 31661 case 8: return 0; 31662 case 7: 31663 if (devinfo->is_haswell) { 31664 return 0; 31665 } else { 31666 return 0; 31667 } 31668 case 6: return 0; 31669 case 5: return 2; 31670 case 4: 31671 if (devinfo->is_g4x) { 31672 return 2; 31673 } else { 31674 return 2; 31675 } 31676 default: 31677 unreachable("Invalid hardware generation"); 31678 } 31679 } 31680 31681 31682 31683 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_start 27 31684 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_start 27 31685 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_start 27 31686 31687 static inline uint32_t ATTRIBUTE_PURE 31688 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_start(const struct gen_device_info *devinfo) 31689 { 31690 switch (devinfo->gen) { 31691 case 10: return 0; 31692 case 9: return 0; 31693 case 8: return 0; 31694 case 7: 31695 if (devinfo->is_haswell) { 31696 return 0; 31697 } else { 31698 return 0; 31699 } 31700 case 6: return 0; 31701 case 5: return 27; 31702 case 4: 31703 if (devinfo->is_g4x) { 31704 return 27; 31705 } else { 31706 return 27; 31707 } 31708 default: 31709 unreachable("Invalid hardware generation"); 31710 } 31711 } 31712 31713 31714 31715 /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::Command Type */ 31716 31717 31718 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_bits 3 31719 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_bits 3 31720 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_bits 3 31721 31722 static inline uint32_t ATTRIBUTE_PURE 31723 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_bits(const struct gen_device_info *devinfo) 31724 { 31725 switch (devinfo->gen) { 31726 case 10: return 0; 31727 case 9: return 0; 31728 case 8: return 0; 31729 case 7: 31730 if (devinfo->is_haswell) { 31731 return 0; 31732 } else { 31733 return 0; 31734 } 31735 case 6: return 0; 31736 case 5: return 3; 31737 case 4: 31738 if (devinfo->is_g4x) { 31739 return 3; 31740 } else { 31741 return 3; 31742 } 31743 default: 31744 unreachable("Invalid hardware generation"); 31745 } 31746 } 31747 31748 31749 31750 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_start 29 31751 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_start 29 31752 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_start 29 31753 31754 static inline uint32_t ATTRIBUTE_PURE 31755 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_start(const struct gen_device_info *devinfo) 31756 { 31757 switch (devinfo->gen) { 31758 case 10: return 0; 31759 case 9: return 0; 31760 case 8: return 0; 31761 case 7: 31762 if (devinfo->is_haswell) { 31763 return 0; 31764 } else { 31765 return 0; 31766 } 31767 case 6: return 0; 31768 case 5: return 29; 31769 case 4: 31770 if (devinfo->is_g4x) { 31771 return 29; 31772 } else { 31773 return 29; 31774 } 31775 default: 31776 unreachable("Invalid hardware generation"); 31777 } 31778 } 31779 31780 31781 31782 /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::DWord Length */ 31783 31784 31785 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_bits 8 31786 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_bits 8 31787 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_bits 8 31788 31789 static inline uint32_t ATTRIBUTE_PURE 31790 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_bits(const struct gen_device_info *devinfo) 31791 { 31792 switch (devinfo->gen) { 31793 case 10: return 0; 31794 case 9: return 0; 31795 case 8: return 0; 31796 case 7: 31797 if (devinfo->is_haswell) { 31798 return 0; 31799 } else { 31800 return 0; 31801 } 31802 case 6: return 0; 31803 case 5: return 8; 31804 case 4: 31805 if (devinfo->is_g4x) { 31806 return 8; 31807 } else { 31808 return 8; 31809 } 31810 default: 31811 unreachable("Invalid hardware generation"); 31812 } 31813 } 31814 31815 31816 31817 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_start 0 31818 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_start 0 31819 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_start 0 31820 31821 static inline uint32_t ATTRIBUTE_PURE 31822 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_start(const struct gen_device_info *devinfo) 31823 { 31824 switch (devinfo->gen) { 31825 case 10: return 0; 31826 case 9: return 0; 31827 case 8: return 0; 31828 case 7: 31829 if (devinfo->is_haswell) { 31830 return 0; 31831 } else { 31832 return 0; 31833 } 31834 case 6: return 0; 31835 case 5: return 0; 31836 case 4: 31837 if (devinfo->is_g4x) { 31838 return 0; 31839 } else { 31840 return 0; 31841 } 31842 default: 31843 unreachable("Invalid hardware generation"); 31844 } 31845 } 31846 31847 31848 31849 /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::Global Depth Offset Clamp */ 31850 31851 31852 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_bits 32 31853 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_bits 32 31854 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_bits 32 31855 31856 static inline uint32_t ATTRIBUTE_PURE 31857 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_bits(const struct gen_device_info *devinfo) 31858 { 31859 switch (devinfo->gen) { 31860 case 10: return 0; 31861 case 9: return 0; 31862 case 8: return 0; 31863 case 7: 31864 if (devinfo->is_haswell) { 31865 return 0; 31866 } else { 31867 return 0; 31868 } 31869 case 6: return 0; 31870 case 5: return 32; 31871 case 4: 31872 if (devinfo->is_g4x) { 31873 return 32; 31874 } else { 31875 return 32; 31876 } 31877 default: 31878 unreachable("Invalid hardware generation"); 31879 } 31880 } 31881 31882 31883 31884 #define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_start 32 31885 #define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_start 32 31886 #define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_start 32 31887 31888 static inline uint32_t ATTRIBUTE_PURE 31889 _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_start(const struct gen_device_info *devinfo) 31890 { 31891 switch (devinfo->gen) { 31892 case 10: return 0; 31893 case 9: return 0; 31894 case 8: return 0; 31895 case 7: 31896 if (devinfo->is_haswell) { 31897 return 0; 31898 } else { 31899 return 0; 31900 } 31901 case 6: return 0; 31902 case 5: return 32; 31903 case 4: 31904 if (devinfo->is_g4x) { 31905 return 32; 31906 } else { 31907 return 32; 31908 } 31909 default: 31910 unreachable("Invalid hardware generation"); 31911 } 31912 } 31913 31914 31915 31916 /* 3DSTATE_GS */ 31917 31918 31919 #define GEN10_3DSTATE_GS_length 10 31920 #define GEN9_3DSTATE_GS_length 10 31921 #define GEN8_3DSTATE_GS_length 10 31922 #define GEN75_3DSTATE_GS_length 7 31923 #define GEN7_3DSTATE_GS_length 7 31924 #define GEN6_3DSTATE_GS_length 7 31925 31926 static inline uint32_t ATTRIBUTE_PURE 31927 _3DSTATE_GS_length(const struct gen_device_info *devinfo) 31928 { 31929 switch (devinfo->gen) { 31930 case 10: return 10; 31931 case 9: return 10; 31932 case 8: return 10; 31933 case 7: 31934 if (devinfo->is_haswell) { 31935 return 7; 31936 } else { 31937 return 7; 31938 } 31939 case 6: return 7; 31940 case 5: return 0; 31941 case 4: 31942 if (devinfo->is_g4x) { 31943 return 0; 31944 } else { 31945 return 0; 31946 } 31947 default: 31948 unreachable("Invalid hardware generation"); 31949 } 31950 } 31951 31952 31953 31954 /* 3DSTATE_GS::3D Command Opcode */ 31955 31956 31957 #define GEN10_3DSTATE_GS_3DCommandOpcode_bits 3 31958 #define GEN9_3DSTATE_GS_3DCommandOpcode_bits 3 31959 #define GEN8_3DSTATE_GS_3DCommandOpcode_bits 3 31960 #define GEN75_3DSTATE_GS_3DCommandOpcode_bits 3 31961 #define GEN7_3DSTATE_GS_3DCommandOpcode_bits 3 31962 #define GEN6_3DSTATE_GS_3DCommandOpcode_bits 3 31963 31964 static inline uint32_t ATTRIBUTE_PURE 31965 _3DSTATE_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 31966 { 31967 switch (devinfo->gen) { 31968 case 10: return 3; 31969 case 9: return 3; 31970 case 8: return 3; 31971 case 7: 31972 if (devinfo->is_haswell) { 31973 return 3; 31974 } else { 31975 return 3; 31976 } 31977 case 6: return 3; 31978 case 5: return 0; 31979 case 4: 31980 if (devinfo->is_g4x) { 31981 return 0; 31982 } else { 31983 return 0; 31984 } 31985 default: 31986 unreachable("Invalid hardware generation"); 31987 } 31988 } 31989 31990 31991 31992 #define GEN10_3DSTATE_GS_3DCommandOpcode_start 24 31993 #define GEN9_3DSTATE_GS_3DCommandOpcode_start 24 31994 #define GEN8_3DSTATE_GS_3DCommandOpcode_start 24 31995 #define GEN75_3DSTATE_GS_3DCommandOpcode_start 24 31996 #define GEN7_3DSTATE_GS_3DCommandOpcode_start 24 31997 #define GEN6_3DSTATE_GS_3DCommandOpcode_start 24 31998 31999 static inline uint32_t ATTRIBUTE_PURE 32000 _3DSTATE_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 32001 { 32002 switch (devinfo->gen) { 32003 case 10: return 24; 32004 case 9: return 24; 32005 case 8: return 24; 32006 case 7: 32007 if (devinfo->is_haswell) { 32008 return 24; 32009 } else { 32010 return 24; 32011 } 32012 case 6: return 24; 32013 case 5: return 0; 32014 case 4: 32015 if (devinfo->is_g4x) { 32016 return 0; 32017 } else { 32018 return 0; 32019 } 32020 default: 32021 unreachable("Invalid hardware generation"); 32022 } 32023 } 32024 32025 32026 32027 /* 3DSTATE_GS::3D Command Sub Opcode */ 32028 32029 32030 #define GEN10_3DSTATE_GS_3DCommandSubOpcode_bits 8 32031 #define GEN9_3DSTATE_GS_3DCommandSubOpcode_bits 8 32032 #define GEN8_3DSTATE_GS_3DCommandSubOpcode_bits 8 32033 #define GEN75_3DSTATE_GS_3DCommandSubOpcode_bits 8 32034 #define GEN7_3DSTATE_GS_3DCommandSubOpcode_bits 8 32035 #define GEN6_3DSTATE_GS_3DCommandSubOpcode_bits 8 32036 32037 static inline uint32_t ATTRIBUTE_PURE 32038 _3DSTATE_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 32039 { 32040 switch (devinfo->gen) { 32041 case 10: return 8; 32042 case 9: return 8; 32043 case 8: return 8; 32044 case 7: 32045 if (devinfo->is_haswell) { 32046 return 8; 32047 } else { 32048 return 8; 32049 } 32050 case 6: return 8; 32051 case 5: return 0; 32052 case 4: 32053 if (devinfo->is_g4x) { 32054 return 0; 32055 } else { 32056 return 0; 32057 } 32058 default: 32059 unreachable("Invalid hardware generation"); 32060 } 32061 } 32062 32063 32064 32065 #define GEN10_3DSTATE_GS_3DCommandSubOpcode_start 16 32066 #define GEN9_3DSTATE_GS_3DCommandSubOpcode_start 16 32067 #define GEN8_3DSTATE_GS_3DCommandSubOpcode_start 16 32068 #define GEN75_3DSTATE_GS_3DCommandSubOpcode_start 16 32069 #define GEN7_3DSTATE_GS_3DCommandSubOpcode_start 16 32070 #define GEN6_3DSTATE_GS_3DCommandSubOpcode_start 16 32071 32072 static inline uint32_t ATTRIBUTE_PURE 32073 _3DSTATE_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 32074 { 32075 switch (devinfo->gen) { 32076 case 10: return 16; 32077 case 9: return 16; 32078 case 8: return 16; 32079 case 7: 32080 if (devinfo->is_haswell) { 32081 return 16; 32082 } else { 32083 return 16; 32084 } 32085 case 6: return 16; 32086 case 5: return 0; 32087 case 4: 32088 if (devinfo->is_g4x) { 32089 return 0; 32090 } else { 32091 return 0; 32092 } 32093 default: 32094 unreachable("Invalid hardware generation"); 32095 } 32096 } 32097 32098 32099 32100 /* 3DSTATE_GS::Accesses UAV */ 32101 32102 32103 #define GEN10_3DSTATE_GS_AccessesUAV_bits 1 32104 #define GEN9_3DSTATE_GS_AccessesUAV_bits 1 32105 #define GEN8_3DSTATE_GS_AccessesUAV_bits 1 32106 32107 static inline uint32_t ATTRIBUTE_PURE 32108 _3DSTATE_GS_AccessesUAV_bits(const struct gen_device_info *devinfo) 32109 { 32110 switch (devinfo->gen) { 32111 case 10: return 1; 32112 case 9: return 1; 32113 case 8: return 1; 32114 case 7: 32115 if (devinfo->is_haswell) { 32116 return 0; 32117 } else { 32118 return 0; 32119 } 32120 case 6: return 0; 32121 case 5: return 0; 32122 case 4: 32123 if (devinfo->is_g4x) { 32124 return 0; 32125 } else { 32126 return 0; 32127 } 32128 default: 32129 unreachable("Invalid hardware generation"); 32130 } 32131 } 32132 32133 32134 32135 #define GEN10_3DSTATE_GS_AccessesUAV_start 108 32136 #define GEN9_3DSTATE_GS_AccessesUAV_start 108 32137 #define GEN8_3DSTATE_GS_AccessesUAV_start 108 32138 32139 static inline uint32_t ATTRIBUTE_PURE 32140 _3DSTATE_GS_AccessesUAV_start(const struct gen_device_info *devinfo) 32141 { 32142 switch (devinfo->gen) { 32143 case 10: return 108; 32144 case 9: return 108; 32145 case 8: return 108; 32146 case 7: 32147 if (devinfo->is_haswell) { 32148 return 0; 32149 } else { 32150 return 0; 32151 } 32152 case 6: return 0; 32153 case 5: return 0; 32154 case 4: 32155 if (devinfo->is_g4x) { 32156 return 0; 32157 } else { 32158 return 0; 32159 } 32160 default: 32161 unreachable("Invalid hardware generation"); 32162 } 32163 } 32164 32165 32166 32167 /* 3DSTATE_GS::Binding Table Entry Count */ 32168 32169 32170 #define GEN10_3DSTATE_GS_BindingTableEntryCount_bits 8 32171 #define GEN9_3DSTATE_GS_BindingTableEntryCount_bits 8 32172 #define GEN8_3DSTATE_GS_BindingTableEntryCount_bits 8 32173 #define GEN75_3DSTATE_GS_BindingTableEntryCount_bits 8 32174 #define GEN7_3DSTATE_GS_BindingTableEntryCount_bits 8 32175 #define GEN6_3DSTATE_GS_BindingTableEntryCount_bits 8 32176 32177 static inline uint32_t ATTRIBUTE_PURE 32178 _3DSTATE_GS_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) 32179 { 32180 switch (devinfo->gen) { 32181 case 10: return 8; 32182 case 9: return 8; 32183 case 8: return 8; 32184 case 7: 32185 if (devinfo->is_haswell) { 32186 return 8; 32187 } else { 32188 return 8; 32189 } 32190 case 6: return 8; 32191 case 5: return 0; 32192 case 4: 32193 if (devinfo->is_g4x) { 32194 return 0; 32195 } else { 32196 return 0; 32197 } 32198 default: 32199 unreachable("Invalid hardware generation"); 32200 } 32201 } 32202 32203 32204 32205 #define GEN10_3DSTATE_GS_BindingTableEntryCount_start 114 32206 #define GEN9_3DSTATE_GS_BindingTableEntryCount_start 114 32207 #define GEN8_3DSTATE_GS_BindingTableEntryCount_start 114 32208 #define GEN75_3DSTATE_GS_BindingTableEntryCount_start 82 32209 #define GEN7_3DSTATE_GS_BindingTableEntryCount_start 82 32210 #define GEN6_3DSTATE_GS_BindingTableEntryCount_start 82 32211 32212 static inline uint32_t ATTRIBUTE_PURE 32213 _3DSTATE_GS_BindingTableEntryCount_start(const struct gen_device_info *devinfo) 32214 { 32215 switch (devinfo->gen) { 32216 case 10: return 114; 32217 case 9: return 114; 32218 case 8: return 114; 32219 case 7: 32220 if (devinfo->is_haswell) { 32221 return 82; 32222 } else { 32223 return 82; 32224 } 32225 case 6: return 82; 32226 case 5: return 0; 32227 case 4: 32228 if (devinfo->is_g4x) { 32229 return 0; 32230 } else { 32231 return 0; 32232 } 32233 default: 32234 unreachable("Invalid hardware generation"); 32235 } 32236 } 32237 32238 32239 32240 /* 3DSTATE_GS::Command SubType */ 32241 32242 32243 #define GEN10_3DSTATE_GS_CommandSubType_bits 2 32244 #define GEN9_3DSTATE_GS_CommandSubType_bits 2 32245 #define GEN8_3DSTATE_GS_CommandSubType_bits 2 32246 #define GEN75_3DSTATE_GS_CommandSubType_bits 2 32247 #define GEN7_3DSTATE_GS_CommandSubType_bits 2 32248 #define GEN6_3DSTATE_GS_CommandSubType_bits 2 32249 32250 static inline uint32_t ATTRIBUTE_PURE 32251 _3DSTATE_GS_CommandSubType_bits(const struct gen_device_info *devinfo) 32252 { 32253 switch (devinfo->gen) { 32254 case 10: return 2; 32255 case 9: return 2; 32256 case 8: return 2; 32257 case 7: 32258 if (devinfo->is_haswell) { 32259 return 2; 32260 } else { 32261 return 2; 32262 } 32263 case 6: return 2; 32264 case 5: return 0; 32265 case 4: 32266 if (devinfo->is_g4x) { 32267 return 0; 32268 } else { 32269 return 0; 32270 } 32271 default: 32272 unreachable("Invalid hardware generation"); 32273 } 32274 } 32275 32276 32277 32278 #define GEN10_3DSTATE_GS_CommandSubType_start 27 32279 #define GEN9_3DSTATE_GS_CommandSubType_start 27 32280 #define GEN8_3DSTATE_GS_CommandSubType_start 27 32281 #define GEN75_3DSTATE_GS_CommandSubType_start 27 32282 #define GEN7_3DSTATE_GS_CommandSubType_start 27 32283 #define GEN6_3DSTATE_GS_CommandSubType_start 27 32284 32285 static inline uint32_t ATTRIBUTE_PURE 32286 _3DSTATE_GS_CommandSubType_start(const struct gen_device_info *devinfo) 32287 { 32288 switch (devinfo->gen) { 32289 case 10: return 27; 32290 case 9: return 27; 32291 case 8: return 27; 32292 case 7: 32293 if (devinfo->is_haswell) { 32294 return 27; 32295 } else { 32296 return 27; 32297 } 32298 case 6: return 27; 32299 case 5: return 0; 32300 case 4: 32301 if (devinfo->is_g4x) { 32302 return 0; 32303 } else { 32304 return 0; 32305 } 32306 default: 32307 unreachable("Invalid hardware generation"); 32308 } 32309 } 32310 32311 32312 32313 /* 3DSTATE_GS::Command Type */ 32314 32315 32316 #define GEN10_3DSTATE_GS_CommandType_bits 3 32317 #define GEN9_3DSTATE_GS_CommandType_bits 3 32318 #define GEN8_3DSTATE_GS_CommandType_bits 3 32319 #define GEN75_3DSTATE_GS_CommandType_bits 3 32320 #define GEN7_3DSTATE_GS_CommandType_bits 3 32321 #define GEN6_3DSTATE_GS_CommandType_bits 3 32322 32323 static inline uint32_t ATTRIBUTE_PURE 32324 _3DSTATE_GS_CommandType_bits(const struct gen_device_info *devinfo) 32325 { 32326 switch (devinfo->gen) { 32327 case 10: return 3; 32328 case 9: return 3; 32329 case 8: return 3; 32330 case 7: 32331 if (devinfo->is_haswell) { 32332 return 3; 32333 } else { 32334 return 3; 32335 } 32336 case 6: return 3; 32337 case 5: return 0; 32338 case 4: 32339 if (devinfo->is_g4x) { 32340 return 0; 32341 } else { 32342 return 0; 32343 } 32344 default: 32345 unreachable("Invalid hardware generation"); 32346 } 32347 } 32348 32349 32350 32351 #define GEN10_3DSTATE_GS_CommandType_start 29 32352 #define GEN9_3DSTATE_GS_CommandType_start 29 32353 #define GEN8_3DSTATE_GS_CommandType_start 29 32354 #define GEN75_3DSTATE_GS_CommandType_start 29 32355 #define GEN7_3DSTATE_GS_CommandType_start 29 32356 #define GEN6_3DSTATE_GS_CommandType_start 29 32357 32358 static inline uint32_t ATTRIBUTE_PURE 32359 _3DSTATE_GS_CommandType_start(const struct gen_device_info *devinfo) 32360 { 32361 switch (devinfo->gen) { 32362 case 10: return 29; 32363 case 9: return 29; 32364 case 8: return 29; 32365 case 7: 32366 if (devinfo->is_haswell) { 32367 return 29; 32368 } else { 32369 return 29; 32370 } 32371 case 6: return 29; 32372 case 5: return 0; 32373 case 4: 32374 if (devinfo->is_g4x) { 32375 return 0; 32376 } else { 32377 return 0; 32378 } 32379 default: 32380 unreachable("Invalid hardware generation"); 32381 } 32382 } 32383 32384 32385 32386 /* 3DSTATE_GS::Control Data Format */ 32387 32388 32389 #define GEN10_3DSTATE_GS_ControlDataFormat_bits 1 32390 #define GEN9_3DSTATE_GS_ControlDataFormat_bits 1 32391 #define GEN8_3DSTATE_GS_ControlDataFormat_bits 1 32392 #define GEN75_3DSTATE_GS_ControlDataFormat_bits 1 32393 #define GEN7_3DSTATE_GS_ControlDataFormat_bits 1 32394 32395 static inline uint32_t ATTRIBUTE_PURE 32396 _3DSTATE_GS_ControlDataFormat_bits(const struct gen_device_info *devinfo) 32397 { 32398 switch (devinfo->gen) { 32399 case 10: return 1; 32400 case 9: return 1; 32401 case 8: return 1; 32402 case 7: 32403 if (devinfo->is_haswell) { 32404 return 1; 32405 } else { 32406 return 1; 32407 } 32408 case 6: return 0; 32409 case 5: return 0; 32410 case 4: 32411 if (devinfo->is_g4x) { 32412 return 0; 32413 } else { 32414 return 0; 32415 } 32416 default: 32417 unreachable("Invalid hardware generation"); 32418 } 32419 } 32420 32421 32422 32423 #define GEN10_3DSTATE_GS_ControlDataFormat_start 287 32424 #define GEN9_3DSTATE_GS_ControlDataFormat_start 287 32425 #define GEN8_3DSTATE_GS_ControlDataFormat_start 287 32426 #define GEN75_3DSTATE_GS_ControlDataFormat_start 223 32427 #define GEN7_3DSTATE_GS_ControlDataFormat_start 184 32428 32429 static inline uint32_t ATTRIBUTE_PURE 32430 _3DSTATE_GS_ControlDataFormat_start(const struct gen_device_info *devinfo) 32431 { 32432 switch (devinfo->gen) { 32433 case 10: return 287; 32434 case 9: return 287; 32435 case 8: return 287; 32436 case 7: 32437 if (devinfo->is_haswell) { 32438 return 223; 32439 } else { 32440 return 184; 32441 } 32442 case 6: return 0; 32443 case 5: return 0; 32444 case 4: 32445 if (devinfo->is_g4x) { 32446 return 0; 32447 } else { 32448 return 0; 32449 } 32450 default: 32451 unreachable("Invalid hardware generation"); 32452 } 32453 } 32454 32455 32456 32457 /* 3DSTATE_GS::Control Data Header Size */ 32458 32459 32460 #define GEN10_3DSTATE_GS_ControlDataHeaderSize_bits 4 32461 #define GEN9_3DSTATE_GS_ControlDataHeaderSize_bits 4 32462 #define GEN8_3DSTATE_GS_ControlDataHeaderSize_bits 4 32463 #define GEN75_3DSTATE_GS_ControlDataHeaderSize_bits 4 32464 #define GEN7_3DSTATE_GS_ControlDataHeaderSize_bits 4 32465 32466 static inline uint32_t ATTRIBUTE_PURE 32467 _3DSTATE_GS_ControlDataHeaderSize_bits(const struct gen_device_info *devinfo) 32468 { 32469 switch (devinfo->gen) { 32470 case 10: return 4; 32471 case 9: return 4; 32472 case 8: return 4; 32473 case 7: 32474 if (devinfo->is_haswell) { 32475 return 4; 32476 } else { 32477 return 4; 32478 } 32479 case 6: return 0; 32480 case 5: return 0; 32481 case 4: 32482 if (devinfo->is_g4x) { 32483 return 0; 32484 } else { 32485 return 0; 32486 } 32487 default: 32488 unreachable("Invalid hardware generation"); 32489 } 32490 } 32491 32492 32493 32494 #define GEN10_3DSTATE_GS_ControlDataHeaderSize_start 244 32495 #define GEN9_3DSTATE_GS_ControlDataHeaderSize_start 244 32496 #define GEN8_3DSTATE_GS_ControlDataHeaderSize_start 244 32497 #define GEN75_3DSTATE_GS_ControlDataHeaderSize_start 180 32498 #define GEN7_3DSTATE_GS_ControlDataHeaderSize_start 180 32499 32500 static inline uint32_t ATTRIBUTE_PURE 32501 _3DSTATE_GS_ControlDataHeaderSize_start(const struct gen_device_info *devinfo) 32502 { 32503 switch (devinfo->gen) { 32504 case 10: return 244; 32505 case 9: return 244; 32506 case 8: return 244; 32507 case 7: 32508 if (devinfo->is_haswell) { 32509 return 180; 32510 } else { 32511 return 180; 32512 } 32513 case 6: return 0; 32514 case 5: return 0; 32515 case 4: 32516 if (devinfo->is_g4x) { 32517 return 0; 32518 } else { 32519 return 0; 32520 } 32521 default: 32522 unreachable("Invalid hardware generation"); 32523 } 32524 } 32525 32526 32527 32528 /* 3DSTATE_GS::DWord Length */ 32529 32530 32531 #define GEN10_3DSTATE_GS_DWordLength_bits 8 32532 #define GEN9_3DSTATE_GS_DWordLength_bits 8 32533 #define GEN8_3DSTATE_GS_DWordLength_bits 8 32534 #define GEN75_3DSTATE_GS_DWordLength_bits 8 32535 #define GEN7_3DSTATE_GS_DWordLength_bits 8 32536 #define GEN6_3DSTATE_GS_DWordLength_bits 8 32537 32538 static inline uint32_t ATTRIBUTE_PURE 32539 _3DSTATE_GS_DWordLength_bits(const struct gen_device_info *devinfo) 32540 { 32541 switch (devinfo->gen) { 32542 case 10: return 8; 32543 case 9: return 8; 32544 case 8: return 8; 32545 case 7: 32546 if (devinfo->is_haswell) { 32547 return 8; 32548 } else { 32549 return 8; 32550 } 32551 case 6: return 8; 32552 case 5: return 0; 32553 case 4: 32554 if (devinfo->is_g4x) { 32555 return 0; 32556 } else { 32557 return 0; 32558 } 32559 default: 32560 unreachable("Invalid hardware generation"); 32561 } 32562 } 32563 32564 32565 32566 #define GEN10_3DSTATE_GS_DWordLength_start 0 32567 #define GEN9_3DSTATE_GS_DWordLength_start 0 32568 #define GEN8_3DSTATE_GS_DWordLength_start 0 32569 #define GEN75_3DSTATE_GS_DWordLength_start 0 32570 #define GEN7_3DSTATE_GS_DWordLength_start 0 32571 #define GEN6_3DSTATE_GS_DWordLength_start 0 32572 32573 static inline uint32_t ATTRIBUTE_PURE 32574 _3DSTATE_GS_DWordLength_start(const struct gen_device_info *devinfo) 32575 { 32576 switch (devinfo->gen) { 32577 case 10: return 0; 32578 case 9: return 0; 32579 case 8: return 0; 32580 case 7: 32581 if (devinfo->is_haswell) { 32582 return 0; 32583 } else { 32584 return 0; 32585 } 32586 case 6: return 0; 32587 case 5: return 0; 32588 case 4: 32589 if (devinfo->is_g4x) { 32590 return 0; 32591 } else { 32592 return 0; 32593 } 32594 default: 32595 unreachable("Invalid hardware generation"); 32596 } 32597 } 32598 32599 32600 32601 /* 3DSTATE_GS::Default Stream Id */ 32602 32603 32604 #define GEN10_3DSTATE_GS_DefaultStreamId_bits 2 32605 #define GEN9_3DSTATE_GS_DefaultStreamId_bits 2 32606 #define GEN8_3DSTATE_GS_DefaultStreamId_bits 2 32607 32608 static inline uint32_t ATTRIBUTE_PURE 32609 _3DSTATE_GS_DefaultStreamId_bits(const struct gen_device_info *devinfo) 32610 { 32611 switch (devinfo->gen) { 32612 case 10: return 2; 32613 case 9: return 2; 32614 case 8: return 2; 32615 case 7: 32616 if (devinfo->is_haswell) { 32617 return 0; 32618 } else { 32619 return 0; 32620 } 32621 case 6: return 0; 32622 case 5: return 0; 32623 case 4: 32624 if (devinfo->is_g4x) { 32625 return 0; 32626 } else { 32627 return 0; 32628 } 32629 default: 32630 unreachable("Invalid hardware generation"); 32631 } 32632 } 32633 32634 32635 32636 #define GEN10_3DSTATE_GS_DefaultStreamId_start 237 32637 #define GEN9_3DSTATE_GS_DefaultStreamId_start 237 32638 #define GEN8_3DSTATE_GS_DefaultStreamId_start 237 32639 32640 static inline uint32_t ATTRIBUTE_PURE 32641 _3DSTATE_GS_DefaultStreamId_start(const struct gen_device_info *devinfo) 32642 { 32643 switch (devinfo->gen) { 32644 case 10: return 237; 32645 case 9: return 237; 32646 case 8: return 237; 32647 case 7: 32648 if (devinfo->is_haswell) { 32649 return 0; 32650 } else { 32651 return 0; 32652 } 32653 case 6: return 0; 32654 case 5: return 0; 32655 case 4: 32656 if (devinfo->is_g4x) { 32657 return 0; 32658 } else { 32659 return 0; 32660 } 32661 default: 32662 unreachable("Invalid hardware generation"); 32663 } 32664 } 32665 32666 32667 32668 /* 3DSTATE_GS::Default StreamID */ 32669 32670 32671 #define GEN75_3DSTATE_GS_DefaultStreamID_bits 2 32672 #define GEN7_3DSTATE_GS_DefaultStreamID_bits 2 32673 32674 static inline uint32_t ATTRIBUTE_PURE 32675 _3DSTATE_GS_DefaultStreamID_bits(const struct gen_device_info *devinfo) 32676 { 32677 switch (devinfo->gen) { 32678 case 10: return 0; 32679 case 9: return 0; 32680 case 8: return 0; 32681 case 7: 32682 if (devinfo->is_haswell) { 32683 return 2; 32684 } else { 32685 return 2; 32686 } 32687 case 6: return 0; 32688 case 5: return 0; 32689 case 4: 32690 if (devinfo->is_g4x) { 32691 return 0; 32692 } else { 32693 return 0; 32694 } 32695 default: 32696 unreachable("Invalid hardware generation"); 32697 } 32698 } 32699 32700 32701 32702 #define GEN75_3DSTATE_GS_DefaultStreamID_start 173 32703 #define GEN7_3DSTATE_GS_DefaultStreamID_start 173 32704 32705 static inline uint32_t ATTRIBUTE_PURE 32706 _3DSTATE_GS_DefaultStreamID_start(const struct gen_device_info *devinfo) 32707 { 32708 switch (devinfo->gen) { 32709 case 10: return 0; 32710 case 9: return 0; 32711 case 8: return 0; 32712 case 7: 32713 if (devinfo->is_haswell) { 32714 return 173; 32715 } else { 32716 return 173; 32717 } 32718 case 6: return 0; 32719 case 5: return 0; 32720 case 4: 32721 if (devinfo->is_g4x) { 32722 return 0; 32723 } else { 32724 return 0; 32725 } 32726 default: 32727 unreachable("Invalid hardware generation"); 32728 } 32729 } 32730 32731 32732 32733 /* 3DSTATE_GS::Discard Adjacency */ 32734 32735 32736 #define GEN10_3DSTATE_GS_DiscardAdjacency_bits 1 32737 #define GEN9_3DSTATE_GS_DiscardAdjacency_bits 1 32738 #define GEN8_3DSTATE_GS_DiscardAdjacency_bits 1 32739 #define GEN75_3DSTATE_GS_DiscardAdjacency_bits 1 32740 #define GEN7_3DSTATE_GS_DiscardAdjacency_bits 1 32741 #define GEN6_3DSTATE_GS_DiscardAdjacency_bits 1 32742 32743 static inline uint32_t ATTRIBUTE_PURE 32744 _3DSTATE_GS_DiscardAdjacency_bits(const struct gen_device_info *devinfo) 32745 { 32746 switch (devinfo->gen) { 32747 case 10: return 1; 32748 case 9: return 1; 32749 case 8: return 1; 32750 case 7: 32751 if (devinfo->is_haswell) { 32752 return 1; 32753 } else { 32754 return 1; 32755 } 32756 case 6: return 1; 32757 case 5: return 0; 32758 case 4: 32759 if (devinfo->is_g4x) { 32760 return 0; 32761 } else { 32762 return 0; 32763 } 32764 default: 32765 unreachable("Invalid hardware generation"); 32766 } 32767 } 32768 32769 32770 32771 #define GEN10_3DSTATE_GS_DiscardAdjacency_start 225 32772 #define GEN9_3DSTATE_GS_DiscardAdjacency_start 225 32773 #define GEN8_3DSTATE_GS_DiscardAdjacency_start 225 32774 #define GEN75_3DSTATE_GS_DiscardAdjacency_start 161 32775 #define GEN7_3DSTATE_GS_DiscardAdjacency_start 161 32776 #define GEN6_3DSTATE_GS_DiscardAdjacency_start 221 32777 32778 static inline uint32_t ATTRIBUTE_PURE 32779 _3DSTATE_GS_DiscardAdjacency_start(const struct gen_device_info *devinfo) 32780 { 32781 switch (devinfo->gen) { 32782 case 10: return 225; 32783 case 9: return 225; 32784 case 8: return 225; 32785 case 7: 32786 if (devinfo->is_haswell) { 32787 return 161; 32788 } else { 32789 return 161; 32790 } 32791 case 6: return 221; 32792 case 5: return 0; 32793 case 4: 32794 if (devinfo->is_g4x) { 32795 return 0; 32796 } else { 32797 return 0; 32798 } 32799 default: 32800 unreachable("Invalid hardware generation"); 32801 } 32802 } 32803 32804 32805 32806 /* 3DSTATE_GS::Dispatch GRF Start Register For URB Data */ 32807 32808 32809 #define GEN10_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 32810 #define GEN9_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 32811 #define GEN8_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 32812 #define GEN75_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 32813 #define GEN7_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 32814 #define GEN6_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 32815 32816 static inline uint32_t ATTRIBUTE_PURE 32817 _3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits(const struct gen_device_info *devinfo) 32818 { 32819 switch (devinfo->gen) { 32820 case 10: return 4; 32821 case 9: return 4; 32822 case 8: return 4; 32823 case 7: 32824 if (devinfo->is_haswell) { 32825 return 4; 32826 } else { 32827 return 4; 32828 } 32829 case 6: return 4; 32830 case 5: return 0; 32831 case 4: 32832 if (devinfo->is_g4x) { 32833 return 0; 32834 } else { 32835 return 0; 32836 } 32837 default: 32838 unreachable("Invalid hardware generation"); 32839 } 32840 } 32841 32842 32843 32844 #define GEN10_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 192 32845 #define GEN9_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 192 32846 #define GEN8_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 192 32847 #define GEN75_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 128 32848 #define GEN7_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 128 32849 #define GEN6_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 128 32850 32851 static inline uint32_t ATTRIBUTE_PURE 32852 _3DSTATE_GS_DispatchGRFStartRegisterForURBData_start(const struct gen_device_info *devinfo) 32853 { 32854 switch (devinfo->gen) { 32855 case 10: return 192; 32856 case 9: return 192; 32857 case 8: return 192; 32858 case 7: 32859 if (devinfo->is_haswell) { 32860 return 128; 32861 } else { 32862 return 128; 32863 } 32864 case 6: return 128; 32865 case 5: return 0; 32866 case 4: 32867 if (devinfo->is_g4x) { 32868 return 0; 32869 } else { 32870 return 0; 32871 } 32872 default: 32873 unreachable("Invalid hardware generation"); 32874 } 32875 } 32876 32877 32878 32879 /* 3DSTATE_GS::Dispatch GRF Start Register For URB Data [5:4] */ 32880 32881 32882 #define GEN10_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_bits 2 32883 #define GEN9_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_bits 2 32884 32885 static inline uint32_t ATTRIBUTE_PURE 32886 _3DSTATE_GS_DispatchGRFStartRegisterForURBData54_bits(const struct gen_device_info *devinfo) 32887 { 32888 switch (devinfo->gen) { 32889 case 10: return 2; 32890 case 9: return 2; 32891 case 8: return 0; 32892 case 7: 32893 if (devinfo->is_haswell) { 32894 return 0; 32895 } else { 32896 return 0; 32897 } 32898 case 6: return 0; 32899 case 5: return 0; 32900 case 4: 32901 if (devinfo->is_g4x) { 32902 return 0; 32903 } else { 32904 return 0; 32905 } 32906 default: 32907 unreachable("Invalid hardware generation"); 32908 } 32909 } 32910 32911 32912 32913 #define GEN10_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_start 221 32914 #define GEN9_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_start 221 32915 32916 static inline uint32_t ATTRIBUTE_PURE 32917 _3DSTATE_GS_DispatchGRFStartRegisterForURBData54_start(const struct gen_device_info *devinfo) 32918 { 32919 switch (devinfo->gen) { 32920 case 10: return 221; 32921 case 9: return 221; 32922 case 8: return 0; 32923 case 7: 32924 if (devinfo->is_haswell) { 32925 return 0; 32926 } else { 32927 return 0; 32928 } 32929 case 6: return 0; 32930 case 5: return 0; 32931 case 4: 32932 if (devinfo->is_g4x) { 32933 return 0; 32934 } else { 32935 return 0; 32936 } 32937 default: 32938 unreachable("Invalid hardware generation"); 32939 } 32940 } 32941 32942 32943 32944 /* 3DSTATE_GS::Dispatch Mode */ 32945 32946 32947 #define GEN10_3DSTATE_GS_DispatchMode_bits 2 32948 #define GEN9_3DSTATE_GS_DispatchMode_bits 2 32949 #define GEN8_3DSTATE_GS_DispatchMode_bits 2 32950 #define GEN75_3DSTATE_GS_DispatchMode_bits 2 32951 #define GEN7_3DSTATE_GS_DispatchMode_bits 2 32952 32953 static inline uint32_t ATTRIBUTE_PURE 32954 _3DSTATE_GS_DispatchMode_bits(const struct gen_device_info *devinfo) 32955 { 32956 switch (devinfo->gen) { 32957 case 10: return 2; 32958 case 9: return 2; 32959 case 8: return 2; 32960 case 7: 32961 if (devinfo->is_haswell) { 32962 return 2; 32963 } else { 32964 return 2; 32965 } 32966 case 6: return 0; 32967 case 5: return 0; 32968 case 4: 32969 if (devinfo->is_g4x) { 32970 return 0; 32971 } else { 32972 return 0; 32973 } 32974 default: 32975 unreachable("Invalid hardware generation"); 32976 } 32977 } 32978 32979 32980 32981 #define GEN10_3DSTATE_GS_DispatchMode_start 235 32982 #define GEN9_3DSTATE_GS_DispatchMode_start 235 32983 #define GEN8_3DSTATE_GS_DispatchMode_start 235 32984 #define GEN75_3DSTATE_GS_DispatchMode_start 171 32985 #define GEN7_3DSTATE_GS_DispatchMode_start 171 32986 32987 static inline uint32_t ATTRIBUTE_PURE 32988 _3DSTATE_GS_DispatchMode_start(const struct gen_device_info *devinfo) 32989 { 32990 switch (devinfo->gen) { 32991 case 10: return 235; 32992 case 9: return 235; 32993 case 8: return 235; 32994 case 7: 32995 if (devinfo->is_haswell) { 32996 return 171; 32997 } else { 32998 return 171; 32999 } 33000 case 6: return 0; 33001 case 5: return 0; 33002 case 4: 33003 if (devinfo->is_g4x) { 33004 return 0; 33005 } else { 33006 return 0; 33007 } 33008 default: 33009 unreachable("Invalid hardware generation"); 33010 } 33011 } 33012 33013 33014 33015 /* 3DSTATE_GS::Enable */ 33016 33017 33018 #define GEN10_3DSTATE_GS_Enable_bits 1 33019 #define GEN9_3DSTATE_GS_Enable_bits 1 33020 #define GEN8_3DSTATE_GS_Enable_bits 1 33021 #define GEN75_3DSTATE_GS_Enable_bits 1 33022 #define GEN7_3DSTATE_GS_Enable_bits 1 33023 #define GEN6_3DSTATE_GS_Enable_bits 1 33024 33025 static inline uint32_t ATTRIBUTE_PURE 33026 _3DSTATE_GS_Enable_bits(const struct gen_device_info *devinfo) 33027 { 33028 switch (devinfo->gen) { 33029 case 10: return 1; 33030 case 9: return 1; 33031 case 8: return 1; 33032 case 7: 33033 if (devinfo->is_haswell) { 33034 return 1; 33035 } else { 33036 return 1; 33037 } 33038 case 6: return 1; 33039 case 5: return 0; 33040 case 4: 33041 if (devinfo->is_g4x) { 33042 return 0; 33043 } else { 33044 return 0; 33045 } 33046 default: 33047 unreachable("Invalid hardware generation"); 33048 } 33049 } 33050 33051 33052 33053 #define GEN10_3DSTATE_GS_Enable_start 224 33054 #define GEN9_3DSTATE_GS_Enable_start 224 33055 #define GEN8_3DSTATE_GS_Enable_start 224 33056 #define GEN75_3DSTATE_GS_Enable_start 160 33057 #define GEN7_3DSTATE_GS_Enable_start 160 33058 #define GEN6_3DSTATE_GS_Enable_start 207 33059 33060 static inline uint32_t ATTRIBUTE_PURE 33061 _3DSTATE_GS_Enable_start(const struct gen_device_info *devinfo) 33062 { 33063 switch (devinfo->gen) { 33064 case 10: return 224; 33065 case 9: return 224; 33066 case 8: return 224; 33067 case 7: 33068 if (devinfo->is_haswell) { 33069 return 160; 33070 } else { 33071 return 160; 33072 } 33073 case 6: return 207; 33074 case 5: return 0; 33075 case 4: 33076 if (devinfo->is_g4x) { 33077 return 0; 33078 } else { 33079 return 0; 33080 } 33081 default: 33082 unreachable("Invalid hardware generation"); 33083 } 33084 } 33085 33086 33087 33088 /* 3DSTATE_GS::Expected Vertex Count */ 33089 33090 33091 #define GEN10_3DSTATE_GS_ExpectedVertexCount_bits 6 33092 #define GEN9_3DSTATE_GS_ExpectedVertexCount_bits 6 33093 #define GEN8_3DSTATE_GS_ExpectedVertexCount_bits 6 33094 33095 static inline uint32_t ATTRIBUTE_PURE 33096 _3DSTATE_GS_ExpectedVertexCount_bits(const struct gen_device_info *devinfo) 33097 { 33098 switch (devinfo->gen) { 33099 case 10: return 6; 33100 case 9: return 6; 33101 case 8: return 6; 33102 case 7: 33103 if (devinfo->is_haswell) { 33104 return 0; 33105 } else { 33106 return 0; 33107 } 33108 case 6: return 0; 33109 case 5: return 0; 33110 case 4: 33111 if (devinfo->is_g4x) { 33112 return 0; 33113 } else { 33114 return 0; 33115 } 33116 default: 33117 unreachable("Invalid hardware generation"); 33118 } 33119 } 33120 33121 33122 33123 #define GEN10_3DSTATE_GS_ExpectedVertexCount_start 96 33124 #define GEN9_3DSTATE_GS_ExpectedVertexCount_start 96 33125 #define GEN8_3DSTATE_GS_ExpectedVertexCount_start 96 33126 33127 static inline uint32_t ATTRIBUTE_PURE 33128 _3DSTATE_GS_ExpectedVertexCount_start(const struct gen_device_info *devinfo) 33129 { 33130 switch (devinfo->gen) { 33131 case 10: return 96; 33132 case 9: return 96; 33133 case 8: return 96; 33134 case 7: 33135 if (devinfo->is_haswell) { 33136 return 0; 33137 } else { 33138 return 0; 33139 } 33140 case 6: return 0; 33141 case 5: return 0; 33142 case 4: 33143 if (devinfo->is_g4x) { 33144 return 0; 33145 } else { 33146 return 0; 33147 } 33148 default: 33149 unreachable("Invalid hardware generation"); 33150 } 33151 } 33152 33153 33154 33155 /* 3DSTATE_GS::Floating Point Mode */ 33156 33157 33158 #define GEN10_3DSTATE_GS_FloatingPointMode_bits 1 33159 #define GEN9_3DSTATE_GS_FloatingPointMode_bits 1 33160 #define GEN8_3DSTATE_GS_FloatingPointMode_bits 1 33161 #define GEN75_3DSTATE_GS_FloatingPointMode_bits 1 33162 #define GEN7_3DSTATE_GS_FloatingPointMode_bits 1 33163 #define GEN6_3DSTATE_GS_FloatingPointMode_bits 1 33164 33165 static inline uint32_t ATTRIBUTE_PURE 33166 _3DSTATE_GS_FloatingPointMode_bits(const struct gen_device_info *devinfo) 33167 { 33168 switch (devinfo->gen) { 33169 case 10: return 1; 33170 case 9: return 1; 33171 case 8: return 1; 33172 case 7: 33173 if (devinfo->is_haswell) { 33174 return 1; 33175 } else { 33176 return 1; 33177 } 33178 case 6: return 1; 33179 case 5: return 0; 33180 case 4: 33181 if (devinfo->is_g4x) { 33182 return 0; 33183 } else { 33184 return 0; 33185 } 33186 default: 33187 unreachable("Invalid hardware generation"); 33188 } 33189 } 33190 33191 33192 33193 #define GEN10_3DSTATE_GS_FloatingPointMode_start 112 33194 #define GEN9_3DSTATE_GS_FloatingPointMode_start 112 33195 #define GEN8_3DSTATE_GS_FloatingPointMode_start 112 33196 #define GEN75_3DSTATE_GS_FloatingPointMode_start 80 33197 #define GEN7_3DSTATE_GS_FloatingPointMode_start 80 33198 #define GEN6_3DSTATE_GS_FloatingPointMode_start 80 33199 33200 static inline uint32_t ATTRIBUTE_PURE 33201 _3DSTATE_GS_FloatingPointMode_start(const struct gen_device_info *devinfo) 33202 { 33203 switch (devinfo->gen) { 33204 case 10: return 112; 33205 case 9: return 112; 33206 case 8: return 112; 33207 case 7: 33208 if (devinfo->is_haswell) { 33209 return 80; 33210 } else { 33211 return 80; 33212 } 33213 case 6: return 80; 33214 case 5: return 0; 33215 case 4: 33216 if (devinfo->is_g4x) { 33217 return 0; 33218 } else { 33219 return 0; 33220 } 33221 default: 33222 unreachable("Invalid hardware generation"); 33223 } 33224 } 33225 33226 33227 33228 /* 3DSTATE_GS::GS Invocations Increment Value */ 33229 33230 33231 #define GEN75_3DSTATE_GS_GSInvocationsIncrementValue_bits 5 33232 #define GEN7_3DSTATE_GS_GSInvocationsIncrementValue_bits 5 33233 33234 static inline uint32_t ATTRIBUTE_PURE 33235 _3DSTATE_GS_GSInvocationsIncrementValue_bits(const struct gen_device_info *devinfo) 33236 { 33237 switch (devinfo->gen) { 33238 case 10: return 0; 33239 case 9: return 0; 33240 case 8: return 0; 33241 case 7: 33242 if (devinfo->is_haswell) { 33243 return 5; 33244 } else { 33245 return 5; 33246 } 33247 case 6: return 0; 33248 case 5: return 0; 33249 case 4: 33250 if (devinfo->is_g4x) { 33251 return 0; 33252 } else { 33253 return 0; 33254 } 33255 default: 33256 unreachable("Invalid hardware generation"); 33257 } 33258 } 33259 33260 33261 33262 #define GEN75_3DSTATE_GS_GSInvocationsIncrementValue_start 165 33263 #define GEN7_3DSTATE_GS_GSInvocationsIncrementValue_start 165 33264 33265 static inline uint32_t ATTRIBUTE_PURE 33266 _3DSTATE_GS_GSInvocationsIncrementValue_start(const struct gen_device_info *devinfo) 33267 { 33268 switch (devinfo->gen) { 33269 case 10: return 0; 33270 case 9: return 0; 33271 case 8: return 0; 33272 case 7: 33273 if (devinfo->is_haswell) { 33274 return 165; 33275 } else { 33276 return 165; 33277 } 33278 case 6: return 0; 33279 case 5: return 0; 33280 case 4: 33281 if (devinfo->is_g4x) { 33282 return 0; 33283 } else { 33284 return 0; 33285 } 33286 default: 33287 unreachable("Invalid hardware generation"); 33288 } 33289 } 33290 33291 33292 33293 /* 3DSTATE_GS::GS accesses UAV */ 33294 33295 33296 #define GEN75_3DSTATE_GS_GSaccessesUAV_bits 1 33297 33298 static inline uint32_t ATTRIBUTE_PURE 33299 _3DSTATE_GS_GSaccessesUAV_bits(const struct gen_device_info *devinfo) 33300 { 33301 switch (devinfo->gen) { 33302 case 10: return 0; 33303 case 9: return 0; 33304 case 8: return 0; 33305 case 7: 33306 if (devinfo->is_haswell) { 33307 return 1; 33308 } else { 33309 return 0; 33310 } 33311 case 6: return 0; 33312 case 5: return 0; 33313 case 4: 33314 if (devinfo->is_g4x) { 33315 return 0; 33316 } else { 33317 return 0; 33318 } 33319 default: 33320 unreachable("Invalid hardware generation"); 33321 } 33322 } 33323 33324 33325 33326 #define GEN75_3DSTATE_GS_GSaccessesUAV_start 76 33327 33328 static inline uint32_t ATTRIBUTE_PURE 33329 _3DSTATE_GS_GSaccessesUAV_start(const struct gen_device_info *devinfo) 33330 { 33331 switch (devinfo->gen) { 33332 case 10: return 0; 33333 case 9: return 0; 33334 case 8: return 0; 33335 case 7: 33336 if (devinfo->is_haswell) { 33337 return 76; 33338 } else { 33339 return 0; 33340 } 33341 case 6: return 0; 33342 case 5: return 0; 33343 case 4: 33344 if (devinfo->is_g4x) { 33345 return 0; 33346 } else { 33347 return 0; 33348 } 33349 default: 33350 unreachable("Invalid hardware generation"); 33351 } 33352 } 33353 33354 33355 33356 /* 3DSTATE_GS::Hint */ 33357 33358 33359 #define GEN10_3DSTATE_GS_Hint_bits 1 33360 #define GEN9_3DSTATE_GS_Hint_bits 1 33361 #define GEN8_3DSTATE_GS_Hint_bits 1 33362 #define GEN75_3DSTATE_GS_Hint_bits 1 33363 #define GEN7_3DSTATE_GS_Hint_bits 1 33364 33365 static inline uint32_t ATTRIBUTE_PURE 33366 _3DSTATE_GS_Hint_bits(const struct gen_device_info *devinfo) 33367 { 33368 switch (devinfo->gen) { 33369 case 10: return 1; 33370 case 9: return 1; 33371 case 8: return 1; 33372 case 7: 33373 if (devinfo->is_haswell) { 33374 return 1; 33375 } else { 33376 return 1; 33377 } 33378 case 6: return 0; 33379 case 5: return 0; 33380 case 4: 33381 if (devinfo->is_g4x) { 33382 return 0; 33383 } else { 33384 return 0; 33385 } 33386 default: 33387 unreachable("Invalid hardware generation"); 33388 } 33389 } 33390 33391 33392 33393 #define GEN10_3DSTATE_GS_Hint_start 227 33394 #define GEN9_3DSTATE_GS_Hint_start 227 33395 #define GEN8_3DSTATE_GS_Hint_start 227 33396 #define GEN75_3DSTATE_GS_Hint_start 163 33397 #define GEN7_3DSTATE_GS_Hint_start 163 33398 33399 static inline uint32_t ATTRIBUTE_PURE 33400 _3DSTATE_GS_Hint_start(const struct gen_device_info *devinfo) 33401 { 33402 switch (devinfo->gen) { 33403 case 10: return 227; 33404 case 9: return 227; 33405 case 8: return 227; 33406 case 7: 33407 if (devinfo->is_haswell) { 33408 return 163; 33409 } else { 33410 return 163; 33411 } 33412 case 6: return 0; 33413 case 5: return 0; 33414 case 4: 33415 if (devinfo->is_g4x) { 33416 return 0; 33417 } else { 33418 return 0; 33419 } 33420 default: 33421 unreachable("Invalid hardware generation"); 33422 } 33423 } 33424 33425 33426 33427 /* 3DSTATE_GS::Illegal Opcode Exception Enable */ 33428 33429 33430 #define GEN10_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 33431 #define GEN9_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 33432 #define GEN8_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 33433 #define GEN75_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 33434 #define GEN7_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 33435 #define GEN6_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 33436 33437 static inline uint32_t ATTRIBUTE_PURE 33438 _3DSTATE_GS_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) 33439 { 33440 switch (devinfo->gen) { 33441 case 10: return 1; 33442 case 9: return 1; 33443 case 8: return 1; 33444 case 7: 33445 if (devinfo->is_haswell) { 33446 return 1; 33447 } else { 33448 return 1; 33449 } 33450 case 6: return 1; 33451 case 5: return 0; 33452 case 4: 33453 if (devinfo->is_g4x) { 33454 return 0; 33455 } else { 33456 return 0; 33457 } 33458 default: 33459 unreachable("Invalid hardware generation"); 33460 } 33461 } 33462 33463 33464 33465 #define GEN10_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 109 33466 #define GEN9_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 109 33467 #define GEN8_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 109 33468 #define GEN75_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 77 33469 #define GEN7_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 77 33470 #define GEN6_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 77 33471 33472 static inline uint32_t ATTRIBUTE_PURE 33473 _3DSTATE_GS_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) 33474 { 33475 switch (devinfo->gen) { 33476 case 10: return 109; 33477 case 9: return 109; 33478 case 8: return 109; 33479 case 7: 33480 if (devinfo->is_haswell) { 33481 return 77; 33482 } else { 33483 return 77; 33484 } 33485 case 6: return 77; 33486 case 5: return 0; 33487 case 4: 33488 if (devinfo->is_g4x) { 33489 return 0; 33490 } else { 33491 return 0; 33492 } 33493 default: 33494 unreachable("Invalid hardware generation"); 33495 } 33496 } 33497 33498 33499 33500 /* 3DSTATE_GS::Include Primitive ID */ 33501 33502 33503 #define GEN10_3DSTATE_GS_IncludePrimitiveID_bits 1 33504 #define GEN9_3DSTATE_GS_IncludePrimitiveID_bits 1 33505 #define GEN8_3DSTATE_GS_IncludePrimitiveID_bits 1 33506 #define GEN75_3DSTATE_GS_IncludePrimitiveID_bits 1 33507 #define GEN7_3DSTATE_GS_IncludePrimitiveID_bits 1 33508 33509 static inline uint32_t ATTRIBUTE_PURE 33510 _3DSTATE_GS_IncludePrimitiveID_bits(const struct gen_device_info *devinfo) 33511 { 33512 switch (devinfo->gen) { 33513 case 10: return 1; 33514 case 9: return 1; 33515 case 8: return 1; 33516 case 7: 33517 if (devinfo->is_haswell) { 33518 return 1; 33519 } else { 33520 return 1; 33521 } 33522 case 6: return 0; 33523 case 5: return 0; 33524 case 4: 33525 if (devinfo->is_g4x) { 33526 return 0; 33527 } else { 33528 return 0; 33529 } 33530 default: 33531 unreachable("Invalid hardware generation"); 33532 } 33533 } 33534 33535 33536 33537 #define GEN10_3DSTATE_GS_IncludePrimitiveID_start 228 33538 #define GEN9_3DSTATE_GS_IncludePrimitiveID_start 228 33539 #define GEN8_3DSTATE_GS_IncludePrimitiveID_start 228 33540 #define GEN75_3DSTATE_GS_IncludePrimitiveID_start 164 33541 #define GEN7_3DSTATE_GS_IncludePrimitiveID_start 164 33542 33543 static inline uint32_t ATTRIBUTE_PURE 33544 _3DSTATE_GS_IncludePrimitiveID_start(const struct gen_device_info *devinfo) 33545 { 33546 switch (devinfo->gen) { 33547 case 10: return 228; 33548 case 9: return 228; 33549 case 8: return 228; 33550 case 7: 33551 if (devinfo->is_haswell) { 33552 return 164; 33553 } else { 33554 return 164; 33555 } 33556 case 6: return 0; 33557 case 5: return 0; 33558 case 4: 33559 if (devinfo->is_g4x) { 33560 return 0; 33561 } else { 33562 return 0; 33563 } 33564 default: 33565 unreachable("Invalid hardware generation"); 33566 } 33567 } 33568 33569 33570 33571 /* 3DSTATE_GS::Include Vertex Handles */ 33572 33573 33574 #define GEN10_3DSTATE_GS_IncludeVertexHandles_bits 1 33575 #define GEN9_3DSTATE_GS_IncludeVertexHandles_bits 1 33576 #define GEN8_3DSTATE_GS_IncludeVertexHandles_bits 1 33577 #define GEN75_3DSTATE_GS_IncludeVertexHandles_bits 1 33578 #define GEN7_3DSTATE_GS_IncludeVertexHandles_bits 1 33579 33580 static inline uint32_t ATTRIBUTE_PURE 33581 _3DSTATE_GS_IncludeVertexHandles_bits(const struct gen_device_info *devinfo) 33582 { 33583 switch (devinfo->gen) { 33584 case 10: return 1; 33585 case 9: return 1; 33586 case 8: return 1; 33587 case 7: 33588 if (devinfo->is_haswell) { 33589 return 1; 33590 } else { 33591 return 1; 33592 } 33593 case 6: return 0; 33594 case 5: return 0; 33595 case 4: 33596 if (devinfo->is_g4x) { 33597 return 0; 33598 } else { 33599 return 0; 33600 } 33601 default: 33602 unreachable("Invalid hardware generation"); 33603 } 33604 } 33605 33606 33607 33608 #define GEN10_3DSTATE_GS_IncludeVertexHandles_start 202 33609 #define GEN9_3DSTATE_GS_IncludeVertexHandles_start 202 33610 #define GEN8_3DSTATE_GS_IncludeVertexHandles_start 202 33611 #define GEN75_3DSTATE_GS_IncludeVertexHandles_start 138 33612 #define GEN7_3DSTATE_GS_IncludeVertexHandles_start 138 33613 33614 static inline uint32_t ATTRIBUTE_PURE 33615 _3DSTATE_GS_IncludeVertexHandles_start(const struct gen_device_info *devinfo) 33616 { 33617 switch (devinfo->gen) { 33618 case 10: return 202; 33619 case 9: return 202; 33620 case 8: return 202; 33621 case 7: 33622 if (devinfo->is_haswell) { 33623 return 138; 33624 } else { 33625 return 138; 33626 } 33627 case 6: return 0; 33628 case 5: return 0; 33629 case 4: 33630 if (devinfo->is_g4x) { 33631 return 0; 33632 } else { 33633 return 0; 33634 } 33635 default: 33636 unreachable("Invalid hardware generation"); 33637 } 33638 } 33639 33640 33641 33642 /* 3DSTATE_GS::Instance Control */ 33643 33644 33645 #define GEN10_3DSTATE_GS_InstanceControl_bits 5 33646 #define GEN9_3DSTATE_GS_InstanceControl_bits 5 33647 #define GEN8_3DSTATE_GS_InstanceControl_bits 5 33648 #define GEN75_3DSTATE_GS_InstanceControl_bits 5 33649 #define GEN7_3DSTATE_GS_InstanceControl_bits 5 33650 33651 static inline uint32_t ATTRIBUTE_PURE 33652 _3DSTATE_GS_InstanceControl_bits(const struct gen_device_info *devinfo) 33653 { 33654 switch (devinfo->gen) { 33655 case 10: return 5; 33656 case 9: return 5; 33657 case 8: return 5; 33658 case 7: 33659 if (devinfo->is_haswell) { 33660 return 5; 33661 } else { 33662 return 5; 33663 } 33664 case 6: return 0; 33665 case 5: return 0; 33666 case 4: 33667 if (devinfo->is_g4x) { 33668 return 0; 33669 } else { 33670 return 0; 33671 } 33672 default: 33673 unreachable("Invalid hardware generation"); 33674 } 33675 } 33676 33677 33678 33679 #define GEN10_3DSTATE_GS_InstanceControl_start 239 33680 #define GEN9_3DSTATE_GS_InstanceControl_start 239 33681 #define GEN8_3DSTATE_GS_InstanceControl_start 239 33682 #define GEN75_3DSTATE_GS_InstanceControl_start 175 33683 #define GEN7_3DSTATE_GS_InstanceControl_start 175 33684 33685 static inline uint32_t ATTRIBUTE_PURE 33686 _3DSTATE_GS_InstanceControl_start(const struct gen_device_info *devinfo) 33687 { 33688 switch (devinfo->gen) { 33689 case 10: return 239; 33690 case 9: return 239; 33691 case 8: return 239; 33692 case 7: 33693 if (devinfo->is_haswell) { 33694 return 175; 33695 } else { 33696 return 175; 33697 } 33698 case 6: return 0; 33699 case 5: return 0; 33700 case 4: 33701 if (devinfo->is_g4x) { 33702 return 0; 33703 } else { 33704 return 0; 33705 } 33706 default: 33707 unreachable("Invalid hardware generation"); 33708 } 33709 } 33710 33711 33712 33713 /* 3DSTATE_GS::Invocations Increment Value */ 33714 33715 33716 #define GEN10_3DSTATE_GS_InvocationsIncrementValue_bits 5 33717 #define GEN9_3DSTATE_GS_InvocationsIncrementValue_bits 5 33718 #define GEN8_3DSTATE_GS_InvocationsIncrementValue_bits 5 33719 33720 static inline uint32_t ATTRIBUTE_PURE 33721 _3DSTATE_GS_InvocationsIncrementValue_bits(const struct gen_device_info *devinfo) 33722 { 33723 switch (devinfo->gen) { 33724 case 10: return 5; 33725 case 9: return 5; 33726 case 8: return 5; 33727 case 7: 33728 if (devinfo->is_haswell) { 33729 return 0; 33730 } else { 33731 return 0; 33732 } 33733 case 6: return 0; 33734 case 5: return 0; 33735 case 4: 33736 if (devinfo->is_g4x) { 33737 return 0; 33738 } else { 33739 return 0; 33740 } 33741 default: 33742 unreachable("Invalid hardware generation"); 33743 } 33744 } 33745 33746 33747 33748 #define GEN10_3DSTATE_GS_InvocationsIncrementValue_start 229 33749 #define GEN9_3DSTATE_GS_InvocationsIncrementValue_start 229 33750 #define GEN8_3DSTATE_GS_InvocationsIncrementValue_start 229 33751 33752 static inline uint32_t ATTRIBUTE_PURE 33753 _3DSTATE_GS_InvocationsIncrementValue_start(const struct gen_device_info *devinfo) 33754 { 33755 switch (devinfo->gen) { 33756 case 10: return 229; 33757 case 9: return 229; 33758 case 8: return 229; 33759 case 7: 33760 if (devinfo->is_haswell) { 33761 return 0; 33762 } else { 33763 return 0; 33764 } 33765 case 6: return 0; 33766 case 5: return 0; 33767 case 4: 33768 if (devinfo->is_g4x) { 33769 return 0; 33770 } else { 33771 return 0; 33772 } 33773 default: 33774 unreachable("Invalid hardware generation"); 33775 } 33776 } 33777 33778 33779 33780 /* 3DSTATE_GS::Kernel Start Pointer */ 33781 33782 33783 #define GEN10_3DSTATE_GS_KernelStartPointer_bits 58 33784 #define GEN9_3DSTATE_GS_KernelStartPointer_bits 58 33785 #define GEN8_3DSTATE_GS_KernelStartPointer_bits 58 33786 #define GEN75_3DSTATE_GS_KernelStartPointer_bits 26 33787 #define GEN7_3DSTATE_GS_KernelStartPointer_bits 26 33788 #define GEN6_3DSTATE_GS_KernelStartPointer_bits 26 33789 33790 static inline uint32_t ATTRIBUTE_PURE 33791 _3DSTATE_GS_KernelStartPointer_bits(const struct gen_device_info *devinfo) 33792 { 33793 switch (devinfo->gen) { 33794 case 10: return 58; 33795 case 9: return 58; 33796 case 8: return 58; 33797 case 7: 33798 if (devinfo->is_haswell) { 33799 return 26; 33800 } else { 33801 return 26; 33802 } 33803 case 6: return 26; 33804 case 5: return 0; 33805 case 4: 33806 if (devinfo->is_g4x) { 33807 return 0; 33808 } else { 33809 return 0; 33810 } 33811 default: 33812 unreachable("Invalid hardware generation"); 33813 } 33814 } 33815 33816 33817 33818 #define GEN10_3DSTATE_GS_KernelStartPointer_start 38 33819 #define GEN9_3DSTATE_GS_KernelStartPointer_start 38 33820 #define GEN8_3DSTATE_GS_KernelStartPointer_start 38 33821 #define GEN75_3DSTATE_GS_KernelStartPointer_start 38 33822 #define GEN7_3DSTATE_GS_KernelStartPointer_start 38 33823 #define GEN6_3DSTATE_GS_KernelStartPointer_start 38 33824 33825 static inline uint32_t ATTRIBUTE_PURE 33826 _3DSTATE_GS_KernelStartPointer_start(const struct gen_device_info *devinfo) 33827 { 33828 switch (devinfo->gen) { 33829 case 10: return 38; 33830 case 9: return 38; 33831 case 8: return 38; 33832 case 7: 33833 if (devinfo->is_haswell) { 33834 return 38; 33835 } else { 33836 return 38; 33837 } 33838 case 6: return 38; 33839 case 5: return 0; 33840 case 4: 33841 if (devinfo->is_g4x) { 33842 return 0; 33843 } else { 33844 return 0; 33845 } 33846 default: 33847 unreachable("Invalid hardware generation"); 33848 } 33849 } 33850 33851 33852 33853 /* 3DSTATE_GS::Mask Stack Exception Enable */ 33854 33855 33856 #define GEN10_3DSTATE_GS_MaskStackExceptionEnable_bits 1 33857 #define GEN9_3DSTATE_GS_MaskStackExceptionEnable_bits 1 33858 #define GEN8_3DSTATE_GS_MaskStackExceptionEnable_bits 1 33859 #define GEN75_3DSTATE_GS_MaskStackExceptionEnable_bits 1 33860 #define GEN7_3DSTATE_GS_MaskStackExceptionEnable_bits 1 33861 #define GEN6_3DSTATE_GS_MaskStackExceptionEnable_bits 1 33862 33863 static inline uint32_t ATTRIBUTE_PURE 33864 _3DSTATE_GS_MaskStackExceptionEnable_bits(const struct gen_device_info *devinfo) 33865 { 33866 switch (devinfo->gen) { 33867 case 10: return 1; 33868 case 9: return 1; 33869 case 8: return 1; 33870 case 7: 33871 if (devinfo->is_haswell) { 33872 return 1; 33873 } else { 33874 return 1; 33875 } 33876 case 6: return 1; 33877 case 5: return 0; 33878 case 4: 33879 if (devinfo->is_g4x) { 33880 return 0; 33881 } else { 33882 return 0; 33883 } 33884 default: 33885 unreachable("Invalid hardware generation"); 33886 } 33887 } 33888 33889 33890 33891 #define GEN10_3DSTATE_GS_MaskStackExceptionEnable_start 107 33892 #define GEN9_3DSTATE_GS_MaskStackExceptionEnable_start 107 33893 #define GEN8_3DSTATE_GS_MaskStackExceptionEnable_start 107 33894 #define GEN75_3DSTATE_GS_MaskStackExceptionEnable_start 75 33895 #define GEN7_3DSTATE_GS_MaskStackExceptionEnable_start 75 33896 #define GEN6_3DSTATE_GS_MaskStackExceptionEnable_start 75 33897 33898 static inline uint32_t ATTRIBUTE_PURE 33899 _3DSTATE_GS_MaskStackExceptionEnable_start(const struct gen_device_info *devinfo) 33900 { 33901 switch (devinfo->gen) { 33902 case 10: return 107; 33903 case 9: return 107; 33904 case 8: return 107; 33905 case 7: 33906 if (devinfo->is_haswell) { 33907 return 75; 33908 } else { 33909 return 75; 33910 } 33911 case 6: return 75; 33912 case 5: return 0; 33913 case 4: 33914 if (devinfo->is_g4x) { 33915 return 0; 33916 } else { 33917 return 0; 33918 } 33919 default: 33920 unreachable("Invalid hardware generation"); 33921 } 33922 } 33923 33924 33925 33926 /* 3DSTATE_GS::Maximum Number of Threads */ 33927 33928 33929 #define GEN10_3DSTATE_GS_MaximumNumberofThreads_bits 9 33930 #define GEN9_3DSTATE_GS_MaximumNumberofThreads_bits 9 33931 #define GEN8_3DSTATE_GS_MaximumNumberofThreads_bits 8 33932 #define GEN75_3DSTATE_GS_MaximumNumberofThreads_bits 8 33933 #define GEN7_3DSTATE_GS_MaximumNumberofThreads_bits 7 33934 #define GEN6_3DSTATE_GS_MaximumNumberofThreads_bits 7 33935 33936 static inline uint32_t ATTRIBUTE_PURE 33937 _3DSTATE_GS_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) 33938 { 33939 switch (devinfo->gen) { 33940 case 10: return 9; 33941 case 9: return 9; 33942 case 8: return 8; 33943 case 7: 33944 if (devinfo->is_haswell) { 33945 return 8; 33946 } else { 33947 return 7; 33948 } 33949 case 6: return 7; 33950 case 5: return 0; 33951 case 4: 33952 if (devinfo->is_g4x) { 33953 return 0; 33954 } else { 33955 return 0; 33956 } 33957 default: 33958 unreachable("Invalid hardware generation"); 33959 } 33960 } 33961 33962 33963 33964 #define GEN10_3DSTATE_GS_MaximumNumberofThreads_start 256 33965 #define GEN9_3DSTATE_GS_MaximumNumberofThreads_start 256 33966 #define GEN8_3DSTATE_GS_MaximumNumberofThreads_start 248 33967 #define GEN75_3DSTATE_GS_MaximumNumberofThreads_start 184 33968 #define GEN7_3DSTATE_GS_MaximumNumberofThreads_start 185 33969 #define GEN6_3DSTATE_GS_MaximumNumberofThreads_start 185 33970 33971 static inline uint32_t ATTRIBUTE_PURE 33972 _3DSTATE_GS_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) 33973 { 33974 switch (devinfo->gen) { 33975 case 10: return 256; 33976 case 9: return 256; 33977 case 8: return 248; 33978 case 7: 33979 if (devinfo->is_haswell) { 33980 return 184; 33981 } else { 33982 return 185; 33983 } 33984 case 6: return 185; 33985 case 5: return 0; 33986 case 4: 33987 if (devinfo->is_g4x) { 33988 return 0; 33989 } else { 33990 return 0; 33991 } 33992 default: 33993 unreachable("Invalid hardware generation"); 33994 } 33995 } 33996 33997 33998 33999 /* 3DSTATE_GS::Output Topology */ 34000 34001 34002 #define GEN10_3DSTATE_GS_OutputTopology_bits 6 34003 #define GEN9_3DSTATE_GS_OutputTopology_bits 6 34004 #define GEN8_3DSTATE_GS_OutputTopology_bits 6 34005 #define GEN75_3DSTATE_GS_OutputTopology_bits 6 34006 #define GEN7_3DSTATE_GS_OutputTopology_bits 6 34007 34008 static inline uint32_t ATTRIBUTE_PURE 34009 _3DSTATE_GS_OutputTopology_bits(const struct gen_device_info *devinfo) 34010 { 34011 switch (devinfo->gen) { 34012 case 10: return 6; 34013 case 9: return 6; 34014 case 8: return 6; 34015 case 7: 34016 if (devinfo->is_haswell) { 34017 return 6; 34018 } else { 34019 return 6; 34020 } 34021 case 6: return 0; 34022 case 5: return 0; 34023 case 4: 34024 if (devinfo->is_g4x) { 34025 return 0; 34026 } else { 34027 return 0; 34028 } 34029 default: 34030 unreachable("Invalid hardware generation"); 34031 } 34032 } 34033 34034 34035 34036 #define GEN10_3DSTATE_GS_OutputTopology_start 209 34037 #define GEN9_3DSTATE_GS_OutputTopology_start 209 34038 #define GEN8_3DSTATE_GS_OutputTopology_start 209 34039 #define GEN75_3DSTATE_GS_OutputTopology_start 145 34040 #define GEN7_3DSTATE_GS_OutputTopology_start 145 34041 34042 static inline uint32_t ATTRIBUTE_PURE 34043 _3DSTATE_GS_OutputTopology_start(const struct gen_device_info *devinfo) 34044 { 34045 switch (devinfo->gen) { 34046 case 10: return 209; 34047 case 9: return 209; 34048 case 8: return 209; 34049 case 7: 34050 if (devinfo->is_haswell) { 34051 return 145; 34052 } else { 34053 return 145; 34054 } 34055 case 6: return 0; 34056 case 5: return 0; 34057 case 4: 34058 if (devinfo->is_g4x) { 34059 return 0; 34060 } else { 34061 return 0; 34062 } 34063 default: 34064 unreachable("Invalid hardware generation"); 34065 } 34066 } 34067 34068 34069 34070 /* 3DSTATE_GS::Output Vertex Size */ 34071 34072 34073 #define GEN10_3DSTATE_GS_OutputVertexSize_bits 6 34074 #define GEN9_3DSTATE_GS_OutputVertexSize_bits 6 34075 #define GEN8_3DSTATE_GS_OutputVertexSize_bits 6 34076 #define GEN75_3DSTATE_GS_OutputVertexSize_bits 6 34077 #define GEN7_3DSTATE_GS_OutputVertexSize_bits 6 34078 34079 static inline uint32_t ATTRIBUTE_PURE 34080 _3DSTATE_GS_OutputVertexSize_bits(const struct gen_device_info *devinfo) 34081 { 34082 switch (devinfo->gen) { 34083 case 10: return 6; 34084 case 9: return 6; 34085 case 8: return 6; 34086 case 7: 34087 if (devinfo->is_haswell) { 34088 return 6; 34089 } else { 34090 return 6; 34091 } 34092 case 6: return 0; 34093 case 5: return 0; 34094 case 4: 34095 if (devinfo->is_g4x) { 34096 return 0; 34097 } else { 34098 return 0; 34099 } 34100 default: 34101 unreachable("Invalid hardware generation"); 34102 } 34103 } 34104 34105 34106 34107 #define GEN10_3DSTATE_GS_OutputVertexSize_start 215 34108 #define GEN9_3DSTATE_GS_OutputVertexSize_start 215 34109 #define GEN8_3DSTATE_GS_OutputVertexSize_start 215 34110 #define GEN75_3DSTATE_GS_OutputVertexSize_start 151 34111 #define GEN7_3DSTATE_GS_OutputVertexSize_start 151 34112 34113 static inline uint32_t ATTRIBUTE_PURE 34114 _3DSTATE_GS_OutputVertexSize_start(const struct gen_device_info *devinfo) 34115 { 34116 switch (devinfo->gen) { 34117 case 10: return 215; 34118 case 9: return 215; 34119 case 8: return 215; 34120 case 7: 34121 if (devinfo->is_haswell) { 34122 return 151; 34123 } else { 34124 return 151; 34125 } 34126 case 6: return 0; 34127 case 5: return 0; 34128 case 4: 34129 if (devinfo->is_g4x) { 34130 return 0; 34131 } else { 34132 return 0; 34133 } 34134 default: 34135 unreachable("Invalid hardware generation"); 34136 } 34137 } 34138 34139 34140 34141 /* 3DSTATE_GS::Per-Thread Scratch Space */ 34142 34143 34144 #define GEN10_3DSTATE_GS_PerThreadScratchSpace_bits 4 34145 #define GEN9_3DSTATE_GS_PerThreadScratchSpace_bits 4 34146 #define GEN8_3DSTATE_GS_PerThreadScratchSpace_bits 4 34147 #define GEN75_3DSTATE_GS_PerThreadScratchSpace_bits 4 34148 #define GEN7_3DSTATE_GS_PerThreadScratchSpace_bits 4 34149 #define GEN6_3DSTATE_GS_PerThreadScratchSpace_bits 4 34150 34151 static inline uint32_t ATTRIBUTE_PURE 34152 _3DSTATE_GS_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) 34153 { 34154 switch (devinfo->gen) { 34155 case 10: return 4; 34156 case 9: return 4; 34157 case 8: return 4; 34158 case 7: 34159 if (devinfo->is_haswell) { 34160 return 4; 34161 } else { 34162 return 4; 34163 } 34164 case 6: return 4; 34165 case 5: return 0; 34166 case 4: 34167 if (devinfo->is_g4x) { 34168 return 0; 34169 } else { 34170 return 0; 34171 } 34172 default: 34173 unreachable("Invalid hardware generation"); 34174 } 34175 } 34176 34177 34178 34179 #define GEN10_3DSTATE_GS_PerThreadScratchSpace_start 128 34180 #define GEN9_3DSTATE_GS_PerThreadScratchSpace_start 128 34181 #define GEN8_3DSTATE_GS_PerThreadScratchSpace_start 128 34182 #define GEN75_3DSTATE_GS_PerThreadScratchSpace_start 96 34183 #define GEN7_3DSTATE_GS_PerThreadScratchSpace_start 96 34184 #define GEN6_3DSTATE_GS_PerThreadScratchSpace_start 96 34185 34186 static inline uint32_t ATTRIBUTE_PURE 34187 _3DSTATE_GS_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) 34188 { 34189 switch (devinfo->gen) { 34190 case 10: return 128; 34191 case 9: return 128; 34192 case 8: return 128; 34193 case 7: 34194 if (devinfo->is_haswell) { 34195 return 96; 34196 } else { 34197 return 96; 34198 } 34199 case 6: return 96; 34200 case 5: return 0; 34201 case 4: 34202 if (devinfo->is_g4x) { 34203 return 0; 34204 } else { 34205 return 0; 34206 } 34207 default: 34208 unreachable("Invalid hardware generation"); 34209 } 34210 } 34211 34212 34213 34214 /* 3DSTATE_GS::Rendering Enabled */ 34215 34216 34217 #define GEN6_3DSTATE_GS_RenderingEnabled_bits 1 34218 34219 static inline uint32_t ATTRIBUTE_PURE 34220 _3DSTATE_GS_RenderingEnabled_bits(const struct gen_device_info *devinfo) 34221 { 34222 switch (devinfo->gen) { 34223 case 10: return 0; 34224 case 9: return 0; 34225 case 8: return 0; 34226 case 7: 34227 if (devinfo->is_haswell) { 34228 return 0; 34229 } else { 34230 return 0; 34231 } 34232 case 6: return 1; 34233 case 5: return 0; 34234 case 4: 34235 if (devinfo->is_g4x) { 34236 return 0; 34237 } else { 34238 return 0; 34239 } 34240 default: 34241 unreachable("Invalid hardware generation"); 34242 } 34243 } 34244 34245 34246 34247 #define GEN6_3DSTATE_GS_RenderingEnabled_start 168 34248 34249 static inline uint32_t ATTRIBUTE_PURE 34250 _3DSTATE_GS_RenderingEnabled_start(const struct gen_device_info *devinfo) 34251 { 34252 switch (devinfo->gen) { 34253 case 10: return 0; 34254 case 9: return 0; 34255 case 8: return 0; 34256 case 7: 34257 if (devinfo->is_haswell) { 34258 return 0; 34259 } else { 34260 return 0; 34261 } 34262 case 6: return 168; 34263 case 5: return 0; 34264 case 4: 34265 if (devinfo->is_g4x) { 34266 return 0; 34267 } else { 34268 return 0; 34269 } 34270 default: 34271 unreachable("Invalid hardware generation"); 34272 } 34273 } 34274 34275 34276 34277 /* 3DSTATE_GS::Reorder Mode */ 34278 34279 34280 #define GEN10_3DSTATE_GS_ReorderMode_bits 1 34281 #define GEN9_3DSTATE_GS_ReorderMode_bits 1 34282 #define GEN8_3DSTATE_GS_ReorderMode_bits 1 34283 #define GEN75_3DSTATE_GS_ReorderMode_bits 1 34284 #define GEN7_3DSTATE_GS_ReorderMode_bits 1 34285 #define GEN6_3DSTATE_GS_ReorderMode_bits 1 34286 34287 static inline uint32_t ATTRIBUTE_PURE 34288 _3DSTATE_GS_ReorderMode_bits(const struct gen_device_info *devinfo) 34289 { 34290 switch (devinfo->gen) { 34291 case 10: return 1; 34292 case 9: return 1; 34293 case 8: return 1; 34294 case 7: 34295 if (devinfo->is_haswell) { 34296 return 1; 34297 } else { 34298 return 1; 34299 } 34300 case 6: return 1; 34301 case 5: return 0; 34302 case 4: 34303 if (devinfo->is_g4x) { 34304 return 0; 34305 } else { 34306 return 0; 34307 } 34308 default: 34309 unreachable("Invalid hardware generation"); 34310 } 34311 } 34312 34313 34314 34315 #define GEN10_3DSTATE_GS_ReorderMode_start 226 34316 #define GEN9_3DSTATE_GS_ReorderMode_start 226 34317 #define GEN8_3DSTATE_GS_ReorderMode_start 226 34318 #define GEN75_3DSTATE_GS_ReorderMode_start 162 34319 #define GEN7_3DSTATE_GS_ReorderMode_start 162 34320 #define GEN6_3DSTATE_GS_ReorderMode_start 222 34321 34322 static inline uint32_t ATTRIBUTE_PURE 34323 _3DSTATE_GS_ReorderMode_start(const struct gen_device_info *devinfo) 34324 { 34325 switch (devinfo->gen) { 34326 case 10: return 226; 34327 case 9: return 226; 34328 case 8: return 226; 34329 case 7: 34330 if (devinfo->is_haswell) { 34331 return 162; 34332 } else { 34333 return 162; 34334 } 34335 case 6: return 222; 34336 case 5: return 0; 34337 case 4: 34338 if (devinfo->is_g4x) { 34339 return 0; 34340 } else { 34341 return 0; 34342 } 34343 default: 34344 unreachable("Invalid hardware generation"); 34345 } 34346 } 34347 34348 34349 34350 /* 3DSTATE_GS::SO Statistics Enable */ 34351 34352 34353 #define GEN6_3DSTATE_GS_SOStatisticsEnable_bits 1 34354 34355 static inline uint32_t ATTRIBUTE_PURE 34356 _3DSTATE_GS_SOStatisticsEnable_bits(const struct gen_device_info *devinfo) 34357 { 34358 switch (devinfo->gen) { 34359 case 10: return 0; 34360 case 9: return 0; 34361 case 8: return 0; 34362 case 7: 34363 if (devinfo->is_haswell) { 34364 return 0; 34365 } else { 34366 return 0; 34367 } 34368 case 6: return 1; 34369 case 5: return 0; 34370 case 4: 34371 if (devinfo->is_g4x) { 34372 return 0; 34373 } else { 34374 return 0; 34375 } 34376 default: 34377 unreachable("Invalid hardware generation"); 34378 } 34379 } 34380 34381 34382 34383 #define GEN6_3DSTATE_GS_SOStatisticsEnable_start 169 34384 34385 static inline uint32_t ATTRIBUTE_PURE 34386 _3DSTATE_GS_SOStatisticsEnable_start(const struct gen_device_info *devinfo) 34387 { 34388 switch (devinfo->gen) { 34389 case 10: return 0; 34390 case 9: return 0; 34391 case 8: return 0; 34392 case 7: 34393 if (devinfo->is_haswell) { 34394 return 0; 34395 } else { 34396 return 0; 34397 } 34398 case 6: return 169; 34399 case 5: return 0; 34400 case 4: 34401 if (devinfo->is_g4x) { 34402 return 0; 34403 } else { 34404 return 0; 34405 } 34406 default: 34407 unreachable("Invalid hardware generation"); 34408 } 34409 } 34410 34411 34412 34413 /* 3DSTATE_GS::SVBI Payload Enable */ 34414 34415 34416 #define GEN6_3DSTATE_GS_SVBIPayloadEnable_bits 1 34417 34418 static inline uint32_t ATTRIBUTE_PURE 34419 _3DSTATE_GS_SVBIPayloadEnable_bits(const struct gen_device_info *devinfo) 34420 { 34421 switch (devinfo->gen) { 34422 case 10: return 0; 34423 case 9: return 0; 34424 case 8: return 0; 34425 case 7: 34426 if (devinfo->is_haswell) { 34427 return 0; 34428 } else { 34429 return 0; 34430 } 34431 case 6: return 1; 34432 case 5: return 0; 34433 case 4: 34434 if (devinfo->is_g4x) { 34435 return 0; 34436 } else { 34437 return 0; 34438 } 34439 default: 34440 unreachable("Invalid hardware generation"); 34441 } 34442 } 34443 34444 34445 34446 #define GEN6_3DSTATE_GS_SVBIPayloadEnable_start 220 34447 34448 static inline uint32_t ATTRIBUTE_PURE 34449 _3DSTATE_GS_SVBIPayloadEnable_start(const struct gen_device_info *devinfo) 34450 { 34451 switch (devinfo->gen) { 34452 case 10: return 0; 34453 case 9: return 0; 34454 case 8: return 0; 34455 case 7: 34456 if (devinfo->is_haswell) { 34457 return 0; 34458 } else { 34459 return 0; 34460 } 34461 case 6: return 220; 34462 case 5: return 0; 34463 case 4: 34464 if (devinfo->is_g4x) { 34465 return 0; 34466 } else { 34467 return 0; 34468 } 34469 default: 34470 unreachable("Invalid hardware generation"); 34471 } 34472 } 34473 34474 34475 34476 /* 3DSTATE_GS::SVBI Post-Increment Enable */ 34477 34478 34479 #define GEN6_3DSTATE_GS_SVBIPostIncrementEnable_bits 1 34480 34481 static inline uint32_t ATTRIBUTE_PURE 34482 _3DSTATE_GS_SVBIPostIncrementEnable_bits(const struct gen_device_info *devinfo) 34483 { 34484 switch (devinfo->gen) { 34485 case 10: return 0; 34486 case 9: return 0; 34487 case 8: return 0; 34488 case 7: 34489 if (devinfo->is_haswell) { 34490 return 0; 34491 } else { 34492 return 0; 34493 } 34494 case 6: return 1; 34495 case 5: return 0; 34496 case 4: 34497 if (devinfo->is_g4x) { 34498 return 0; 34499 } else { 34500 return 0; 34501 } 34502 default: 34503 unreachable("Invalid hardware generation"); 34504 } 34505 } 34506 34507 34508 34509 #define GEN6_3DSTATE_GS_SVBIPostIncrementEnable_start 219 34510 34511 static inline uint32_t ATTRIBUTE_PURE 34512 _3DSTATE_GS_SVBIPostIncrementEnable_start(const struct gen_device_info *devinfo) 34513 { 34514 switch (devinfo->gen) { 34515 case 10: return 0; 34516 case 9: return 0; 34517 case 8: return 0; 34518 case 7: 34519 if (devinfo->is_haswell) { 34520 return 0; 34521 } else { 34522 return 0; 34523 } 34524 case 6: return 219; 34525 case 5: return 0; 34526 case 4: 34527 if (devinfo->is_g4x) { 34528 return 0; 34529 } else { 34530 return 0; 34531 } 34532 default: 34533 unreachable("Invalid hardware generation"); 34534 } 34535 } 34536 34537 34538 34539 /* 3DSTATE_GS::SVBI Post-Increment Value */ 34540 34541 34542 #define GEN6_3DSTATE_GS_SVBIPostIncrementValue_bits 10 34543 34544 static inline uint32_t ATTRIBUTE_PURE 34545 _3DSTATE_GS_SVBIPostIncrementValue_bits(const struct gen_device_info *devinfo) 34546 { 34547 switch (devinfo->gen) { 34548 case 10: return 0; 34549 case 9: return 0; 34550 case 8: return 0; 34551 case 7: 34552 if (devinfo->is_haswell) { 34553 return 0; 34554 } else { 34555 return 0; 34556 } 34557 case 6: return 10; 34558 case 5: return 0; 34559 case 4: 34560 if (devinfo->is_g4x) { 34561 return 0; 34562 } else { 34563 return 0; 34564 } 34565 default: 34566 unreachable("Invalid hardware generation"); 34567 } 34568 } 34569 34570 34571 34572 #define GEN6_3DSTATE_GS_SVBIPostIncrementValue_start 208 34573 34574 static inline uint32_t ATTRIBUTE_PURE 34575 _3DSTATE_GS_SVBIPostIncrementValue_start(const struct gen_device_info *devinfo) 34576 { 34577 switch (devinfo->gen) { 34578 case 10: return 0; 34579 case 9: return 0; 34580 case 8: return 0; 34581 case 7: 34582 if (devinfo->is_haswell) { 34583 return 0; 34584 } else { 34585 return 0; 34586 } 34587 case 6: return 208; 34588 case 5: return 0; 34589 case 4: 34590 if (devinfo->is_g4x) { 34591 return 0; 34592 } else { 34593 return 0; 34594 } 34595 default: 34596 unreachable("Invalid hardware generation"); 34597 } 34598 } 34599 34600 34601 34602 /* 3DSTATE_GS::Sampler Count */ 34603 34604 34605 #define GEN10_3DSTATE_GS_SamplerCount_bits 3 34606 #define GEN9_3DSTATE_GS_SamplerCount_bits 3 34607 #define GEN8_3DSTATE_GS_SamplerCount_bits 3 34608 #define GEN75_3DSTATE_GS_SamplerCount_bits 3 34609 #define GEN7_3DSTATE_GS_SamplerCount_bits 3 34610 #define GEN6_3DSTATE_GS_SamplerCount_bits 3 34611 34612 static inline uint32_t ATTRIBUTE_PURE 34613 _3DSTATE_GS_SamplerCount_bits(const struct gen_device_info *devinfo) 34614 { 34615 switch (devinfo->gen) { 34616 case 10: return 3; 34617 case 9: return 3; 34618 case 8: return 3; 34619 case 7: 34620 if (devinfo->is_haswell) { 34621 return 3; 34622 } else { 34623 return 3; 34624 } 34625 case 6: return 3; 34626 case 5: return 0; 34627 case 4: 34628 if (devinfo->is_g4x) { 34629 return 0; 34630 } else { 34631 return 0; 34632 } 34633 default: 34634 unreachable("Invalid hardware generation"); 34635 } 34636 } 34637 34638 34639 34640 #define GEN10_3DSTATE_GS_SamplerCount_start 123 34641 #define GEN9_3DSTATE_GS_SamplerCount_start 123 34642 #define GEN8_3DSTATE_GS_SamplerCount_start 123 34643 #define GEN75_3DSTATE_GS_SamplerCount_start 91 34644 #define GEN7_3DSTATE_GS_SamplerCount_start 91 34645 #define GEN6_3DSTATE_GS_SamplerCount_start 91 34646 34647 static inline uint32_t ATTRIBUTE_PURE 34648 _3DSTATE_GS_SamplerCount_start(const struct gen_device_info *devinfo) 34649 { 34650 switch (devinfo->gen) { 34651 case 10: return 123; 34652 case 9: return 123; 34653 case 8: return 123; 34654 case 7: 34655 if (devinfo->is_haswell) { 34656 return 91; 34657 } else { 34658 return 91; 34659 } 34660 case 6: return 91; 34661 case 5: return 0; 34662 case 4: 34663 if (devinfo->is_g4x) { 34664 return 0; 34665 } else { 34666 return 0; 34667 } 34668 default: 34669 unreachable("Invalid hardware generation"); 34670 } 34671 } 34672 34673 34674 34675 /* 3DSTATE_GS::Scratch Space Base Pointer */ 34676 34677 34678 #define GEN10_3DSTATE_GS_ScratchSpaceBasePointer_bits 54 34679 #define GEN9_3DSTATE_GS_ScratchSpaceBasePointer_bits 54 34680 #define GEN8_3DSTATE_GS_ScratchSpaceBasePointer_bits 54 34681 #define GEN75_3DSTATE_GS_ScratchSpaceBasePointer_bits 22 34682 #define GEN7_3DSTATE_GS_ScratchSpaceBasePointer_bits 22 34683 #define GEN6_3DSTATE_GS_ScratchSpaceBasePointer_bits 22 34684 34685 static inline uint32_t ATTRIBUTE_PURE 34686 _3DSTATE_GS_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) 34687 { 34688 switch (devinfo->gen) { 34689 case 10: return 54; 34690 case 9: return 54; 34691 case 8: return 54; 34692 case 7: 34693 if (devinfo->is_haswell) { 34694 return 22; 34695 } else { 34696 return 22; 34697 } 34698 case 6: return 22; 34699 case 5: return 0; 34700 case 4: 34701 if (devinfo->is_g4x) { 34702 return 0; 34703 } else { 34704 return 0; 34705 } 34706 default: 34707 unreachable("Invalid hardware generation"); 34708 } 34709 } 34710 34711 34712 34713 #define GEN10_3DSTATE_GS_ScratchSpaceBasePointer_start 138 34714 #define GEN9_3DSTATE_GS_ScratchSpaceBasePointer_start 138 34715 #define GEN8_3DSTATE_GS_ScratchSpaceBasePointer_start 138 34716 #define GEN75_3DSTATE_GS_ScratchSpaceBasePointer_start 106 34717 #define GEN7_3DSTATE_GS_ScratchSpaceBasePointer_start 106 34718 #define GEN6_3DSTATE_GS_ScratchSpaceBasePointer_start 106 34719 34720 static inline uint32_t ATTRIBUTE_PURE 34721 _3DSTATE_GS_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) 34722 { 34723 switch (devinfo->gen) { 34724 case 10: return 138; 34725 case 9: return 138; 34726 case 8: return 138; 34727 case 7: 34728 if (devinfo->is_haswell) { 34729 return 106; 34730 } else { 34731 return 106; 34732 } 34733 case 6: return 106; 34734 case 5: return 0; 34735 case 4: 34736 if (devinfo->is_g4x) { 34737 return 0; 34738 } else { 34739 return 0; 34740 } 34741 default: 34742 unreachable("Invalid hardware generation"); 34743 } 34744 } 34745 34746 34747 34748 /* 3DSTATE_GS::Semaphore Handle */ 34749 34750 34751 #define GEN75_3DSTATE_GS_SemaphoreHandle_bits 13 34752 #define GEN7_3DSTATE_GS_SemaphoreHandle_bits 12 34753 34754 static inline uint32_t ATTRIBUTE_PURE 34755 _3DSTATE_GS_SemaphoreHandle_bits(const struct gen_device_info *devinfo) 34756 { 34757 switch (devinfo->gen) { 34758 case 10: return 0; 34759 case 9: return 0; 34760 case 8: return 0; 34761 case 7: 34762 if (devinfo->is_haswell) { 34763 return 13; 34764 } else { 34765 return 12; 34766 } 34767 case 6: return 0; 34768 case 5: return 0; 34769 case 4: 34770 if (devinfo->is_g4x) { 34771 return 0; 34772 } else { 34773 return 0; 34774 } 34775 default: 34776 unreachable("Invalid hardware generation"); 34777 } 34778 } 34779 34780 34781 34782 #define GEN75_3DSTATE_GS_SemaphoreHandle_start 192 34783 #define GEN7_3DSTATE_GS_SemaphoreHandle_start 192 34784 34785 static inline uint32_t ATTRIBUTE_PURE 34786 _3DSTATE_GS_SemaphoreHandle_start(const struct gen_device_info *devinfo) 34787 { 34788 switch (devinfo->gen) { 34789 case 10: return 0; 34790 case 9: return 0; 34791 case 8: return 0; 34792 case 7: 34793 if (devinfo->is_haswell) { 34794 return 192; 34795 } else { 34796 return 192; 34797 } 34798 case 6: return 0; 34799 case 5: return 0; 34800 case 4: 34801 if (devinfo->is_g4x) { 34802 return 0; 34803 } else { 34804 return 0; 34805 } 34806 default: 34807 unreachable("Invalid hardware generation"); 34808 } 34809 } 34810 34811 34812 34813 /* 3DSTATE_GS::Single Program Flow */ 34814 34815 34816 #define GEN10_3DSTATE_GS_SingleProgramFlow_bits 1 34817 #define GEN9_3DSTATE_GS_SingleProgramFlow_bits 1 34818 #define GEN8_3DSTATE_GS_SingleProgramFlow_bits 1 34819 #define GEN75_3DSTATE_GS_SingleProgramFlow_bits 1 34820 #define GEN7_3DSTATE_GS_SingleProgramFlow_bits 1 34821 #define GEN6_3DSTATE_GS_SingleProgramFlow_bits 1 34822 34823 static inline uint32_t ATTRIBUTE_PURE 34824 _3DSTATE_GS_SingleProgramFlow_bits(const struct gen_device_info *devinfo) 34825 { 34826 switch (devinfo->gen) { 34827 case 10: return 1; 34828 case 9: return 1; 34829 case 8: return 1; 34830 case 7: 34831 if (devinfo->is_haswell) { 34832 return 1; 34833 } else { 34834 return 1; 34835 } 34836 case 6: return 1; 34837 case 5: return 0; 34838 case 4: 34839 if (devinfo->is_g4x) { 34840 return 0; 34841 } else { 34842 return 0; 34843 } 34844 default: 34845 unreachable("Invalid hardware generation"); 34846 } 34847 } 34848 34849 34850 34851 #define GEN10_3DSTATE_GS_SingleProgramFlow_start 127 34852 #define GEN9_3DSTATE_GS_SingleProgramFlow_start 127 34853 #define GEN8_3DSTATE_GS_SingleProgramFlow_start 127 34854 #define GEN75_3DSTATE_GS_SingleProgramFlow_start 95 34855 #define GEN7_3DSTATE_GS_SingleProgramFlow_start 95 34856 #define GEN6_3DSTATE_GS_SingleProgramFlow_start 95 34857 34858 static inline uint32_t ATTRIBUTE_PURE 34859 _3DSTATE_GS_SingleProgramFlow_start(const struct gen_device_info *devinfo) 34860 { 34861 switch (devinfo->gen) { 34862 case 10: return 127; 34863 case 9: return 127; 34864 case 8: return 127; 34865 case 7: 34866 if (devinfo->is_haswell) { 34867 return 95; 34868 } else { 34869 return 95; 34870 } 34871 case 6: return 95; 34872 case 5: return 0; 34873 case 4: 34874 if (devinfo->is_g4x) { 34875 return 0; 34876 } else { 34877 return 0; 34878 } 34879 default: 34880 unreachable("Invalid hardware generation"); 34881 } 34882 } 34883 34884 34885 34886 /* 3DSTATE_GS::Software Exception Enable */ 34887 34888 34889 #define GEN10_3DSTATE_GS_SoftwareExceptionEnable_bits 1 34890 #define GEN9_3DSTATE_GS_SoftwareExceptionEnable_bits 1 34891 #define GEN8_3DSTATE_GS_SoftwareExceptionEnable_bits 1 34892 #define GEN75_3DSTATE_GS_SoftwareExceptionEnable_bits 1 34893 #define GEN7_3DSTATE_GS_SoftwareExceptionEnable_bits 1 34894 #define GEN6_3DSTATE_GS_SoftwareExceptionEnable_bits 1 34895 34896 static inline uint32_t ATTRIBUTE_PURE 34897 _3DSTATE_GS_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) 34898 { 34899 switch (devinfo->gen) { 34900 case 10: return 1; 34901 case 9: return 1; 34902 case 8: return 1; 34903 case 7: 34904 if (devinfo->is_haswell) { 34905 return 1; 34906 } else { 34907 return 1; 34908 } 34909 case 6: return 1; 34910 case 5: return 0; 34911 case 4: 34912 if (devinfo->is_g4x) { 34913 return 0; 34914 } else { 34915 return 0; 34916 } 34917 default: 34918 unreachable("Invalid hardware generation"); 34919 } 34920 } 34921 34922 34923 34924 #define GEN10_3DSTATE_GS_SoftwareExceptionEnable_start 103 34925 #define GEN9_3DSTATE_GS_SoftwareExceptionEnable_start 103 34926 #define GEN8_3DSTATE_GS_SoftwareExceptionEnable_start 103 34927 #define GEN75_3DSTATE_GS_SoftwareExceptionEnable_start 71 34928 #define GEN7_3DSTATE_GS_SoftwareExceptionEnable_start 71 34929 #define GEN6_3DSTATE_GS_SoftwareExceptionEnable_start 71 34930 34931 static inline uint32_t ATTRIBUTE_PURE 34932 _3DSTATE_GS_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) 34933 { 34934 switch (devinfo->gen) { 34935 case 10: return 103; 34936 case 9: return 103; 34937 case 8: return 103; 34938 case 7: 34939 if (devinfo->is_haswell) { 34940 return 71; 34941 } else { 34942 return 71; 34943 } 34944 case 6: return 71; 34945 case 5: return 0; 34946 case 4: 34947 if (devinfo->is_g4x) { 34948 return 0; 34949 } else { 34950 return 0; 34951 } 34952 default: 34953 unreachable("Invalid hardware generation"); 34954 } 34955 } 34956 34957 34958 34959 /* 3DSTATE_GS::Static Output */ 34960 34961 34962 #define GEN10_3DSTATE_GS_StaticOutput_bits 1 34963 #define GEN9_3DSTATE_GS_StaticOutput_bits 1 34964 #define GEN8_3DSTATE_GS_StaticOutput_bits 1 34965 34966 static inline uint32_t ATTRIBUTE_PURE 34967 _3DSTATE_GS_StaticOutput_bits(const struct gen_device_info *devinfo) 34968 { 34969 switch (devinfo->gen) { 34970 case 10: return 1; 34971 case 9: return 1; 34972 case 8: return 1; 34973 case 7: 34974 if (devinfo->is_haswell) { 34975 return 0; 34976 } else { 34977 return 0; 34978 } 34979 case 6: return 0; 34980 case 5: return 0; 34981 case 4: 34982 if (devinfo->is_g4x) { 34983 return 0; 34984 } else { 34985 return 0; 34986 } 34987 default: 34988 unreachable("Invalid hardware generation"); 34989 } 34990 } 34991 34992 34993 34994 #define GEN10_3DSTATE_GS_StaticOutput_start 286 34995 #define GEN9_3DSTATE_GS_StaticOutput_start 286 34996 #define GEN8_3DSTATE_GS_StaticOutput_start 286 34997 34998 static inline uint32_t ATTRIBUTE_PURE 34999 _3DSTATE_GS_StaticOutput_start(const struct gen_device_info *devinfo) 35000 { 35001 switch (devinfo->gen) { 35002 case 10: return 286; 35003 case 9: return 286; 35004 case 8: return 286; 35005 case 7: 35006 if (devinfo->is_haswell) { 35007 return 0; 35008 } else { 35009 return 0; 35010 } 35011 case 6: return 0; 35012 case 5: return 0; 35013 case 4: 35014 if (devinfo->is_g4x) { 35015 return 0; 35016 } else { 35017 return 0; 35018 } 35019 default: 35020 unreachable("Invalid hardware generation"); 35021 } 35022 } 35023 35024 35025 35026 /* 3DSTATE_GS::Static Output Vertex Count */ 35027 35028 35029 #define GEN10_3DSTATE_GS_StaticOutputVertexCount_bits 11 35030 #define GEN9_3DSTATE_GS_StaticOutputVertexCount_bits 11 35031 #define GEN8_3DSTATE_GS_StaticOutputVertexCount_bits 11 35032 35033 static inline uint32_t ATTRIBUTE_PURE 35034 _3DSTATE_GS_StaticOutputVertexCount_bits(const struct gen_device_info *devinfo) 35035 { 35036 switch (devinfo->gen) { 35037 case 10: return 11; 35038 case 9: return 11; 35039 case 8: return 11; 35040 case 7: 35041 if (devinfo->is_haswell) { 35042 return 0; 35043 } else { 35044 return 0; 35045 } 35046 case 6: return 0; 35047 case 5: return 0; 35048 case 4: 35049 if (devinfo->is_g4x) { 35050 return 0; 35051 } else { 35052 return 0; 35053 } 35054 default: 35055 unreachable("Invalid hardware generation"); 35056 } 35057 } 35058 35059 35060 35061 #define GEN10_3DSTATE_GS_StaticOutputVertexCount_start 272 35062 #define GEN9_3DSTATE_GS_StaticOutputVertexCount_start 272 35063 #define GEN8_3DSTATE_GS_StaticOutputVertexCount_start 272 35064 35065 static inline uint32_t ATTRIBUTE_PURE 35066 _3DSTATE_GS_StaticOutputVertexCount_start(const struct gen_device_info *devinfo) 35067 { 35068 switch (devinfo->gen) { 35069 case 10: return 272; 35070 case 9: return 272; 35071 case 8: return 272; 35072 case 7: 35073 if (devinfo->is_haswell) { 35074 return 0; 35075 } else { 35076 return 0; 35077 } 35078 case 6: return 0; 35079 case 5: return 0; 35080 case 4: 35081 if (devinfo->is_g4x) { 35082 return 0; 35083 } else { 35084 return 0; 35085 } 35086 default: 35087 unreachable("Invalid hardware generation"); 35088 } 35089 } 35090 35091 35092 35093 /* 3DSTATE_GS::Statistics Enable */ 35094 35095 35096 #define GEN10_3DSTATE_GS_StatisticsEnable_bits 1 35097 #define GEN9_3DSTATE_GS_StatisticsEnable_bits 1 35098 #define GEN8_3DSTATE_GS_StatisticsEnable_bits 1 35099 #define GEN75_3DSTATE_GS_StatisticsEnable_bits 1 35100 #define GEN7_3DSTATE_GS_StatisticsEnable_bits 1 35101 #define GEN6_3DSTATE_GS_StatisticsEnable_bits 1 35102 35103 static inline uint32_t ATTRIBUTE_PURE 35104 _3DSTATE_GS_StatisticsEnable_bits(const struct gen_device_info *devinfo) 35105 { 35106 switch (devinfo->gen) { 35107 case 10: return 1; 35108 case 9: return 1; 35109 case 8: return 1; 35110 case 7: 35111 if (devinfo->is_haswell) { 35112 return 1; 35113 } else { 35114 return 1; 35115 } 35116 case 6: return 1; 35117 case 5: return 0; 35118 case 4: 35119 if (devinfo->is_g4x) { 35120 return 0; 35121 } else { 35122 return 0; 35123 } 35124 default: 35125 unreachable("Invalid hardware generation"); 35126 } 35127 } 35128 35129 35130 35131 #define GEN10_3DSTATE_GS_StatisticsEnable_start 234 35132 #define GEN9_3DSTATE_GS_StatisticsEnable_start 234 35133 #define GEN8_3DSTATE_GS_StatisticsEnable_start 234 35134 #define GEN75_3DSTATE_GS_StatisticsEnable_start 170 35135 #define GEN7_3DSTATE_GS_StatisticsEnable_start 170 35136 #define GEN6_3DSTATE_GS_StatisticsEnable_start 170 35137 35138 static inline uint32_t ATTRIBUTE_PURE 35139 _3DSTATE_GS_StatisticsEnable_start(const struct gen_device_info *devinfo) 35140 { 35141 switch (devinfo->gen) { 35142 case 10: return 234; 35143 case 9: return 234; 35144 case 8: return 234; 35145 case 7: 35146 if (devinfo->is_haswell) { 35147 return 170; 35148 } else { 35149 return 170; 35150 } 35151 case 6: return 170; 35152 case 5: return 0; 35153 case 4: 35154 if (devinfo->is_g4x) { 35155 return 0; 35156 } else { 35157 return 0; 35158 } 35159 default: 35160 unreachable("Invalid hardware generation"); 35161 } 35162 } 35163 35164 35165 35166 /* 3DSTATE_GS::Thread Dispatch Priority */ 35167 35168 35169 #define GEN10_3DSTATE_GS_ThreadDispatchPriority_bits 1 35170 #define GEN9_3DSTATE_GS_ThreadDispatchPriority_bits 1 35171 #define GEN8_3DSTATE_GS_ThreadDispatchPriority_bits 1 35172 35173 static inline uint32_t ATTRIBUTE_PURE 35174 _3DSTATE_GS_ThreadDispatchPriority_bits(const struct gen_device_info *devinfo) 35175 { 35176 switch (devinfo->gen) { 35177 case 10: return 1; 35178 case 9: return 1; 35179 case 8: return 1; 35180 case 7: 35181 if (devinfo->is_haswell) { 35182 return 0; 35183 } else { 35184 return 0; 35185 } 35186 case 6: return 0; 35187 case 5: return 0; 35188 case 4: 35189 if (devinfo->is_g4x) { 35190 return 0; 35191 } else { 35192 return 0; 35193 } 35194 default: 35195 unreachable("Invalid hardware generation"); 35196 } 35197 } 35198 35199 35200 35201 #define GEN10_3DSTATE_GS_ThreadDispatchPriority_start 113 35202 #define GEN9_3DSTATE_GS_ThreadDispatchPriority_start 113 35203 #define GEN8_3DSTATE_GS_ThreadDispatchPriority_start 113 35204 35205 static inline uint32_t ATTRIBUTE_PURE 35206 _3DSTATE_GS_ThreadDispatchPriority_start(const struct gen_device_info *devinfo) 35207 { 35208 switch (devinfo->gen) { 35209 case 10: return 113; 35210 case 9: return 113; 35211 case 8: return 113; 35212 case 7: 35213 if (devinfo->is_haswell) { 35214 return 0; 35215 } else { 35216 return 0; 35217 } 35218 case 6: return 0; 35219 case 5: return 0; 35220 case 4: 35221 if (devinfo->is_g4x) { 35222 return 0; 35223 } else { 35224 return 0; 35225 } 35226 default: 35227 unreachable("Invalid hardware generation"); 35228 } 35229 } 35230 35231 35232 35233 /* 3DSTATE_GS::Thread Priority */ 35234 35235 35236 #define GEN75_3DSTATE_GS_ThreadPriority_bits 1 35237 #define GEN7_3DSTATE_GS_ThreadPriority_bits 1 35238 #define GEN6_3DSTATE_GS_ThreadPriority_bits 1 35239 35240 static inline uint32_t ATTRIBUTE_PURE 35241 _3DSTATE_GS_ThreadPriority_bits(const struct gen_device_info *devinfo) 35242 { 35243 switch (devinfo->gen) { 35244 case 10: return 0; 35245 case 9: return 0; 35246 case 8: return 0; 35247 case 7: 35248 if (devinfo->is_haswell) { 35249 return 1; 35250 } else { 35251 return 1; 35252 } 35253 case 6: return 1; 35254 case 5: return 0; 35255 case 4: 35256 if (devinfo->is_g4x) { 35257 return 0; 35258 } else { 35259 return 0; 35260 } 35261 default: 35262 unreachable("Invalid hardware generation"); 35263 } 35264 } 35265 35266 35267 35268 #define GEN75_3DSTATE_GS_ThreadPriority_start 81 35269 #define GEN7_3DSTATE_GS_ThreadPriority_start 81 35270 #define GEN6_3DSTATE_GS_ThreadPriority_start 81 35271 35272 static inline uint32_t ATTRIBUTE_PURE 35273 _3DSTATE_GS_ThreadPriority_start(const struct gen_device_info *devinfo) 35274 { 35275 switch (devinfo->gen) { 35276 case 10: return 0; 35277 case 9: return 0; 35278 case 8: return 0; 35279 case 7: 35280 if (devinfo->is_haswell) { 35281 return 81; 35282 } else { 35283 return 81; 35284 } 35285 case 6: return 81; 35286 case 5: return 0; 35287 case 4: 35288 if (devinfo->is_g4x) { 35289 return 0; 35290 } else { 35291 return 0; 35292 } 35293 default: 35294 unreachable("Invalid hardware generation"); 35295 } 35296 } 35297 35298 35299 35300 /* 3DSTATE_GS::User Clip Distance Clip Test Enable Bitmask */ 35301 35302 35303 #define GEN10_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits 8 35304 #define GEN9_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits 8 35305 #define GEN8_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits 8 35306 35307 static inline uint32_t ATTRIBUTE_PURE 35308 _3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits(const struct gen_device_info *devinfo) 35309 { 35310 switch (devinfo->gen) { 35311 case 10: return 8; 35312 case 9: return 8; 35313 case 8: return 8; 35314 case 7: 35315 if (devinfo->is_haswell) { 35316 return 0; 35317 } else { 35318 return 0; 35319 } 35320 case 6: return 0; 35321 case 5: return 0; 35322 case 4: 35323 if (devinfo->is_g4x) { 35324 return 0; 35325 } else { 35326 return 0; 35327 } 35328 default: 35329 unreachable("Invalid hardware generation"); 35330 } 35331 } 35332 35333 35334 35335 #define GEN10_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start 296 35336 #define GEN9_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start 296 35337 #define GEN8_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start 296 35338 35339 static inline uint32_t ATTRIBUTE_PURE 35340 _3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start(const struct gen_device_info *devinfo) 35341 { 35342 switch (devinfo->gen) { 35343 case 10: return 296; 35344 case 9: return 296; 35345 case 8: return 296; 35346 case 7: 35347 if (devinfo->is_haswell) { 35348 return 0; 35349 } else { 35350 return 0; 35351 } 35352 case 6: return 0; 35353 case 5: return 0; 35354 case 4: 35355 if (devinfo->is_g4x) { 35356 return 0; 35357 } else { 35358 return 0; 35359 } 35360 default: 35361 unreachable("Invalid hardware generation"); 35362 } 35363 } 35364 35365 35366 35367 /* 3DSTATE_GS::User Clip Distance Cull Test Enable Bitmask */ 35368 35369 35370 #define GEN10_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits 8 35371 #define GEN9_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits 8 35372 #define GEN8_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits 8 35373 35374 static inline uint32_t ATTRIBUTE_PURE 35375 _3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits(const struct gen_device_info *devinfo) 35376 { 35377 switch (devinfo->gen) { 35378 case 10: return 8; 35379 case 9: return 8; 35380 case 8: return 8; 35381 case 7: 35382 if (devinfo->is_haswell) { 35383 return 0; 35384 } else { 35385 return 0; 35386 } 35387 case 6: return 0; 35388 case 5: return 0; 35389 case 4: 35390 if (devinfo->is_g4x) { 35391 return 0; 35392 } else { 35393 return 0; 35394 } 35395 default: 35396 unreachable("Invalid hardware generation"); 35397 } 35398 } 35399 35400 35401 35402 #define GEN10_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start 288 35403 #define GEN9_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start 288 35404 #define GEN8_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start 288 35405 35406 static inline uint32_t ATTRIBUTE_PURE 35407 _3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start(const struct gen_device_info *devinfo) 35408 { 35409 switch (devinfo->gen) { 35410 case 10: return 288; 35411 case 9: return 288; 35412 case 8: return 288; 35413 case 7: 35414 if (devinfo->is_haswell) { 35415 return 0; 35416 } else { 35417 return 0; 35418 } 35419 case 6: return 0; 35420 case 5: return 0; 35421 case 4: 35422 if (devinfo->is_g4x) { 35423 return 0; 35424 } else { 35425 return 0; 35426 } 35427 default: 35428 unreachable("Invalid hardware generation"); 35429 } 35430 } 35431 35432 35433 35434 /* 3DSTATE_GS::Vector Mask Enable */ 35435 35436 35437 #define GEN10_3DSTATE_GS_VectorMaskEnable_bits 1 35438 #define GEN9_3DSTATE_GS_VectorMaskEnable_bits 1 35439 #define GEN8_3DSTATE_GS_VectorMaskEnable_bits 1 35440 #define GEN75_3DSTATE_GS_VectorMaskEnable_bits 1 35441 #define GEN7_3DSTATE_GS_VectorMaskEnable_bits 1 35442 #define GEN6_3DSTATE_GS_VectorMaskEnable_bits 1 35443 35444 static inline uint32_t ATTRIBUTE_PURE 35445 _3DSTATE_GS_VectorMaskEnable_bits(const struct gen_device_info *devinfo) 35446 { 35447 switch (devinfo->gen) { 35448 case 10: return 1; 35449 case 9: return 1; 35450 case 8: return 1; 35451 case 7: 35452 if (devinfo->is_haswell) { 35453 return 1; 35454 } else { 35455 return 1; 35456 } 35457 case 6: return 1; 35458 case 5: return 0; 35459 case 4: 35460 if (devinfo->is_g4x) { 35461 return 0; 35462 } else { 35463 return 0; 35464 } 35465 default: 35466 unreachable("Invalid hardware generation"); 35467 } 35468 } 35469 35470 35471 35472 #define GEN10_3DSTATE_GS_VectorMaskEnable_start 126 35473 #define GEN9_3DSTATE_GS_VectorMaskEnable_start 126 35474 #define GEN8_3DSTATE_GS_VectorMaskEnable_start 126 35475 #define GEN75_3DSTATE_GS_VectorMaskEnable_start 94 35476 #define GEN7_3DSTATE_GS_VectorMaskEnable_start 94 35477 #define GEN6_3DSTATE_GS_VectorMaskEnable_start 94 35478 35479 static inline uint32_t ATTRIBUTE_PURE 35480 _3DSTATE_GS_VectorMaskEnable_start(const struct gen_device_info *devinfo) 35481 { 35482 switch (devinfo->gen) { 35483 case 10: return 126; 35484 case 9: return 126; 35485 case 8: return 126; 35486 case 7: 35487 if (devinfo->is_haswell) { 35488 return 94; 35489 } else { 35490 return 94; 35491 } 35492 case 6: return 94; 35493 case 5: return 0; 35494 case 4: 35495 if (devinfo->is_g4x) { 35496 return 0; 35497 } else { 35498 return 0; 35499 } 35500 default: 35501 unreachable("Invalid hardware generation"); 35502 } 35503 } 35504 35505 35506 35507 /* 3DSTATE_GS::Vertex URB Entry Output Length */ 35508 35509 35510 #define GEN10_3DSTATE_GS_VertexURBEntryOutputLength_bits 5 35511 #define GEN9_3DSTATE_GS_VertexURBEntryOutputLength_bits 5 35512 #define GEN8_3DSTATE_GS_VertexURBEntryOutputLength_bits 5 35513 35514 static inline uint32_t ATTRIBUTE_PURE 35515 _3DSTATE_GS_VertexURBEntryOutputLength_bits(const struct gen_device_info *devinfo) 35516 { 35517 switch (devinfo->gen) { 35518 case 10: return 5; 35519 case 9: return 5; 35520 case 8: return 5; 35521 case 7: 35522 if (devinfo->is_haswell) { 35523 return 0; 35524 } else { 35525 return 0; 35526 } 35527 case 6: return 0; 35528 case 5: return 0; 35529 case 4: 35530 if (devinfo->is_g4x) { 35531 return 0; 35532 } else { 35533 return 0; 35534 } 35535 default: 35536 unreachable("Invalid hardware generation"); 35537 } 35538 } 35539 35540 35541 35542 #define GEN10_3DSTATE_GS_VertexURBEntryOutputLength_start 304 35543 #define GEN9_3DSTATE_GS_VertexURBEntryOutputLength_start 304 35544 #define GEN8_3DSTATE_GS_VertexURBEntryOutputLength_start 304 35545 35546 static inline uint32_t ATTRIBUTE_PURE 35547 _3DSTATE_GS_VertexURBEntryOutputLength_start(const struct gen_device_info *devinfo) 35548 { 35549 switch (devinfo->gen) { 35550 case 10: return 304; 35551 case 9: return 304; 35552 case 8: return 304; 35553 case 7: 35554 if (devinfo->is_haswell) { 35555 return 0; 35556 } else { 35557 return 0; 35558 } 35559 case 6: return 0; 35560 case 5: return 0; 35561 case 4: 35562 if (devinfo->is_g4x) { 35563 return 0; 35564 } else { 35565 return 0; 35566 } 35567 default: 35568 unreachable("Invalid hardware generation"); 35569 } 35570 } 35571 35572 35573 35574 /* 3DSTATE_GS::Vertex URB Entry Output Read Offset */ 35575 35576 35577 #define GEN10_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits 6 35578 #define GEN9_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits 6 35579 #define GEN8_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits 6 35580 35581 static inline uint32_t ATTRIBUTE_PURE 35582 _3DSTATE_GS_VertexURBEntryOutputReadOffset_bits(const struct gen_device_info *devinfo) 35583 { 35584 switch (devinfo->gen) { 35585 case 10: return 6; 35586 case 9: return 6; 35587 case 8: return 6; 35588 case 7: 35589 if (devinfo->is_haswell) { 35590 return 0; 35591 } else { 35592 return 0; 35593 } 35594 case 6: return 0; 35595 case 5: return 0; 35596 case 4: 35597 if (devinfo->is_g4x) { 35598 return 0; 35599 } else { 35600 return 0; 35601 } 35602 default: 35603 unreachable("Invalid hardware generation"); 35604 } 35605 } 35606 35607 35608 35609 #define GEN10_3DSTATE_GS_VertexURBEntryOutputReadOffset_start 309 35610 #define GEN9_3DSTATE_GS_VertexURBEntryOutputReadOffset_start 309 35611 #define GEN8_3DSTATE_GS_VertexURBEntryOutputReadOffset_start 309 35612 35613 static inline uint32_t ATTRIBUTE_PURE 35614 _3DSTATE_GS_VertexURBEntryOutputReadOffset_start(const struct gen_device_info *devinfo) 35615 { 35616 switch (devinfo->gen) { 35617 case 10: return 309; 35618 case 9: return 309; 35619 case 8: return 309; 35620 case 7: 35621 if (devinfo->is_haswell) { 35622 return 0; 35623 } else { 35624 return 0; 35625 } 35626 case 6: return 0; 35627 case 5: return 0; 35628 case 4: 35629 if (devinfo->is_g4x) { 35630 return 0; 35631 } else { 35632 return 0; 35633 } 35634 default: 35635 unreachable("Invalid hardware generation"); 35636 } 35637 } 35638 35639 35640 35641 /* 3DSTATE_GS::Vertex URB Entry Read Length */ 35642 35643 35644 #define GEN10_3DSTATE_GS_VertexURBEntryReadLength_bits 6 35645 #define GEN9_3DSTATE_GS_VertexURBEntryReadLength_bits 6 35646 #define GEN8_3DSTATE_GS_VertexURBEntryReadLength_bits 6 35647 #define GEN75_3DSTATE_GS_VertexURBEntryReadLength_bits 6 35648 #define GEN7_3DSTATE_GS_VertexURBEntryReadLength_bits 6 35649 #define GEN6_3DSTATE_GS_VertexURBEntryReadLength_bits 6 35650 35651 static inline uint32_t ATTRIBUTE_PURE 35652 _3DSTATE_GS_VertexURBEntryReadLength_bits(const struct gen_device_info *devinfo) 35653 { 35654 switch (devinfo->gen) { 35655 case 10: return 6; 35656 case 9: return 6; 35657 case 8: return 6; 35658 case 7: 35659 if (devinfo->is_haswell) { 35660 return 6; 35661 } else { 35662 return 6; 35663 } 35664 case 6: return 6; 35665 case 5: return 0; 35666 case 4: 35667 if (devinfo->is_g4x) { 35668 return 0; 35669 } else { 35670 return 0; 35671 } 35672 default: 35673 unreachable("Invalid hardware generation"); 35674 } 35675 } 35676 35677 35678 35679 #define GEN10_3DSTATE_GS_VertexURBEntryReadLength_start 203 35680 #define GEN9_3DSTATE_GS_VertexURBEntryReadLength_start 203 35681 #define GEN8_3DSTATE_GS_VertexURBEntryReadLength_start 203 35682 #define GEN75_3DSTATE_GS_VertexURBEntryReadLength_start 139 35683 #define GEN7_3DSTATE_GS_VertexURBEntryReadLength_start 139 35684 #define GEN6_3DSTATE_GS_VertexURBEntryReadLength_start 139 35685 35686 static inline uint32_t ATTRIBUTE_PURE 35687 _3DSTATE_GS_VertexURBEntryReadLength_start(const struct gen_device_info *devinfo) 35688 { 35689 switch (devinfo->gen) { 35690 case 10: return 203; 35691 case 9: return 203; 35692 case 8: return 203; 35693 case 7: 35694 if (devinfo->is_haswell) { 35695 return 139; 35696 } else { 35697 return 139; 35698 } 35699 case 6: return 139; 35700 case 5: return 0; 35701 case 4: 35702 if (devinfo->is_g4x) { 35703 return 0; 35704 } else { 35705 return 0; 35706 } 35707 default: 35708 unreachable("Invalid hardware generation"); 35709 } 35710 } 35711 35712 35713 35714 /* 3DSTATE_GS::Vertex URB Entry Read Offset */ 35715 35716 35717 #define GEN10_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 35718 #define GEN9_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 35719 #define GEN8_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 35720 #define GEN75_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 35721 #define GEN7_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 35722 #define GEN6_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 35723 35724 static inline uint32_t ATTRIBUTE_PURE 35725 _3DSTATE_GS_VertexURBEntryReadOffset_bits(const struct gen_device_info *devinfo) 35726 { 35727 switch (devinfo->gen) { 35728 case 10: return 6; 35729 case 9: return 6; 35730 case 8: return 6; 35731 case 7: 35732 if (devinfo->is_haswell) { 35733 return 6; 35734 } else { 35735 return 6; 35736 } 35737 case 6: return 6; 35738 case 5: return 0; 35739 case 4: 35740 if (devinfo->is_g4x) { 35741 return 0; 35742 } else { 35743 return 0; 35744 } 35745 default: 35746 unreachable("Invalid hardware generation"); 35747 } 35748 } 35749 35750 35751 35752 #define GEN10_3DSTATE_GS_VertexURBEntryReadOffset_start 196 35753 #define GEN9_3DSTATE_GS_VertexURBEntryReadOffset_start 196 35754 #define GEN8_3DSTATE_GS_VertexURBEntryReadOffset_start 196 35755 #define GEN75_3DSTATE_GS_VertexURBEntryReadOffset_start 132 35756 #define GEN7_3DSTATE_GS_VertexURBEntryReadOffset_start 132 35757 #define GEN6_3DSTATE_GS_VertexURBEntryReadOffset_start 132 35758 35759 static inline uint32_t ATTRIBUTE_PURE 35760 _3DSTATE_GS_VertexURBEntryReadOffset_start(const struct gen_device_info *devinfo) 35761 { 35762 switch (devinfo->gen) { 35763 case 10: return 196; 35764 case 9: return 196; 35765 case 8: return 196; 35766 case 7: 35767 if (devinfo->is_haswell) { 35768 return 132; 35769 } else { 35770 return 132; 35771 } 35772 case 6: return 132; 35773 case 5: return 0; 35774 case 4: 35775 if (devinfo->is_g4x) { 35776 return 0; 35777 } else { 35778 return 0; 35779 } 35780 default: 35781 unreachable("Invalid hardware generation"); 35782 } 35783 } 35784 35785 35786 35787 /* 3DSTATE_GS_SVB_INDEX */ 35788 35789 35790 #define GEN6_3DSTATE_GS_SVB_INDEX_length 7 35791 35792 static inline uint32_t ATTRIBUTE_PURE 35793 _3DSTATE_GS_SVB_INDEX_length(const struct gen_device_info *devinfo) 35794 { 35795 switch (devinfo->gen) { 35796 case 10: return 0; 35797 case 9: return 0; 35798 case 8: return 0; 35799 case 7: 35800 if (devinfo->is_haswell) { 35801 return 0; 35802 } else { 35803 return 0; 35804 } 35805 case 6: return 7; 35806 case 5: return 0; 35807 case 4: 35808 if (devinfo->is_g4x) { 35809 return 0; 35810 } else { 35811 return 0; 35812 } 35813 default: 35814 unreachable("Invalid hardware generation"); 35815 } 35816 } 35817 35818 35819 35820 /* 3DSTATE_GS_SVB_INDEX::3D Command Opcode */ 35821 35822 35823 #define GEN6_3DSTATE_GS_SVB_INDEX_3DCommandOpcode_bits 3 35824 35825 static inline uint32_t ATTRIBUTE_PURE 35826 _3DSTATE_GS_SVB_INDEX_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 35827 { 35828 switch (devinfo->gen) { 35829 case 10: return 0; 35830 case 9: return 0; 35831 case 8: return 0; 35832 case 7: 35833 if (devinfo->is_haswell) { 35834 return 0; 35835 } else { 35836 return 0; 35837 } 35838 case 6: return 3; 35839 case 5: return 0; 35840 case 4: 35841 if (devinfo->is_g4x) { 35842 return 0; 35843 } else { 35844 return 0; 35845 } 35846 default: 35847 unreachable("Invalid hardware generation"); 35848 } 35849 } 35850 35851 35852 35853 #define GEN6_3DSTATE_GS_SVB_INDEX_3DCommandOpcode_start 24 35854 35855 static inline uint32_t ATTRIBUTE_PURE 35856 _3DSTATE_GS_SVB_INDEX_3DCommandOpcode_start(const struct gen_device_info *devinfo) 35857 { 35858 switch (devinfo->gen) { 35859 case 10: return 0; 35860 case 9: return 0; 35861 case 8: return 0; 35862 case 7: 35863 if (devinfo->is_haswell) { 35864 return 0; 35865 } else { 35866 return 0; 35867 } 35868 case 6: return 24; 35869 case 5: return 0; 35870 case 4: 35871 if (devinfo->is_g4x) { 35872 return 0; 35873 } else { 35874 return 0; 35875 } 35876 default: 35877 unreachable("Invalid hardware generation"); 35878 } 35879 } 35880 35881 35882 35883 /* 3DSTATE_GS_SVB_INDEX::3D Command Sub Opcode */ 35884 35885 35886 #define GEN6_3DSTATE_GS_SVB_INDEX_3DCommandSubOpcode_bits 8 35887 35888 static inline uint32_t ATTRIBUTE_PURE 35889 _3DSTATE_GS_SVB_INDEX_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 35890 { 35891 switch (devinfo->gen) { 35892 case 10: return 0; 35893 case 9: return 0; 35894 case 8: return 0; 35895 case 7: 35896 if (devinfo->is_haswell) { 35897 return 0; 35898 } else { 35899 return 0; 35900 } 35901 case 6: return 8; 35902 case 5: return 0; 35903 case 4: 35904 if (devinfo->is_g4x) { 35905 return 0; 35906 } else { 35907 return 0; 35908 } 35909 default: 35910 unreachable("Invalid hardware generation"); 35911 } 35912 } 35913 35914 35915 35916 #define GEN6_3DSTATE_GS_SVB_INDEX_3DCommandSubOpcode_start 16 35917 35918 static inline uint32_t ATTRIBUTE_PURE 35919 _3DSTATE_GS_SVB_INDEX_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 35920 { 35921 switch (devinfo->gen) { 35922 case 10: return 0; 35923 case 9: return 0; 35924 case 8: return 0; 35925 case 7: 35926 if (devinfo->is_haswell) { 35927 return 0; 35928 } else { 35929 return 0; 35930 } 35931 case 6: return 16; 35932 case 5: return 0; 35933 case 4: 35934 if (devinfo->is_g4x) { 35935 return 0; 35936 } else { 35937 return 0; 35938 } 35939 default: 35940 unreachable("Invalid hardware generation"); 35941 } 35942 } 35943 35944 35945 35946 /* 3DSTATE_GS_SVB_INDEX::Command SubType */ 35947 35948 35949 #define GEN6_3DSTATE_GS_SVB_INDEX_CommandSubType_bits 2 35950 35951 static inline uint32_t ATTRIBUTE_PURE 35952 _3DSTATE_GS_SVB_INDEX_CommandSubType_bits(const struct gen_device_info *devinfo) 35953 { 35954 switch (devinfo->gen) { 35955 case 10: return 0; 35956 case 9: return 0; 35957 case 8: return 0; 35958 case 7: 35959 if (devinfo->is_haswell) { 35960 return 0; 35961 } else { 35962 return 0; 35963 } 35964 case 6: return 2; 35965 case 5: return 0; 35966 case 4: 35967 if (devinfo->is_g4x) { 35968 return 0; 35969 } else { 35970 return 0; 35971 } 35972 default: 35973 unreachable("Invalid hardware generation"); 35974 } 35975 } 35976 35977 35978 35979 #define GEN6_3DSTATE_GS_SVB_INDEX_CommandSubType_start 27 35980 35981 static inline uint32_t ATTRIBUTE_PURE 35982 _3DSTATE_GS_SVB_INDEX_CommandSubType_start(const struct gen_device_info *devinfo) 35983 { 35984 switch (devinfo->gen) { 35985 case 10: return 0; 35986 case 9: return 0; 35987 case 8: return 0; 35988 case 7: 35989 if (devinfo->is_haswell) { 35990 return 0; 35991 } else { 35992 return 0; 35993 } 35994 case 6: return 27; 35995 case 5: return 0; 35996 case 4: 35997 if (devinfo->is_g4x) { 35998 return 0; 35999 } else { 36000 return 0; 36001 } 36002 default: 36003 unreachable("Invalid hardware generation"); 36004 } 36005 } 36006 36007 36008 36009 /* 3DSTATE_GS_SVB_INDEX::Command Type */ 36010 36011 36012 #define GEN6_3DSTATE_GS_SVB_INDEX_CommandType_bits 3 36013 36014 static inline uint32_t ATTRIBUTE_PURE 36015 _3DSTATE_GS_SVB_INDEX_CommandType_bits(const struct gen_device_info *devinfo) 36016 { 36017 switch (devinfo->gen) { 36018 case 10: return 0; 36019 case 9: return 0; 36020 case 8: return 0; 36021 case 7: 36022 if (devinfo->is_haswell) { 36023 return 0; 36024 } else { 36025 return 0; 36026 } 36027 case 6: return 3; 36028 case 5: return 0; 36029 case 4: 36030 if (devinfo->is_g4x) { 36031 return 0; 36032 } else { 36033 return 0; 36034 } 36035 default: 36036 unreachable("Invalid hardware generation"); 36037 } 36038 } 36039 36040 36041 36042 #define GEN6_3DSTATE_GS_SVB_INDEX_CommandType_start 29 36043 36044 static inline uint32_t ATTRIBUTE_PURE 36045 _3DSTATE_GS_SVB_INDEX_CommandType_start(const struct gen_device_info *devinfo) 36046 { 36047 switch (devinfo->gen) { 36048 case 10: return 0; 36049 case 9: return 0; 36050 case 8: return 0; 36051 case 7: 36052 if (devinfo->is_haswell) { 36053 return 0; 36054 } else { 36055 return 0; 36056 } 36057 case 6: return 29; 36058 case 5: return 0; 36059 case 4: 36060 if (devinfo->is_g4x) { 36061 return 0; 36062 } else { 36063 return 0; 36064 } 36065 default: 36066 unreachable("Invalid hardware generation"); 36067 } 36068 } 36069 36070 36071 36072 /* 3DSTATE_GS_SVB_INDEX::DWord Length */ 36073 36074 36075 #define GEN6_3DSTATE_GS_SVB_INDEX_DWordLength_bits 8 36076 36077 static inline uint32_t ATTRIBUTE_PURE 36078 _3DSTATE_GS_SVB_INDEX_DWordLength_bits(const struct gen_device_info *devinfo) 36079 { 36080 switch (devinfo->gen) { 36081 case 10: return 0; 36082 case 9: return 0; 36083 case 8: return 0; 36084 case 7: 36085 if (devinfo->is_haswell) { 36086 return 0; 36087 } else { 36088 return 0; 36089 } 36090 case 6: return 8; 36091 case 5: return 0; 36092 case 4: 36093 if (devinfo->is_g4x) { 36094 return 0; 36095 } else { 36096 return 0; 36097 } 36098 default: 36099 unreachable("Invalid hardware generation"); 36100 } 36101 } 36102 36103 36104 36105 #define GEN6_3DSTATE_GS_SVB_INDEX_DWordLength_start 0 36106 36107 static inline uint32_t ATTRIBUTE_PURE 36108 _3DSTATE_GS_SVB_INDEX_DWordLength_start(const struct gen_device_info *devinfo) 36109 { 36110 switch (devinfo->gen) { 36111 case 10: return 0; 36112 case 9: return 0; 36113 case 8: return 0; 36114 case 7: 36115 if (devinfo->is_haswell) { 36116 return 0; 36117 } else { 36118 return 0; 36119 } 36120 case 6: return 0; 36121 case 5: return 0; 36122 case 4: 36123 if (devinfo->is_g4x) { 36124 return 0; 36125 } else { 36126 return 0; 36127 } 36128 default: 36129 unreachable("Invalid hardware generation"); 36130 } 36131 } 36132 36133 36134 36135 /* 3DSTATE_GS_SVB_INDEX::Index Number */ 36136 36137 36138 #define GEN6_3DSTATE_GS_SVB_INDEX_IndexNumber_bits 2 36139 36140 static inline uint32_t ATTRIBUTE_PURE 36141 _3DSTATE_GS_SVB_INDEX_IndexNumber_bits(const struct gen_device_info *devinfo) 36142 { 36143 switch (devinfo->gen) { 36144 case 10: return 0; 36145 case 9: return 0; 36146 case 8: return 0; 36147 case 7: 36148 if (devinfo->is_haswell) { 36149 return 0; 36150 } else { 36151 return 0; 36152 } 36153 case 6: return 2; 36154 case 5: return 0; 36155 case 4: 36156 if (devinfo->is_g4x) { 36157 return 0; 36158 } else { 36159 return 0; 36160 } 36161 default: 36162 unreachable("Invalid hardware generation"); 36163 } 36164 } 36165 36166 36167 36168 #define GEN6_3DSTATE_GS_SVB_INDEX_IndexNumber_start 61 36169 36170 static inline uint32_t ATTRIBUTE_PURE 36171 _3DSTATE_GS_SVB_INDEX_IndexNumber_start(const struct gen_device_info *devinfo) 36172 { 36173 switch (devinfo->gen) { 36174 case 10: return 0; 36175 case 9: return 0; 36176 case 8: return 0; 36177 case 7: 36178 if (devinfo->is_haswell) { 36179 return 0; 36180 } else { 36181 return 0; 36182 } 36183 case 6: return 61; 36184 case 5: return 0; 36185 case 4: 36186 if (devinfo->is_g4x) { 36187 return 0; 36188 } else { 36189 return 0; 36190 } 36191 default: 36192 unreachable("Invalid hardware generation"); 36193 } 36194 } 36195 36196 36197 36198 /* 3DSTATE_GS_SVB_INDEX::Load Internal Vertex Count */ 36199 36200 36201 #define GEN6_3DSTATE_GS_SVB_INDEX_LoadInternalVertexCount_bits 1 36202 36203 static inline uint32_t ATTRIBUTE_PURE 36204 _3DSTATE_GS_SVB_INDEX_LoadInternalVertexCount_bits(const struct gen_device_info *devinfo) 36205 { 36206 switch (devinfo->gen) { 36207 case 10: return 0; 36208 case 9: return 0; 36209 case 8: return 0; 36210 case 7: 36211 if (devinfo->is_haswell) { 36212 return 0; 36213 } else { 36214 return 0; 36215 } 36216 case 6: return 1; 36217 case 5: return 0; 36218 case 4: 36219 if (devinfo->is_g4x) { 36220 return 0; 36221 } else { 36222 return 0; 36223 } 36224 default: 36225 unreachable("Invalid hardware generation"); 36226 } 36227 } 36228 36229 36230 36231 #define GEN6_3DSTATE_GS_SVB_INDEX_LoadInternalVertexCount_start 32 36232 36233 static inline uint32_t ATTRIBUTE_PURE 36234 _3DSTATE_GS_SVB_INDEX_LoadInternalVertexCount_start(const struct gen_device_info *devinfo) 36235 { 36236 switch (devinfo->gen) { 36237 case 10: return 0; 36238 case 9: return 0; 36239 case 8: return 0; 36240 case 7: 36241 if (devinfo->is_haswell) { 36242 return 0; 36243 } else { 36244 return 0; 36245 } 36246 case 6: return 32; 36247 case 5: return 0; 36248 case 4: 36249 if (devinfo->is_g4x) { 36250 return 0; 36251 } else { 36252 return 0; 36253 } 36254 default: 36255 unreachable("Invalid hardware generation"); 36256 } 36257 } 36258 36259 36260 36261 /* 3DSTATE_GS_SVB_INDEX::Maximum Index */ 36262 36263 36264 #define GEN6_3DSTATE_GS_SVB_INDEX_MaximumIndex_bits 32 36265 36266 static inline uint32_t ATTRIBUTE_PURE 36267 _3DSTATE_GS_SVB_INDEX_MaximumIndex_bits(const struct gen_device_info *devinfo) 36268 { 36269 switch (devinfo->gen) { 36270 case 10: return 0; 36271 case 9: return 0; 36272 case 8: return 0; 36273 case 7: 36274 if (devinfo->is_haswell) { 36275 return 0; 36276 } else { 36277 return 0; 36278 } 36279 case 6: return 32; 36280 case 5: return 0; 36281 case 4: 36282 if (devinfo->is_g4x) { 36283 return 0; 36284 } else { 36285 return 0; 36286 } 36287 default: 36288 unreachable("Invalid hardware generation"); 36289 } 36290 } 36291 36292 36293 36294 #define GEN6_3DSTATE_GS_SVB_INDEX_MaximumIndex_start 96 36295 36296 static inline uint32_t ATTRIBUTE_PURE 36297 _3DSTATE_GS_SVB_INDEX_MaximumIndex_start(const struct gen_device_info *devinfo) 36298 { 36299 switch (devinfo->gen) { 36300 case 10: return 0; 36301 case 9: return 0; 36302 case 8: return 0; 36303 case 7: 36304 if (devinfo->is_haswell) { 36305 return 0; 36306 } else { 36307 return 0; 36308 } 36309 case 6: return 96; 36310 case 5: return 0; 36311 case 4: 36312 if (devinfo->is_g4x) { 36313 return 0; 36314 } else { 36315 return 0; 36316 } 36317 default: 36318 unreachable("Invalid hardware generation"); 36319 } 36320 } 36321 36322 36323 36324 /* 3DSTATE_GS_SVB_INDEX::Streamed Vertex Buffer Index */ 36325 36326 36327 #define GEN6_3DSTATE_GS_SVB_INDEX_StreamedVertexBufferIndex_bits 32 36328 36329 static inline uint32_t ATTRIBUTE_PURE 36330 _3DSTATE_GS_SVB_INDEX_StreamedVertexBufferIndex_bits(const struct gen_device_info *devinfo) 36331 { 36332 switch (devinfo->gen) { 36333 case 10: return 0; 36334 case 9: return 0; 36335 case 8: return 0; 36336 case 7: 36337 if (devinfo->is_haswell) { 36338 return 0; 36339 } else { 36340 return 0; 36341 } 36342 case 6: return 32; 36343 case 5: return 0; 36344 case 4: 36345 if (devinfo->is_g4x) { 36346 return 0; 36347 } else { 36348 return 0; 36349 } 36350 default: 36351 unreachable("Invalid hardware generation"); 36352 } 36353 } 36354 36355 36356 36357 #define GEN6_3DSTATE_GS_SVB_INDEX_StreamedVertexBufferIndex_start 64 36358 36359 static inline uint32_t ATTRIBUTE_PURE 36360 _3DSTATE_GS_SVB_INDEX_StreamedVertexBufferIndex_start(const struct gen_device_info *devinfo) 36361 { 36362 switch (devinfo->gen) { 36363 case 10: return 0; 36364 case 9: return 0; 36365 case 8: return 0; 36366 case 7: 36367 if (devinfo->is_haswell) { 36368 return 0; 36369 } else { 36370 return 0; 36371 } 36372 case 6: return 64; 36373 case 5: return 0; 36374 case 4: 36375 if (devinfo->is_g4x) { 36376 return 0; 36377 } else { 36378 return 0; 36379 } 36380 default: 36381 unreachable("Invalid hardware generation"); 36382 } 36383 } 36384 36385 36386 36387 /* 3DSTATE_HIER_DEPTH_BUFFER */ 36388 36389 36390 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_length 5 36391 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_length 5 36392 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_length 5 36393 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_length 3 36394 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_length 3 36395 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_length 3 36396 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_length 3 36397 36398 static inline uint32_t ATTRIBUTE_PURE 36399 _3DSTATE_HIER_DEPTH_BUFFER_length(const struct gen_device_info *devinfo) 36400 { 36401 switch (devinfo->gen) { 36402 case 10: return 5; 36403 case 9: return 5; 36404 case 8: return 5; 36405 case 7: 36406 if (devinfo->is_haswell) { 36407 return 3; 36408 } else { 36409 return 3; 36410 } 36411 case 6: return 3; 36412 case 5: return 3; 36413 case 4: 36414 if (devinfo->is_g4x) { 36415 return 0; 36416 } else { 36417 return 0; 36418 } 36419 default: 36420 unreachable("Invalid hardware generation"); 36421 } 36422 } 36423 36424 36425 36426 /* 3DSTATE_HIER_DEPTH_BUFFER::3D Command Opcode */ 36427 36428 36429 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 36430 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 36431 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 36432 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 36433 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 36434 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 36435 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 36436 36437 static inline uint32_t ATTRIBUTE_PURE 36438 _3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 36439 { 36440 switch (devinfo->gen) { 36441 case 10: return 3; 36442 case 9: return 3; 36443 case 8: return 3; 36444 case 7: 36445 if (devinfo->is_haswell) { 36446 return 3; 36447 } else { 36448 return 3; 36449 } 36450 case 6: return 3; 36451 case 5: return 3; 36452 case 4: 36453 if (devinfo->is_g4x) { 36454 return 0; 36455 } else { 36456 return 0; 36457 } 36458 default: 36459 unreachable("Invalid hardware generation"); 36460 } 36461 } 36462 36463 36464 36465 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 36466 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 36467 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 36468 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 36469 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 36470 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 36471 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 36472 36473 static inline uint32_t ATTRIBUTE_PURE 36474 _3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start(const struct gen_device_info *devinfo) 36475 { 36476 switch (devinfo->gen) { 36477 case 10: return 24; 36478 case 9: return 24; 36479 case 8: return 24; 36480 case 7: 36481 if (devinfo->is_haswell) { 36482 return 24; 36483 } else { 36484 return 24; 36485 } 36486 case 6: return 24; 36487 case 5: return 24; 36488 case 4: 36489 if (devinfo->is_g4x) { 36490 return 0; 36491 } else { 36492 return 0; 36493 } 36494 default: 36495 unreachable("Invalid hardware generation"); 36496 } 36497 } 36498 36499 36500 36501 /* 3DSTATE_HIER_DEPTH_BUFFER::3D Command Sub Opcode */ 36502 36503 36504 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 36505 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 36506 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 36507 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 36508 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 36509 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 36510 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 36511 36512 static inline uint32_t ATTRIBUTE_PURE 36513 _3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 36514 { 36515 switch (devinfo->gen) { 36516 case 10: return 8; 36517 case 9: return 8; 36518 case 8: return 8; 36519 case 7: 36520 if (devinfo->is_haswell) { 36521 return 8; 36522 } else { 36523 return 8; 36524 } 36525 case 6: return 8; 36526 case 5: return 8; 36527 case 4: 36528 if (devinfo->is_g4x) { 36529 return 0; 36530 } else { 36531 return 0; 36532 } 36533 default: 36534 unreachable("Invalid hardware generation"); 36535 } 36536 } 36537 36538 36539 36540 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 36541 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 36542 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 36543 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 36544 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 36545 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 36546 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 36547 36548 static inline uint32_t ATTRIBUTE_PURE 36549 _3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 36550 { 36551 switch (devinfo->gen) { 36552 case 10: return 16; 36553 case 9: return 16; 36554 case 8: return 16; 36555 case 7: 36556 if (devinfo->is_haswell) { 36557 return 16; 36558 } else { 36559 return 16; 36560 } 36561 case 6: return 16; 36562 case 5: return 16; 36563 case 4: 36564 if (devinfo->is_g4x) { 36565 return 0; 36566 } else { 36567 return 0; 36568 } 36569 default: 36570 unreachable("Invalid hardware generation"); 36571 } 36572 } 36573 36574 36575 36576 /* 3DSTATE_HIER_DEPTH_BUFFER::Command SubType */ 36577 36578 36579 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 36580 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 36581 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 36582 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 36583 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 36584 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 36585 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 36586 36587 static inline uint32_t ATTRIBUTE_PURE 36588 _3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits(const struct gen_device_info *devinfo) 36589 { 36590 switch (devinfo->gen) { 36591 case 10: return 2; 36592 case 9: return 2; 36593 case 8: return 2; 36594 case 7: 36595 if (devinfo->is_haswell) { 36596 return 2; 36597 } else { 36598 return 2; 36599 } 36600 case 6: return 2; 36601 case 5: return 2; 36602 case 4: 36603 if (devinfo->is_g4x) { 36604 return 0; 36605 } else { 36606 return 0; 36607 } 36608 default: 36609 unreachable("Invalid hardware generation"); 36610 } 36611 } 36612 36613 36614 36615 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 36616 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 36617 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 36618 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 36619 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 36620 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 36621 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 36622 36623 static inline uint32_t ATTRIBUTE_PURE 36624 _3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start(const struct gen_device_info *devinfo) 36625 { 36626 switch (devinfo->gen) { 36627 case 10: return 27; 36628 case 9: return 27; 36629 case 8: return 27; 36630 case 7: 36631 if (devinfo->is_haswell) { 36632 return 27; 36633 } else { 36634 return 27; 36635 } 36636 case 6: return 27; 36637 case 5: return 27; 36638 case 4: 36639 if (devinfo->is_g4x) { 36640 return 0; 36641 } else { 36642 return 0; 36643 } 36644 default: 36645 unreachable("Invalid hardware generation"); 36646 } 36647 } 36648 36649 36650 36651 /* 3DSTATE_HIER_DEPTH_BUFFER::Command Type */ 36652 36653 36654 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 36655 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 36656 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 36657 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 36658 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 36659 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 36660 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 36661 36662 static inline uint32_t ATTRIBUTE_PURE 36663 _3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits(const struct gen_device_info *devinfo) 36664 { 36665 switch (devinfo->gen) { 36666 case 10: return 3; 36667 case 9: return 3; 36668 case 8: return 3; 36669 case 7: 36670 if (devinfo->is_haswell) { 36671 return 3; 36672 } else { 36673 return 3; 36674 } 36675 case 6: return 3; 36676 case 5: return 3; 36677 case 4: 36678 if (devinfo->is_g4x) { 36679 return 0; 36680 } else { 36681 return 0; 36682 } 36683 default: 36684 unreachable("Invalid hardware generation"); 36685 } 36686 } 36687 36688 36689 36690 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 36691 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 36692 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 36693 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 36694 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 36695 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 36696 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 36697 36698 static inline uint32_t ATTRIBUTE_PURE 36699 _3DSTATE_HIER_DEPTH_BUFFER_CommandType_start(const struct gen_device_info *devinfo) 36700 { 36701 switch (devinfo->gen) { 36702 case 10: return 29; 36703 case 9: return 29; 36704 case 8: return 29; 36705 case 7: 36706 if (devinfo->is_haswell) { 36707 return 29; 36708 } else { 36709 return 29; 36710 } 36711 case 6: return 29; 36712 case 5: return 29; 36713 case 4: 36714 if (devinfo->is_g4x) { 36715 return 0; 36716 } else { 36717 return 0; 36718 } 36719 default: 36720 unreachable("Invalid hardware generation"); 36721 } 36722 } 36723 36724 36725 36726 /* 3DSTATE_HIER_DEPTH_BUFFER::DWord Length */ 36727 36728 36729 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 36730 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 36731 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 36732 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 36733 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 36734 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 36735 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 36736 36737 static inline uint32_t ATTRIBUTE_PURE 36738 _3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits(const struct gen_device_info *devinfo) 36739 { 36740 switch (devinfo->gen) { 36741 case 10: return 8; 36742 case 9: return 8; 36743 case 8: return 8; 36744 case 7: 36745 if (devinfo->is_haswell) { 36746 return 8; 36747 } else { 36748 return 8; 36749 } 36750 case 6: return 8; 36751 case 5: return 8; 36752 case 4: 36753 if (devinfo->is_g4x) { 36754 return 0; 36755 } else { 36756 return 0; 36757 } 36758 default: 36759 unreachable("Invalid hardware generation"); 36760 } 36761 } 36762 36763 36764 36765 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 36766 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 36767 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 36768 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 36769 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 36770 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 36771 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 36772 36773 static inline uint32_t ATTRIBUTE_PURE 36774 _3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start(const struct gen_device_info *devinfo) 36775 { 36776 switch (devinfo->gen) { 36777 case 10: return 0; 36778 case 9: return 0; 36779 case 8: return 0; 36780 case 7: 36781 if (devinfo->is_haswell) { 36782 return 0; 36783 } else { 36784 return 0; 36785 } 36786 case 6: return 0; 36787 case 5: return 0; 36788 case 4: 36789 if (devinfo->is_g4x) { 36790 return 0; 36791 } else { 36792 return 0; 36793 } 36794 default: 36795 unreachable("Invalid hardware generation"); 36796 } 36797 } 36798 36799 36800 36801 /* 3DSTATE_HIER_DEPTH_BUFFER::Hierarchical Depth Buffer MOCS */ 36802 36803 36804 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 7 36805 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 7 36806 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 7 36807 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 4 36808 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 4 36809 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 4 36810 36811 static inline uint32_t ATTRIBUTE_PURE 36812 _3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits(const struct gen_device_info *devinfo) 36813 { 36814 switch (devinfo->gen) { 36815 case 10: return 7; 36816 case 9: return 7; 36817 case 8: return 7; 36818 case 7: 36819 if (devinfo->is_haswell) { 36820 return 4; 36821 } else { 36822 return 4; 36823 } 36824 case 6: return 4; 36825 case 5: return 0; 36826 case 4: 36827 if (devinfo->is_g4x) { 36828 return 0; 36829 } else { 36830 return 0; 36831 } 36832 default: 36833 unreachable("Invalid hardware generation"); 36834 } 36835 } 36836 36837 36838 36839 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 36840 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 36841 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 36842 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 36843 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 36844 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 36845 36846 static inline uint32_t ATTRIBUTE_PURE 36847 _3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start(const struct gen_device_info *devinfo) 36848 { 36849 switch (devinfo->gen) { 36850 case 10: return 57; 36851 case 9: return 57; 36852 case 8: return 57; 36853 case 7: 36854 if (devinfo->is_haswell) { 36855 return 57; 36856 } else { 36857 return 57; 36858 } 36859 case 6: return 57; 36860 case 5: return 0; 36861 case 4: 36862 if (devinfo->is_g4x) { 36863 return 0; 36864 } else { 36865 return 0; 36866 } 36867 default: 36868 unreachable("Invalid hardware generation"); 36869 } 36870 } 36871 36872 36873 36874 /* 3DSTATE_HIER_DEPTH_BUFFER::Hierarchical Depth Buffer Object Control State */ 36875 36876 36877 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 7 36878 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 7 36879 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 7 36880 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 4 36881 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 4 36882 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 4 36883 36884 static inline uint32_t ATTRIBUTE_PURE 36885 _3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits(const struct gen_device_info *devinfo) 36886 { 36887 switch (devinfo->gen) { 36888 case 10: return 7; 36889 case 9: return 7; 36890 case 8: return 7; 36891 case 7: 36892 if (devinfo->is_haswell) { 36893 return 4; 36894 } else { 36895 return 4; 36896 } 36897 case 6: return 4; 36898 case 5: return 0; 36899 case 4: 36900 if (devinfo->is_g4x) { 36901 return 0; 36902 } else { 36903 return 0; 36904 } 36905 default: 36906 unreachable("Invalid hardware generation"); 36907 } 36908 } 36909 36910 36911 36912 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 36913 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 36914 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 36915 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 36916 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 36917 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 36918 36919 static inline uint32_t ATTRIBUTE_PURE 36920 _3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start(const struct gen_device_info *devinfo) 36921 { 36922 switch (devinfo->gen) { 36923 case 10: return 57; 36924 case 9: return 57; 36925 case 8: return 57; 36926 case 7: 36927 if (devinfo->is_haswell) { 36928 return 57; 36929 } else { 36930 return 57; 36931 } 36932 case 6: return 57; 36933 case 5: return 0; 36934 case 4: 36935 if (devinfo->is_g4x) { 36936 return 0; 36937 } else { 36938 return 0; 36939 } 36940 default: 36941 unreachable("Invalid hardware generation"); 36942 } 36943 } 36944 36945 36946 36947 /* 3DSTATE_HIER_DEPTH_BUFFER::Surface Base Address */ 36948 36949 36950 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 36951 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 36952 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 36953 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 36954 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 36955 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 36956 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 36957 36958 static inline uint32_t ATTRIBUTE_PURE 36959 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits(const struct gen_device_info *devinfo) 36960 { 36961 switch (devinfo->gen) { 36962 case 10: return 64; 36963 case 9: return 64; 36964 case 8: return 64; 36965 case 7: 36966 if (devinfo->is_haswell) { 36967 return 32; 36968 } else { 36969 return 32; 36970 } 36971 case 6: return 32; 36972 case 5: return 32; 36973 case 4: 36974 if (devinfo->is_g4x) { 36975 return 0; 36976 } else { 36977 return 0; 36978 } 36979 default: 36980 unreachable("Invalid hardware generation"); 36981 } 36982 } 36983 36984 36985 36986 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 36987 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 36988 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 36989 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 36990 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 36991 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 36992 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 36993 36994 static inline uint32_t ATTRIBUTE_PURE 36995 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(const struct gen_device_info *devinfo) 36996 { 36997 switch (devinfo->gen) { 36998 case 10: return 64; 36999 case 9: return 64; 37000 case 8: return 64; 37001 case 7: 37002 if (devinfo->is_haswell) { 37003 return 64; 37004 } else { 37005 return 64; 37006 } 37007 case 6: return 64; 37008 case 5: return 64; 37009 case 4: 37010 if (devinfo->is_g4x) { 37011 return 0; 37012 } else { 37013 return 0; 37014 } 37015 default: 37016 unreachable("Invalid hardware generation"); 37017 } 37018 } 37019 37020 37021 37022 /* 3DSTATE_HIER_DEPTH_BUFFER::Surface Pitch */ 37023 37024 37025 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 37026 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 37027 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 37028 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 37029 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 37030 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 37031 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 37032 37033 static inline uint32_t ATTRIBUTE_PURE 37034 _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(const struct gen_device_info *devinfo) 37035 { 37036 switch (devinfo->gen) { 37037 case 10: return 17; 37038 case 9: return 17; 37039 case 8: return 17; 37040 case 7: 37041 if (devinfo->is_haswell) { 37042 return 17; 37043 } else { 37044 return 17; 37045 } 37046 case 6: return 17; 37047 case 5: return 17; 37048 case 4: 37049 if (devinfo->is_g4x) { 37050 return 0; 37051 } else { 37052 return 0; 37053 } 37054 default: 37055 unreachable("Invalid hardware generation"); 37056 } 37057 } 37058 37059 37060 37061 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 37062 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 37063 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 37064 #define GEN75_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 37065 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 37066 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 37067 #define GEN5_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 37068 37069 static inline uint32_t ATTRIBUTE_PURE 37070 _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start(const struct gen_device_info *devinfo) 37071 { 37072 switch (devinfo->gen) { 37073 case 10: return 32; 37074 case 9: return 32; 37075 case 8: return 32; 37076 case 7: 37077 if (devinfo->is_haswell) { 37078 return 32; 37079 } else { 37080 return 32; 37081 } 37082 case 6: return 32; 37083 case 5: return 32; 37084 case 4: 37085 if (devinfo->is_g4x) { 37086 return 0; 37087 } else { 37088 return 0; 37089 } 37090 default: 37091 unreachable("Invalid hardware generation"); 37092 } 37093 } 37094 37095 37096 37097 /* 3DSTATE_HIER_DEPTH_BUFFER::Surface QPitch */ 37098 37099 37100 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits 15 37101 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits 15 37102 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits 15 37103 37104 static inline uint32_t ATTRIBUTE_PURE 37105 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits(const struct gen_device_info *devinfo) 37106 { 37107 switch (devinfo->gen) { 37108 case 10: return 15; 37109 case 9: return 15; 37110 case 8: return 15; 37111 case 7: 37112 if (devinfo->is_haswell) { 37113 return 0; 37114 } else { 37115 return 0; 37116 } 37117 case 6: return 0; 37118 case 5: return 0; 37119 case 4: 37120 if (devinfo->is_g4x) { 37121 return 0; 37122 } else { 37123 return 0; 37124 } 37125 default: 37126 unreachable("Invalid hardware generation"); 37127 } 37128 } 37129 37130 37131 37132 #define GEN10_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start 128 37133 #define GEN9_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start 128 37134 #define GEN8_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start 128 37135 37136 static inline uint32_t ATTRIBUTE_PURE 37137 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start(const struct gen_device_info *devinfo) 37138 { 37139 switch (devinfo->gen) { 37140 case 10: return 128; 37141 case 9: return 128; 37142 case 8: return 128; 37143 case 7: 37144 if (devinfo->is_haswell) { 37145 return 0; 37146 } else { 37147 return 0; 37148 } 37149 case 6: return 0; 37150 case 5: return 0; 37151 case 4: 37152 if (devinfo->is_g4x) { 37153 return 0; 37154 } else { 37155 return 0; 37156 } 37157 default: 37158 unreachable("Invalid hardware generation"); 37159 } 37160 } 37161 37162 37163 37164 /* 3DSTATE_HS */ 37165 37166 37167 #define GEN10_3DSTATE_HS_length 9 37168 #define GEN9_3DSTATE_HS_length 9 37169 #define GEN8_3DSTATE_HS_length 9 37170 #define GEN75_3DSTATE_HS_length 7 37171 #define GEN7_3DSTATE_HS_length 7 37172 37173 static inline uint32_t ATTRIBUTE_PURE 37174 _3DSTATE_HS_length(const struct gen_device_info *devinfo) 37175 { 37176 switch (devinfo->gen) { 37177 case 10: return 9; 37178 case 9: return 9; 37179 case 8: return 9; 37180 case 7: 37181 if (devinfo->is_haswell) { 37182 return 7; 37183 } else { 37184 return 7; 37185 } 37186 case 6: return 0; 37187 case 5: return 0; 37188 case 4: 37189 if (devinfo->is_g4x) { 37190 return 0; 37191 } else { 37192 return 0; 37193 } 37194 default: 37195 unreachable("Invalid hardware generation"); 37196 } 37197 } 37198 37199 37200 37201 /* 3DSTATE_HS::3D Command Opcode */ 37202 37203 37204 #define GEN10_3DSTATE_HS_3DCommandOpcode_bits 3 37205 #define GEN9_3DSTATE_HS_3DCommandOpcode_bits 3 37206 #define GEN8_3DSTATE_HS_3DCommandOpcode_bits 3 37207 #define GEN75_3DSTATE_HS_3DCommandOpcode_bits 3 37208 #define GEN7_3DSTATE_HS_3DCommandOpcode_bits 3 37209 37210 static inline uint32_t ATTRIBUTE_PURE 37211 _3DSTATE_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 37212 { 37213 switch (devinfo->gen) { 37214 case 10: return 3; 37215 case 9: return 3; 37216 case 8: return 3; 37217 case 7: 37218 if (devinfo->is_haswell) { 37219 return 3; 37220 } else { 37221 return 3; 37222 } 37223 case 6: return 0; 37224 case 5: return 0; 37225 case 4: 37226 if (devinfo->is_g4x) { 37227 return 0; 37228 } else { 37229 return 0; 37230 } 37231 default: 37232 unreachable("Invalid hardware generation"); 37233 } 37234 } 37235 37236 37237 37238 #define GEN10_3DSTATE_HS_3DCommandOpcode_start 24 37239 #define GEN9_3DSTATE_HS_3DCommandOpcode_start 24 37240 #define GEN8_3DSTATE_HS_3DCommandOpcode_start 24 37241 #define GEN75_3DSTATE_HS_3DCommandOpcode_start 24 37242 #define GEN7_3DSTATE_HS_3DCommandOpcode_start 24 37243 37244 static inline uint32_t ATTRIBUTE_PURE 37245 _3DSTATE_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) 37246 { 37247 switch (devinfo->gen) { 37248 case 10: return 24; 37249 case 9: return 24; 37250 case 8: return 24; 37251 case 7: 37252 if (devinfo->is_haswell) { 37253 return 24; 37254 } else { 37255 return 24; 37256 } 37257 case 6: return 0; 37258 case 5: return 0; 37259 case 4: 37260 if (devinfo->is_g4x) { 37261 return 0; 37262 } else { 37263 return 0; 37264 } 37265 default: 37266 unreachable("Invalid hardware generation"); 37267 } 37268 } 37269 37270 37271 37272 /* 3DSTATE_HS::3D Command Sub Opcode */ 37273 37274 37275 #define GEN10_3DSTATE_HS_3DCommandSubOpcode_bits 8 37276 #define GEN9_3DSTATE_HS_3DCommandSubOpcode_bits 8 37277 #define GEN8_3DSTATE_HS_3DCommandSubOpcode_bits 8 37278 #define GEN75_3DSTATE_HS_3DCommandSubOpcode_bits 8 37279 #define GEN7_3DSTATE_HS_3DCommandSubOpcode_bits 8 37280 37281 static inline uint32_t ATTRIBUTE_PURE 37282 _3DSTATE_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 37283 { 37284 switch (devinfo->gen) { 37285 case 10: return 8; 37286 case 9: return 8; 37287 case 8: return 8; 37288 case 7: 37289 if (devinfo->is_haswell) { 37290 return 8; 37291 } else { 37292 return 8; 37293 } 37294 case 6: return 0; 37295 case 5: return 0; 37296 case 4: 37297 if (devinfo->is_g4x) { 37298 return 0; 37299 } else { 37300 return 0; 37301 } 37302 default: 37303 unreachable("Invalid hardware generation"); 37304 } 37305 } 37306 37307 37308 37309 #define GEN10_3DSTATE_HS_3DCommandSubOpcode_start 16 37310 #define GEN9_3DSTATE_HS_3DCommandSubOpcode_start 16 37311 #define GEN8_3DSTATE_HS_3DCommandSubOpcode_start 16 37312 #define GEN75_3DSTATE_HS_3DCommandSubOpcode_start 16 37313 #define GEN7_3DSTATE_HS_3DCommandSubOpcode_start 16 37314 37315 static inline uint32_t ATTRIBUTE_PURE 37316 _3DSTATE_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 37317 { 37318 switch (devinfo->gen) { 37319 case 10: return 16; 37320 case 9: return 16; 37321 case 8: return 16; 37322 case 7: 37323 if (devinfo->is_haswell) { 37324 return 16; 37325 } else { 37326 return 16; 37327 } 37328 case 6: return 0; 37329 case 5: return 0; 37330 case 4: 37331 if (devinfo->is_g4x) { 37332 return 0; 37333 } else { 37334 return 0; 37335 } 37336 default: 37337 unreachable("Invalid hardware generation"); 37338 } 37339 } 37340 37341 37342 37343 /* 3DSTATE_HS::Accesses UAV */ 37344 37345 37346 #define GEN10_3DSTATE_HS_AccessesUAV_bits 1 37347 #define GEN9_3DSTATE_HS_AccessesUAV_bits 1 37348 #define GEN8_3DSTATE_HS_AccessesUAV_bits 1 37349 37350 static inline uint32_t ATTRIBUTE_PURE 37351 _3DSTATE_HS_AccessesUAV_bits(const struct gen_device_info *devinfo) 37352 { 37353 switch (devinfo->gen) { 37354 case 10: return 1; 37355 case 9: return 1; 37356 case 8: return 1; 37357 case 7: 37358 if (devinfo->is_haswell) { 37359 return 0; 37360 } else { 37361 return 0; 37362 } 37363 case 6: return 0; 37364 case 5: return 0; 37365 case 4: 37366 if (devinfo->is_g4x) { 37367 return 0; 37368 } else { 37369 return 0; 37370 } 37371 default: 37372 unreachable("Invalid hardware generation"); 37373 } 37374 } 37375 37376 37377 37378 #define GEN10_3DSTATE_HS_AccessesUAV_start 249 37379 #define GEN9_3DSTATE_HS_AccessesUAV_start 249 37380 #define GEN8_3DSTATE_HS_AccessesUAV_start 249 37381 37382 static inline uint32_t ATTRIBUTE_PURE 37383 _3DSTATE_HS_AccessesUAV_start(const struct gen_device_info *devinfo) 37384 { 37385 switch (devinfo->gen) { 37386 case 10: return 249; 37387 case 9: return 249; 37388 case 8: return 249; 37389 case 7: 37390 if (devinfo->is_haswell) { 37391 return 0; 37392 } else { 37393 return 0; 37394 } 37395 case 6: return 0; 37396 case 5: return 0; 37397 case 4: 37398 if (devinfo->is_g4x) { 37399 return 0; 37400 } else { 37401 return 0; 37402 } 37403 default: 37404 unreachable("Invalid hardware generation"); 37405 } 37406 } 37407 37408 37409 37410 /* 3DSTATE_HS::Binding Table Entry Count */ 37411 37412 37413 #define GEN10_3DSTATE_HS_BindingTableEntryCount_bits 8 37414 #define GEN9_3DSTATE_HS_BindingTableEntryCount_bits 8 37415 #define GEN8_3DSTATE_HS_BindingTableEntryCount_bits 8 37416 #define GEN75_3DSTATE_HS_BindingTableEntryCount_bits 8 37417 #define GEN7_3DSTATE_HS_BindingTableEntryCount_bits 8 37418 37419 static inline uint32_t ATTRIBUTE_PURE 37420 _3DSTATE_HS_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) 37421 { 37422 switch (devinfo->gen) { 37423 case 10: return 8; 37424 case 9: return 8; 37425 case 8: return 8; 37426 case 7: 37427 if (devinfo->is_haswell) { 37428 return 8; 37429 } else { 37430 return 8; 37431 } 37432 case 6: return 0; 37433 case 5: return 0; 37434 case 4: 37435 if (devinfo->is_g4x) { 37436 return 0; 37437 } else { 37438 return 0; 37439 } 37440 default: 37441 unreachable("Invalid hardware generation"); 37442 } 37443 } 37444 37445 37446 37447 #define GEN10_3DSTATE_HS_BindingTableEntryCount_start 50 37448 #define GEN9_3DSTATE_HS_BindingTableEntryCount_start 50 37449 #define GEN8_3DSTATE_HS_BindingTableEntryCount_start 50 37450 #define GEN75_3DSTATE_HS_BindingTableEntryCount_start 50 37451 #define GEN7_3DSTATE_HS_BindingTableEntryCount_start 50 37452 37453 static inline uint32_t ATTRIBUTE_PURE 37454 _3DSTATE_HS_BindingTableEntryCount_start(const struct gen_device_info *devinfo) 37455 { 37456 switch (devinfo->gen) { 37457 case 10: return 50; 37458 case 9: return 50; 37459 case 8: return 50; 37460 case 7: 37461 if (devinfo->is_haswell) { 37462 return 50; 37463 } else { 37464 return 50; 37465 } 37466 case 6: return 0; 37467 case 5: return 0; 37468 case 4: 37469 if (devinfo->is_g4x) { 37470 return 0; 37471 } else { 37472 return 0; 37473 } 37474 default: 37475 unreachable("Invalid hardware generation"); 37476 } 37477 } 37478 37479 37480 37481 /* 3DSTATE_HS::Command SubType */ 37482 37483 37484 #define GEN10_3DSTATE_HS_CommandSubType_bits 2 37485 #define GEN9_3DSTATE_HS_CommandSubType_bits 2 37486 #define GEN8_3DSTATE_HS_CommandSubType_bits 2 37487 #define GEN75_3DSTATE_HS_CommandSubType_bits 2 37488 #define GEN7_3DSTATE_HS_CommandSubType_bits 2 37489 37490 static inline uint32_t ATTRIBUTE_PURE 37491 _3DSTATE_HS_CommandSubType_bits(const struct gen_device_info *devinfo) 37492 { 37493 switch (devinfo->gen) { 37494 case 10: return 2; 37495 case 9: return 2; 37496 case 8: return 2; 37497 case 7: 37498 if (devinfo->is_haswell) { 37499 return 2; 37500 } else { 37501 return 2; 37502 } 37503 case 6: return 0; 37504 case 5: return 0; 37505 case 4: 37506 if (devinfo->is_g4x) { 37507 return 0; 37508 } else { 37509 return 0; 37510 } 37511 default: 37512 unreachable("Invalid hardware generation"); 37513 } 37514 } 37515 37516 37517 37518 #define GEN10_3DSTATE_HS_CommandSubType_start 27 37519 #define GEN9_3DSTATE_HS_CommandSubType_start 27 37520 #define GEN8_3DSTATE_HS_CommandSubType_start 27 37521 #define GEN75_3DSTATE_HS_CommandSubType_start 27 37522 #define GEN7_3DSTATE_HS_CommandSubType_start 27 37523 37524 static inline uint32_t ATTRIBUTE_PURE 37525 _3DSTATE_HS_CommandSubType_start(const struct gen_device_info *devinfo) 37526 { 37527 switch (devinfo->gen) { 37528 case 10: return 27; 37529 case 9: return 27; 37530 case 8: return 27; 37531 case 7: 37532 if (devinfo->is_haswell) { 37533 return 27; 37534 } else { 37535 return 27; 37536 } 37537 case 6: return 0; 37538 case 5: return 0; 37539 case 4: 37540 if (devinfo->is_g4x) { 37541 return 0; 37542 } else { 37543 return 0; 37544 } 37545 default: 37546 unreachable("Invalid hardware generation"); 37547 } 37548 } 37549 37550 37551 37552 /* 3DSTATE_HS::Command Type */ 37553 37554 37555 #define GEN10_3DSTATE_HS_CommandType_bits 3 37556 #define GEN9_3DSTATE_HS_CommandType_bits 3 37557 #define GEN8_3DSTATE_HS_CommandType_bits 3 37558 #define GEN75_3DSTATE_HS_CommandType_bits 3 37559 #define GEN7_3DSTATE_HS_CommandType_bits 3 37560 37561 static inline uint32_t ATTRIBUTE_PURE 37562 _3DSTATE_HS_CommandType_bits(const struct gen_device_info *devinfo) 37563 { 37564 switch (devinfo->gen) { 37565 case 10: return 3; 37566 case 9: return 3; 37567 case 8: return 3; 37568 case 7: 37569 if (devinfo->is_haswell) { 37570 return 3; 37571 } else { 37572 return 3; 37573 } 37574 case 6: return 0; 37575 case 5: return 0; 37576 case 4: 37577 if (devinfo->is_g4x) { 37578 return 0; 37579 } else { 37580 return 0; 37581 } 37582 default: 37583 unreachable("Invalid hardware generation"); 37584 } 37585 } 37586 37587 37588 37589 #define GEN10_3DSTATE_HS_CommandType_start 29 37590 #define GEN9_3DSTATE_HS_CommandType_start 29 37591 #define GEN8_3DSTATE_HS_CommandType_start 29 37592 #define GEN75_3DSTATE_HS_CommandType_start 29 37593 #define GEN7_3DSTATE_HS_CommandType_start 29 37594 37595 static inline uint32_t ATTRIBUTE_PURE 37596 _3DSTATE_HS_CommandType_start(const struct gen_device_info *devinfo) 37597 { 37598 switch (devinfo->gen) { 37599 case 10: return 29; 37600 case 9: return 29; 37601 case 8: return 29; 37602 case 7: 37603 if (devinfo->is_haswell) { 37604 return 29; 37605 } else { 37606 return 29; 37607 } 37608 case 6: return 0; 37609 case 5: return 0; 37610 case 4: 37611 if (devinfo->is_g4x) { 37612 return 0; 37613 } else { 37614 return 0; 37615 } 37616 default: 37617 unreachable("Invalid hardware generation"); 37618 } 37619 } 37620 37621 37622 37623 /* 3DSTATE_HS::DWord Length */ 37624 37625 37626 #define GEN10_3DSTATE_HS_DWordLength_bits 8 37627 #define GEN9_3DSTATE_HS_DWordLength_bits 8 37628 #define GEN8_3DSTATE_HS_DWordLength_bits 8 37629 #define GEN75_3DSTATE_HS_DWordLength_bits 8 37630 #define GEN7_3DSTATE_HS_DWordLength_bits 8 37631 37632 static inline uint32_t ATTRIBUTE_PURE 37633 _3DSTATE_HS_DWordLength_bits(const struct gen_device_info *devinfo) 37634 { 37635 switch (devinfo->gen) { 37636 case 10: return 8; 37637 case 9: return 8; 37638 case 8: return 8; 37639 case 7: 37640 if (devinfo->is_haswell) { 37641 return 8; 37642 } else { 37643 return 8; 37644 } 37645 case 6: return 0; 37646 case 5: return 0; 37647 case 4: 37648 if (devinfo->is_g4x) { 37649 return 0; 37650 } else { 37651 return 0; 37652 } 37653 default: 37654 unreachable("Invalid hardware generation"); 37655 } 37656 } 37657 37658 37659 37660 #define GEN10_3DSTATE_HS_DWordLength_start 0 37661 #define GEN9_3DSTATE_HS_DWordLength_start 0 37662 #define GEN8_3DSTATE_HS_DWordLength_start 0 37663 #define GEN75_3DSTATE_HS_DWordLength_start 0 37664 #define GEN7_3DSTATE_HS_DWordLength_start 0 37665 37666 static inline uint32_t ATTRIBUTE_PURE 37667 _3DSTATE_HS_DWordLength_start(const struct gen_device_info *devinfo) 37668 { 37669 switch (devinfo->gen) { 37670 case 10: return 0; 37671 case 9: return 0; 37672 case 8: return 0; 37673 case 7: 37674 if (devinfo->is_haswell) { 37675 return 0; 37676 } else { 37677 return 0; 37678 } 37679 case 6: return 0; 37680 case 5: return 0; 37681 case 4: 37682 if (devinfo->is_g4x) { 37683 return 0; 37684 } else { 37685 return 0; 37686 } 37687 default: 37688 unreachable("Invalid hardware generation"); 37689 } 37690 } 37691 37692 37693 37694 /* 3DSTATE_HS::Dispatch GRF Start Register For URB Data */ 37695 37696 37697 #define GEN10_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 37698 #define GEN9_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 37699 #define GEN8_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 37700 #define GEN75_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 37701 #define GEN7_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 37702 37703 static inline uint32_t ATTRIBUTE_PURE 37704 _3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits(const struct gen_device_info *devinfo) 37705 { 37706 switch (devinfo->gen) { 37707 case 10: return 5; 37708 case 9: return 5; 37709 case 8: return 5; 37710 case 7: 37711 if (devinfo->is_haswell) { 37712 return 5; 37713 } else { 37714 return 5; 37715 } 37716 case 6: return 0; 37717 case 5: return 0; 37718 case 4: 37719 if (devinfo->is_g4x) { 37720 return 0; 37721 } else { 37722 return 0; 37723 } 37724 default: 37725 unreachable("Invalid hardware generation"); 37726 } 37727 } 37728 37729 37730 37731 #define GEN10_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 243 37732 #define GEN9_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 243 37733 #define GEN8_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 243 37734 #define GEN75_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 179 37735 #define GEN7_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 179 37736 37737 static inline uint32_t ATTRIBUTE_PURE 37738 _3DSTATE_HS_DispatchGRFStartRegisterForURBData_start(const struct gen_device_info *devinfo) 37739 { 37740 switch (devinfo->gen) { 37741 case 10: return 243; 37742 case 9: return 243; 37743 case 8: return 243; 37744 case 7: 37745 if (devinfo->is_haswell) { 37746 return 179; 37747 } else { 37748 return 179; 37749 } 37750 case 6: return 0; 37751 case 5: return 0; 37752 case 4: 37753 if (devinfo->is_g4x) { 37754 return 0; 37755 } else { 37756 return 0; 37757 } 37758 default: 37759 unreachable("Invalid hardware generation"); 37760 } 37761 } 37762 37763 37764 37765 /* 3DSTATE_HS::Dispatch GRF Start Register For URB Data [5] */ 37766 37767 37768 #define GEN10_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_bits 1 37769 #define GEN9_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_bits 1 37770 37771 static inline uint32_t ATTRIBUTE_PURE 37772 _3DSTATE_HS_DispatchGRFStartRegisterForURBData5_bits(const struct gen_device_info *devinfo) 37773 { 37774 switch (devinfo->gen) { 37775 case 10: return 1; 37776 case 9: return 1; 37777 case 8: return 0; 37778 case 7: 37779 if (devinfo->is_haswell) { 37780 return 0; 37781 } else { 37782 return 0; 37783 } 37784 case 6: return 0; 37785 case 5: return 0; 37786 case 4: 37787 if (devinfo->is_g4x) { 37788 return 0; 37789 } else { 37790 return 0; 37791 } 37792 default: 37793 unreachable("Invalid hardware generation"); 37794 } 37795 } 37796 37797 37798 37799 #define GEN10_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_start 252 37800 #define GEN9_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_start 252 37801 37802 static inline uint32_t ATTRIBUTE_PURE 37803 _3DSTATE_HS_DispatchGRFStartRegisterForURBData5_start(const struct gen_device_info *devinfo) 37804 { 37805 switch (devinfo->gen) { 37806 case 10: return 252; 37807 case 9: return 252; 37808 case 8: return 0; 37809 case 7: 37810 if (devinfo->is_haswell) { 37811 return 0; 37812 } else { 37813 return 0; 37814 } 37815 case 6: return 0; 37816 case 5: return 0; 37817 case 4: 37818 if (devinfo->is_g4x) { 37819 return 0; 37820 } else { 37821 return 0; 37822 } 37823 default: 37824 unreachable("Invalid hardware generation"); 37825 } 37826 } 37827 37828 37829 37830 /* 3DSTATE_HS::Dispatch Mode */ 37831 37832 37833 #define GEN10_3DSTATE_HS_DispatchMode_bits 2 37834 #define GEN9_3DSTATE_HS_DispatchMode_bits 2 37835 37836 static inline uint32_t ATTRIBUTE_PURE 37837 _3DSTATE_HS_DispatchMode_bits(const struct gen_device_info *devinfo) 37838 { 37839 switch (devinfo->gen) { 37840 case 10: return 2; 37841 case 9: return 2; 37842 case 8: return 0; 37843 case 7: 37844 if (devinfo->is_haswell) { 37845 return 0; 37846 } else { 37847 return 0; 37848 } 37849 case 6: return 0; 37850 case 5: return 0; 37851 case 4: 37852 if (devinfo->is_g4x) { 37853 return 0; 37854 } else { 37855 return 0; 37856 } 37857 default: 37858 unreachable("Invalid hardware generation"); 37859 } 37860 } 37861 37862 37863 37864 #define GEN10_3DSTATE_HS_DispatchMode_start 241 37865 #define GEN9_3DSTATE_HS_DispatchMode_start 241 37866 37867 static inline uint32_t ATTRIBUTE_PURE 37868 _3DSTATE_HS_DispatchMode_start(const struct gen_device_info *devinfo) 37869 { 37870 switch (devinfo->gen) { 37871 case 10: return 241; 37872 case 9: return 241; 37873 case 8: return 0; 37874 case 7: 37875 if (devinfo->is_haswell) { 37876 return 0; 37877 } else { 37878 return 0; 37879 } 37880 case 6: return 0; 37881 case 5: return 0; 37882 case 4: 37883 if (devinfo->is_g4x) { 37884 return 0; 37885 } else { 37886 return 0; 37887 } 37888 default: 37889 unreachable("Invalid hardware generation"); 37890 } 37891 } 37892 37893 37894 37895 /* 3DSTATE_HS::Enable */ 37896 37897 37898 #define GEN10_3DSTATE_HS_Enable_bits 1 37899 #define GEN9_3DSTATE_HS_Enable_bits 1 37900 #define GEN8_3DSTATE_HS_Enable_bits 1 37901 #define GEN75_3DSTATE_HS_Enable_bits 1 37902 #define GEN7_3DSTATE_HS_Enable_bits 1 37903 37904 static inline uint32_t ATTRIBUTE_PURE 37905 _3DSTATE_HS_Enable_bits(const struct gen_device_info *devinfo) 37906 { 37907 switch (devinfo->gen) { 37908 case 10: return 1; 37909 case 9: return 1; 37910 case 8: return 1; 37911 case 7: 37912 if (devinfo->is_haswell) { 37913 return 1; 37914 } else { 37915 return 1; 37916 } 37917 case 6: return 0; 37918 case 5: return 0; 37919 case 4: 37920 if (devinfo->is_g4x) { 37921 return 0; 37922 } else { 37923 return 0; 37924 } 37925 default: 37926 unreachable("Invalid hardware generation"); 37927 } 37928 } 37929 37930 37931 37932 #define GEN10_3DSTATE_HS_Enable_start 95 37933 #define GEN9_3DSTATE_HS_Enable_start 95 37934 #define GEN8_3DSTATE_HS_Enable_start 95 37935 #define GEN75_3DSTATE_HS_Enable_start 95 37936 #define GEN7_3DSTATE_HS_Enable_start 95 37937 37938 static inline uint32_t ATTRIBUTE_PURE 37939 _3DSTATE_HS_Enable_start(const struct gen_device_info *devinfo) 37940 { 37941 switch (devinfo->gen) { 37942 case 10: return 95; 37943 case 9: return 95; 37944 case 8: return 95; 37945 case 7: 37946 if (devinfo->is_haswell) { 37947 return 95; 37948 } else { 37949 return 95; 37950 } 37951 case 6: return 0; 37952 case 5: return 0; 37953 case 4: 37954 if (devinfo->is_g4x) { 37955 return 0; 37956 } else { 37957 return 0; 37958 } 37959 default: 37960 unreachable("Invalid hardware generation"); 37961 } 37962 } 37963 37964 37965 37966 /* 3DSTATE_HS::Floating Point Mode */ 37967 37968 37969 #define GEN10_3DSTATE_HS_FloatingPointMode_bits 1 37970 #define GEN9_3DSTATE_HS_FloatingPointMode_bits 1 37971 #define GEN8_3DSTATE_HS_FloatingPointMode_bits 1 37972 #define GEN75_3DSTATE_HS_FloatingPointMode_bits 1 37973 #define GEN7_3DSTATE_HS_FloatingPointMode_bits 1 37974 37975 static inline uint32_t ATTRIBUTE_PURE 37976 _3DSTATE_HS_FloatingPointMode_bits(const struct gen_device_info *devinfo) 37977 { 37978 switch (devinfo->gen) { 37979 case 10: return 1; 37980 case 9: return 1; 37981 case 8: return 1; 37982 case 7: 37983 if (devinfo->is_haswell) { 37984 return 1; 37985 } else { 37986 return 1; 37987 } 37988 case 6: return 0; 37989 case 5: return 0; 37990 case 4: 37991 if (devinfo->is_g4x) { 37992 return 0; 37993 } else { 37994 return 0; 37995 } 37996 default: 37997 unreachable("Invalid hardware generation"); 37998 } 37999 } 38000 38001 38002 38003 #define GEN10_3DSTATE_HS_FloatingPointMode_start 48 38004 #define GEN9_3DSTATE_HS_FloatingPointMode_start 48 38005 #define GEN8_3DSTATE_HS_FloatingPointMode_start 48 38006 #define GEN75_3DSTATE_HS_FloatingPointMode_start 48 38007 #define GEN7_3DSTATE_HS_FloatingPointMode_start 48 38008 38009 static inline uint32_t ATTRIBUTE_PURE 38010 _3DSTATE_HS_FloatingPointMode_start(const struct gen_device_info *devinfo) 38011 { 38012 switch (devinfo->gen) { 38013 case 10: return 48; 38014 case 9: return 48; 38015 case 8: return 48; 38016 case 7: 38017 if (devinfo->is_haswell) { 38018 return 48; 38019 } else { 38020 return 48; 38021 } 38022 case 6: return 0; 38023 case 5: return 0; 38024 case 4: 38025 if (devinfo->is_g4x) { 38026 return 0; 38027 } else { 38028 return 0; 38029 } 38030 default: 38031 unreachable("Invalid hardware generation"); 38032 } 38033 } 38034 38035 38036 38037 /* 3DSTATE_HS::HS accesses UAV */ 38038 38039 38040 #define GEN75_3DSTATE_HS_HSaccessesUAV_bits 1 38041 38042 static inline uint32_t ATTRIBUTE_PURE 38043 _3DSTATE_HS_HSaccessesUAV_bits(const struct gen_device_info *devinfo) 38044 { 38045 switch (devinfo->gen) { 38046 case 10: return 0; 38047 case 9: return 0; 38048 case 8: return 0; 38049 case 7: 38050 if (devinfo->is_haswell) { 38051 return 1; 38052 } else { 38053 return 0; 38054 } 38055 case 6: return 0; 38056 case 5: return 0; 38057 case 4: 38058 if (devinfo->is_g4x) { 38059 return 0; 38060 } else { 38061 return 0; 38062 } 38063 default: 38064 unreachable("Invalid hardware generation"); 38065 } 38066 } 38067 38068 38069 38070 #define GEN75_3DSTATE_HS_HSaccessesUAV_start 185 38071 38072 static inline uint32_t ATTRIBUTE_PURE 38073 _3DSTATE_HS_HSaccessesUAV_start(const struct gen_device_info *devinfo) 38074 { 38075 switch (devinfo->gen) { 38076 case 10: return 0; 38077 case 9: return 0; 38078 case 8: return 0; 38079 case 7: 38080 if (devinfo->is_haswell) { 38081 return 185; 38082 } else { 38083 return 0; 38084 } 38085 case 6: return 0; 38086 case 5: return 0; 38087 case 4: 38088 if (devinfo->is_g4x) { 38089 return 0; 38090 } else { 38091 return 0; 38092 } 38093 default: 38094 unreachable("Invalid hardware generation"); 38095 } 38096 } 38097 38098 38099 38100 /* 3DSTATE_HS::Illegal Opcode Exception Enable */ 38101 38102 38103 #define GEN10_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 38104 #define GEN9_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 38105 #define GEN8_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 38106 #define GEN75_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 38107 #define GEN7_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 38108 38109 static inline uint32_t ATTRIBUTE_PURE 38110 _3DSTATE_HS_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) 38111 { 38112 switch (devinfo->gen) { 38113 case 10: return 1; 38114 case 9: return 1; 38115 case 8: return 1; 38116 case 7: 38117 if (devinfo->is_haswell) { 38118 return 1; 38119 } else { 38120 return 1; 38121 } 38122 case 6: return 0; 38123 case 5: return 0; 38124 case 4: 38125 if (devinfo->is_g4x) { 38126 return 0; 38127 } else { 38128 return 0; 38129 } 38130 default: 38131 unreachable("Invalid hardware generation"); 38132 } 38133 } 38134 38135 38136 38137 #define GEN10_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 38138 #define GEN9_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 38139 #define GEN8_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 38140 #define GEN75_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 38141 #define GEN7_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 38142 38143 static inline uint32_t ATTRIBUTE_PURE 38144 _3DSTATE_HS_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) 38145 { 38146 switch (devinfo->gen) { 38147 case 10: return 45; 38148 case 9: return 45; 38149 case 8: return 45; 38150 case 7: 38151 if (devinfo->is_haswell) { 38152 return 45; 38153 } else { 38154 return 45; 38155 } 38156 case 6: return 0; 38157 case 5: return 0; 38158 case 4: 38159 if (devinfo->is_g4x) { 38160 return 0; 38161 } else { 38162 return 0; 38163 } 38164 default: 38165 unreachable("Invalid hardware generation"); 38166 } 38167 } 38168 38169 38170 38171 /* 3DSTATE_HS::Include Primitive ID */ 38172 38173 38174 #define GEN10_3DSTATE_HS_IncludePrimitiveID_bits 1 38175 #define GEN9_3DSTATE_HS_IncludePrimitiveID_bits 1 38176 38177 static inline uint32_t ATTRIBUTE_PURE 38178 _3DSTATE_HS_IncludePrimitiveID_bits(const struct gen_device_info *devinfo) 38179 { 38180 switch (devinfo->gen) { 38181 case 10: return 1; 38182 case 9: return 1; 38183 case 8: return 0; 38184 case 7: 38185 if (devinfo->is_haswell) { 38186 return 0; 38187 } else { 38188 return 0; 38189 } 38190 case 6: return 0; 38191 case 5: return 0; 38192 case 4: 38193 if (devinfo->is_g4x) { 38194 return 0; 38195 } else { 38196 return 0; 38197 } 38198 default: 38199 unreachable("Invalid hardware generation"); 38200 } 38201 } 38202 38203 38204 38205 #define GEN10_3DSTATE_HS_IncludePrimitiveID_start 224 38206 #define GEN9_3DSTATE_HS_IncludePrimitiveID_start 224 38207 38208 static inline uint32_t ATTRIBUTE_PURE 38209 _3DSTATE_HS_IncludePrimitiveID_start(const struct gen_device_info *devinfo) 38210 { 38211 switch (devinfo->gen) { 38212 case 10: return 224; 38213 case 9: return 224; 38214 case 8: return 0; 38215 case 7: 38216 if (devinfo->is_haswell) { 38217 return 0; 38218 } else { 38219 return 0; 38220 } 38221 case 6: return 0; 38222 case 5: return 0; 38223 case 4: 38224 if (devinfo->is_g4x) { 38225 return 0; 38226 } else { 38227 return 0; 38228 } 38229 default: 38230 unreachable("Invalid hardware generation"); 38231 } 38232 } 38233 38234 38235 38236 /* 3DSTATE_HS::Include Vertex Handles */ 38237 38238 38239 #define GEN10_3DSTATE_HS_IncludeVertexHandles_bits 1 38240 #define GEN9_3DSTATE_HS_IncludeVertexHandles_bits 1 38241 #define GEN8_3DSTATE_HS_IncludeVertexHandles_bits 1 38242 #define GEN75_3DSTATE_HS_IncludeVertexHandles_bits 1 38243 #define GEN7_3DSTATE_HS_IncludeVertexHandles_bits 1 38244 38245 static inline uint32_t ATTRIBUTE_PURE 38246 _3DSTATE_HS_IncludeVertexHandles_bits(const struct gen_device_info *devinfo) 38247 { 38248 switch (devinfo->gen) { 38249 case 10: return 1; 38250 case 9: return 1; 38251 case 8: return 1; 38252 case 7: 38253 if (devinfo->is_haswell) { 38254 return 1; 38255 } else { 38256 return 1; 38257 } 38258 case 6: return 0; 38259 case 5: return 0; 38260 case 4: 38261 if (devinfo->is_g4x) { 38262 return 0; 38263 } else { 38264 return 0; 38265 } 38266 default: 38267 unreachable("Invalid hardware generation"); 38268 } 38269 } 38270 38271 38272 38273 #define GEN10_3DSTATE_HS_IncludeVertexHandles_start 248 38274 #define GEN9_3DSTATE_HS_IncludeVertexHandles_start 248 38275 #define GEN8_3DSTATE_HS_IncludeVertexHandles_start 248 38276 #define GEN75_3DSTATE_HS_IncludeVertexHandles_start 184 38277 #define GEN7_3DSTATE_HS_IncludeVertexHandles_start 184 38278 38279 static inline uint32_t ATTRIBUTE_PURE 38280 _3DSTATE_HS_IncludeVertexHandles_start(const struct gen_device_info *devinfo) 38281 { 38282 switch (devinfo->gen) { 38283 case 10: return 248; 38284 case 9: return 248; 38285 case 8: return 248; 38286 case 7: 38287 if (devinfo->is_haswell) { 38288 return 184; 38289 } else { 38290 return 184; 38291 } 38292 case 6: return 0; 38293 case 5: return 0; 38294 case 4: 38295 if (devinfo->is_g4x) { 38296 return 0; 38297 } else { 38298 return 0; 38299 } 38300 default: 38301 unreachable("Invalid hardware generation"); 38302 } 38303 } 38304 38305 38306 38307 /* 3DSTATE_HS::Instance Count */ 38308 38309 38310 #define GEN10_3DSTATE_HS_InstanceCount_bits 4 38311 #define GEN9_3DSTATE_HS_InstanceCount_bits 4 38312 #define GEN8_3DSTATE_HS_InstanceCount_bits 4 38313 #define GEN75_3DSTATE_HS_InstanceCount_bits 4 38314 #define GEN7_3DSTATE_HS_InstanceCount_bits 4 38315 38316 static inline uint32_t ATTRIBUTE_PURE 38317 _3DSTATE_HS_InstanceCount_bits(const struct gen_device_info *devinfo) 38318 { 38319 switch (devinfo->gen) { 38320 case 10: return 4; 38321 case 9: return 4; 38322 case 8: return 4; 38323 case 7: 38324 if (devinfo->is_haswell) { 38325 return 4; 38326 } else { 38327 return 4; 38328 } 38329 case 6: return 0; 38330 case 5: return 0; 38331 case 4: 38332 if (devinfo->is_g4x) { 38333 return 0; 38334 } else { 38335 return 0; 38336 } 38337 default: 38338 unreachable("Invalid hardware generation"); 38339 } 38340 } 38341 38342 38343 38344 #define GEN10_3DSTATE_HS_InstanceCount_start 64 38345 #define GEN9_3DSTATE_HS_InstanceCount_start 64 38346 #define GEN8_3DSTATE_HS_InstanceCount_start 64 38347 #define GEN75_3DSTATE_HS_InstanceCount_start 64 38348 #define GEN7_3DSTATE_HS_InstanceCount_start 64 38349 38350 static inline uint32_t ATTRIBUTE_PURE 38351 _3DSTATE_HS_InstanceCount_start(const struct gen_device_info *devinfo) 38352 { 38353 switch (devinfo->gen) { 38354 case 10: return 64; 38355 case 9: return 64; 38356 case 8: return 64; 38357 case 7: 38358 if (devinfo->is_haswell) { 38359 return 64; 38360 } else { 38361 return 64; 38362 } 38363 case 6: return 0; 38364 case 5: return 0; 38365 case 4: 38366 if (devinfo->is_g4x) { 38367 return 0; 38368 } else { 38369 return 0; 38370 } 38371 default: 38372 unreachable("Invalid hardware generation"); 38373 } 38374 } 38375 38376 38377 38378 /* 3DSTATE_HS::Kernel Start Pointer */ 38379 38380 38381 #define GEN10_3DSTATE_HS_KernelStartPointer_bits 58 38382 #define GEN9_3DSTATE_HS_KernelStartPointer_bits 58 38383 #define GEN8_3DSTATE_HS_KernelStartPointer_bits 58 38384 #define GEN75_3DSTATE_HS_KernelStartPointer_bits 26 38385 #define GEN7_3DSTATE_HS_KernelStartPointer_bits 26 38386 38387 static inline uint32_t ATTRIBUTE_PURE 38388 _3DSTATE_HS_KernelStartPointer_bits(const struct gen_device_info *devinfo) 38389 { 38390 switch (devinfo->gen) { 38391 case 10: return 58; 38392 case 9: return 58; 38393 case 8: return 58; 38394 case 7: 38395 if (devinfo->is_haswell) { 38396 return 26; 38397 } else { 38398 return 26; 38399 } 38400 case 6: return 0; 38401 case 5: return 0; 38402 case 4: 38403 if (devinfo->is_g4x) { 38404 return 0; 38405 } else { 38406 return 0; 38407 } 38408 default: 38409 unreachable("Invalid hardware generation"); 38410 } 38411 } 38412 38413 38414 38415 #define GEN10_3DSTATE_HS_KernelStartPointer_start 102 38416 #define GEN9_3DSTATE_HS_KernelStartPointer_start 102 38417 #define GEN8_3DSTATE_HS_KernelStartPointer_start 102 38418 #define GEN75_3DSTATE_HS_KernelStartPointer_start 102 38419 #define GEN7_3DSTATE_HS_KernelStartPointer_start 102 38420 38421 static inline uint32_t ATTRIBUTE_PURE 38422 _3DSTATE_HS_KernelStartPointer_start(const struct gen_device_info *devinfo) 38423 { 38424 switch (devinfo->gen) { 38425 case 10: return 102; 38426 case 9: return 102; 38427 case 8: return 102; 38428 case 7: 38429 if (devinfo->is_haswell) { 38430 return 102; 38431 } else { 38432 return 102; 38433 } 38434 case 6: return 0; 38435 case 5: return 0; 38436 case 4: 38437 if (devinfo->is_g4x) { 38438 return 0; 38439 } else { 38440 return 0; 38441 } 38442 default: 38443 unreachable("Invalid hardware generation"); 38444 } 38445 } 38446 38447 38448 38449 /* 3DSTATE_HS::Maximum Number of Threads */ 38450 38451 38452 #define GEN10_3DSTATE_HS_MaximumNumberofThreads_bits 9 38453 #define GEN9_3DSTATE_HS_MaximumNumberofThreads_bits 9 38454 #define GEN8_3DSTATE_HS_MaximumNumberofThreads_bits 9 38455 #define GEN75_3DSTATE_HS_MaximumNumberofThreads_bits 8 38456 #define GEN7_3DSTATE_HS_MaximumNumberofThreads_bits 7 38457 38458 static inline uint32_t ATTRIBUTE_PURE 38459 _3DSTATE_HS_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) 38460 { 38461 switch (devinfo->gen) { 38462 case 10: return 9; 38463 case 9: return 9; 38464 case 8: return 9; 38465 case 7: 38466 if (devinfo->is_haswell) { 38467 return 8; 38468 } else { 38469 return 7; 38470 } 38471 case 6: return 0; 38472 case 5: return 0; 38473 case 4: 38474 if (devinfo->is_g4x) { 38475 return 0; 38476 } else { 38477 return 0; 38478 } 38479 default: 38480 unreachable("Invalid hardware generation"); 38481 } 38482 } 38483 38484 38485 38486 #define GEN10_3DSTATE_HS_MaximumNumberofThreads_start 72 38487 #define GEN9_3DSTATE_HS_MaximumNumberofThreads_start 72 38488 #define GEN8_3DSTATE_HS_MaximumNumberofThreads_start 72 38489 #define GEN75_3DSTATE_HS_MaximumNumberofThreads_start 32 38490 #define GEN7_3DSTATE_HS_MaximumNumberofThreads_start 32 38491 38492 static inline uint32_t ATTRIBUTE_PURE 38493 _3DSTATE_HS_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) 38494 { 38495 switch (devinfo->gen) { 38496 case 10: return 72; 38497 case 9: return 72; 38498 case 8: return 72; 38499 case 7: 38500 if (devinfo->is_haswell) { 38501 return 32; 38502 } else { 38503 return 32; 38504 } 38505 case 6: return 0; 38506 case 5: return 0; 38507 case 4: 38508 if (devinfo->is_g4x) { 38509 return 0; 38510 } else { 38511 return 0; 38512 } 38513 default: 38514 unreachable("Invalid hardware generation"); 38515 } 38516 } 38517 38518 38519 38520 /* 3DSTATE_HS::Per-Thread Scratch Space */ 38521 38522 38523 #define GEN10_3DSTATE_HS_PerThreadScratchSpace_bits 4 38524 #define GEN9_3DSTATE_HS_PerThreadScratchSpace_bits 4 38525 #define GEN8_3DSTATE_HS_PerThreadScratchSpace_bits 4 38526 #define GEN75_3DSTATE_HS_PerThreadScratchSpace_bits 4 38527 #define GEN7_3DSTATE_HS_PerThreadScratchSpace_bits 4 38528 38529 static inline uint32_t ATTRIBUTE_PURE 38530 _3DSTATE_HS_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) 38531 { 38532 switch (devinfo->gen) { 38533 case 10: return 4; 38534 case 9: return 4; 38535 case 8: return 4; 38536 case 7: 38537 if (devinfo->is_haswell) { 38538 return 4; 38539 } else { 38540 return 4; 38541 } 38542 case 6: return 0; 38543 case 5: return 0; 38544 case 4: 38545 if (devinfo->is_g4x) { 38546 return 0; 38547 } else { 38548 return 0; 38549 } 38550 default: 38551 unreachable("Invalid hardware generation"); 38552 } 38553 } 38554 38555 38556 38557 #define GEN10_3DSTATE_HS_PerThreadScratchSpace_start 160 38558 #define GEN9_3DSTATE_HS_PerThreadScratchSpace_start 160 38559 #define GEN8_3DSTATE_HS_PerThreadScratchSpace_start 160 38560 #define GEN75_3DSTATE_HS_PerThreadScratchSpace_start 128 38561 #define GEN7_3DSTATE_HS_PerThreadScratchSpace_start 128 38562 38563 static inline uint32_t ATTRIBUTE_PURE 38564 _3DSTATE_HS_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) 38565 { 38566 switch (devinfo->gen) { 38567 case 10: return 160; 38568 case 9: return 160; 38569 case 8: return 160; 38570 case 7: 38571 if (devinfo->is_haswell) { 38572 return 128; 38573 } else { 38574 return 128; 38575 } 38576 case 6: return 0; 38577 case 5: return 0; 38578 case 4: 38579 if (devinfo->is_g4x) { 38580 return 0; 38581 } else { 38582 return 0; 38583 } 38584 default: 38585 unreachable("Invalid hardware generation"); 38586 } 38587 } 38588 38589 38590 38591 /* 3DSTATE_HS::Sampler Count */ 38592 38593 38594 #define GEN10_3DSTATE_HS_SamplerCount_bits 3 38595 #define GEN9_3DSTATE_HS_SamplerCount_bits 3 38596 #define GEN8_3DSTATE_HS_SamplerCount_bits 3 38597 #define GEN75_3DSTATE_HS_SamplerCount_bits 3 38598 #define GEN7_3DSTATE_HS_SamplerCount_bits 3 38599 38600 static inline uint32_t ATTRIBUTE_PURE 38601 _3DSTATE_HS_SamplerCount_bits(const struct gen_device_info *devinfo) 38602 { 38603 switch (devinfo->gen) { 38604 case 10: return 3; 38605 case 9: return 3; 38606 case 8: return 3; 38607 case 7: 38608 if (devinfo->is_haswell) { 38609 return 3; 38610 } else { 38611 return 3; 38612 } 38613 case 6: return 0; 38614 case 5: return 0; 38615 case 4: 38616 if (devinfo->is_g4x) { 38617 return 0; 38618 } else { 38619 return 0; 38620 } 38621 default: 38622 unreachable("Invalid hardware generation"); 38623 } 38624 } 38625 38626 38627 38628 #define GEN10_3DSTATE_HS_SamplerCount_start 59 38629 #define GEN9_3DSTATE_HS_SamplerCount_start 59 38630 #define GEN8_3DSTATE_HS_SamplerCount_start 59 38631 #define GEN75_3DSTATE_HS_SamplerCount_start 59 38632 #define GEN7_3DSTATE_HS_SamplerCount_start 59 38633 38634 static inline uint32_t ATTRIBUTE_PURE 38635 _3DSTATE_HS_SamplerCount_start(const struct gen_device_info *devinfo) 38636 { 38637 switch (devinfo->gen) { 38638 case 10: return 59; 38639 case 9: return 59; 38640 case 8: return 59; 38641 case 7: 38642 if (devinfo->is_haswell) { 38643 return 59; 38644 } else { 38645 return 59; 38646 } 38647 case 6: return 0; 38648 case 5: return 0; 38649 case 4: 38650 if (devinfo->is_g4x) { 38651 return 0; 38652 } else { 38653 return 0; 38654 } 38655 default: 38656 unreachable("Invalid hardware generation"); 38657 } 38658 } 38659 38660 38661 38662 /* 3DSTATE_HS::Scratch Space Base Pointer */ 38663 38664 38665 #define GEN10_3DSTATE_HS_ScratchSpaceBasePointer_bits 54 38666 #define GEN9_3DSTATE_HS_ScratchSpaceBasePointer_bits 54 38667 #define GEN8_3DSTATE_HS_ScratchSpaceBasePointer_bits 54 38668 #define GEN75_3DSTATE_HS_ScratchSpaceBasePointer_bits 22 38669 #define GEN7_3DSTATE_HS_ScratchSpaceBasePointer_bits 22 38670 38671 static inline uint32_t ATTRIBUTE_PURE 38672 _3DSTATE_HS_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) 38673 { 38674 switch (devinfo->gen) { 38675 case 10: return 54; 38676 case 9: return 54; 38677 case 8: return 54; 38678 case 7: 38679 if (devinfo->is_haswell) { 38680 return 22; 38681 } else { 38682 return 22; 38683 } 38684 case 6: return 0; 38685 case 5: return 0; 38686 case 4: 38687 if (devinfo->is_g4x) { 38688 return 0; 38689 } else { 38690 return 0; 38691 } 38692 default: 38693 unreachable("Invalid hardware generation"); 38694 } 38695 } 38696 38697 38698 38699 #define GEN10_3DSTATE_HS_ScratchSpaceBasePointer_start 170 38700 #define GEN9_3DSTATE_HS_ScratchSpaceBasePointer_start 170 38701 #define GEN8_3DSTATE_HS_ScratchSpaceBasePointer_start 170 38702 #define GEN75_3DSTATE_HS_ScratchSpaceBasePointer_start 138 38703 #define GEN7_3DSTATE_HS_ScratchSpaceBasePointer_start 138 38704 38705 static inline uint32_t ATTRIBUTE_PURE 38706 _3DSTATE_HS_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) 38707 { 38708 switch (devinfo->gen) { 38709 case 10: return 170; 38710 case 9: return 170; 38711 case 8: return 170; 38712 case 7: 38713 if (devinfo->is_haswell) { 38714 return 138; 38715 } else { 38716 return 138; 38717 } 38718 case 6: return 0; 38719 case 5: return 0; 38720 case 4: 38721 if (devinfo->is_g4x) { 38722 return 0; 38723 } else { 38724 return 0; 38725 } 38726 default: 38727 unreachable("Invalid hardware generation"); 38728 } 38729 } 38730 38731 38732 38733 /* 3DSTATE_HS::Semaphore Handle */ 38734 38735 38736 #define GEN75_3DSTATE_HS_SemaphoreHandle_bits 13 38737 #define GEN7_3DSTATE_HS_SemaphoreHandle_bits 12 38738 38739 static inline uint32_t ATTRIBUTE_PURE 38740 _3DSTATE_HS_SemaphoreHandle_bits(const struct gen_device_info *devinfo) 38741 { 38742 switch (devinfo->gen) { 38743 case 10: return 0; 38744 case 9: return 0; 38745 case 8: return 0; 38746 case 7: 38747 if (devinfo->is_haswell) { 38748 return 13; 38749 } else { 38750 return 12; 38751 } 38752 case 6: return 0; 38753 case 5: return 0; 38754 case 4: 38755 if (devinfo->is_g4x) { 38756 return 0; 38757 } else { 38758 return 0; 38759 } 38760 default: 38761 unreachable("Invalid hardware generation"); 38762 } 38763 } 38764 38765 38766 38767 #define GEN75_3DSTATE_HS_SemaphoreHandle_start 192 38768 #define GEN7_3DSTATE_HS_SemaphoreHandle_start 192 38769 38770 static inline uint32_t ATTRIBUTE_PURE 38771 _3DSTATE_HS_SemaphoreHandle_start(const struct gen_device_info *devinfo) 38772 { 38773 switch (devinfo->gen) { 38774 case 10: return 0; 38775 case 9: return 0; 38776 case 8: return 0; 38777 case 7: 38778 if (devinfo->is_haswell) { 38779 return 192; 38780 } else { 38781 return 192; 38782 } 38783 case 6: return 0; 38784 case 5: return 0; 38785 case 4: 38786 if (devinfo->is_g4x) { 38787 return 0; 38788 } else { 38789 return 0; 38790 } 38791 default: 38792 unreachable("Invalid hardware generation"); 38793 } 38794 } 38795 38796 38797 38798 /* 3DSTATE_HS::Single Program Flow */ 38799 38800 38801 #define GEN10_3DSTATE_HS_SingleProgramFlow_bits 1 38802 #define GEN9_3DSTATE_HS_SingleProgramFlow_bits 1 38803 #define GEN8_3DSTATE_HS_SingleProgramFlow_bits 1 38804 #define GEN75_3DSTATE_HS_SingleProgramFlow_bits 1 38805 #define GEN7_3DSTATE_HS_SingleProgramFlow_bits 1 38806 38807 static inline uint32_t ATTRIBUTE_PURE 38808 _3DSTATE_HS_SingleProgramFlow_bits(const struct gen_device_info *devinfo) 38809 { 38810 switch (devinfo->gen) { 38811 case 10: return 1; 38812 case 9: return 1; 38813 case 8: return 1; 38814 case 7: 38815 if (devinfo->is_haswell) { 38816 return 1; 38817 } else { 38818 return 1; 38819 } 38820 case 6: return 0; 38821 case 5: return 0; 38822 case 4: 38823 if (devinfo->is_g4x) { 38824 return 0; 38825 } else { 38826 return 0; 38827 } 38828 default: 38829 unreachable("Invalid hardware generation"); 38830 } 38831 } 38832 38833 38834 38835 #define GEN10_3DSTATE_HS_SingleProgramFlow_start 251 38836 #define GEN9_3DSTATE_HS_SingleProgramFlow_start 251 38837 #define GEN8_3DSTATE_HS_SingleProgramFlow_start 251 38838 #define GEN75_3DSTATE_HS_SingleProgramFlow_start 187 38839 #define GEN7_3DSTATE_HS_SingleProgramFlow_start 187 38840 38841 static inline uint32_t ATTRIBUTE_PURE 38842 _3DSTATE_HS_SingleProgramFlow_start(const struct gen_device_info *devinfo) 38843 { 38844 switch (devinfo->gen) { 38845 case 10: return 251; 38846 case 9: return 251; 38847 case 8: return 251; 38848 case 7: 38849 if (devinfo->is_haswell) { 38850 return 187; 38851 } else { 38852 return 187; 38853 } 38854 case 6: return 0; 38855 case 5: return 0; 38856 case 4: 38857 if (devinfo->is_g4x) { 38858 return 0; 38859 } else { 38860 return 0; 38861 } 38862 default: 38863 unreachable("Invalid hardware generation"); 38864 } 38865 } 38866 38867 38868 38869 /* 3DSTATE_HS::Software Exception Enable */ 38870 38871 38872 #define GEN10_3DSTATE_HS_SoftwareExceptionEnable_bits 1 38873 #define GEN9_3DSTATE_HS_SoftwareExceptionEnable_bits 1 38874 #define GEN8_3DSTATE_HS_SoftwareExceptionEnable_bits 1 38875 #define GEN75_3DSTATE_HS_SoftwareExceptionEnable_bits 1 38876 #define GEN7_3DSTATE_HS_SoftwareExceptionEnable_bits 1 38877 38878 static inline uint32_t ATTRIBUTE_PURE 38879 _3DSTATE_HS_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) 38880 { 38881 switch (devinfo->gen) { 38882 case 10: return 1; 38883 case 9: return 1; 38884 case 8: return 1; 38885 case 7: 38886 if (devinfo->is_haswell) { 38887 return 1; 38888 } else { 38889 return 1; 38890 } 38891 case 6: return 0; 38892 case 5: return 0; 38893 case 4: 38894 if (devinfo->is_g4x) { 38895 return 0; 38896 } else { 38897 return 0; 38898 } 38899 default: 38900 unreachable("Invalid hardware generation"); 38901 } 38902 } 38903 38904 38905 38906 #define GEN10_3DSTATE_HS_SoftwareExceptionEnable_start 44 38907 #define GEN9_3DSTATE_HS_SoftwareExceptionEnable_start 44 38908 #define GEN8_3DSTATE_HS_SoftwareExceptionEnable_start 44 38909 #define GEN75_3DSTATE_HS_SoftwareExceptionEnable_start 44 38910 #define GEN7_3DSTATE_HS_SoftwareExceptionEnable_start 39 38911 38912 static inline uint32_t ATTRIBUTE_PURE 38913 _3DSTATE_HS_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) 38914 { 38915 switch (devinfo->gen) { 38916 case 10: return 44; 38917 case 9: return 44; 38918 case 8: return 44; 38919 case 7: 38920 if (devinfo->is_haswell) { 38921 return 44; 38922 } else { 38923 return 39; 38924 } 38925 case 6: return 0; 38926 case 5: return 0; 38927 case 4: 38928 if (devinfo->is_g4x) { 38929 return 0; 38930 } else { 38931 return 0; 38932 } 38933 default: 38934 unreachable("Invalid hardware generation"); 38935 } 38936 } 38937 38938 38939 38940 /* 3DSTATE_HS::Statistics Enable */ 38941 38942 38943 #define GEN10_3DSTATE_HS_StatisticsEnable_bits 1 38944 #define GEN9_3DSTATE_HS_StatisticsEnable_bits 1 38945 #define GEN8_3DSTATE_HS_StatisticsEnable_bits 1 38946 #define GEN75_3DSTATE_HS_StatisticsEnable_bits 1 38947 #define GEN7_3DSTATE_HS_StatisticsEnable_bits 1 38948 38949 static inline uint32_t ATTRIBUTE_PURE 38950 _3DSTATE_HS_StatisticsEnable_bits(const struct gen_device_info *devinfo) 38951 { 38952 switch (devinfo->gen) { 38953 case 10: return 1; 38954 case 9: return 1; 38955 case 8: return 1; 38956 case 7: 38957 if (devinfo->is_haswell) { 38958 return 1; 38959 } else { 38960 return 1; 38961 } 38962 case 6: return 0; 38963 case 5: return 0; 38964 case 4: 38965 if (devinfo->is_g4x) { 38966 return 0; 38967 } else { 38968 return 0; 38969 } 38970 default: 38971 unreachable("Invalid hardware generation"); 38972 } 38973 } 38974 38975 38976 38977 #define GEN10_3DSTATE_HS_StatisticsEnable_start 93 38978 #define GEN9_3DSTATE_HS_StatisticsEnable_start 93 38979 #define GEN8_3DSTATE_HS_StatisticsEnable_start 93 38980 #define GEN75_3DSTATE_HS_StatisticsEnable_start 93 38981 #define GEN7_3DSTATE_HS_StatisticsEnable_start 93 38982 38983 static inline uint32_t ATTRIBUTE_PURE 38984 _3DSTATE_HS_StatisticsEnable_start(const struct gen_device_info *devinfo) 38985 { 38986 switch (devinfo->gen) { 38987 case 10: return 93; 38988 case 9: return 93; 38989 case 8: return 93; 38990 case 7: 38991 if (devinfo->is_haswell) { 38992 return 93; 38993 } else { 38994 return 93; 38995 } 38996 case 6: return 0; 38997 case 5: return 0; 38998 case 4: 38999 if (devinfo->is_g4x) { 39000 return 0; 39001 } else { 39002 return 0; 39003 } 39004 default: 39005 unreachable("Invalid hardware generation"); 39006 } 39007 } 39008 39009 39010 39011 /* 3DSTATE_HS::Thread Dispatch Priority */ 39012 39013 39014 #define GEN10_3DSTATE_HS_ThreadDispatchPriority_bits 1 39015 #define GEN9_3DSTATE_HS_ThreadDispatchPriority_bits 1 39016 #define GEN8_3DSTATE_HS_ThreadDispatchPriority_bits 1 39017 #define GEN75_3DSTATE_HS_ThreadDispatchPriority_bits 1 39018 39019 static inline uint32_t ATTRIBUTE_PURE 39020 _3DSTATE_HS_ThreadDispatchPriority_bits(const struct gen_device_info *devinfo) 39021 { 39022 switch (devinfo->gen) { 39023 case 10: return 1; 39024 case 9: return 1; 39025 case 8: return 1; 39026 case 7: 39027 if (devinfo->is_haswell) { 39028 return 1; 39029 } else { 39030 return 0; 39031 } 39032 case 6: return 0; 39033 case 5: return 0; 39034 case 4: 39035 if (devinfo->is_g4x) { 39036 return 0; 39037 } else { 39038 return 0; 39039 } 39040 default: 39041 unreachable("Invalid hardware generation"); 39042 } 39043 } 39044 39045 39046 39047 #define GEN10_3DSTATE_HS_ThreadDispatchPriority_start 49 39048 #define GEN9_3DSTATE_HS_ThreadDispatchPriority_start 49 39049 #define GEN8_3DSTATE_HS_ThreadDispatchPriority_start 49 39050 #define GEN75_3DSTATE_HS_ThreadDispatchPriority_start 49 39051 39052 static inline uint32_t ATTRIBUTE_PURE 39053 _3DSTATE_HS_ThreadDispatchPriority_start(const struct gen_device_info *devinfo) 39054 { 39055 switch (devinfo->gen) { 39056 case 10: return 49; 39057 case 9: return 49; 39058 case 8: return 49; 39059 case 7: 39060 if (devinfo->is_haswell) { 39061 return 49; 39062 } else { 39063 return 0; 39064 } 39065 case 6: return 0; 39066 case 5: return 0; 39067 case 4: 39068 if (devinfo->is_g4x) { 39069 return 0; 39070 } else { 39071 return 0; 39072 } 39073 default: 39074 unreachable("Invalid hardware generation"); 39075 } 39076 } 39077 39078 39079 39080 /* 3DSTATE_HS::Vector Mask Enable */ 39081 39082 39083 #define GEN10_3DSTATE_HS_VectorMaskEnable_bits 1 39084 #define GEN9_3DSTATE_HS_VectorMaskEnable_bits 1 39085 #define GEN8_3DSTATE_HS_VectorMaskEnable_bits 1 39086 #define GEN75_3DSTATE_HS_VectorMaskEnable_bits 1 39087 #define GEN7_3DSTATE_HS_VectorMaskEnable_bits 1 39088 39089 static inline uint32_t ATTRIBUTE_PURE 39090 _3DSTATE_HS_VectorMaskEnable_bits(const struct gen_device_info *devinfo) 39091 { 39092 switch (devinfo->gen) { 39093 case 10: return 1; 39094 case 9: return 1; 39095 case 8: return 1; 39096 case 7: 39097 if (devinfo->is_haswell) { 39098 return 1; 39099 } else { 39100 return 1; 39101 } 39102 case 6: return 0; 39103 case 5: return 0; 39104 case 4: 39105 if (devinfo->is_g4x) { 39106 return 0; 39107 } else { 39108 return 0; 39109 } 39110 default: 39111 unreachable("Invalid hardware generation"); 39112 } 39113 } 39114 39115 39116 39117 #define GEN10_3DSTATE_HS_VectorMaskEnable_start 250 39118 #define GEN9_3DSTATE_HS_VectorMaskEnable_start 250 39119 #define GEN8_3DSTATE_HS_VectorMaskEnable_start 250 39120 #define GEN75_3DSTATE_HS_VectorMaskEnable_start 186 39121 #define GEN7_3DSTATE_HS_VectorMaskEnable_start 186 39122 39123 static inline uint32_t ATTRIBUTE_PURE 39124 _3DSTATE_HS_VectorMaskEnable_start(const struct gen_device_info *devinfo) 39125 { 39126 switch (devinfo->gen) { 39127 case 10: return 250; 39128 case 9: return 250; 39129 case 8: return 250; 39130 case 7: 39131 if (devinfo->is_haswell) { 39132 return 186; 39133 } else { 39134 return 186; 39135 } 39136 case 6: return 0; 39137 case 5: return 0; 39138 case 4: 39139 if (devinfo->is_g4x) { 39140 return 0; 39141 } else { 39142 return 0; 39143 } 39144 default: 39145 unreachable("Invalid hardware generation"); 39146 } 39147 } 39148 39149 39150 39151 /* 3DSTATE_HS::Vertex URB Entry Read Length */ 39152 39153 39154 #define GEN10_3DSTATE_HS_VertexURBEntryReadLength_bits 6 39155 #define GEN9_3DSTATE_HS_VertexURBEntryReadLength_bits 6 39156 #define GEN8_3DSTATE_HS_VertexURBEntryReadLength_bits 6 39157 #define GEN75_3DSTATE_HS_VertexURBEntryReadLength_bits 6 39158 #define GEN7_3DSTATE_HS_VertexURBEntryReadLength_bits 6 39159 39160 static inline uint32_t ATTRIBUTE_PURE 39161 _3DSTATE_HS_VertexURBEntryReadLength_bits(const struct gen_device_info *devinfo) 39162 { 39163 switch (devinfo->gen) { 39164 case 10: return 6; 39165 case 9: return 6; 39166 case 8: return 6; 39167 case 7: 39168 if (devinfo->is_haswell) { 39169 return 6; 39170 } else { 39171 return 6; 39172 } 39173 case 6: return 0; 39174 case 5: return 0; 39175 case 4: 39176 if (devinfo->is_g4x) { 39177 return 0; 39178 } else { 39179 return 0; 39180 } 39181 default: 39182 unreachable("Invalid hardware generation"); 39183 } 39184 } 39185 39186 39187 39188 #define GEN10_3DSTATE_HS_VertexURBEntryReadLength_start 235 39189 #define GEN9_3DSTATE_HS_VertexURBEntryReadLength_start 235 39190 #define GEN8_3DSTATE_HS_VertexURBEntryReadLength_start 235 39191 #define GEN75_3DSTATE_HS_VertexURBEntryReadLength_start 171 39192 #define GEN7_3DSTATE_HS_VertexURBEntryReadLength_start 171 39193 39194 static inline uint32_t ATTRIBUTE_PURE 39195 _3DSTATE_HS_VertexURBEntryReadLength_start(const struct gen_device_info *devinfo) 39196 { 39197 switch (devinfo->gen) { 39198 case 10: return 235; 39199 case 9: return 235; 39200 case 8: return 235; 39201 case 7: 39202 if (devinfo->is_haswell) { 39203 return 171; 39204 } else { 39205 return 171; 39206 } 39207 case 6: return 0; 39208 case 5: return 0; 39209 case 4: 39210 if (devinfo->is_g4x) { 39211 return 0; 39212 } else { 39213 return 0; 39214 } 39215 default: 39216 unreachable("Invalid hardware generation"); 39217 } 39218 } 39219 39220 39221 39222 /* 3DSTATE_HS::Vertex URB Entry Read Offset */ 39223 39224 39225 #define GEN10_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 39226 #define GEN9_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 39227 #define GEN8_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 39228 #define GEN75_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 39229 #define GEN7_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 39230 39231 static inline uint32_t ATTRIBUTE_PURE 39232 _3DSTATE_HS_VertexURBEntryReadOffset_bits(const struct gen_device_info *devinfo) 39233 { 39234 switch (devinfo->gen) { 39235 case 10: return 6; 39236 case 9: return 6; 39237 case 8: return 6; 39238 case 7: 39239 if (devinfo->is_haswell) { 39240 return 6; 39241 } else { 39242 return 6; 39243 } 39244 case 6: return 0; 39245 case 5: return 0; 39246 case 4: 39247 if (devinfo->is_g4x) { 39248 return 0; 39249 } else { 39250 return 0; 39251 } 39252 default: 39253 unreachable("Invalid hardware generation"); 39254 } 39255 } 39256 39257 39258 39259 #define GEN10_3DSTATE_HS_VertexURBEntryReadOffset_start 228 39260 #define GEN9_3DSTATE_HS_VertexURBEntryReadOffset_start 228 39261 #define GEN8_3DSTATE_HS_VertexURBEntryReadOffset_start 228 39262 #define GEN75_3DSTATE_HS_VertexURBEntryReadOffset_start 164 39263 #define GEN7_3DSTATE_HS_VertexURBEntryReadOffset_start 164 39264 39265 static inline uint32_t ATTRIBUTE_PURE 39266 _3DSTATE_HS_VertexURBEntryReadOffset_start(const struct gen_device_info *devinfo) 39267 { 39268 switch (devinfo->gen) { 39269 case 10: return 228; 39270 case 9: return 228; 39271 case 8: return 228; 39272 case 7: 39273 if (devinfo->is_haswell) { 39274 return 164; 39275 } else { 39276 return 164; 39277 } 39278 case 6: return 0; 39279 case 5: return 0; 39280 case 4: 39281 if (devinfo->is_g4x) { 39282 return 0; 39283 } else { 39284 return 0; 39285 } 39286 default: 39287 unreachable("Invalid hardware generation"); 39288 } 39289 } 39290 39291 39292 39293 /* 3DSTATE_INDEX_BUFFER */ 39294 39295 39296 #define GEN10_3DSTATE_INDEX_BUFFER_length 5 39297 #define GEN9_3DSTATE_INDEX_BUFFER_length 5 39298 #define GEN8_3DSTATE_INDEX_BUFFER_length 5 39299 #define GEN75_3DSTATE_INDEX_BUFFER_length 3 39300 #define GEN7_3DSTATE_INDEX_BUFFER_length 3 39301 #define GEN6_3DSTATE_INDEX_BUFFER_length 3 39302 #define GEN5_3DSTATE_INDEX_BUFFER_length 3 39303 #define GEN45_3DSTATE_INDEX_BUFFER_length 3 39304 #define GEN4_3DSTATE_INDEX_BUFFER_length 3 39305 39306 static inline uint32_t ATTRIBUTE_PURE 39307 _3DSTATE_INDEX_BUFFER_length(const struct gen_device_info *devinfo) 39308 { 39309 switch (devinfo->gen) { 39310 case 10: return 5; 39311 case 9: return 5; 39312 case 8: return 5; 39313 case 7: 39314 if (devinfo->is_haswell) { 39315 return 3; 39316 } else { 39317 return 3; 39318 } 39319 case 6: return 3; 39320 case 5: return 3; 39321 case 4: 39322 if (devinfo->is_g4x) { 39323 return 3; 39324 } else { 39325 return 3; 39326 } 39327 default: 39328 unreachable("Invalid hardware generation"); 39329 } 39330 } 39331 39332 39333 39334 /* 3DSTATE_INDEX_BUFFER::3D Command Opcode */ 39335 39336 39337 #define GEN10_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 39338 #define GEN9_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 39339 #define GEN8_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 39340 #define GEN75_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 39341 #define GEN7_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 39342 #define GEN6_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 39343 #define GEN5_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 39344 #define GEN45_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 39345 #define GEN4_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 39346 39347 static inline uint32_t ATTRIBUTE_PURE 39348 _3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 39349 { 39350 switch (devinfo->gen) { 39351 case 10: return 3; 39352 case 9: return 3; 39353 case 8: return 3; 39354 case 7: 39355 if (devinfo->is_haswell) { 39356 return 3; 39357 } else { 39358 return 3; 39359 } 39360 case 6: return 3; 39361 case 5: return 3; 39362 case 4: 39363 if (devinfo->is_g4x) { 39364 return 3; 39365 } else { 39366 return 3; 39367 } 39368 default: 39369 unreachable("Invalid hardware generation"); 39370 } 39371 } 39372 39373 39374 39375 #define GEN10_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 39376 #define GEN9_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 39377 #define GEN8_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 39378 #define GEN75_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 39379 #define GEN7_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 39380 #define GEN6_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 39381 #define GEN5_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 39382 #define GEN45_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 39383 #define GEN4_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 39384 39385 static inline uint32_t ATTRIBUTE_PURE 39386 _3DSTATE_INDEX_BUFFER_3DCommandOpcode_start(const struct gen_device_info *devinfo) 39387 { 39388 switch (devinfo->gen) { 39389 case 10: return 24; 39390 case 9: return 24; 39391 case 8: return 24; 39392 case 7: 39393 if (devinfo->is_haswell) { 39394 return 24; 39395 } else { 39396 return 24; 39397 } 39398 case 6: return 24; 39399 case 5: return 24; 39400 case 4: 39401 if (devinfo->is_g4x) { 39402 return 24; 39403 } else { 39404 return 24; 39405 } 39406 default: 39407 unreachable("Invalid hardware generation"); 39408 } 39409 } 39410 39411 39412 39413 /* 3DSTATE_INDEX_BUFFER::3D Command Sub Opcode */ 39414 39415 39416 #define GEN10_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 39417 #define GEN9_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 39418 #define GEN8_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 39419 #define GEN75_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 39420 #define GEN7_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 39421 #define GEN6_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 39422 #define GEN5_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 39423 #define GEN45_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 39424 #define GEN4_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 39425 39426 static inline uint32_t ATTRIBUTE_PURE 39427 _3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 39428 { 39429 switch (devinfo->gen) { 39430 case 10: return 8; 39431 case 9: return 8; 39432 case 8: return 8; 39433 case 7: 39434 if (devinfo->is_haswell) { 39435 return 8; 39436 } else { 39437 return 8; 39438 } 39439 case 6: return 8; 39440 case 5: return 8; 39441 case 4: 39442 if (devinfo->is_g4x) { 39443 return 8; 39444 } else { 39445 return 8; 39446 } 39447 default: 39448 unreachable("Invalid hardware generation"); 39449 } 39450 } 39451 39452 39453 39454 #define GEN10_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 39455 #define GEN9_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 39456 #define GEN8_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 39457 #define GEN75_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 39458 #define GEN7_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 39459 #define GEN6_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 39460 #define GEN5_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 39461 #define GEN45_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 39462 #define GEN4_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 39463 39464 static inline uint32_t ATTRIBUTE_PURE 39465 _3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 39466 { 39467 switch (devinfo->gen) { 39468 case 10: return 16; 39469 case 9: return 16; 39470 case 8: return 16; 39471 case 7: 39472 if (devinfo->is_haswell) { 39473 return 16; 39474 } else { 39475 return 16; 39476 } 39477 case 6: return 16; 39478 case 5: return 16; 39479 case 4: 39480 if (devinfo->is_g4x) { 39481 return 16; 39482 } else { 39483 return 16; 39484 } 39485 default: 39486 unreachable("Invalid hardware generation"); 39487 } 39488 } 39489 39490 39491 39492 /* 3DSTATE_INDEX_BUFFER::Buffer Ending Address */ 39493 39494 39495 #define GEN75_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 39496 #define GEN7_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 39497 #define GEN6_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 39498 #define GEN5_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 39499 #define GEN45_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 39500 #define GEN4_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 39501 39502 static inline uint32_t ATTRIBUTE_PURE 39503 _3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits(const struct gen_device_info *devinfo) 39504 { 39505 switch (devinfo->gen) { 39506 case 10: return 0; 39507 case 9: return 0; 39508 case 8: return 0; 39509 case 7: 39510 if (devinfo->is_haswell) { 39511 return 32; 39512 } else { 39513 return 32; 39514 } 39515 case 6: return 32; 39516 case 5: return 32; 39517 case 4: 39518 if (devinfo->is_g4x) { 39519 return 32; 39520 } else { 39521 return 32; 39522 } 39523 default: 39524 unreachable("Invalid hardware generation"); 39525 } 39526 } 39527 39528 39529 39530 #define GEN75_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 39531 #define GEN7_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 39532 #define GEN6_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 39533 #define GEN5_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 39534 #define GEN45_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 39535 #define GEN4_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 39536 39537 static inline uint32_t ATTRIBUTE_PURE 39538 _3DSTATE_INDEX_BUFFER_BufferEndingAddress_start(const struct gen_device_info *devinfo) 39539 { 39540 switch (devinfo->gen) { 39541 case 10: return 0; 39542 case 9: return 0; 39543 case 8: return 0; 39544 case 7: 39545 if (devinfo->is_haswell) { 39546 return 64; 39547 } else { 39548 return 64; 39549 } 39550 case 6: return 64; 39551 case 5: return 64; 39552 case 4: 39553 if (devinfo->is_g4x) { 39554 return 64; 39555 } else { 39556 return 64; 39557 } 39558 default: 39559 unreachable("Invalid hardware generation"); 39560 } 39561 } 39562 39563 39564 39565 /* 3DSTATE_INDEX_BUFFER::Buffer Size */ 39566 39567 39568 #define GEN10_3DSTATE_INDEX_BUFFER_BufferSize_bits 32 39569 #define GEN9_3DSTATE_INDEX_BUFFER_BufferSize_bits 32 39570 #define GEN8_3DSTATE_INDEX_BUFFER_BufferSize_bits 32 39571 39572 static inline uint32_t ATTRIBUTE_PURE 39573 _3DSTATE_INDEX_BUFFER_BufferSize_bits(const struct gen_device_info *devinfo) 39574 { 39575 switch (devinfo->gen) { 39576 case 10: return 32; 39577 case 9: return 32; 39578 case 8: return 32; 39579 case 7: 39580 if (devinfo->is_haswell) { 39581 return 0; 39582 } else { 39583 return 0; 39584 } 39585 case 6: return 0; 39586 case 5: return 0; 39587 case 4: 39588 if (devinfo->is_g4x) { 39589 return 0; 39590 } else { 39591 return 0; 39592 } 39593 default: 39594 unreachable("Invalid hardware generation"); 39595 } 39596 } 39597 39598 39599 39600 #define GEN10_3DSTATE_INDEX_BUFFER_BufferSize_start 128 39601 #define GEN9_3DSTATE_INDEX_BUFFER_BufferSize_start 128 39602 #define GEN8_3DSTATE_INDEX_BUFFER_BufferSize_start 128 39603 39604 static inline uint32_t ATTRIBUTE_PURE 39605 _3DSTATE_INDEX_BUFFER_BufferSize_start(const struct gen_device_info *devinfo) 39606 { 39607 switch (devinfo->gen) { 39608 case 10: return 128; 39609 case 9: return 128; 39610 case 8: return 128; 39611 case 7: 39612 if (devinfo->is_haswell) { 39613 return 0; 39614 } else { 39615 return 0; 39616 } 39617 case 6: return 0; 39618 case 5: return 0; 39619 case 4: 39620 if (devinfo->is_g4x) { 39621 return 0; 39622 } else { 39623 return 0; 39624 } 39625 default: 39626 unreachable("Invalid hardware generation"); 39627 } 39628 } 39629 39630 39631 39632 /* 3DSTATE_INDEX_BUFFER::Buffer Starting Address */ 39633 39634 39635 #define GEN10_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 64 39636 #define GEN9_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 64 39637 #define GEN8_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 64 39638 #define GEN75_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 39639 #define GEN7_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 39640 #define GEN6_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 39641 #define GEN5_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 39642 #define GEN45_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 39643 #define GEN4_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 39644 39645 static inline uint32_t ATTRIBUTE_PURE 39646 _3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits(const struct gen_device_info *devinfo) 39647 { 39648 switch (devinfo->gen) { 39649 case 10: return 64; 39650 case 9: return 64; 39651 case 8: return 64; 39652 case 7: 39653 if (devinfo->is_haswell) { 39654 return 32; 39655 } else { 39656 return 32; 39657 } 39658 case 6: return 32; 39659 case 5: return 32; 39660 case 4: 39661 if (devinfo->is_g4x) { 39662 return 32; 39663 } else { 39664 return 32; 39665 } 39666 default: 39667 unreachable("Invalid hardware generation"); 39668 } 39669 } 39670 39671 39672 39673 #define GEN10_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 64 39674 #define GEN9_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 64 39675 #define GEN8_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 64 39676 #define GEN75_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 39677 #define GEN7_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 39678 #define GEN6_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 39679 #define GEN5_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 39680 #define GEN45_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 39681 #define GEN4_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 39682 39683 static inline uint32_t ATTRIBUTE_PURE 39684 _3DSTATE_INDEX_BUFFER_BufferStartingAddress_start(const struct gen_device_info *devinfo) 39685 { 39686 switch (devinfo->gen) { 39687 case 10: return 64; 39688 case 9: return 64; 39689 case 8: return 64; 39690 case 7: 39691 if (devinfo->is_haswell) { 39692 return 32; 39693 } else { 39694 return 32; 39695 } 39696 case 6: return 32; 39697 case 5: return 32; 39698 case 4: 39699 if (devinfo->is_g4x) { 39700 return 32; 39701 } else { 39702 return 32; 39703 } 39704 default: 39705 unreachable("Invalid hardware generation"); 39706 } 39707 } 39708 39709 39710 39711 /* 3DSTATE_INDEX_BUFFER::Command SubType */ 39712 39713 39714 #define GEN10_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 39715 #define GEN9_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 39716 #define GEN8_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 39717 #define GEN75_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 39718 #define GEN7_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 39719 #define GEN6_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 39720 #define GEN5_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 39721 #define GEN45_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 39722 #define GEN4_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 39723 39724 static inline uint32_t ATTRIBUTE_PURE 39725 _3DSTATE_INDEX_BUFFER_CommandSubType_bits(const struct gen_device_info *devinfo) 39726 { 39727 switch (devinfo->gen) { 39728 case 10: return 2; 39729 case 9: return 2; 39730 case 8: return 2; 39731 case 7: 39732 if (devinfo->is_haswell) { 39733 return 2; 39734 } else { 39735 return 2; 39736 } 39737 case 6: return 2; 39738 case 5: return 2; 39739 case 4: 39740 if (devinfo->is_g4x) { 39741 return 2; 39742 } else { 39743 return 2; 39744 } 39745 default: 39746 unreachable("Invalid hardware generation"); 39747 } 39748 } 39749 39750 39751 39752 #define GEN10_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 39753 #define GEN9_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 39754 #define GEN8_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 39755 #define GEN75_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 39756 #define GEN7_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 39757 #define GEN6_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 39758 #define GEN5_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 39759 #define GEN45_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 39760 #define GEN4_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 39761 39762 static inline uint32_t ATTRIBUTE_PURE 39763 _3DSTATE_INDEX_BUFFER_CommandSubType_start(const struct gen_device_info *devinfo) 39764 { 39765 switch (devinfo->gen) { 39766 case 10: return 27; 39767 case 9: return 27; 39768 case 8: return 27; 39769 case 7: 39770 if (devinfo->is_haswell) { 39771 return 27; 39772 } else { 39773 return 27; 39774 } 39775 case 6: return 27; 39776 case 5: return 27; 39777 case 4: 39778 if (devinfo->is_g4x) { 39779 return 27; 39780 } else { 39781 return 27; 39782 } 39783 default: 39784 unreachable("Invalid hardware generation"); 39785 } 39786 } 39787 39788 39789 39790 /* 3DSTATE_INDEX_BUFFER::Command Type */ 39791 39792 39793 #define GEN10_3DSTATE_INDEX_BUFFER_CommandType_bits 3 39794 #define GEN9_3DSTATE_INDEX_BUFFER_CommandType_bits 3 39795 #define GEN8_3DSTATE_INDEX_BUFFER_CommandType_bits 3 39796 #define GEN75_3DSTATE_INDEX_BUFFER_CommandType_bits 3 39797 #define GEN7_3DSTATE_INDEX_BUFFER_CommandType_bits 3 39798 #define GEN6_3DSTATE_INDEX_BUFFER_CommandType_bits 3 39799 #define GEN5_3DSTATE_INDEX_BUFFER_CommandType_bits 3 39800 #define GEN45_3DSTATE_INDEX_BUFFER_CommandType_bits 3 39801 #define GEN4_3DSTATE_INDEX_BUFFER_CommandType_bits 3 39802 39803 static inline uint32_t ATTRIBUTE_PURE 39804 _3DSTATE_INDEX_BUFFER_CommandType_bits(const struct gen_device_info *devinfo) 39805 { 39806 switch (devinfo->gen) { 39807 case 10: return 3; 39808 case 9: return 3; 39809 case 8: return 3; 39810 case 7: 39811 if (devinfo->is_haswell) { 39812 return 3; 39813 } else { 39814 return 3; 39815 } 39816 case 6: return 3; 39817 case 5: return 3; 39818 case 4: 39819 if (devinfo->is_g4x) { 39820 return 3; 39821 } else { 39822 return 3; 39823 } 39824 default: 39825 unreachable("Invalid hardware generation"); 39826 } 39827 } 39828 39829 39830 39831 #define GEN10_3DSTATE_INDEX_BUFFER_CommandType_start 29 39832 #define GEN9_3DSTATE_INDEX_BUFFER_CommandType_start 29 39833 #define GEN8_3DSTATE_INDEX_BUFFER_CommandType_start 29 39834 #define GEN75_3DSTATE_INDEX_BUFFER_CommandType_start 29 39835 #define GEN7_3DSTATE_INDEX_BUFFER_CommandType_start 29 39836 #define GEN6_3DSTATE_INDEX_BUFFER_CommandType_start 29 39837 #define GEN5_3DSTATE_INDEX_BUFFER_CommandType_start 29 39838 #define GEN45_3DSTATE_INDEX_BUFFER_CommandType_start 29 39839 #define GEN4_3DSTATE_INDEX_BUFFER_CommandType_start 29 39840 39841 static inline uint32_t ATTRIBUTE_PURE 39842 _3DSTATE_INDEX_BUFFER_CommandType_start(const struct gen_device_info *devinfo) 39843 { 39844 switch (devinfo->gen) { 39845 case 10: return 29; 39846 case 9: return 29; 39847 case 8: return 29; 39848 case 7: 39849 if (devinfo->is_haswell) { 39850 return 29; 39851 } else { 39852 return 29; 39853 } 39854 case 6: return 29; 39855 case 5: return 29; 39856 case 4: 39857 if (devinfo->is_g4x) { 39858 return 29; 39859 } else { 39860 return 29; 39861 } 39862 default: 39863 unreachable("Invalid hardware generation"); 39864 } 39865 } 39866 39867 39868 39869 /* 3DSTATE_INDEX_BUFFER::Cut Index Enable */ 39870 39871 39872 #define GEN7_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 39873 #define GEN6_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 39874 #define GEN5_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 39875 #define GEN45_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 39876 #define GEN4_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 39877 39878 static inline uint32_t ATTRIBUTE_PURE 39879 _3DSTATE_INDEX_BUFFER_CutIndexEnable_bits(const struct gen_device_info *devinfo) 39880 { 39881 switch (devinfo->gen) { 39882 case 10: return 0; 39883 case 9: return 0; 39884 case 8: return 0; 39885 case 7: 39886 if (devinfo->is_haswell) { 39887 return 0; 39888 } else { 39889 return 1; 39890 } 39891 case 6: return 1; 39892 case 5: return 1; 39893 case 4: 39894 if (devinfo->is_g4x) { 39895 return 1; 39896 } else { 39897 return 1; 39898 } 39899 default: 39900 unreachable("Invalid hardware generation"); 39901 } 39902 } 39903 39904 39905 39906 #define GEN7_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 39907 #define GEN6_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 39908 #define GEN5_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 39909 #define GEN45_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 39910 #define GEN4_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 39911 39912 static inline uint32_t ATTRIBUTE_PURE 39913 _3DSTATE_INDEX_BUFFER_CutIndexEnable_start(const struct gen_device_info *devinfo) 39914 { 39915 switch (devinfo->gen) { 39916 case 10: return 0; 39917 case 9: return 0; 39918 case 8: return 0; 39919 case 7: 39920 if (devinfo->is_haswell) { 39921 return 0; 39922 } else { 39923 return 10; 39924 } 39925 case 6: return 10; 39926 case 5: return 10; 39927 case 4: 39928 if (devinfo->is_g4x) { 39929 return 10; 39930 } else { 39931 return 10; 39932 } 39933 default: 39934 unreachable("Invalid hardware generation"); 39935 } 39936 } 39937 39938 39939 39940 /* 3DSTATE_INDEX_BUFFER::DWord Length */ 39941 39942 39943 #define GEN10_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 39944 #define GEN9_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 39945 #define GEN8_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 39946 #define GEN75_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 39947 #define GEN7_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 39948 #define GEN6_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 39949 #define GEN5_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 39950 #define GEN45_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 39951 #define GEN4_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 39952 39953 static inline uint32_t ATTRIBUTE_PURE 39954 _3DSTATE_INDEX_BUFFER_DWordLength_bits(const struct gen_device_info *devinfo) 39955 { 39956 switch (devinfo->gen) { 39957 case 10: return 8; 39958 case 9: return 8; 39959 case 8: return 8; 39960 case 7: 39961 if (devinfo->is_haswell) { 39962 return 8; 39963 } else { 39964 return 8; 39965 } 39966 case 6: return 8; 39967 case 5: return 8; 39968 case 4: 39969 if (devinfo->is_g4x) { 39970 return 8; 39971 } else { 39972 return 8; 39973 } 39974 default: 39975 unreachable("Invalid hardware generation"); 39976 } 39977 } 39978 39979 39980 39981 #define GEN10_3DSTATE_INDEX_BUFFER_DWordLength_start 0 39982 #define GEN9_3DSTATE_INDEX_BUFFER_DWordLength_start 0 39983 #define GEN8_3DSTATE_INDEX_BUFFER_DWordLength_start 0 39984 #define GEN75_3DSTATE_INDEX_BUFFER_DWordLength_start 0 39985 #define GEN7_3DSTATE_INDEX_BUFFER_DWordLength_start 0 39986 #define GEN6_3DSTATE_INDEX_BUFFER_DWordLength_start 0 39987 #define GEN5_3DSTATE_INDEX_BUFFER_DWordLength_start 0 39988 #define GEN45_3DSTATE_INDEX_BUFFER_DWordLength_start 0 39989 #define GEN4_3DSTATE_INDEX_BUFFER_DWordLength_start 0 39990 39991 static inline uint32_t ATTRIBUTE_PURE 39992 _3DSTATE_INDEX_BUFFER_DWordLength_start(const struct gen_device_info *devinfo) 39993 { 39994 switch (devinfo->gen) { 39995 case 10: return 0; 39996 case 9: return 0; 39997 case 8: return 0; 39998 case 7: 39999 if (devinfo->is_haswell) { 40000 return 0; 40001 } else { 40002 return 0; 40003 } 40004 case 6: return 0; 40005 case 5: return 0; 40006 case 4: 40007 if (devinfo->is_g4x) { 40008 return 0; 40009 } else { 40010 return 0; 40011 } 40012 default: 40013 unreachable("Invalid hardware generation"); 40014 } 40015 } 40016 40017 40018 40019 /* 3DSTATE_INDEX_BUFFER::Index Format */ 40020 40021 40022 #define GEN10_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 40023 #define GEN9_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 40024 #define GEN8_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 40025 #define GEN75_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 40026 #define GEN7_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 40027 #define GEN6_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 40028 #define GEN5_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 40029 #define GEN45_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 40030 #define GEN4_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 40031 40032 static inline uint32_t ATTRIBUTE_PURE 40033 _3DSTATE_INDEX_BUFFER_IndexFormat_bits(const struct gen_device_info *devinfo) 40034 { 40035 switch (devinfo->gen) { 40036 case 10: return 2; 40037 case 9: return 2; 40038 case 8: return 2; 40039 case 7: 40040 if (devinfo->is_haswell) { 40041 return 2; 40042 } else { 40043 return 2; 40044 } 40045 case 6: return 2; 40046 case 5: return 2; 40047 case 4: 40048 if (devinfo->is_g4x) { 40049 return 2; 40050 } else { 40051 return 2; 40052 } 40053 default: 40054 unreachable("Invalid hardware generation"); 40055 } 40056 } 40057 40058 40059 40060 #define GEN10_3DSTATE_INDEX_BUFFER_IndexFormat_start 40 40061 #define GEN9_3DSTATE_INDEX_BUFFER_IndexFormat_start 40 40062 #define GEN8_3DSTATE_INDEX_BUFFER_IndexFormat_start 40 40063 #define GEN75_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 40064 #define GEN7_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 40065 #define GEN6_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 40066 #define GEN5_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 40067 #define GEN45_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 40068 #define GEN4_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 40069 40070 static inline uint32_t ATTRIBUTE_PURE 40071 _3DSTATE_INDEX_BUFFER_IndexFormat_start(const struct gen_device_info *devinfo) 40072 { 40073 switch (devinfo->gen) { 40074 case 10: return 40; 40075 case 9: return 40; 40076 case 8: return 40; 40077 case 7: 40078 if (devinfo->is_haswell) { 40079 return 8; 40080 } else { 40081 return 8; 40082 } 40083 case 6: return 8; 40084 case 5: return 8; 40085 case 4: 40086 if (devinfo->is_g4x) { 40087 return 8; 40088 } else { 40089 return 8; 40090 } 40091 default: 40092 unreachable("Invalid hardware generation"); 40093 } 40094 } 40095 40096 40097 40098 /* 3DSTATE_INDEX_BUFFER::IndexBufferMOCS */ 40099 40100 40101 #define GEN10_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 7 40102 #define GEN9_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 7 40103 #define GEN8_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 7 40104 #define GEN75_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 4 40105 #define GEN7_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 4 40106 #define GEN6_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 4 40107 40108 static inline uint32_t ATTRIBUTE_PURE 40109 _3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits(const struct gen_device_info *devinfo) 40110 { 40111 switch (devinfo->gen) { 40112 case 10: return 7; 40113 case 9: return 7; 40114 case 8: return 7; 40115 case 7: 40116 if (devinfo->is_haswell) { 40117 return 4; 40118 } else { 40119 return 4; 40120 } 40121 case 6: return 4; 40122 case 5: return 0; 40123 case 4: 40124 if (devinfo->is_g4x) { 40125 return 0; 40126 } else { 40127 return 0; 40128 } 40129 default: 40130 unreachable("Invalid hardware generation"); 40131 } 40132 } 40133 40134 40135 40136 #define GEN10_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 32 40137 #define GEN9_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 32 40138 #define GEN8_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 32 40139 #define GEN75_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 12 40140 #define GEN7_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 12 40141 #define GEN6_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 12 40142 40143 static inline uint32_t ATTRIBUTE_PURE 40144 _3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start(const struct gen_device_info *devinfo) 40145 { 40146 switch (devinfo->gen) { 40147 case 10: return 32; 40148 case 9: return 32; 40149 case 8: return 32; 40150 case 7: 40151 if (devinfo->is_haswell) { 40152 return 12; 40153 } else { 40154 return 12; 40155 } 40156 case 6: return 12; 40157 case 5: return 0; 40158 case 4: 40159 if (devinfo->is_g4x) { 40160 return 0; 40161 } else { 40162 return 0; 40163 } 40164 default: 40165 unreachable("Invalid hardware generation"); 40166 } 40167 } 40168 40169 40170 40171 /* 3DSTATE_INDEX_BUFFER::Memory Object Control State */ 40172 40173 40174 #define GEN10_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 7 40175 #define GEN9_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 7 40176 #define GEN8_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 7 40177 #define GEN75_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 4 40178 #define GEN7_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 4 40179 #define GEN6_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 4 40180 40181 static inline uint32_t ATTRIBUTE_PURE 40182 _3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits(const struct gen_device_info *devinfo) 40183 { 40184 switch (devinfo->gen) { 40185 case 10: return 7; 40186 case 9: return 7; 40187 case 8: return 7; 40188 case 7: 40189 if (devinfo->is_haswell) { 40190 return 4; 40191 } else { 40192 return 4; 40193 } 40194 case 6: return 4; 40195 case 5: return 0; 40196 case 4: 40197 if (devinfo->is_g4x) { 40198 return 0; 40199 } else { 40200 return 0; 40201 } 40202 default: 40203 unreachable("Invalid hardware generation"); 40204 } 40205 } 40206 40207 40208 40209 #define GEN10_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 32 40210 #define GEN9_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 32 40211 #define GEN8_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 32 40212 #define GEN75_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 12 40213 #define GEN7_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 12 40214 #define GEN6_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 12 40215 40216 static inline uint32_t ATTRIBUTE_PURE 40217 _3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start(const struct gen_device_info *devinfo) 40218 { 40219 switch (devinfo->gen) { 40220 case 10: return 32; 40221 case 9: return 32; 40222 case 8: return 32; 40223 case 7: 40224 if (devinfo->is_haswell) { 40225 return 12; 40226 } else { 40227 return 12; 40228 } 40229 case 6: return 12; 40230 case 5: return 0; 40231 case 4: 40232 if (devinfo->is_g4x) { 40233 return 0; 40234 } else { 40235 return 0; 40236 } 40237 default: 40238 unreachable("Invalid hardware generation"); 40239 } 40240 } 40241 40242 40243 40244 /* 3DSTATE_LINE_STIPPLE */ 40245 40246 40247 #define GEN10_3DSTATE_LINE_STIPPLE_length 3 40248 #define GEN9_3DSTATE_LINE_STIPPLE_length 3 40249 #define GEN8_3DSTATE_LINE_STIPPLE_length 3 40250 #define GEN75_3DSTATE_LINE_STIPPLE_length 3 40251 #define GEN7_3DSTATE_LINE_STIPPLE_length 3 40252 #define GEN6_3DSTATE_LINE_STIPPLE_length 3 40253 #define GEN5_3DSTATE_LINE_STIPPLE_length 3 40254 #define GEN45_3DSTATE_LINE_STIPPLE_length 3 40255 #define GEN4_3DSTATE_LINE_STIPPLE_length 3 40256 40257 static inline uint32_t ATTRIBUTE_PURE 40258 _3DSTATE_LINE_STIPPLE_length(const struct gen_device_info *devinfo) 40259 { 40260 switch (devinfo->gen) { 40261 case 10: return 3; 40262 case 9: return 3; 40263 case 8: return 3; 40264 case 7: 40265 if (devinfo->is_haswell) { 40266 return 3; 40267 } else { 40268 return 3; 40269 } 40270 case 6: return 3; 40271 case 5: return 3; 40272 case 4: 40273 if (devinfo->is_g4x) { 40274 return 3; 40275 } else { 40276 return 3; 40277 } 40278 default: 40279 unreachable("Invalid hardware generation"); 40280 } 40281 } 40282 40283 40284 40285 /* 3DSTATE_LINE_STIPPLE::3D Command Opcode */ 40286 40287 40288 #define GEN10_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 40289 #define GEN9_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 40290 #define GEN8_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 40291 #define GEN75_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 40292 #define GEN7_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 40293 #define GEN6_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 40294 #define GEN5_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 40295 #define GEN45_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 40296 #define GEN4_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 40297 40298 static inline uint32_t ATTRIBUTE_PURE 40299 _3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 40300 { 40301 switch (devinfo->gen) { 40302 case 10: return 3; 40303 case 9: return 3; 40304 case 8: return 3; 40305 case 7: 40306 if (devinfo->is_haswell) { 40307 return 3; 40308 } else { 40309 return 3; 40310 } 40311 case 6: return 3; 40312 case 5: return 3; 40313 case 4: 40314 if (devinfo->is_g4x) { 40315 return 3; 40316 } else { 40317 return 3; 40318 } 40319 default: 40320 unreachable("Invalid hardware generation"); 40321 } 40322 } 40323 40324 40325 40326 #define GEN10_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 40327 #define GEN9_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 40328 #define GEN8_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 40329 #define GEN75_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 40330 #define GEN7_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 40331 #define GEN6_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 40332 #define GEN5_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 40333 #define GEN45_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 40334 #define GEN4_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 40335 40336 static inline uint32_t ATTRIBUTE_PURE 40337 _3DSTATE_LINE_STIPPLE_3DCommandOpcode_start(const struct gen_device_info *devinfo) 40338 { 40339 switch (devinfo->gen) { 40340 case 10: return 24; 40341 case 9: return 24; 40342 case 8: return 24; 40343 case 7: 40344 if (devinfo->is_haswell) { 40345 return 24; 40346 } else { 40347 return 24; 40348 } 40349 case 6: return 24; 40350 case 5: return 24; 40351 case 4: 40352 if (devinfo->is_g4x) { 40353 return 24; 40354 } else { 40355 return 24; 40356 } 40357 default: 40358 unreachable("Invalid hardware generation"); 40359 } 40360 } 40361 40362 40363 40364 /* 3DSTATE_LINE_STIPPLE::3D Command Sub Opcode */ 40365 40366 40367 #define GEN10_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 40368 #define GEN9_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 40369 #define GEN8_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 40370 #define GEN75_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 40371 #define GEN7_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 40372 #define GEN6_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 40373 #define GEN5_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 40374 #define GEN45_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 40375 #define GEN4_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 40376 40377 static inline uint32_t ATTRIBUTE_PURE 40378 _3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 40379 { 40380 switch (devinfo->gen) { 40381 case 10: return 8; 40382 case 9: return 8; 40383 case 8: return 8; 40384 case 7: 40385 if (devinfo->is_haswell) { 40386 return 8; 40387 } else { 40388 return 8; 40389 } 40390 case 6: return 8; 40391 case 5: return 8; 40392 case 4: 40393 if (devinfo->is_g4x) { 40394 return 8; 40395 } else { 40396 return 8; 40397 } 40398 default: 40399 unreachable("Invalid hardware generation"); 40400 } 40401 } 40402 40403 40404 40405 #define GEN10_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 40406 #define GEN9_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 40407 #define GEN8_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 40408 #define GEN75_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 40409 #define GEN7_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 40410 #define GEN6_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 40411 #define GEN5_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 40412 #define GEN45_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 40413 #define GEN4_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 40414 40415 static inline uint32_t ATTRIBUTE_PURE 40416 _3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 40417 { 40418 switch (devinfo->gen) { 40419 case 10: return 16; 40420 case 9: return 16; 40421 case 8: return 16; 40422 case 7: 40423 if (devinfo->is_haswell) { 40424 return 16; 40425 } else { 40426 return 16; 40427 } 40428 case 6: return 16; 40429 case 5: return 16; 40430 case 4: 40431 if (devinfo->is_g4x) { 40432 return 16; 40433 } else { 40434 return 16; 40435 } 40436 default: 40437 unreachable("Invalid hardware generation"); 40438 } 40439 } 40440 40441 40442 40443 /* 3DSTATE_LINE_STIPPLE::Command SubType */ 40444 40445 40446 #define GEN10_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 40447 #define GEN9_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 40448 #define GEN8_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 40449 #define GEN75_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 40450 #define GEN7_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 40451 #define GEN6_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 40452 #define GEN5_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 40453 #define GEN45_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 40454 #define GEN4_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 40455 40456 static inline uint32_t ATTRIBUTE_PURE 40457 _3DSTATE_LINE_STIPPLE_CommandSubType_bits(const struct gen_device_info *devinfo) 40458 { 40459 switch (devinfo->gen) { 40460 case 10: return 2; 40461 case 9: return 2; 40462 case 8: return 2; 40463 case 7: 40464 if (devinfo->is_haswell) { 40465 return 2; 40466 } else { 40467 return 2; 40468 } 40469 case 6: return 2; 40470 case 5: return 2; 40471 case 4: 40472 if (devinfo->is_g4x) { 40473 return 2; 40474 } else { 40475 return 2; 40476 } 40477 default: 40478 unreachable("Invalid hardware generation"); 40479 } 40480 } 40481 40482 40483 40484 #define GEN10_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 40485 #define GEN9_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 40486 #define GEN8_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 40487 #define GEN75_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 40488 #define GEN7_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 40489 #define GEN6_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 40490 #define GEN5_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 40491 #define GEN45_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 40492 #define GEN4_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 40493 40494 static inline uint32_t ATTRIBUTE_PURE 40495 _3DSTATE_LINE_STIPPLE_CommandSubType_start(const struct gen_device_info *devinfo) 40496 { 40497 switch (devinfo->gen) { 40498 case 10: return 27; 40499 case 9: return 27; 40500 case 8: return 27; 40501 case 7: 40502 if (devinfo->is_haswell) { 40503 return 27; 40504 } else { 40505 return 27; 40506 } 40507 case 6: return 27; 40508 case 5: return 27; 40509 case 4: 40510 if (devinfo->is_g4x) { 40511 return 27; 40512 } else { 40513 return 27; 40514 } 40515 default: 40516 unreachable("Invalid hardware generation"); 40517 } 40518 } 40519 40520 40521 40522 /* 3DSTATE_LINE_STIPPLE::Command Type */ 40523 40524 40525 #define GEN10_3DSTATE_LINE_STIPPLE_CommandType_bits 3 40526 #define GEN9_3DSTATE_LINE_STIPPLE_CommandType_bits 3 40527 #define GEN8_3DSTATE_LINE_STIPPLE_CommandType_bits 3 40528 #define GEN75_3DSTATE_LINE_STIPPLE_CommandType_bits 3 40529 #define GEN7_3DSTATE_LINE_STIPPLE_CommandType_bits 3 40530 #define GEN6_3DSTATE_LINE_STIPPLE_CommandType_bits 3 40531 #define GEN5_3DSTATE_LINE_STIPPLE_CommandType_bits 3 40532 #define GEN45_3DSTATE_LINE_STIPPLE_CommandType_bits 3 40533 #define GEN4_3DSTATE_LINE_STIPPLE_CommandType_bits 3 40534 40535 static inline uint32_t ATTRIBUTE_PURE 40536 _3DSTATE_LINE_STIPPLE_CommandType_bits(const struct gen_device_info *devinfo) 40537 { 40538 switch (devinfo->gen) { 40539 case 10: return 3; 40540 case 9: return 3; 40541 case 8: return 3; 40542 case 7: 40543 if (devinfo->is_haswell) { 40544 return 3; 40545 } else { 40546 return 3; 40547 } 40548 case 6: return 3; 40549 case 5: return 3; 40550 case 4: 40551 if (devinfo->is_g4x) { 40552 return 3; 40553 } else { 40554 return 3; 40555 } 40556 default: 40557 unreachable("Invalid hardware generation"); 40558 } 40559 } 40560 40561 40562 40563 #define GEN10_3DSTATE_LINE_STIPPLE_CommandType_start 29 40564 #define GEN9_3DSTATE_LINE_STIPPLE_CommandType_start 29 40565 #define GEN8_3DSTATE_LINE_STIPPLE_CommandType_start 29 40566 #define GEN75_3DSTATE_LINE_STIPPLE_CommandType_start 29 40567 #define GEN7_3DSTATE_LINE_STIPPLE_CommandType_start 29 40568 #define GEN6_3DSTATE_LINE_STIPPLE_CommandType_start 29 40569 #define GEN5_3DSTATE_LINE_STIPPLE_CommandType_start 29 40570 #define GEN45_3DSTATE_LINE_STIPPLE_CommandType_start 29 40571 #define GEN4_3DSTATE_LINE_STIPPLE_CommandType_start 29 40572 40573 static inline uint32_t ATTRIBUTE_PURE 40574 _3DSTATE_LINE_STIPPLE_CommandType_start(const struct gen_device_info *devinfo) 40575 { 40576 switch (devinfo->gen) { 40577 case 10: return 29; 40578 case 9: return 29; 40579 case 8: return 29; 40580 case 7: 40581 if (devinfo->is_haswell) { 40582 return 29; 40583 } else { 40584 return 29; 40585 } 40586 case 6: return 29; 40587 case 5: return 29; 40588 case 4: 40589 if (devinfo->is_g4x) { 40590 return 29; 40591 } else { 40592 return 29; 40593 } 40594 default: 40595 unreachable("Invalid hardware generation"); 40596 } 40597 } 40598 40599 40600 40601 /* 3DSTATE_LINE_STIPPLE::Current Repeat Counter */ 40602 40603 40604 #define GEN10_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 40605 #define GEN9_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 40606 #define GEN8_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 40607 #define GEN75_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 40608 #define GEN7_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 40609 #define GEN6_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 40610 #define GEN5_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 40611 #define GEN45_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 40612 #define GEN4_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 40613 40614 static inline uint32_t ATTRIBUTE_PURE 40615 _3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits(const struct gen_device_info *devinfo) 40616 { 40617 switch (devinfo->gen) { 40618 case 10: return 9; 40619 case 9: return 9; 40620 case 8: return 9; 40621 case 7: 40622 if (devinfo->is_haswell) { 40623 return 9; 40624 } else { 40625 return 9; 40626 } 40627 case 6: return 9; 40628 case 5: return 9; 40629 case 4: 40630 if (devinfo->is_g4x) { 40631 return 9; 40632 } else { 40633 return 9; 40634 } 40635 default: 40636 unreachable("Invalid hardware generation"); 40637 } 40638 } 40639 40640 40641 40642 #define GEN10_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 40643 #define GEN9_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 40644 #define GEN8_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 40645 #define GEN75_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 40646 #define GEN7_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 40647 #define GEN6_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 40648 #define GEN5_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 40649 #define GEN45_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 40650 #define GEN4_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 40651 40652 static inline uint32_t ATTRIBUTE_PURE 40653 _3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start(const struct gen_device_info *devinfo) 40654 { 40655 switch (devinfo->gen) { 40656 case 10: return 53; 40657 case 9: return 53; 40658 case 8: return 53; 40659 case 7: 40660 if (devinfo->is_haswell) { 40661 return 53; 40662 } else { 40663 return 53; 40664 } 40665 case 6: return 53; 40666 case 5: return 53; 40667 case 4: 40668 if (devinfo->is_g4x) { 40669 return 53; 40670 } else { 40671 return 53; 40672 } 40673 default: 40674 unreachable("Invalid hardware generation"); 40675 } 40676 } 40677 40678 40679 40680 /* 3DSTATE_LINE_STIPPLE::Current Stipple Index */ 40681 40682 40683 #define GEN10_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 40684 #define GEN9_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 40685 #define GEN8_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 40686 #define GEN75_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 40687 #define GEN7_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 40688 #define GEN6_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 40689 #define GEN5_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 40690 #define GEN45_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 40691 #define GEN4_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 40692 40693 static inline uint32_t ATTRIBUTE_PURE 40694 _3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits(const struct gen_device_info *devinfo) 40695 { 40696 switch (devinfo->gen) { 40697 case 10: return 4; 40698 case 9: return 4; 40699 case 8: return 4; 40700 case 7: 40701 if (devinfo->is_haswell) { 40702 return 4; 40703 } else { 40704 return 4; 40705 } 40706 case 6: return 4; 40707 case 5: return 4; 40708 case 4: 40709 if (devinfo->is_g4x) { 40710 return 4; 40711 } else { 40712 return 4; 40713 } 40714 default: 40715 unreachable("Invalid hardware generation"); 40716 } 40717 } 40718 40719 40720 40721 #define GEN10_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 40722 #define GEN9_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 40723 #define GEN8_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 40724 #define GEN75_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 40725 #define GEN7_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 40726 #define GEN6_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 40727 #define GEN5_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 40728 #define GEN45_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 40729 #define GEN4_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 40730 40731 static inline uint32_t ATTRIBUTE_PURE 40732 _3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start(const struct gen_device_info *devinfo) 40733 { 40734 switch (devinfo->gen) { 40735 case 10: return 48; 40736 case 9: return 48; 40737 case 8: return 48; 40738 case 7: 40739 if (devinfo->is_haswell) { 40740 return 48; 40741 } else { 40742 return 48; 40743 } 40744 case 6: return 48; 40745 case 5: return 48; 40746 case 4: 40747 if (devinfo->is_g4x) { 40748 return 48; 40749 } else { 40750 return 48; 40751 } 40752 default: 40753 unreachable("Invalid hardware generation"); 40754 } 40755 } 40756 40757 40758 40759 /* 3DSTATE_LINE_STIPPLE::DWord Length */ 40760 40761 40762 #define GEN10_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 40763 #define GEN9_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 40764 #define GEN8_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 40765 #define GEN75_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 40766 #define GEN7_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 40767 #define GEN6_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 40768 #define GEN5_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 40769 #define GEN45_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 40770 #define GEN4_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 40771 40772 static inline uint32_t ATTRIBUTE_PURE 40773 _3DSTATE_LINE_STIPPLE_DWordLength_bits(const struct gen_device_info *devinfo) 40774 { 40775 switch (devinfo->gen) { 40776 case 10: return 8; 40777 case 9: return 8; 40778 case 8: return 8; 40779 case 7: 40780 if (devinfo->is_haswell) { 40781 return 8; 40782 } else { 40783 return 8; 40784 } 40785 case 6: return 8; 40786 case 5: return 8; 40787 case 4: 40788 if (devinfo->is_g4x) { 40789 return 8; 40790 } else { 40791 return 8; 40792 } 40793 default: 40794 unreachable("Invalid hardware generation"); 40795 } 40796 } 40797 40798 40799 40800 #define GEN10_3DSTATE_LINE_STIPPLE_DWordLength_start 0 40801 #define GEN9_3DSTATE_LINE_STIPPLE_DWordLength_start 0 40802 #define GEN8_3DSTATE_LINE_STIPPLE_DWordLength_start 0 40803 #define GEN75_3DSTATE_LINE_STIPPLE_DWordLength_start 0 40804 #define GEN7_3DSTATE_LINE_STIPPLE_DWordLength_start 0 40805 #define GEN6_3DSTATE_LINE_STIPPLE_DWordLength_start 0 40806 #define GEN5_3DSTATE_LINE_STIPPLE_DWordLength_start 0 40807 #define GEN45_3DSTATE_LINE_STIPPLE_DWordLength_start 0 40808 #define GEN4_3DSTATE_LINE_STIPPLE_DWordLength_start 0 40809 40810 static inline uint32_t ATTRIBUTE_PURE 40811 _3DSTATE_LINE_STIPPLE_DWordLength_start(const struct gen_device_info *devinfo) 40812 { 40813 switch (devinfo->gen) { 40814 case 10: return 0; 40815 case 9: return 0; 40816 case 8: return 0; 40817 case 7: 40818 if (devinfo->is_haswell) { 40819 return 0; 40820 } else { 40821 return 0; 40822 } 40823 case 6: return 0; 40824 case 5: return 0; 40825 case 4: 40826 if (devinfo->is_g4x) { 40827 return 0; 40828 } else { 40829 return 0; 40830 } 40831 default: 40832 unreachable("Invalid hardware generation"); 40833 } 40834 } 40835 40836 40837 40838 /* 3DSTATE_LINE_STIPPLE::Line Stipple Inverse Repeat Count */ 40839 40840 40841 #define GEN10_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 40842 #define GEN9_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 40843 #define GEN8_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 40844 #define GEN75_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 40845 #define GEN7_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 40846 #define GEN6_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 16 40847 #define GEN5_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 16 40848 #define GEN45_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 16 40849 #define GEN4_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 16 40850 40851 static inline uint32_t ATTRIBUTE_PURE 40852 _3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits(const struct gen_device_info *devinfo) 40853 { 40854 switch (devinfo->gen) { 40855 case 10: return 17; 40856 case 9: return 17; 40857 case 8: return 17; 40858 case 7: 40859 if (devinfo->is_haswell) { 40860 return 17; 40861 } else { 40862 return 17; 40863 } 40864 case 6: return 16; 40865 case 5: return 16; 40866 case 4: 40867 if (devinfo->is_g4x) { 40868 return 16; 40869 } else { 40870 return 16; 40871 } 40872 default: 40873 unreachable("Invalid hardware generation"); 40874 } 40875 } 40876 40877 40878 40879 #define GEN10_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 40880 #define GEN9_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 40881 #define GEN8_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 40882 #define GEN75_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 40883 #define GEN7_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 40884 #define GEN6_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 80 40885 #define GEN5_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 80 40886 #define GEN45_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 80 40887 #define GEN4_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 80 40888 40889 static inline uint32_t ATTRIBUTE_PURE 40890 _3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start(const struct gen_device_info *devinfo) 40891 { 40892 switch (devinfo->gen) { 40893 case 10: return 79; 40894 case 9: return 79; 40895 case 8: return 79; 40896 case 7: 40897 if (devinfo->is_haswell) { 40898 return 79; 40899 } else { 40900 return 79; 40901 } 40902 case 6: return 80; 40903 case 5: return 80; 40904 case 4: 40905 if (devinfo->is_g4x) { 40906 return 80; 40907 } else { 40908 return 80; 40909 } 40910 default: 40911 unreachable("Invalid hardware generation"); 40912 } 40913 } 40914 40915 40916 40917 /* 3DSTATE_LINE_STIPPLE::Line Stipple Pattern */ 40918 40919 40920 #define GEN10_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 40921 #define GEN9_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 40922 #define GEN8_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 40923 #define GEN75_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 40924 #define GEN7_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 40925 #define GEN6_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 40926 #define GEN5_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 40927 #define GEN45_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 40928 #define GEN4_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 40929 40930 static inline uint32_t ATTRIBUTE_PURE 40931 _3DSTATE_LINE_STIPPLE_LineStipplePattern_bits(const struct gen_device_info *devinfo) 40932 { 40933 switch (devinfo->gen) { 40934 case 10: return 16; 40935 case 9: return 16; 40936 case 8: return 16; 40937 case 7: 40938 if (devinfo->is_haswell) { 40939 return 16; 40940 } else { 40941 return 16; 40942 } 40943 case 6: return 16; 40944 case 5: return 16; 40945 case 4: 40946 if (devinfo->is_g4x) { 40947 return 16; 40948 } else { 40949 return 16; 40950 } 40951 default: 40952 unreachable("Invalid hardware generation"); 40953 } 40954 } 40955 40956 40957 40958 #define GEN10_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 40959 #define GEN9_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 40960 #define GEN8_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 40961 #define GEN75_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 40962 #define GEN7_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 40963 #define GEN6_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 40964 #define GEN5_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 40965 #define GEN45_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 40966 #define GEN4_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 40967 40968 static inline uint32_t ATTRIBUTE_PURE 40969 _3DSTATE_LINE_STIPPLE_LineStipplePattern_start(const struct gen_device_info *devinfo) 40970 { 40971 switch (devinfo->gen) { 40972 case 10: return 32; 40973 case 9: return 32; 40974 case 8: return 32; 40975 case 7: 40976 if (devinfo->is_haswell) { 40977 return 32; 40978 } else { 40979 return 32; 40980 } 40981 case 6: return 32; 40982 case 5: return 32; 40983 case 4: 40984 if (devinfo->is_g4x) { 40985 return 32; 40986 } else { 40987 return 32; 40988 } 40989 default: 40990 unreachable("Invalid hardware generation"); 40991 } 40992 } 40993 40994 40995 40996 /* 3DSTATE_LINE_STIPPLE::Line Stipple Repeat Count */ 40997 40998 40999 #define GEN10_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 41000 #define GEN9_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 41001 #define GEN8_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 41002 #define GEN75_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 41003 #define GEN7_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 41004 #define GEN6_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 41005 #define GEN5_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 41006 #define GEN45_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 41007 #define GEN4_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 41008 41009 static inline uint32_t ATTRIBUTE_PURE 41010 _3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits(const struct gen_device_info *devinfo) 41011 { 41012 switch (devinfo->gen) { 41013 case 10: return 9; 41014 case 9: return 9; 41015 case 8: return 9; 41016 case 7: 41017 if (devinfo->is_haswell) { 41018 return 9; 41019 } else { 41020 return 9; 41021 } 41022 case 6: return 9; 41023 case 5: return 9; 41024 case 4: 41025 if (devinfo->is_g4x) { 41026 return 9; 41027 } else { 41028 return 9; 41029 } 41030 default: 41031 unreachable("Invalid hardware generation"); 41032 } 41033 } 41034 41035 41036 41037 #define GEN10_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 41038 #define GEN9_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 41039 #define GEN8_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 41040 #define GEN75_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 41041 #define GEN7_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 41042 #define GEN6_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 41043 #define GEN5_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 41044 #define GEN45_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 41045 #define GEN4_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 41046 41047 static inline uint32_t ATTRIBUTE_PURE 41048 _3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start(const struct gen_device_info *devinfo) 41049 { 41050 switch (devinfo->gen) { 41051 case 10: return 64; 41052 case 9: return 64; 41053 case 8: return 64; 41054 case 7: 41055 if (devinfo->is_haswell) { 41056 return 64; 41057 } else { 41058 return 64; 41059 } 41060 case 6: return 64; 41061 case 5: return 64; 41062 case 4: 41063 if (devinfo->is_g4x) { 41064 return 64; 41065 } else { 41066 return 64; 41067 } 41068 default: 41069 unreachable("Invalid hardware generation"); 41070 } 41071 } 41072 41073 41074 41075 /* 3DSTATE_LINE_STIPPLE::Modify Enable */ 41076 41077 41078 #define GEN5_3DSTATE_LINE_STIPPLE_ModifyEnable_bits 1 41079 #define GEN4_3DSTATE_LINE_STIPPLE_ModifyEnable_bits 1 41080 41081 static inline uint32_t ATTRIBUTE_PURE 41082 _3DSTATE_LINE_STIPPLE_ModifyEnable_bits(const struct gen_device_info *devinfo) 41083 { 41084 switch (devinfo->gen) { 41085 case 10: return 0; 41086 case 9: return 0; 41087 case 8: return 0; 41088 case 7: 41089 if (devinfo->is_haswell) { 41090 return 0; 41091 } else { 41092 return 0; 41093 } 41094 case 6: return 0; 41095 case 5: return 1; 41096 case 4: 41097 if (devinfo->is_g4x) { 41098 return 0; 41099 } else { 41100 return 1; 41101 } 41102 default: 41103 unreachable("Invalid hardware generation"); 41104 } 41105 } 41106 41107 41108 41109 #define GEN5_3DSTATE_LINE_STIPPLE_ModifyEnable_start 63 41110 #define GEN4_3DSTATE_LINE_STIPPLE_ModifyEnable_start 63 41111 41112 static inline uint32_t ATTRIBUTE_PURE 41113 _3DSTATE_LINE_STIPPLE_ModifyEnable_start(const struct gen_device_info *devinfo) 41114 { 41115 switch (devinfo->gen) { 41116 case 10: return 0; 41117 case 9: return 0; 41118 case 8: return 0; 41119 case 7: 41120 if (devinfo->is_haswell) { 41121 return 0; 41122 } else { 41123 return 0; 41124 } 41125 case 6: return 0; 41126 case 5: return 63; 41127 case 4: 41128 if (devinfo->is_g4x) { 41129 return 0; 41130 } else { 41131 return 63; 41132 } 41133 default: 41134 unreachable("Invalid hardware generation"); 41135 } 41136 } 41137 41138 41139 41140 /* 3DSTATE_LINE_STIPPLE::Modify Enable (Current Repeat Counter, Current Stipple Index) */ 41141 41142 41143 #define GEN10_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 41144 #define GEN9_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 41145 #define GEN8_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 41146 #define GEN75_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 41147 #define GEN7_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 41148 #define GEN6_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 41149 #define GEN45_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 41150 41151 static inline uint32_t ATTRIBUTE_PURE 41152 _3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits(const struct gen_device_info *devinfo) 41153 { 41154 switch (devinfo->gen) { 41155 case 10: return 1; 41156 case 9: return 1; 41157 case 8: return 1; 41158 case 7: 41159 if (devinfo->is_haswell) { 41160 return 1; 41161 } else { 41162 return 1; 41163 } 41164 case 6: return 1; 41165 case 5: return 0; 41166 case 4: 41167 if (devinfo->is_g4x) { 41168 return 1; 41169 } else { 41170 return 0; 41171 } 41172 default: 41173 unreachable("Invalid hardware generation"); 41174 } 41175 } 41176 41177 41178 41179 #define GEN10_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 41180 #define GEN9_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 41181 #define GEN8_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 41182 #define GEN75_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 41183 #define GEN7_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 41184 #define GEN6_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 41185 #define GEN45_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 41186 41187 static inline uint32_t ATTRIBUTE_PURE 41188 _3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start(const struct gen_device_info *devinfo) 41189 { 41190 switch (devinfo->gen) { 41191 case 10: return 63; 41192 case 9: return 63; 41193 case 8: return 63; 41194 case 7: 41195 if (devinfo->is_haswell) { 41196 return 63; 41197 } else { 41198 return 63; 41199 } 41200 case 6: return 63; 41201 case 5: return 0; 41202 case 4: 41203 if (devinfo->is_g4x) { 41204 return 63; 41205 } else { 41206 return 0; 41207 } 41208 default: 41209 unreachable("Invalid hardware generation"); 41210 } 41211 } 41212 41213 41214 41215 /* 3DSTATE_MONOFILTER_SIZE */ 41216 41217 41218 #define GEN10_3DSTATE_MONOFILTER_SIZE_length 2 41219 #define GEN9_3DSTATE_MONOFILTER_SIZE_length 2 41220 #define GEN8_3DSTATE_MONOFILTER_SIZE_length 2 41221 #define GEN75_3DSTATE_MONOFILTER_SIZE_length 2 41222 #define GEN7_3DSTATE_MONOFILTER_SIZE_length 2 41223 #define GEN6_3DSTATE_MONOFILTER_SIZE_length 2 41224 41225 static inline uint32_t ATTRIBUTE_PURE 41226 _3DSTATE_MONOFILTER_SIZE_length(const struct gen_device_info *devinfo) 41227 { 41228 switch (devinfo->gen) { 41229 case 10: return 2; 41230 case 9: return 2; 41231 case 8: return 2; 41232 case 7: 41233 if (devinfo->is_haswell) { 41234 return 2; 41235 } else { 41236 return 2; 41237 } 41238 case 6: return 2; 41239 case 5: return 0; 41240 case 4: 41241 if (devinfo->is_g4x) { 41242 return 0; 41243 } else { 41244 return 0; 41245 } 41246 default: 41247 unreachable("Invalid hardware generation"); 41248 } 41249 } 41250 41251 41252 41253 /* 3DSTATE_MONOFILTER_SIZE::3D Command Opcode */ 41254 41255 41256 #define GEN10_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 41257 #define GEN9_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 41258 #define GEN8_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 41259 #define GEN75_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 41260 #define GEN7_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 41261 #define GEN6_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 41262 41263 static inline uint32_t ATTRIBUTE_PURE 41264 _3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) 41265 { 41266 switch (devinfo->gen) { 41267 case 10: return 3; 41268 case 9: return 3; 41269 case 8: return 3; 41270 case 7: 41271 if (devinfo->is_haswell) { 41272 return 3; 41273 } else { 41274 return 3; 41275 } 41276 case 6: return 3; 41277 case 5: return 0; 41278 case 4: 41279 if (devinfo->is_g4x) { 41280 return 0; 41281 } else { 41282 return 0; 41283 } 41284 default: 41285 unreachable("Invalid hardware generation"); 41286 } 41287 } 41288 41289 41290 41291 #define GEN10_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 41292 #define GEN9_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 41293 #define GEN8_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 41294 #define GEN75_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 41295 #define GEN7_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 41296 #define GEN6_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 41297 41298 static inline uint32_t ATTRIBUTE_PURE 41299 _3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start(const struct gen_device_info *devinfo) 41300 { 41301 switch (devinfo->gen) { 41302 case 10: return 24; 41303 case 9: return 24; 41304 case 8: return 24; 41305 case 7: 41306 if (devinfo->is_haswell) { 41307 return 24; 41308 } else { 41309 return 24; 41310 } 41311 case 6: return 24; 41312 case 5: return 0; 41313 case 4: 41314 if (devinfo->is_g4x) { 41315 return 0; 41316 } else { 41317 return 0; 41318 } 41319 default: 41320 unreachable("Invalid hardware generation"); 41321 } 41322 } 41323 41324 41325 41326 /* 3DSTATE_MONOFILTER_SIZE::3D Command Sub Opcode */ 41327 41328 41329 #define GEN10_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 41330 #define GEN9_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 41331 #define GEN8_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 41332 #define GEN75_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 41333 #define GEN7_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 41334 #define GEN6_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 41335 41336 static inline uint32_t ATTRIBUTE_PURE 41337 _3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) 41338 { 41339 switch (devinfo->gen) { 41340 case 10: return 8; 41341 case 9: return 8; 41342 case 8: return 8; 41343 case 7: 41344 if (devinfo->is_haswell) { 41345 return 8; 41346 } else { 41347 return 8; 41348 } 41349 case 6: return 8; 41350 case 5: return 0; 41351 case 4: 41352 if (devinfo->is_g4x) { 41353 return 0; 41354 } else { 41355 return 0; 41356 } 41357 default: 41358 unreachable("Invalid hardware generation"); 41359 } 41360 } 41361 41362 41363 41364 #define GEN10_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 41365 #define GEN9_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 41366 #define GEN8_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 41367 #define GEN75_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 41368 #define GEN7_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 41369 #define GEN6_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 41370 41371 static inline uint32_t ATTRIBUTE_PURE 41372 _3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) 41373 { 41374 switch (devinfo->gen) { 41375 case 10: return 16; 41376 case 9: return 16; 41377 case 8: return 16; 41378 case 7: 41379 if (devinfo->is_haswell) { 41380 return 16; 41381 } else { 41382 return 16; 41383 } 41384 case 6: return 16; 41385 case 5: return 0; 41386 case 4: 41387 if (devinfo->is_g4x) { 41388 return 0; 41389 } else { 41390 return 0; 41391 } 41392 default: 41393 unreachable("Invalid hardware generation"); 41394 } 41395 } 41396 41397 41398 41399 /* 3DSTATE_MONOFILTER_SIZE::Command SubType */ 41400 41401 41402 #define GEN10_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 41403 #define GEN9_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 41404 #define GEN8_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 41405 #define GEN75_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 41406 #define GEN7_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 41407 #define GEN6_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 41408 41409 static inline uint32_t ATTRIBUTE_PURE 41410 _3DSTATE_MONOFILTER_SIZE_CommandSubType_bits(const struct gen_device_info *devinfo) 41411 { 41412 switch (devinfo->gen) { 41413 case 10: return 2; 41414 case 9: return 2; 41415 case 8: return 2; 41416 case 7: 41417 if (devinfo->is_haswell) { 41418 return 2; 41419 } else { 41420 return 2; 41421 } 41422 case 6: return 2; 41423 case 5: return 0; 41424 case 4: 41425 if (devinfo->is_g4x) { 41426 return 0; 41427 } else { 41428 return 0; 41429 } 41430 default: 41431 unreachable("Invalid hardware generation"); 41432 } 41433 } 41434 41435 41436 41437 #define GEN10_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 41438 #define GEN9_3DSTATE_MONOFILTER_SIZE_CommandSubType_start