1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2004-2010 4 * Texas Instruments, <www.ti.com> 5 */ 6 #ifndef _OMAP2PLUS_I2C_H_ 7 #define _OMAP2PLUS_I2C_H_ 8 9 /* I2C masks */ 10 11 /* I2C Interrupt Enable Register (I2C_IE): */ 12 #define I2C_IE_GC_IE (1 << 5) 13 #define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ 14 #define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ 15 #define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ 16 #define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ 17 #define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ 18 19 /* I2C Status Register (I2C_STAT): */ 20 21 #define I2C_STAT_SBD (1 << 15) /* Single byte data */ 22 #define I2C_STAT_BB (1 << 12) /* Bus busy */ 23 #define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 24 #define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 25 #define I2C_STAT_AAS (1 << 9) /* Address as slave */ 26 #define I2C_STAT_GC (1 << 5) 27 #define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ 28 #define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ 29 #define I2C_STAT_ARDY (1 << 2) /* Register access ready */ 30 #define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ 31 #define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ 32 33 /* I2C Interrupt Code Register (I2C_INTCODE): */ 34 35 #define I2C_INTCODE_MASK 7 36 #define I2C_INTCODE_NONE 0 37 #define I2C_INTCODE_AL 1 /* Arbitration lost */ 38 #define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ 39 #define I2C_INTCODE_ARDY 3 /* Register access ready */ 40 #define I2C_INTCODE_RRDY 4 /* Rcv data ready */ 41 #define I2C_INTCODE_XRDY 5 /* Xmit data ready */ 42 43 /* I2C Buffer Configuration Register (I2C_BUF): */ 44 45 #define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ 46 #define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ 47 48 /* I2C Configuration Register (I2C_CON): */ 49 50 #define I2C_CON_EN (1 << 15) /* I2C module enable */ 51 #define I2C_CON_BE (1 << 14) /* Big endian mode */ 52 #define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ 53 #define I2C_CON_MST (1 << 10) /* Master/slave mode */ 54 #define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ 55 /* (master mode only) */ 56 #define I2C_CON_XA (1 << 8) /* Expand address */ 57 #define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ 58 #define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ 59 60 /* I2C System Test Register (I2C_SYSTEST): */ 61 62 #define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ 63 #define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ 64 #define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ 65 #define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ 66 #define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ 67 #define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ 68 #define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ 69 #define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ 70 71 /* I2C System Status Register (I2C_SYSS): */ 72 73 #define I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */ 74 75 #define I2C_SCLL_SCLL 0 76 #define I2C_SCLL_SCLL_M 0xFF 77 #define I2C_SCLL_HSSCLL 8 78 #define I2C_SCLH_HSSCLL_M 0xFF 79 #define I2C_SCLH_SCLH 0 80 #define I2C_SCLH_SCLH_M 0xFF 81 #define I2C_SCLH_HSSCLH 8 82 #define I2C_SCLH_HSSCLH_M 0xFF 83 84 #define OMAP_I2C_STANDARD 100000 85 #define OMAP_I2C_FAST_MODE 400000 86 #define OMAP_I2C_HIGH_SPEED 3400000 87 88 #define SYSTEM_CLOCK_12 12000000 89 #define SYSTEM_CLOCK_13 13000000 90 #define SYSTEM_CLOCK_192 19200000 91 #define SYSTEM_CLOCK_96 96000000 92 93 /* Use the reference value of 96MHz if not explicitly set by the board */ 94 #ifndef I2C_IP_CLK 95 #define I2C_IP_CLK SYSTEM_CLOCK_96 96 #endif 97 98 /* 99 * The reference minimum clock for high speed is 19.2MHz. 100 * The linux 2.6.30 kernel uses this value. 101 * The reference minimum clock for fast mode is 9.6MHz 102 * The reference minimum clock for standard mode is 4MHz 103 * In TRM, the value of 12MHz is used. 104 */ 105 #ifndef I2C_INTERNAL_SAMPLING_CLK 106 #define I2C_INTERNAL_SAMPLING_CLK 19200000 107 #endif 108 109 /* 110 * The equation for the low and high time is 111 * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed 112 * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed 113 * 114 * If the duty cycle is 50% 115 * 116 * tlow = scll + scll_trim = sampling clock / (2 * speed) 117 * thigh = sclh + sclh_trim = sampling clock / (2 * speed) 118 * 119 * In TRM 120 * scll_trim = 7 121 * sclh_trim = 5 122 * 123 * The linux 4.9 kernel uses 124 * scll_trim = 7 125 * sclh_trim = 5 126 * 127 * These are the trim values for standard and fast speed 128 */ 129 #ifndef I2C_FASTSPEED_SCLL_TRIM 130 #define I2C_FASTSPEED_SCLL_TRIM 7 131 #endif 132 #ifndef I2C_FASTSPEED_SCLH_TRIM 133 #define I2C_FASTSPEED_SCLH_TRIM 5 134 #endif 135 136 /* These are the trim values for high speed */ 137 #ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM 138 #define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM 139 #endif 140 #ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM 141 #define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM 142 #endif 143 #ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM 144 #define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM 145 #endif 146 #ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM 147 #define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM 148 #endif 149 150 #define I2C_PSC_MAX 0x0f 151 #define I2C_PSC_MIN 0x00 152 153 #endif /* _OMAP24XX_I2C_H_ */ 154
