1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010, 2011 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7 #ifndef _WARMBOOT_AVP_H_ 8 #define _WARMBOOT_AVP_H_ 9 10 #define TEGRA_DEV_L 0 11 #define TEGRA_DEV_H 1 12 #define TEGRA_DEV_U 2 13 14 #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) 15 #define SIMPLE_PLLE (CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE) 16 17 #define TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) 18 #define TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) 19 20 #define USEC_CFG_DIVISOR_MASK 0xffff 21 22 #define CONFIG_CTL_TBE (1 << 7) 23 #define CONFIG_CTL_JTAG (1 << 6) 24 25 #define CPU_RST (1 << 0) 26 #define CLK_ENB_CPU (1 << 0) 27 #define SWR_TRIG_SYS_RST (1 << 2) 28 #define SWR_CSITE_RST (1 << 9) 29 30 #define PWRGATE_STATUS_CPU (1 << 0) 31 #define PWRGATE_TOGGLE_PARTID_CPU (0 << 0) 32 #define PWRGATE_TOGGLE_START (1 << 8) 33 34 #define CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 (3 << 0) 35 #define CPU_CMPLX_CPU0_CLK_STP_STOP (1 << 8) 36 #define CPU_CMPLX_CPU0_CLK_STP_RUN (0 << 8) 37 #define CPU_CMPLX_CPU1_CLK_STP_STOP (1 << 9) 38 #define CPU_CMPLX_CPU1_CLK_STP_RUN (0 << 9) 39 40 #define CPU_CMPLX_CPURESET0 (1 << 0) 41 #define CPU_CMPLX_CPURESET1 (1 << 1) 42 #define CPU_CMPLX_DERESET0 (1 << 4) 43 #define CPU_CMPLX_DERESET1 (1 << 5) 44 #define CPU_CMPLX_DBGRESET0 (1 << 12) 45 #define CPU_CMPLX_DBGRESET1 (1 << 13) 46 47 #define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) 48 #define PLLM_OUT1_CLKEN_ENABLE (1 << 1) 49 #define PLLM_OUT1_RATIO_VAL_8 (8 << 8) 50 51 #define SCLK_SYS_STATE_IDLE (1 << 28) 52 #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) 53 #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) 54 #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) 55 #define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0) 56 57 #define EVENT_ZERO_VAL_20 (20 << 0) 58 #define EVENT_MSEC (1 << 24) 59 #define EVENT_JTAG (1 << 28) 60 #define EVENT_MODE_STOP (2 << 29) 61 62 #define CCLK_PLLP_BURST_POLICY 0x20004444 63 64 #endif 65
