1 /* 2 * Copyright 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <assert.h> 25 #include <stdbool.h> 26 #include <string.h> 27 #include <unistd.h> 28 #include <fcntl.h> 29 #include <sys/mman.h> 30 #include <drm_fourcc.h> 31 32 #include "anv_private.h" 33 #include "util/debug.h" 34 #include "vk_util.h" 35 36 #include "vk_format_info.h" 37 38 static isl_surf_usage_flags_t 39 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags, 40 VkImageUsageFlags vk_usage, 41 isl_surf_usage_flags_t isl_extra_usage, 42 VkImageAspectFlagBits aspect) 43 { 44 isl_surf_usage_flags_t isl_usage = isl_extra_usage; 45 46 if (vk_usage & VK_IMAGE_USAGE_SAMPLED_BIT) 47 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT; 48 49 if (vk_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT) 50 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT; 51 52 if (vk_usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) 53 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT; 54 55 if (vk_create_flags & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT) 56 isl_usage |= ISL_SURF_USAGE_CUBE_BIT; 57 58 /* Even if we're only using it for transfer operations, clears to depth and 59 * stencil images happen as depth and stencil so they need the right ISL 60 * usage bits or else things will fall apart. 61 */ 62 switch (aspect) { 63 case VK_IMAGE_ASPECT_DEPTH_BIT: 64 isl_usage |= ISL_SURF_USAGE_DEPTH_BIT; 65 break; 66 case VK_IMAGE_ASPECT_STENCIL_BIT: 67 isl_usage |= ISL_SURF_USAGE_STENCIL_BIT; 68 break; 69 case VK_IMAGE_ASPECT_COLOR_BIT: 70 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR: 71 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR: 72 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR: 73 break; 74 default: 75 unreachable("bad VkImageAspect"); 76 } 77 78 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) { 79 /* blorp implements transfers by sampling from the source image. */ 80 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT; 81 } 82 83 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT && 84 aspect == VK_IMAGE_ASPECT_COLOR_BIT) { 85 /* blorp implements transfers by rendering into the destination image. 86 * Only request this with color images, as we deal with depth/stencil 87 * formats differently. */ 88 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT; 89 } 90 91 return isl_usage; 92 } 93 94 static isl_tiling_flags_t 95 choose_isl_tiling_flags(const struct anv_image_create_info *anv_info, 96 const struct isl_drm_modifier_info *isl_mod_info) 97 { 98 const VkImageCreateInfo *base_info = anv_info->vk_info; 99 isl_tiling_flags_t flags = 0; 100 101 switch (base_info->tiling) { 102 default: 103 unreachable("bad VkImageTiling"); 104 case VK_IMAGE_TILING_OPTIMAL: 105 flags = ISL_TILING_ANY_MASK; 106 break; 107 case VK_IMAGE_TILING_LINEAR: 108 flags = ISL_TILING_LINEAR_BIT; 109 break; 110 } 111 112 if (anv_info->isl_tiling_flags) 113 flags &= anv_info->isl_tiling_flags; 114 115 if (isl_mod_info) 116 flags &= 1 << isl_mod_info->tiling; 117 118 assert(flags); 119 120 return flags; 121 } 122 123 static struct anv_surface * 124 get_surface(struct anv_image *image, VkImageAspectFlagBits aspect) 125 { 126 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect); 127 return &image->planes[plane].surface; 128 } 129 130 static void 131 add_surface(struct anv_image *image, struct anv_surface *surf, uint32_t plane) 132 { 133 assert(surf->isl.size > 0); /* isl surface must be initialized */ 134 135 if (image->disjoint) { 136 surf->offset = align_u32(image->planes[plane].size, surf->isl.alignment); 137 /* Plane offset is always 0 when it's disjoint. */ 138 } else { 139 surf->offset = align_u32(image->size, surf->isl.alignment); 140 /* Determine plane's offset only once when the first surface is added. */ 141 if (image->planes[plane].size == 0) 142 image->planes[plane].offset = image->size; 143 } 144 145 image->size = surf->offset + surf->isl.size; 146 image->planes[plane].size = (surf->offset + surf->isl.size) - image->planes[plane].offset; 147 148 image->alignment = MAX2(image->alignment, surf->isl.alignment); 149 image->planes[plane].alignment = MAX2(image->planes[plane].alignment, 150 surf->isl.alignment); 151 } 152 153 154 static bool 155 all_formats_ccs_e_compatible(const struct gen_device_info *devinfo, 156 const struct VkImageCreateInfo *vk_info) 157 { 158 enum isl_format format = 159 anv_get_isl_format(devinfo, vk_info->format, 160 VK_IMAGE_ASPECT_COLOR_BIT, vk_info->tiling); 161 162 if (!isl_format_supports_ccs_e(devinfo, format)) 163 return false; 164 165 if (!(vk_info->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT)) 166 return true; 167 168 const VkImageFormatListCreateInfoKHR *fmt_list = 169 vk_find_struct_const(vk_info->pNext, IMAGE_FORMAT_LIST_CREATE_INFO_KHR); 170 171 if (!fmt_list || fmt_list->viewFormatCount == 0) 172 return false; 173 174 for (uint32_t i = 0; i < fmt_list->viewFormatCount; i++) { 175 enum isl_format view_format = 176 anv_get_isl_format(devinfo, fmt_list->pViewFormats[i], 177 VK_IMAGE_ASPECT_COLOR_BIT, vk_info->tiling); 178 179 if (!isl_formats_are_ccs_e_compatible(devinfo, format, view_format)) 180 return false; 181 } 182 183 return true; 184 } 185 186 /** 187 * For color images that have an auxiliary surface, request allocation for an 188 * additional buffer that mainly stores fast-clear values. Use of this buffer 189 * allows us to access the image's subresources while being aware of their 190 * fast-clear values in non-trivial cases (e.g., outside of a render pass in 191 * which a fast clear has occurred). 192 * 193 * For the purpose of discoverability, the algorithm used to manage this buffer 194 * is described here. A clear value in this buffer is updated when a fast clear 195 * is performed on a subresource. One of two synchronization operations is 196 * performed in order for a following memory access to use the fast-clear 197 * value: 198 * a. Copy the value from the buffer to the surface state object used for 199 * reading. This is done implicitly when the value is the clear value 200 * predetermined to be the default in other surface state objects. This 201 * is currently only done explicitly for the operation below. 202 * b. Do (a) and use the surface state object to resolve the subresource. 203 * This is only done during layout transitions for decent performance. 204 * 205 * With the above scheme, we can fast-clear whenever the hardware allows except 206 * for two cases in which synchronization becomes impossible or undesirable: 207 * * The subresource is in the GENERAL layout and is cleared to a value 208 * other than the special default value. 209 * 210 * Performing a synchronization operation in order to read from the 211 * subresource is undesirable in this case. Firstly, b) is not an option 212 * because a layout transition isn't required between a write and read of 213 * an image in the GENERAL layout. Secondly, it's undesirable to do a) 214 * explicitly because it would require large infrastructural changes. The 215 * Vulkan API supports us in deciding not to optimize this layout by 216 * stating that using this layout may cause suboptimal performance. NOTE: 217 * the auxiliary buffer must always be enabled to support a) implicitly. 218 * 219 * 220 * * For the given miplevel, only some of the layers are cleared at once. 221 * 222 * If the user clears each layer to a different value, then tries to 223 * render to multiple layers at once, we have no ability to perform a 224 * synchronization operation in between. a) is not helpful because the 225 * object can only hold one clear value. b) is not an option because a 226 * layout transition isn't required in this case. 227 */ 228 static void 229 add_fast_clear_state_buffer(struct anv_image *image, 230 VkImageAspectFlagBits aspect, 231 uint32_t plane, 232 const struct anv_device *device) 233 { 234 assert(image && device); 235 assert(image->planes[plane].aux_surface.isl.size > 0 && 236 image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV); 237 238 /* The offset to the buffer of clear values must be dword-aligned for GPU 239 * memcpy operations. It is located immediately after the auxiliary surface. 240 */ 241 242 /* Tiled images are guaranteed to be 4K aligned, so the image alignment 243 * should also be dword-aligned. 244 */ 245 assert(image->alignment % 4 == 0); 246 247 /* Auxiliary buffers should be a multiple of 4K, so the start of the clear 248 * values buffer should already be dword-aligned. 249 */ 250 assert((image->planes[plane].offset + image->planes[plane].size) % 4 == 0); 251 252 /* This buffer should be at the very end of the plane. */ 253 if (image->disjoint) { 254 assert(image->planes[plane].size == 255 (image->planes[plane].offset + image->planes[plane].size)); 256 } else { 257 assert(image->size == 258 (image->planes[plane].offset + image->planes[plane].size)); 259 } 260 261 const unsigned entry_size = anv_fast_clear_state_entry_size(device); 262 /* There's no padding between entries, so ensure that they're always a 263 * multiple of 32 bits in order to enable GPU memcpy operations. 264 */ 265 assert(entry_size % 4 == 0); 266 267 const unsigned plane_state_size = 268 entry_size * anv_image_aux_levels(image, aspect); 269 270 image->planes[plane].fast_clear_state_offset = 271 image->planes[plane].offset + image->planes[plane].size; 272 273 image->planes[plane].size += plane_state_size; 274 image->size += plane_state_size; 275 } 276 277 /** 278 * Initialize the anv_image::*_surface selected by \a aspect. Then update the 279 * image's memory requirements (that is, the image's size and alignment). 280 */ 281 static VkResult 282 make_surface(const struct anv_device *dev, 283 struct anv_image *image, 284 const struct anv_image_create_info *anv_info, 285 isl_tiling_flags_t tiling_flags, 286 VkImageAspectFlagBits aspect) 287 { 288 const VkImageCreateInfo *vk_info = anv_info->vk_info; 289 bool ok UNUSED; 290 291 static const enum isl_surf_dim vk_to_isl_surf_dim[] = { 292 [VK_IMAGE_TYPE_1D] = ISL_SURF_DIM_1D, 293 [VK_IMAGE_TYPE_2D] = ISL_SURF_DIM_2D, 294 [VK_IMAGE_TYPE_3D] = ISL_SURF_DIM_3D, 295 }; 296 297 image->extent = anv_sanitize_image_extent(vk_info->imageType, 298 vk_info->extent); 299 300 const unsigned plane = anv_image_aspect_to_plane(image->aspects, aspect); 301 const struct anv_format_plane plane_format = 302 anv_get_format_plane(&dev->info, image->vk_format, aspect, image->tiling); 303 struct anv_surface *anv_surf = &image->planes[plane].surface; 304 305 const isl_surf_usage_flags_t usage = 306 choose_isl_surf_usage(vk_info->flags, image->usage, 307 anv_info->isl_extra_usage_flags, aspect); 308 309 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to 310 * fall back to linear on Broadwell and earlier because we aren't 311 * guaranteed that we can handle offsets correctly. On Sky Lake, the 312 * horizontal and vertical alignments are sufficiently high that we can 313 * just use RENDER_SURFACE_STATE::X/Y Offset. 314 */ 315 bool needs_shadow = false; 316 if (dev->info.gen <= 8 && 317 (vk_info->flags & VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT_KHR) && 318 vk_info->tiling == VK_IMAGE_TILING_OPTIMAL) { 319 assert(isl_format_is_compressed(plane_format.isl_format)); 320 tiling_flags = ISL_TILING_LINEAR_BIT; 321 needs_shadow = true; 322 } 323 324 ok = isl_surf_init(&dev->isl_dev, &anv_surf->isl, 325 .dim = vk_to_isl_surf_dim[vk_info->imageType], 326 .format = plane_format.isl_format, 327 .width = image->extent.width / plane_format.denominator_scales[0], 328 .height = image->extent.height / plane_format.denominator_scales[1], 329 .depth = image->extent.depth, 330 .levels = vk_info->mipLevels, 331 .array_len = vk_info->arrayLayers, 332 .samples = vk_info->samples, 333 .min_alignment = 0, 334 .row_pitch = anv_info->stride, 335 .usage = usage, 336 .tiling_flags = tiling_flags); 337 338 if (!ok) 339 return VK_ERROR_OUT_OF_DEVICE_MEMORY; 340 341 image->planes[plane].aux_usage = ISL_AUX_USAGE_NONE; 342 343 add_surface(image, anv_surf, plane); 344 345 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to 346 * create an identical tiled shadow surface for use while texturing so we 347 * don't get garbage performance. 348 */ 349 if (needs_shadow) { 350 assert(aspect == VK_IMAGE_ASPECT_COLOR_BIT); 351 assert(tiling_flags == ISL_TILING_LINEAR_BIT); 352 353 ok = isl_surf_init(&dev->isl_dev, &image->planes[plane].shadow_surface.isl, 354 .dim = vk_to_isl_surf_dim[vk_info->imageType], 355 .format = plane_format.isl_format, 356 .width = image->extent.width, 357 .height = image->extent.height, 358 .depth = image->extent.depth, 359 .levels = vk_info->mipLevels, 360 .array_len = vk_info->arrayLayers, 361 .samples = vk_info->samples, 362 .min_alignment = 0, 363 .row_pitch = anv_info->stride, 364 .usage = usage, 365 .tiling_flags = ISL_TILING_ANY_MASK); 366 367 /* isl_surf_init() will fail only if provided invalid input. Invalid input 368 * is illegal in Vulkan. 369 */ 370 assert(ok); 371 372 add_surface(image, &image->planes[plane].shadow_surface, plane); 373 } 374 375 /* Add a HiZ surface to a depth buffer that will be used for rendering. 376 */ 377 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) { 378 /* We don't advertise that depth buffers could be used as storage 379 * images. 380 */ 381 assert(!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)); 382 383 /* Allow the user to control HiZ enabling. Disable by default on gen7 384 * because resolves are not currently implemented pre-BDW. 385 */ 386 if (!(image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) { 387 /* It will never be used as an attachment, HiZ is pointless. */ 388 } else if (dev->info.gen == 7) { 389 anv_perf_warn(dev->instance, image, "Implement gen7 HiZ"); 390 } else if (vk_info->mipLevels > 1) { 391 anv_perf_warn(dev->instance, image, "Enable multi-LOD HiZ"); 392 } else if (vk_info->arrayLayers > 1) { 393 anv_perf_warn(dev->instance, image, 394 "Implement multi-arrayLayer HiZ clears and resolves"); 395 } else if (dev->info.gen == 8 && vk_info->samples > 1) { 396 anv_perf_warn(dev->instance, image, "Enable gen8 multisampled HiZ"); 397 } else if (!unlikely(INTEL_DEBUG & DEBUG_NO_HIZ)) { 398 assert(image->planes[plane].aux_surface.isl.size == 0); 399 ok = isl_surf_get_hiz_surf(&dev->isl_dev, 400 &image->planes[plane].surface.isl, 401 &image->planes[plane].aux_surface.isl); 402 assert(ok); 403 add_surface(image, &image->planes[plane].aux_surface, plane); 404 image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ; 405 } 406 } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && vk_info->samples == 1) { 407 /* TODO: Disallow compression with : 408 * 409 * 1) non multiplanar images (We appear to hit a sampler bug with 410 * CCS & R16G16 format. Putting the clear state a page/4096bytes 411 * further fixes the issue). 412 * 413 * 2) alias images, because they might be aliases of images 414 * described in 1) 415 * 416 * 3) compression disabled by debug 417 */ 418 const bool allow_compression = 419 image->n_planes == 1 && 420 (vk_info->flags & VK_IMAGE_CREATE_ALIAS_BIT_KHR) == 0 && 421 likely((INTEL_DEBUG & DEBUG_NO_RBC) == 0); 422 423 if (allow_compression) { 424 assert(image->planes[plane].aux_surface.isl.size == 0); 425 ok = isl_surf_get_ccs_surf(&dev->isl_dev, 426 &image->planes[plane].surface.isl, 427 &image->planes[plane].aux_surface.isl, 0); 428 if (ok) { 429 430 /* Disable CCS when it is not useful (i.e., when you can't render 431 * to the image with CCS enabled). 432 */ 433 if (!isl_format_supports_rendering(&dev->info, 434 plane_format.isl_format)) { 435 /* While it may be technically possible to enable CCS for this 436 * image, we currently don't have things hooked up to get it 437 * working. 438 */ 439 anv_perf_warn(dev->instance, image, 440 "This image format doesn't support rendering. " 441 "Not allocating an CCS buffer."); 442 image->planes[plane].aux_surface.isl.size = 0; 443 return VK_SUCCESS; 444 } 445 446 add_surface(image, &image->planes[plane].aux_surface, plane); 447 add_fast_clear_state_buffer(image, aspect, plane, dev); 448 449 /* For images created without MUTABLE_FORMAT_BIT set, we know that 450 * they will always be used with the original format. In 451 * particular, they will always be used with a format that 452 * supports color compression. If it's never used as a storage 453 * image, then it will only be used through the sampler or the as 454 * a render target. This means that it's safe to just leave 455 * compression on at all times for these formats. 456 */ 457 if (!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT) && 458 all_formats_ccs_e_compatible(&dev->info, vk_info)) { 459 image->planes[plane].aux_usage = ISL_AUX_USAGE_CCS_E; 460 } 461 } 462 } 463 } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && vk_info->samples > 1) { 464 assert(!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT)); 465 assert(image->planes[plane].aux_surface.isl.size == 0); 466 ok = isl_surf_get_mcs_surf(&dev->isl_dev, 467 &image->planes[plane].surface.isl, 468 &image->planes[plane].aux_surface.isl); 469 if (ok) { 470 add_surface(image, &image->planes[plane].aux_surface, plane); 471 add_fast_clear_state_buffer(image, aspect, plane, dev); 472 image->planes[plane].aux_usage = ISL_AUX_USAGE_MCS; 473 } 474 } 475 476 assert((image->planes[plane].offset + image->planes[plane].size) == image->size); 477 478 /* Upper bound of the last surface should be smaller than the plane's 479 * size. 480 */ 481 assert((MAX2(image->planes[plane].surface.offset, 482 image->planes[plane].aux_surface.offset) + 483 (image->planes[plane].aux_surface.isl.size > 0 ? 484 image->planes[plane].aux_surface.isl.size : 485 image->planes[plane].surface.isl.size)) <= 486 (image->planes[plane].offset + image->planes[plane].size)); 487 488 if (image->planes[plane].aux_surface.isl.size) { 489 /* assert(image->planes[plane].fast_clear_state_offset == */ 490 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */ 491 assert(image->planes[plane].fast_clear_state_offset < 492 (image->planes[plane].offset + image->planes[plane].size)); 493 } 494 495 return VK_SUCCESS; 496 } 497 498 static const struct isl_drm_modifier_info * 499 get_legacy_scanout_drm_format_mod(VkImageTiling tiling) 500 { 501 switch (tiling) { 502 case VK_IMAGE_TILING_OPTIMAL: 503 return isl_drm_modifier_get_info(I915_FORMAT_MOD_X_TILED); 504 case VK_IMAGE_TILING_LINEAR: 505 return isl_drm_modifier_get_info(DRM_FORMAT_MOD_LINEAR); 506 default: 507 unreachable("bad VkImageTiling"); 508 } 509 } 510 511 VkResult 512 anv_image_create(VkDevice _device, 513 const struct anv_image_create_info *create_info, 514 const VkAllocationCallbacks* alloc, 515 VkImage *pImage) 516 { 517 ANV_FROM_HANDLE(anv_device, device, _device); 518 const VkImageCreateInfo *pCreateInfo = create_info->vk_info; 519 const struct isl_drm_modifier_info *isl_mod_info = NULL; 520 struct anv_image *image = NULL; 521 VkResult r; 522 523 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO); 524 525 const struct wsi_image_create_info *wsi_info = 526 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA); 527 if (wsi_info && wsi_info->scanout) 528 isl_mod_info = get_legacy_scanout_drm_format_mod(pCreateInfo->tiling); 529 530 anv_assert(pCreateInfo->mipLevels > 0); 531 anv_assert(pCreateInfo->arrayLayers > 0); 532 anv_assert(pCreateInfo->samples > 0); 533 anv_assert(pCreateInfo->extent.width > 0); 534 anv_assert(pCreateInfo->extent.height > 0); 535 anv_assert(pCreateInfo->extent.depth > 0); 536 537 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8, 538 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); 539 if (!image) 540 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); 541 542 image->type = pCreateInfo->imageType; 543 image->extent = pCreateInfo->extent; 544 image->vk_format = pCreateInfo->format; 545 image->format = anv_get_format(pCreateInfo->format); 546 image->aspects = vk_format_aspects(image->vk_format); 547 image->levels = pCreateInfo->mipLevels; 548 image->array_size = pCreateInfo->arrayLayers; 549 image->samples = pCreateInfo->samples; 550 image->usage = pCreateInfo->usage; 551 image->tiling = pCreateInfo->tiling; 552 image->disjoint = pCreateInfo->flags & VK_IMAGE_CREATE_DISJOINT_BIT_KHR; 553 image->drm_format_mod = isl_mod_info ? isl_mod_info->modifier : 554 DRM_FORMAT_MOD_INVALID; 555 556 const struct anv_format *format = anv_get_format(image->vk_format); 557 assert(format != NULL); 558 559 const isl_tiling_flags_t isl_tiling_flags = 560 choose_isl_tiling_flags(create_info, isl_mod_info); 561 562 image->n_planes = format->n_planes; 563 564 uint32_t b; 565 for_each_bit(b, image->aspects) { 566 r = make_surface(device, image, create_info, isl_tiling_flags, 567 (1 << b)); 568 if (r != VK_SUCCESS) 569 goto fail; 570 } 571 572 *pImage = anv_image_to_handle(image); 573 574 return VK_SUCCESS; 575 576 fail: 577 if (image) 578 vk_free2(&device->alloc, alloc, image); 579 580 return r; 581 } 582 583 VkResult 584 anv_CreateImage(VkDevice device, 585 const VkImageCreateInfo *pCreateInfo, 586 const VkAllocationCallbacks *pAllocator, 587 VkImage *pImage) 588 { 589 #ifdef ANDROID 590 const VkNativeBufferANDROID *gralloc_info = 591 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID); 592 593 if (gralloc_info) 594 return anv_image_from_gralloc(device, pCreateInfo, gralloc_info, 595 pAllocator, pImage); 596 #endif 597 598 return anv_image_create(device, 599 &(struct anv_image_create_info) { 600 .vk_info = pCreateInfo, 601 }, 602 pAllocator, 603 pImage); 604 } 605 606 void 607 anv_DestroyImage(VkDevice _device, VkImage _image, 608 const VkAllocationCallbacks *pAllocator) 609 { 610 ANV_FROM_HANDLE(anv_device, device, _device); 611 ANV_FROM_HANDLE(anv_image, image, _image); 612 613 if (!image) 614 return; 615 616 for (uint32_t p = 0; p < image->n_planes; ++p) { 617 if (image->planes[p].bo_is_owned) { 618 assert(image->planes[p].bo != NULL); 619 anv_bo_cache_release(device, &device->bo_cache, image->planes[p].bo); 620 } 621 } 622 623 vk_free2(&device->alloc, pAllocator, image); 624 } 625 626 static void anv_image_bind_memory_plane(struct anv_device *device, 627 struct anv_image *image, 628 uint32_t plane, 629 struct anv_device_memory *memory, 630 uint32_t memory_offset) 631 { 632 assert(!image->planes[plane].bo_is_owned); 633 634 if (!memory) { 635 image->planes[plane].bo = NULL; 636 image->planes[plane].bo_offset = 0; 637 return; 638 } 639 640 image->planes[plane].bo = memory->bo; 641 image->planes[plane].bo_offset = memory_offset; 642 } 643 644 VkResult anv_BindImageMemory( 645 VkDevice _device, 646 VkImage _image, 647 VkDeviceMemory _memory, 648 VkDeviceSize memoryOffset) 649 { 650 ANV_FROM_HANDLE(anv_device, device, _device); 651 ANV_FROM_HANDLE(anv_device_memory, mem, _memory); 652 ANV_FROM_HANDLE(anv_image, image, _image); 653 654 uint32_t aspect_bit; 655 anv_foreach_image_aspect_bit(aspect_bit, image, image->aspects) { 656 uint32_t plane = 657 anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit); 658 anv_image_bind_memory_plane(device, image, plane, mem, memoryOffset); 659 } 660 661 return VK_SUCCESS; 662 } 663 664 VkResult anv_BindImageMemory2KHR( 665 VkDevice _device, 666 uint32_t bindInfoCount, 667 const VkBindImageMemoryInfoKHR* pBindInfos) 668 { 669 ANV_FROM_HANDLE(anv_device, device, _device); 670 671 for (uint32_t i = 0; i < bindInfoCount; i++) { 672 const VkBindImageMemoryInfoKHR *bind_info = &pBindInfos[i]; 673 ANV_FROM_HANDLE(anv_device_memory, mem, bind_info->memory); 674 ANV_FROM_HANDLE(anv_image, image, bind_info->image); 675 VkImageAspectFlags aspects = image->aspects; 676 677 vk_foreach_struct_const(s, bind_info->pNext) { 678 switch (s->sType) { 679 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO_KHR: { 680 const VkBindImagePlaneMemoryInfoKHR *plane_info = 681 (const VkBindImagePlaneMemoryInfoKHR *) s; 682 683 aspects = plane_info->planeAspect; 684 break; 685 } 686 default: 687 anv_debug_ignored_stype(s->sType); 688 break; 689 } 690 } 691 692 uint32_t aspect_bit; 693 anv_foreach_image_aspect_bit(aspect_bit, image, aspects) { 694 uint32_t plane = 695 anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit); 696 anv_image_bind_memory_plane(device, image, plane, 697 mem, bind_info->memoryOffset); 698 } 699 } 700 701 return VK_SUCCESS; 702 } 703 704 void anv_GetImageSubresourceLayout( 705 VkDevice device, 706 VkImage _image, 707 const VkImageSubresource* subresource, 708 VkSubresourceLayout* layout) 709 { 710 ANV_FROM_HANDLE(anv_image, image, _image); 711 const struct anv_surface *surface = 712 get_surface(image, subresource->aspectMask); 713 714 assert(__builtin_popcount(subresource->aspectMask) == 1); 715 716 /* If we are on a non-zero mip level or array slice, we need to 717 * calculate a real offset. 718 */ 719 anv_assert(subresource->mipLevel == 0); 720 anv_assert(subresource->arrayLayer == 0); 721 722 layout->offset = surface->offset; 723 layout->rowPitch = surface->isl.row_pitch; 724 layout->depthPitch = isl_surf_get_array_pitch(&surface->isl); 725 layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl); 726 layout->size = surface->isl.size; 727 } 728 729 /** 730 * This function determines the optimal buffer to use for a given 731 * VkImageLayout and other pieces of information needed to make that 732 * determination. This does not determine the optimal buffer to use 733 * during a resolve operation. 734 * 735 * @param devinfo The device information of the Intel GPU. 736 * @param image The image that may contain a collection of buffers. 737 * @param plane The plane of the image to be accessed. 738 * @param layout The current layout of the image aspect(s). 739 * 740 * @return The primary buffer that should be used for the given layout. 741 */ 742 enum isl_aux_usage 743 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo, 744 const struct anv_image * const image, 745 const VkImageAspectFlagBits aspect, 746 const VkImageLayout layout) 747 { 748 /* Validate the inputs. */ 749 750 /* The devinfo is needed as the optimal buffer varies across generations. */ 751 assert(devinfo != NULL); 752 753 /* The layout of a NULL image is not properly defined. */ 754 assert(image != NULL); 755 756 /* The aspect must be exactly one of the image aspects. */ 757 assert(_mesa_bitcount(aspect) == 1 && (aspect & image->aspects)); 758 759 /* Determine the optimal buffer. */ 760 761 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect); 762 763 /* If there is no auxiliary surface allocated, we must use the one and only 764 * main buffer. 765 */ 766 if (image->planes[plane].aux_surface.isl.size == 0) 767 return ISL_AUX_USAGE_NONE; 768 769 /* All images that use an auxiliary surface are required to be tiled. */ 770 assert(image->tiling == VK_IMAGE_TILING_OPTIMAL); 771 772 /* Stencil has no aux */ 773 assert(aspect != VK_IMAGE_ASPECT_STENCIL_BIT); 774 775 /* The following switch currently only handles depth stencil aspects. 776 * TODO: Handle the color aspect. 777 */ 778 if (image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) 779 return image->planes[plane].aux_usage; 780 781 switch (layout) { 782 783 /* Invalid Layouts */ 784 case VK_IMAGE_LAYOUT_RANGE_SIZE: 785 case VK_IMAGE_LAYOUT_MAX_ENUM: 786 unreachable("Invalid image layout."); 787 788 /* Undefined layouts 789 * 790 * The pre-initialized layout is equivalent to the undefined layout for 791 * optimally-tiled images. We can only do color compression (CCS or HiZ) 792 * on tiled images. 793 */ 794 case VK_IMAGE_LAYOUT_UNDEFINED: 795 case VK_IMAGE_LAYOUT_PREINITIALIZED: 796 return ISL_AUX_USAGE_NONE; 797 798 799 /* Transfer Layouts 800 * 801 * This buffer could be a depth buffer used in a transfer operation. BLORP 802 * currently doesn't use HiZ for transfer operations so we must use the main 803 * buffer for this layout. TODO: Enable HiZ in BLORP. 804 */ 805 case VK_IMAGE_LAYOUT_GENERAL: 806 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL: 807 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL: 808 return ISL_AUX_USAGE_NONE; 809 810 811 /* Sampling Layouts */ 812 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL: 813 assert((image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0); 814 /* Fall-through */ 815 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL: 816 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL_KHR: 817 assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT); 818 if (anv_can_sample_with_hiz(devinfo, image)) 819 return ISL_AUX_USAGE_HIZ; 820 else 821 return ISL_AUX_USAGE_NONE; 822 823 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR: 824 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT); 825 826 /* On SKL+, the render buffer can be decompressed by the presentation 827 * engine. Support for this feature has not yet landed in the wider 828 * ecosystem. TODO: Update this code when support lands. 829 * 830 * From the BDW PRM, Vol 7, Render Target Resolve: 831 * 832 * If the MCS is enabled on a non-multisampled render target, the 833 * render target must be resolved before being used for other 834 * purposes (display, texture, CPU lock) The clear value from 835 * SURFACE_STATE is written into pixels in the render target 836 * indicated as clear in the MCS. 837 * 838 * Pre-SKL, the render buffer must be resolved before being used for 839 * presentation. We can infer that the auxiliary buffer is not used. 840 */ 841 return ISL_AUX_USAGE_NONE; 842 843 844 /* Rendering Layouts */ 845 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL: 846 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT); 847 unreachable("Color images are not yet supported."); 848 849 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL: 850 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL_KHR: 851 assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT); 852 return ISL_AUX_USAGE_HIZ; 853 854 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR: 855 unreachable("VK_KHR_shared_presentable_image is unsupported"); 856 } 857 858 /* If the layout isn't recognized in the exhaustive switch above, the 859 * VkImageLayout value is not defined in vulkan.h. 860 */ 861 unreachable("layout is not a VkImageLayout enumeration member."); 862 } 863 864 865 static struct anv_state 866 alloc_surface_state(struct anv_device *device) 867 { 868 return anv_state_pool_alloc(&device->surface_state_pool, 64, 64); 869 } 870 871 static enum isl_channel_select 872 remap_swizzle(VkComponentSwizzle swizzle, VkComponentSwizzle component, 873 struct isl_swizzle format_swizzle) 874 { 875 if (swizzle == VK_COMPONENT_SWIZZLE_IDENTITY) 876 swizzle = component; 877 878 switch (swizzle) { 879 case VK_COMPONENT_SWIZZLE_ZERO: return ISL_CHANNEL_SELECT_ZERO; 880 case VK_COMPONENT_SWIZZLE_ONE: return ISL_CHANNEL_SELECT_ONE; 881 case VK_COMPONENT_SWIZZLE_R: return format_swizzle.r; 882 case VK_COMPONENT_SWIZZLE_G: return format_swizzle.g; 883 case VK_COMPONENT_SWIZZLE_B: return format_swizzle.b; 884 case VK_COMPONENT_SWIZZLE_A: return format_swizzle.a; 885 default: 886 unreachable("Invalid swizzle"); 887 } 888 } 889 890 void 891 anv_image_fill_surface_state(struct anv_device *device, 892 const struct anv_image *image, 893 VkImageAspectFlagBits aspect, 894 const struct isl_view *view_in, 895 isl_surf_usage_flags_t view_usage, 896 enum isl_aux_usage aux_usage, 897 const union isl_color_value *clear_color, 898 enum anv_image_view_state_flags flags, 899 struct anv_surface_state *state_inout, 900 struct brw_image_param *image_param_out) 901 { 902 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect); 903 904 const struct anv_surface *surface = &image->planes[plane].surface, 905 *aux_surface = &image->planes[plane].aux_surface; 906 907 struct isl_view view = *view_in; 908 view.usage |= view_usage; 909 910 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a 911 * compressed surface with a shadow surface, we use the shadow instead of 912 * the primary surface. The shadow surface will be tiled, unlike the main 913 * surface, so it should get significantly better performance. 914 */ 915 if (image->planes[plane].shadow_surface.isl.size > 0 && 916 isl_format_is_compressed(view.format) && 917 (flags & ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL)) { 918 assert(isl_format_is_compressed(surface->isl.format)); 919 assert(surface->isl.tiling == ISL_TILING_LINEAR); 920 assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR); 921 surface = &image->planes[plane].shadow_surface; 922 } 923 924 if (view_usage == ISL_SURF_USAGE_RENDER_TARGET_BIT) 925 view.swizzle = anv_swizzle_for_render(view.swizzle); 926 927 /* If this is a HiZ buffer we can sample from with a programmable clear 928 * value (SKL+), define the clear value to the optimal constant. 929 */ 930 union isl_color_value default_clear_color = { .u32 = { 0, } }; 931 if (device->info.gen >= 9 && aux_usage == ISL_AUX_USAGE_HIZ) 932 default_clear_color.f32[0] = ANV_HZ_FC_VAL; 933 if (!clear_color) 934 clear_color = &default_clear_color; 935 936 const uint64_t address = image->planes[plane].bo_offset + surface->offset; 937 const uint64_t aux_address = aux_usage == ISL_AUX_USAGE_NONE ? 938 0 : (image->planes[plane].bo_offset + aux_surface->offset); 939 940 if (view_usage == ISL_SURF_USAGE_STORAGE_BIT && 941 !(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY) && 942 !isl_has_matching_typed_storage_image_format(&device->info, 943 view.format)) { 944 /* In this case, we are a writeable storage buffer which needs to be 945 * lowered to linear. All tiling and offset calculations will be done in 946 * the shader. 947 */ 948 assert(aux_usage == ISL_AUX_USAGE_NONE); 949 isl_buffer_fill_state(&device->isl_dev, state_inout->state.map, 950 .address = address, 951 .size = surface->isl.size, 952 .format = ISL_FORMAT_RAW, 953 .stride = 1, 954 .mocs = device->default_mocs); 955 state_inout->address = address, 956 state_inout->aux_address = 0; 957 } else { 958 if (view_usage == ISL_SURF_USAGE_STORAGE_BIT && 959 !(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY)) { 960 /* Typed surface reads support a very limited subset of the shader 961 * image formats. Translate it into the closest format the hardware 962 * supports. 963 */ 964 assert(aux_usage == ISL_AUX_USAGE_NONE); 965 view.format = isl_lower_storage_image_format(&device->info, 966 view.format); 967 } 968 969 const struct isl_surf *isl_surf = &surface->isl; 970 971 struct isl_surf tmp_surf; 972 uint32_t offset_B = 0, tile_x_sa = 0, tile_y_sa = 0; 973 if (isl_format_is_compressed(surface->isl.format) && 974 !isl_format_is_compressed(view.format)) { 975 /* We're creating an uncompressed view of a compressed surface. This 976 * is allowed but only for a single level/layer. 977 */ 978 assert(surface->isl.samples == 1); 979 assert(view.levels == 1); 980 assert(view.array_len == 1); 981 982 isl_surf_get_image_surf(&device->isl_dev, isl_surf, 983 view.base_level, 984 surface->isl.dim == ISL_SURF_DIM_3D ? 985 0 : view.base_array_layer, 986 surface->isl.dim == ISL_SURF_DIM_3D ? 987 view.base_array_layer : 0, 988 &tmp_surf, 989 &offset_B, &tile_x_sa, &tile_y_sa); 990 991 /* The newly created image represents the one subimage we're 992 * referencing with this view so it only has one array slice and 993 * miplevel. 994 */ 995 view.base_array_layer = 0; 996 view.base_level = 0; 997 998 /* We're making an uncompressed view here. The image dimensions need 999 * to be scaled down by the block size. 1000 */ 1001 const struct isl_format_layout *fmtl = 1002 isl_format_get_layout(surface->isl.format); 1003 tmp_surf.format = view.format; 1004 tmp_surf.logical_level0_px.width = 1005 DIV_ROUND_UP(tmp_surf.logical_level0_px.width, fmtl->bw); 1006 tmp_surf.logical_level0_px.height = 1007 DIV_ROUND_UP(tmp_surf.logical_level0_px.height, fmtl->bh); 1008 tmp_surf.phys_level0_sa.width /= fmtl->bw; 1009 tmp_surf.phys_level0_sa.height /= fmtl->bh; 1010 tile_x_sa /= fmtl->bw; 1011 tile_y_sa /= fmtl->bh; 1012 1013 isl_surf = &tmp_surf; 1014 1015 if (device->info.gen <= 8) { 1016 assert(surface->isl.tiling == ISL_TILING_LINEAR); 1017 assert(tile_x_sa == 0); 1018 assert(tile_y_sa == 0); 1019 } 1020 } 1021 1022 isl_surf_fill_state(&device->isl_dev, state_inout->state.map, 1023 .surf = isl_surf, 1024 .view = &view, 1025 .address = address + offset_B, 1026 .clear_color = *clear_color, 1027 .aux_surf = &aux_surface->isl, 1028 .aux_usage = aux_usage, 1029 .aux_address = aux_address, 1030 .mocs = device->default_mocs, 1031 .x_offset_sa = tile_x_sa, 1032 .y_offset_sa = tile_y_sa); 1033 state_inout->address = address + offset_B; 1034 if (device->info.gen >= 8) { 1035 state_inout->aux_address = aux_address; 1036 } else { 1037 /* On gen7 and prior, the bottom 12 bits of the MCS base address are 1038 * used to store other information. This should be ok, however, 1039 * because surface buffer addresses are always 4K page alinged. 1040 */ 1041 uint32_t *aux_addr_dw = state_inout->state.map + 1042 device->isl_dev.ss.aux_addr_offset; 1043 assert((aux_address & 0xfff) == 0); 1044 assert(aux_address == (*aux_addr_dw & 0xfffff000)); 1045 state_inout->aux_address = *aux_addr_dw; 1046 } 1047 } 1048 1049 anv_state_flush(device, state_inout->state); 1050 1051 if (image_param_out) { 1052 assert(view_usage == ISL_SURF_USAGE_STORAGE_BIT); 1053 isl_surf_fill_image_param(&device->isl_dev, image_param_out, 1054 &surface->isl, &view); 1055 } 1056 } 1057 1058 static VkImageAspectFlags 1059 remap_aspect_flags(VkImageAspectFlags view_aspects) 1060 { 1061 if (view_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) { 1062 if (_mesa_bitcount(view_aspects) == 1) 1063 return VK_IMAGE_ASPECT_COLOR_BIT; 1064 1065 VkImageAspectFlags color_aspects = 0; 1066 for (uint32_t i = 0; i < _mesa_bitcount(view_aspects); i++) 1067 color_aspects |= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << i; 1068 return color_aspects; 1069 } 1070 /* No special remapping needed for depth & stencil aspects. */ 1071 return view_aspects; 1072 } 1073 1074 VkResult 1075 anv_CreateImageView(VkDevice _device, 1076 const VkImageViewCreateInfo *pCreateInfo, 1077 const VkAllocationCallbacks *pAllocator, 1078 VkImageView *pView) 1079 { 1080 ANV_FROM_HANDLE(anv_device, device, _device); 1081 ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image); 1082 struct anv_image_view *iview; 1083 1084 iview = vk_zalloc2(&device->alloc, pAllocator, sizeof(*iview), 8, 1085 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); 1086 if (iview == NULL) 1087 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); 1088 1089 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange; 1090 1091 assert(range->layerCount > 0); 1092 assert(range->baseMipLevel < image->levels); 1093 1094 const VkImageViewUsageCreateInfoKHR *usage_info = 1095 vk_find_struct_const(pCreateInfo, IMAGE_VIEW_USAGE_CREATE_INFO_KHR); 1096 VkImageUsageFlags view_usage = usage_info ? usage_info->usage : image->usage; 1097 /* View usage should be a subset of image usage */ 1098 assert((view_usage & ~image->usage) == 0); 1099 assert(view_usage & (VK_IMAGE_USAGE_SAMPLED_BIT | 1100 VK_IMAGE_USAGE_STORAGE_BIT | 1101 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT | 1102 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT | 1103 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)); 1104 1105 switch (image->type) { 1106 default: 1107 unreachable("bad VkImageType"); 1108 case VK_IMAGE_TYPE_1D: 1109 case VK_IMAGE_TYPE_2D: 1110 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1 <= image->array_size); 1111 break; 1112 case VK_IMAGE_TYPE_3D: 1113 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1 1114 <= anv_minify(image->extent.depth, range->baseMipLevel)); 1115 break; 1116 } 1117 1118 /* First expand aspects to the image's ones (for example 1119 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to 1120 * VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | 1121 * VK_IMAGE_ASPECT_PLANE_2_BIT_KHR for an image of format 1122 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR. 1123 */ 1124 VkImageAspectFlags expanded_aspects = 1125 anv_image_expand_aspects(image, range->aspectMask); 1126 1127 iview->image = image; 1128 1129 /* Remap the expanded aspects for the image view. For example if only 1130 * VK_IMAGE_ASPECT_PLANE_1_BIT_KHR was given in range->aspectMask, we will 1131 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of 1132 * the image view, it only has a single plane. 1133 */ 1134 iview->aspect_mask = remap_aspect_flags(expanded_aspects); 1135 iview->n_planes = anv_image_aspect_get_planes(iview->aspect_mask); 1136 iview->vk_format = pCreateInfo->format; 1137 1138 iview->extent = (VkExtent3D) { 1139 .width = anv_minify(image->extent.width , range->baseMipLevel), 1140 .height = anv_minify(image->extent.height, range->baseMipLevel), 1141 .depth = anv_minify(image->extent.depth , range->baseMipLevel), 1142 }; 1143 1144 /* Now go through the underlying image selected planes (computed in 1145 * expanded_aspects) and map them to planes in the image view. 1146 */ 1147 uint32_t iaspect_bit, vplane = 0; 1148 anv_foreach_image_aspect_bit(iaspect_bit, image, expanded_aspects) { 1149 uint32_t iplane = 1150 anv_image_aspect_to_plane(expanded_aspects, 1UL << iaspect_bit); 1151 VkImageAspectFlags vplane_aspect = 1152 anv_plane_to_aspect(iview->aspect_mask, vplane); 1153 struct anv_format_plane format = 1154 anv_get_format_plane(&device->info, pCreateInfo->format, 1155 vplane_aspect, image->tiling); 1156 1157 iview->planes[vplane].image_plane = iplane; 1158 1159 iview->planes[vplane].isl = (struct isl_view) { 1160 .format = format.isl_format, 1161 .base_level = range->baseMipLevel, 1162 .levels = anv_get_levelCount(image, range), 1163 .base_array_layer = range->baseArrayLayer, 1164 .array_len = anv_get_layerCount(image, range), 1165 .swizzle = { 1166 .r = remap_swizzle(pCreateInfo->components.r, 1167 VK_COMPONENT_SWIZZLE_R, format.swizzle), 1168 .g = remap_swizzle(pCreateInfo->components.g, 1169 VK_COMPONENT_SWIZZLE_G, format.swizzle), 1170 .b = remap_swizzle(pCreateInfo->components.b, 1171 VK_COMPONENT_SWIZZLE_B, format.swizzle), 1172 .a = remap_swizzle(pCreateInfo->components.a, 1173 VK_COMPONENT_SWIZZLE_A, format.swizzle), 1174 }, 1175 }; 1176 1177 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) { 1178 iview->planes[vplane].isl.base_array_layer = 0; 1179 iview->planes[vplane].isl.array_len = iview->extent.depth; 1180 } 1181 1182 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE || 1183 pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) { 1184 iview->planes[vplane].isl.usage = ISL_SURF_USAGE_CUBE_BIT; 1185 } else { 1186 iview->planes[vplane].isl.usage = 0; 1187 } 1188 1189 if (view_usage & VK_IMAGE_USAGE_SAMPLED_BIT || 1190 (view_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT && 1191 !(iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT))) { 1192 iview->planes[vplane].optimal_sampler_surface_state.state = alloc_surface_state(device); 1193 iview->planes[vplane].general_sampler_surface_state.state = alloc_surface_state(device); 1194 1195 enum isl_aux_usage general_aux_usage = 1196 anv_layout_to_aux_usage(&device->info, image, 1UL << iaspect_bit, 1197 VK_IMAGE_LAYOUT_GENERAL); 1198 enum isl_aux_usage optimal_aux_usage = 1199 anv_layout_to_aux_usage(&device->info, image, 1UL << iaspect_bit, 1200 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL); 1201 1202 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit, 1203 &iview->planes[vplane].isl, 1204 ISL_SURF_USAGE_TEXTURE_BIT, 1205 optimal_aux_usage, NULL, 1206 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL, 1207 &iview->planes[vplane].optimal_sampler_surface_state, 1208 NULL); 1209 1210 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit, 1211 &iview->planes[vplane].isl, 1212 ISL_SURF_USAGE_TEXTURE_BIT, 1213 general_aux_usage, NULL, 1214 0, 1215 &iview->planes[vplane].general_sampler_surface_state, 1216 NULL); 1217 } 1218 1219 /* NOTE: This one needs to go last since it may stomp isl_view.format */ 1220 if (view_usage & VK_IMAGE_USAGE_STORAGE_BIT) { 1221 iview->planes[vplane].storage_surface_state.state = alloc_surface_state(device); 1222 iview->planes[vplane].writeonly_storage_surface_state.state = alloc_surface_state(device); 1223 1224 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit, 1225 &iview->planes[vplane].isl, 1226 ISL_SURF_USAGE_STORAGE_BIT, 1227 ISL_AUX_USAGE_NONE, NULL, 1228 0, 1229 &iview->planes[vplane].storage_surface_state, 1230 &iview->planes[vplane].storage_image_param); 1231 1232 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit, 1233 &iview->planes[vplane].isl, 1234 ISL_SURF_USAGE_STORAGE_BIT, 1235 ISL_AUX_USAGE_NONE, NULL, 1236 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY, 1237 &iview->planes[vplane].writeonly_storage_surface_state, 1238 NULL); 1239 } 1240 1241 vplane++; 1242 } 1243 1244 *pView = anv_image_view_to_handle(iview); 1245 1246 return VK_SUCCESS; 1247 } 1248 1249 void 1250 anv_DestroyImageView(VkDevice _device, VkImageView _iview, 1251 const VkAllocationCallbacks *pAllocator) 1252 { 1253 ANV_FROM_HANDLE(anv_device, device, _device); 1254 ANV_FROM_HANDLE(anv_image_view, iview, _iview); 1255 1256 if (!iview) 1257 return; 1258 1259 for (uint32_t plane = 0; plane < iview->n_planes; plane++) { 1260 if (iview->planes[plane].optimal_sampler_surface_state.state.alloc_size > 0) { 1261 anv_state_pool_free(&device->surface_state_pool, 1262 iview->planes[plane].optimal_sampler_surface_state.state); 1263 } 1264 1265 if (iview->planes[plane].general_sampler_surface_state.state.alloc_size > 0) { 1266 anv_state_pool_free(&device->surface_state_pool, 1267 iview->planes[plane].general_sampler_surface_state.state); 1268 } 1269 1270 if (iview->planes[plane].storage_surface_state.state.alloc_size > 0) { 1271 anv_state_pool_free(&device->surface_state_pool, 1272 iview->planes[plane].storage_surface_state.state); 1273 } 1274 1275 if (iview->planes[plane].writeonly_storage_surface_state.state.alloc_size > 0) { 1276 anv_state_pool_free(&device->surface_state_pool, 1277 iview->planes[plane].writeonly_storage_surface_state.state); 1278 } 1279 } 1280 1281 vk_free2(&device->alloc, pAllocator, iview); 1282 } 1283 1284 1285 VkResult 1286 anv_CreateBufferView(VkDevice _device, 1287 const VkBufferViewCreateInfo *pCreateInfo, 1288 const VkAllocationCallbacks *pAllocator, 1289 VkBufferView *pView) 1290 { 1291 ANV_FROM_HANDLE(anv_device, device, _device); 1292 ANV_FROM_HANDLE(anv_buffer, buffer, pCreateInfo->buffer); 1293 struct anv_buffer_view *view; 1294 1295 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8, 1296 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); 1297 if (!view) 1298 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); 1299 1300 /* TODO: Handle the format swizzle? */ 1301 1302 view->format = anv_get_isl_format(&device->info, pCreateInfo->format, 1303 VK_IMAGE_ASPECT_COLOR_BIT, 1304 VK_IMAGE_TILING_LINEAR); 1305 const uint32_t format_bs = isl_format_get_layout(view->format)->bpb / 8; 1306 view->bo = buffer->bo; 1307 view->offset = buffer->offset + pCreateInfo->offset; 1308 view->range = anv_buffer_get_range(buffer, pCreateInfo->offset, 1309 pCreateInfo->range); 1310 view->range = align_down_npot_u32(view->range, format_bs); 1311 1312 if (buffer->usage & VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT) { 1313 view->surface_state = alloc_surface_state(device); 1314 1315 anv_fill_buffer_surface_state(device, view->surface_state, 1316 view->format, 1317 view->offset, view->range, format_bs); 1318 } else { 1319 view->surface_state = (struct anv_state){ 0 }; 1320 } 1321 1322 if (buffer->usage & VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT) { 1323 view->storage_surface_state = alloc_surface_state(device); 1324 view->writeonly_storage_surface_state = alloc_surface_state(device); 1325 1326 enum isl_format storage_format = 1327 isl_has_matching_typed_storage_image_format(&device->info, 1328 view->format) ? 1329 isl_lower_storage_image_format(&device->info, view->format) : 1330 ISL_FORMAT_RAW; 1331 1332 anv_fill_buffer_surface_state(device, view->storage_surface_state, 1333 storage_format, 1334 view->offset, view->range, 1335 (storage_format == ISL_FORMAT_RAW ? 1 : 1336 isl_format_get_layout(storage_format)->bpb / 8)); 1337 1338 /* Write-only accesses should use the original format. */ 1339 anv_fill_buffer_surface_state(device, view->writeonly_storage_surface_state, 1340 view->format, 1341 view->offset, view->range, 1342 isl_format_get_layout(view->format)->bpb / 8); 1343 1344 isl_buffer_fill_image_param(&device->isl_dev, 1345 &view->storage_image_param, 1346 view->format, view->range); 1347 } else { 1348 view->storage_surface_state = (struct anv_state){ 0 }; 1349 view->writeonly_storage_surface_state = (struct anv_state){ 0 }; 1350 } 1351 1352 *pView = anv_buffer_view_to_handle(view); 1353 1354 return VK_SUCCESS; 1355 } 1356 1357 void 1358 anv_DestroyBufferView(VkDevice _device, VkBufferView bufferView, 1359 const VkAllocationCallbacks *pAllocator) 1360 { 1361 ANV_FROM_HANDLE(anv_device, device, _device); 1362 ANV_FROM_HANDLE(anv_buffer_view, view, bufferView); 1363 1364 if (!view) 1365 return; 1366 1367 if (view->surface_state.alloc_size > 0) 1368 anv_state_pool_free(&device->surface_state_pool, 1369 view->surface_state); 1370 1371 if (view->storage_surface_state.alloc_size > 0) 1372 anv_state_pool_free(&device->surface_state_pool, 1373 view->storage_surface_state); 1374 1375 if (view->writeonly_storage_surface_state.alloc_size > 0) 1376 anv_state_pool_free(&device->surface_state_pool, 1377 view->writeonly_storage_surface_state); 1378 1379 vk_free2(&device->alloc, pAllocator, view); 1380 } 1381 1382 const struct anv_surface * 1383 anv_image_get_surface_for_aspect_mask(const struct anv_image *image, 1384 VkImageAspectFlags aspect_mask) 1385 { 1386 VkImageAspectFlags sanitized_mask; 1387 1388 switch (aspect_mask) { 1389 case VK_IMAGE_ASPECT_COLOR_BIT: 1390 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT); 1391 sanitized_mask = VK_IMAGE_ASPECT_COLOR_BIT; 1392 break; 1393 case VK_IMAGE_ASPECT_DEPTH_BIT: 1394 assert(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT); 1395 sanitized_mask = VK_IMAGE_ASPECT_DEPTH_BIT; 1396 break; 1397 case VK_IMAGE_ASPECT_STENCIL_BIT: 1398 assert(image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT); 1399 sanitized_mask = VK_IMAGE_ASPECT_STENCIL_BIT; 1400 break; 1401 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT: 1402 /* FINISHME: The Vulkan spec (git a511ba2) requires support for 1403 * combined depth stencil formats. Specifically, it states: 1404 * 1405 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or 1406 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported. 1407 * 1408 * Image views with both depth and stencil aspects are only valid for 1409 * render target attachments, in which case 1410 * cmd_buffer_emit_depth_stencil() will pick out both the depth and 1411 * stencil surfaces from the underlying surface. 1412 */ 1413 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) { 1414 sanitized_mask = VK_IMAGE_ASPECT_DEPTH_BIT; 1415 } else { 1416 assert(image->aspects == VK_IMAGE_ASPECT_STENCIL_BIT); 1417 sanitized_mask = VK_IMAGE_ASPECT_STENCIL_BIT; 1418 } 1419 break; 1420 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR: 1421 assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0); 1422 sanitized_mask = VK_IMAGE_ASPECT_PLANE_0_BIT_KHR; 1423 break; 1424 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR: 1425 assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0); 1426 sanitized_mask = VK_IMAGE_ASPECT_PLANE_1_BIT_KHR; 1427 break; 1428 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR: 1429 assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0); 1430 sanitized_mask = VK_IMAGE_ASPECT_PLANE_2_BIT_KHR; 1431 break; 1432 default: 1433 unreachable("image does not have aspect"); 1434 return NULL; 1435 } 1436 1437 uint32_t plane = anv_image_aspect_to_plane(image->aspects, sanitized_mask); 1438 return &image->planes[plane].surface; 1439 } 1440
