| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen8_multisample_state.c | 61 brw_load_register_imm32(brw, GEN7_CACHE_MODE_0, 0);
|
| gen7_sol_state.c | 57 brw_load_register_imm32(brw, GEN7_SO_WRITE_OFFSET(i), 0);
|
| brw_state_upload.c | 66 brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS,
89 brw_load_register_imm32(brw, GEN7_CACHE_MODE_1,
96 brw_load_register_imm32(brw, GEN7_GT_MODE,
|
| gen7_l3_state.c | 131 brw_load_register_imm32(brw, GEN8_L3CNTLREG, imm_data);
|
| gen8_depth_state.c | 334 brw_load_register_imm32(brw, GEN7_CACHE_MODE_1,
|
| hsw_sol.c | 93 brw_load_register_imm32(brw, HSW_CS_GPR(0) + 4, 0);
|
| hsw_queryobj.c | 158 brw_load_register_imm32(brw, HSW_CS_GPR(0) + 4, 0);
|
| brw_draw.c | 246 brw_load_register_imm32(brw, GEN7_3DPRIM_BASE_VERTEX, 0);
[all...] |
| brw_misc_state.c | 531 brw_load_register_imm32(brw, SLICE_COMMON_ECO_CHICKEN1,
|
| brw_context.h | [all...] |
| intel_batchbuffer.c | 1307 brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm) function
[all...] |
