| /external/u-boot/drivers/ddr/marvell/a38x/ |
| ddr3_training_hw_algo.c | 44 u32 cs_num = 0, max_read_sample = 0, min_read_sample = 0x1f; local
61 for (cs_num = 0; cs_num < MAX_CS_NUM; cs_num++) {
62 read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num);
65 if (read_sample[cs_num] >= max_read_sample) {
66 if (read_sample[cs_num] == max_read_sample)
69 max_read_sample = read_sample[cs_num];
78 RL_PHY_REG(cs_num),
115 u32 cs_num; local
[all...] |
| ddr3_training_ip_bist.h | 43 u32 offset, u32 cs_num, u32 pattern_addr_length);
45 u32 cs_num);
|
| ddr3_init.c | 187 u32 cs_num; local
193 CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num));
209 if (cs_num == 1) {
|
| ddr3_training_ip_engine.h | 60 enum hws_ddr_cs cs_type, u32 cs_num,
74 enum hws_ddr_cs train_cs_type, u32 cs_num,
|
| ddr3_training_pbs.c | 45 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; local
80 pbs_pattern, search_edge, CS_SINGLE, cs_num,
211 search_edge, CS_SINGLE, cs_num,
394 CS_SINGLE, cs_num, train_status);
523 cs_num, train_status);
620 search_edge, CS_SINGLE, cs_num,
937 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode)
941 PBS_RX_PHY_REG(cs_num, 0) :
942 PBS_TX_PHY_REG(cs_num , 0);
947 (pbs_mode == PBS_RX_MODE) ? "Rx" : "Tx", cs_num);
[all...] |
| ddr3_training.c | 10 #define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num])
258 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable)
269 SDRAM_ADDR_CTRL_REG, (data << (cs_num * 4)),
270 0x3 << (cs_num * 4)));
277 (addr_hi << (2 + cs_num * 4)),
278 0x3 << (2 + cs_num * 4)));
284 data_high << (20 + cs_num), 1 << (20 + cs_num)));
289 SDRAM_ADDR_CTRL_REG, 1 << (16 + cs_num),
355 u32 cs_num; local
1270 u32 cs_num; local
1896 u32 if_id, bus_num, cs_bitmask, data_val, cs_num; local
[all...] |
| ddr3_training_bist.c | 25 u32 offset, u32 cs_num, u32 pattern_addr_length)
54 rd_mode, cs_num, addr_stress_jump, duration);
118 u32 cs_num)
128 hws_ddr3_cs_base_adr_calc(i, cs_num, &win_base);
134 cs_num, 15);
145 cs_num, 15);
|
| ddr3_init.h | 188 int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num);
192 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
|
| ddr3_training_ip_engine.c | 343 enum hws_ddr_cs cs_type, u32 cs_num,
391 ODPG_DATA_CTRL_REG, 0x3 | cs_num << 26,
626 u32 delay_between_burst, u32 rd_mode, u32 cs_num,
634 (rx_phases << 21) | (rd_mode << 25) | (cs_num << 26) |
[all...] |
| ddr3_training_ip.h | 121 u8 cs_num; member in struct:cs_element
|
| ddr3_training_ip_prv_if.h | 78 enum hws_bist_operation oper_type, u32 offset, u32 cs_num,
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| ddr3_training_ip_flow.h | 175 u32 delay_between_burst, u32 rd_mode, u32 cs_num,
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Include/Library/ |
| SerdesLib.h | 122 int serdes_cs_write(UINT32 macro,UINT32 cs_num,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value);
123 UINT32 serdes_cs_read(UINT32 macro,UINT32 cs_num,UINT32 reg_num);
|
| /external/u-boot/drivers/ddr/marvell/axp/ |
| ddr3_sdram.c | 494 u32 chan, byte_count, cs_num, byte; local
510 cs_num = (src / (1 + SDRAM_CS_SIZE));
512 ((cs_num << 1) | (1 << 0)));
517 cs_num = (dst / (1 + SDRAM_CS_SIZE));
519 ((cs_num << 25) | (1 << 24)));
|
| ddr3_spd.c | 581 u32 cs, cl, cs_num, cs_ena; local
638 cs_num = 0;
640 cs_num = ddr3_get_cs_num_from_reg();
644 cs_num += dimm_info[dimm].num_of_module_ranks;
646 if (cs_num > MAX_CS) {
687 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Number of CS = ", cs_num, 1);
1071 if (cs_num > 1)
[all...] |
