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      1 /** @file
      2 *
      3 *  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
      4 *  Copyright (c) 2016, Linaro Limited. All rights reserved.
      5 *
      6 *  This program and the accompanying materials
      7 *  are licensed and made available under the terms and conditions of the BSD License
      8 *  which accompanies this distribution.  The full text of the license may be found at
      9 *  http://opensource.org/licenses/bsd-license.php
     10 *
     11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     13 *
     14 **/
     15 
     16 #ifndef _SERDES_LIB_H_
     17 #define _SERDES_LIB_H_
     18 
     19 typedef enum {
     20   EmHilink0Hccs1X8 = 0,
     21   EmHilink0Pcie1X8 = 2,
     22   EmHilink0Pcie1X4Pcie2X4 = 3,
     23   EmHilink0Sas2X8 = 4,
     24   EmHilink0Hccs1X8Width16,
     25   EmHilink0Hccs1X8Width32,
     26 } HILINK0_MODE_TYPE;
     27 
     28 typedef enum {
     29   EmHilink1Sas2X1 = 0,
     30   EmHilink1Hccs0X8 = 1,
     31   EmHilink1Pcie0X8 = 2,
     32   EmHilink1Hccs0X8Width16,
     33   EmHilink1Hccs0X8Width32,
     34 } HILINK1_MODE_TYPE;
     35 
     36 typedef enum {
     37   EmHilink2Pcie2X8 = 0,
     38   EmHilink2Sas0X8 = 2,
     39 } HILINK2_MODE_TYPE;
     40 
     41 typedef enum {
     42   EmHilink5Pcie3X4 = 0,
     43   EmHilink5Pcie2X2Pcie3X2 = 1,
     44   EmHilink5Sas1X4 = 2,
     45 } HILINK5_MODE_TYPE;
     46 
     47 typedef enum {
     48   Em32coreEvbBoard = 0,
     49   Em16coreEvbBoard = 1,
     50   EmV2R1CO5Borad = 2,
     51   EmOtherBorad
     52 } BOARD_TYPE;
     53 
     54 
     55 typedef struct {
     56   HILINK0_MODE_TYPE Hilink0Mode;
     57   HILINK1_MODE_TYPE Hilink1Mode;
     58   HILINK2_MODE_TYPE Hilink2Mode;
     59   UINT32 Hilink3Mode;
     60   UINT32 Hilink4Mode;
     61   HILINK5_MODE_TYPE Hilink5Mode;
     62   UINT32 Hilink6Mode;
     63   UINT32 UseSsc;
     64 } SERDES_PARAM;
     65 
     66 
     67 #define SERDES_INVALID_MACRO_ID  0xFFFFFFFF
     68 #define SERDES_INVALID_LANE_NUM  0xFFFFFFFF
     69 #define SERDES_INVALID_RATE_MODE  0xFFFFFFFF
     70 
     71 typedef struct {
     72   UINT32 MacroId;
     73   UINT32 DsNum;
     74   UINT32 DsCfg;
     75 } SERDES_POLARITY_INVERT;
     76 
     77 EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId);
     78 extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
     79 extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
     80 UINT32 GetEthType(UINT8 EthChannel);
     81 
     82 EFI_STATUS
     83 EfiSerdesInitWrap (VOID);
     84 
     85 void SRE_SerdesEnableCTLEDFE(UINT32 macro, UINT32 lane, UINT32 ulDsCfg);
     86 
     87 //EYE test
     88 UINT32 serdes_eye_test(UINT32 uwMacroId, UINT32 uwDsNum, UINT32 eyemode, UINT32 scanwindowvalue, UINT32 uwRateData);
     89 
     90 UINT32 Serdes_ReadBert(UINT32   ulMacroId , UINT32   ulDsNum);
     91 
     92 //PRBS test
     93 int serdes_prbs_test(UINT8 macro, UINT8 lane, UINT8 prbstype);
     94 
     95 int serdes_prbs_test_cancle(UINT8 macro,UINT8 lane);
     96 
     97 //CTLE/DFE
     98 void serdes_ctle_adaptation_close(UINT32 macro,UINT32 lane);
     99 
    100 void serdes_ctle_adaptation_open(UINT32 macro,UINT32 lane);
    101 
    102 void serdes_dfe_adaptation_close(UINT32 macro,UINT32 lane);
    103 
    104 void serdes_dfe_adaptation_open(UINT32 macro,UINT32 lane);
    105 
    106 void serdes_ctle_dfe_reset(UINT32 macro,UINT32 lane);
    107 //int serdes_reset(UINT32 macro);
    108 //int serdes_release_reset(UINT32 macro);
    109 void Custom_Wave(UINT32 macro,UINT32 lane,UINT32 mode);
    110 void serdes_ffe_show(UINT32 macro,UINT32 lane);
    111 void serdes_dfe_show(UINT32 macro,UINT32 lane);
    112 int  serdes_read_bert(UINT8 macro, UINT8 lane);
    113 void  serdes_clean_bert(UINT8 macro, UINT8 lane);
    114 int  serdes_get_four_point_eye_diagram(UINT32 macro, UINT32 lane,UINT32 eyemode, UINT32 data_rate);
    115 void serdes_release_mcu(UINT32 macro,UINT32 val);
    116 int hilink_write(UINT32 macro, UINT32 reg, UINT32 value);
    117 int hilink_read(UINT32 macro, UINT32 reg, UINT32 *value);
    118 int serdes_tx_to_rx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);//TXRXPARLPBKEN
    119 int serdes_rx_to_tx_parallel_loopback(UINT8 macro,UINT8 lane,UINT8 val);
    120 int serdes_tx_to_rx_serial_loopback(UINT8 macro,UINT8 lane,UINT8 val);
    121 void serdes_ctle_show(UINT32 macro,UINT32 lane);
    122 int serdes_cs_write(UINT32 macro,UINT32 cs_num,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value);
    123 UINT32 serdes_cs_read(UINT32 macro,UINT32 cs_num,UINT32 reg_num);
    124 int serdes_ds_write(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num,UINT32 bit_high,UINT32 bit_low,UINT32 value);
    125 int serdes_ds_read(UINT32 macro,UINT32 ds_num,UINT32 ds_index,UINT32 reg_num);
    126 int report_serdes_mux(void);
    127 int serdes_key_reg_show(UINT32 macro);
    128 void serdes_state_show(UINT32 macro);
    129 UINT32 Serdes_ReadBert(UINT32   ulMacroId , UINT32   ulDsNum);
    130 
    131 #endif
    132