1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Stefano Babic, DENX Software Engineering, sbabic (at) denx.de. 5 */ 6 7 #ifndef _IMXIMAGE_H_ 8 #define _IMXIMAGE_H_ 9 10 #define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */ 11 #define MAX_PLUGIN_CODE_SIZE (64 * 1024) 12 #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */ 13 #define APP_CODE_BARKER 0xB1 14 #define DCD_BARKER 0xB17219E9 15 16 /* Specify the offset of the IVT in the IMX header as expected by BootROM */ 17 #define BOOTROM_IVT_HDR_OFFSET 0xC00 18 19 /* 20 * NOTE: This file must be kept in sync with arch/arm/include/asm/\ 21 * mach-imx/imximage.cfg because tools/imximage.c can not 22 * cross-include headers from arch/arm/ and vice-versa. 23 */ 24 #define CMD_DATA_STR "DATA" 25 26 /* Initial Vector Table Offset */ 27 #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF 28 #define FLASH_OFFSET_STANDARD 0x400 29 #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD 30 #define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD 31 #define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD 32 #define FLASH_OFFSET_ONENAND 0x100 33 #define FLASH_OFFSET_NOR 0x1000 34 #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD 35 #define FLASH_OFFSET_QSPI 0x1000 36 37 /* Initial Load Region Size */ 38 #define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF 39 #define FLASH_LOADSIZE_STANDARD 0x1000 40 #define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD 41 #define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD 42 #define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD 43 #define FLASH_LOADSIZE_ONENAND 0x400 44 #define FLASH_LOADSIZE_NOR 0x0 /* entire image */ 45 #define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD 46 #define FLASH_LOADSIZE_QSPI 0x0 /* entire image */ 47 48 /* Command tags and parameters */ 49 #define IVT_HEADER_TAG 0xD1 50 #define IVT_VERSION 0x40 51 #define DCD_HEADER_TAG 0xD2 52 #define DCD_VERSION 0x40 53 #define DCD_WRITE_DATA_COMMAND_TAG 0xCC 54 #define DCD_WRITE_DATA_PARAM 0x4 55 #define DCD_WRITE_CLR_BIT_PARAM 0xC 56 #define DCD_WRITE_SET_BIT_PARAM 0x1C 57 #define DCD_CHECK_DATA_COMMAND_TAG 0xCF 58 #define DCD_CHECK_BITS_SET_PARAM 0x14 59 #define DCD_CHECK_BITS_CLR_PARAM 0x04 60 61 #ifndef __ASSEMBLY__ 62 enum imximage_cmd { 63 CMD_INVALID, 64 CMD_IMAGE_VERSION, 65 CMD_BOOT_FROM, 66 CMD_BOOT_OFFSET, 67 CMD_WRITE_DATA, 68 CMD_WRITE_CLR_BIT, 69 CMD_WRITE_SET_BIT, 70 CMD_CHECK_BITS_SET, 71 CMD_CHECK_BITS_CLR, 72 CMD_CSF, 73 CMD_PLUGIN, 74 }; 75 76 enum imximage_fld_types { 77 CFG_INVALID = -1, 78 CFG_COMMAND, 79 CFG_REG_SIZE, 80 CFG_REG_ADDRESS, 81 CFG_REG_VALUE 82 }; 83 84 enum imximage_version { 85 IMXIMAGE_VER_INVALID = -1, 86 IMXIMAGE_V1 = 1, 87 IMXIMAGE_V2 88 }; 89 90 typedef struct { 91 uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */ 92 uint32_t addr; /* Address to write to */ 93 uint32_t value; /* Data to write */ 94 } dcd_type_addr_data_t; 95 96 typedef struct { 97 uint32_t barker; /* Barker for sanity check */ 98 uint32_t length; /* Device configuration length (without preamble) */ 99 } dcd_preamble_t; 100 101 typedef struct { 102 dcd_preamble_t preamble; 103 dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1]; 104 } dcd_v1_t; 105 106 typedef struct { 107 uint32_t app_code_jump_vector; 108 uint32_t app_code_barker; 109 uint32_t app_code_csf; 110 uint32_t dcd_ptr_ptr; 111 uint32_t super_root_key; 112 uint32_t dcd_ptr; 113 uint32_t app_dest_ptr; 114 } flash_header_v1_t; 115 116 typedef struct { 117 uint32_t length; /* Length of data to be read from flash */ 118 } flash_cfg_parms_t; 119 120 typedef struct { 121 flash_header_v1_t fhdr; 122 dcd_v1_t dcd_table; 123 flash_cfg_parms_t ext_header; 124 } imx_header_v1_t; 125 126 typedef struct { 127 uint32_t addr; 128 uint32_t value; 129 } dcd_addr_data_t; 130 131 typedef struct { 132 uint8_t tag; 133 uint16_t length; 134 uint8_t version; 135 } __attribute__((packed)) ivt_header_t; 136 137 typedef struct { 138 uint8_t tag; 139 uint16_t length; 140 uint8_t param; 141 } __attribute__((packed)) write_dcd_command_t; 142 143 struct dcd_v2_cmd { 144 write_dcd_command_t write_dcd_command; 145 dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2]; 146 }; 147 148 typedef struct { 149 ivt_header_t header; 150 struct dcd_v2_cmd dcd_cmd; 151 uint32_t padding[1]; /* end up on an 8-byte boundary */ 152 } dcd_v2_t; 153 154 typedef struct { 155 uint32_t start; 156 uint32_t size; 157 uint32_t plugin; 158 } boot_data_t; 159 160 typedef struct { 161 ivt_header_t header; 162 uint32_t entry; 163 uint32_t reserved1; 164 uint32_t dcd_ptr; 165 uint32_t boot_data_ptr; 166 uint32_t self; 167 uint32_t csf; 168 uint32_t reserved2; 169 } flash_header_v2_t; 170 171 typedef struct { 172 flash_header_v2_t fhdr; 173 boot_data_t boot_data; 174 union { 175 dcd_v2_t dcd_table; 176 char plugin_code[MAX_PLUGIN_CODE_SIZE]; 177 } data; 178 } imx_header_v2_t; 179 180 /* The header must be aligned to 4k on MX53 for NAND boot */ 181 struct imx_header { 182 union { 183 imx_header_v1_t hdr_v1; 184 imx_header_v2_t hdr_v2; 185 } header; 186 }; 187 188 typedef void (*set_dcd_val_t)(struct imx_header *imxhdr, 189 char *name, int lineno, 190 int fld, uint32_t value, 191 uint32_t off); 192 193 typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len, 194 int32_t cmd); 195 196 typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr, 197 uint32_t dcd_len, 198 char *name, int lineno); 199 200 typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len, 201 uint32_t entry_point, uint32_t flash_offset); 202 203 #endif /* __ASSEMBLY__ */ 204 #endif /* _IMXIMAGE_H_ */ 205
