/external/u-boot/board/freescale/corenet_ds/ |
p4080ds_ddr.c | 92 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, 124 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, 156 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, 188 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, 220 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, 252 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, 284 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, 316 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
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/external/u-boot/board/freescale/p1_twr/ |
ddr.c | 35 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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/external/u-boot/board/freescale/bsc9132qds/ |
ddr.c | 26 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, 53 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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/external/u-boot/board/freescale/ls1043ardb/ |
ddr.h | 64 .ddr_sdram_cfg_2 = 0x00401100,
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/external/u-boot/drivers/ddr/fsl/ |
fsl_ddr_gen4.c | 218 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 228 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 236 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { 282 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 414 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { 434 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 465 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
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mpc85xx_ddr_gen3.c | 153 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 163 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 207 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); 332 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 431 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ 485 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK); 503 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
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mpc85xx_ddr_gen2.c | 70 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 89 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
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mpc86xx_ddr.c | 55 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 77 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
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arm_ddr_gen3.c | 130 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); 140 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); 230 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
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ctrl_regs.c | 871 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ 909 * + [DDR_SDRAM_CFG_2[NUM_PR] 950 ddr->ddr_sdram_cfg_2 = (0 969 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); [all...] |
interactive.c | 633 CFG_REGS(ddr_sdram_cfg_2), 724 CFG_REGS(ddr_sdram_cfg_2), [all...] |
/external/u-boot/board/Arcturus/ucp1020/ |
ddr.c | 95 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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/external/u-boot/board/freescale/p1010rdb/ |
ddr.c | 29 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, 56 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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/external/u-boot/board/freescale/bsc9131rdb/ |
ddr.c | 27 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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/external/u-boot/board/freescale/p1_p2_rdb_pc/ |
ddr.c | 227 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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/external/u-boot/include/ |
fsl_ddr_sdram.h | 253 unsigned int ddr_sdram_cfg_2; member in struct:fsl_ddr_cfg_regs_s
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