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Searched
refs:div_fsys1
(Results
1 - 6
of
6
) sorted by null
/external/u-boot/arch/arm/mach-exynos/
clock_init_exynos4.c
69
writel(CLK_DIV_FSYS1_VAL, &clk->
div_fsys1
);
clock.c
408
div = sub_div = readl(&clk->
div_fsys1
);
502
div = readl(&clk->
div_fsys1
);
806
ratio = readl(&clk->
div_fsys1
);
807
pre_ratio = readl(&clk->
div_fsys1
);
848
addr = (unsigned int)&clk->
div_fsys1
;
881
addr = (unsigned int)&clk->
div_fsys1
;
905
addr = (unsigned int)&clk->
div_fsys1
;
[
all
...]
clock_init_exynos5.c
942
writel(CLK_DIV_FSYS1_VAL, &clk->
div_fsys1
);
999
div_mmc = readl((unsigned int) &clk->
div_fsys1
) & ~FSYS1_MMC0_DIV_MASK;
1001
writel(div_mmc, (unsigned int) &clk->
div_fsys1
);
/external/u-boot/arch/arm/mach-exynos/include/mach/
clock.h
95
unsigned int
div_fsys1
;
member in struct:exynos4_clock
332
unsigned int
div_fsys1
;
member in struct:exynos4x12_clock
723
unsigned int
div_fsys1
;
member in struct:exynos5_clock
1131
unsigned int
div_fsys1
;
member in struct:exynos5420_clock
[
all
...]
/external/u-boot/board/samsung/odroid/
odroid.c
315
clrsetbits_le32(&clk->
div_fsys1
, clr, set);
/external/u-boot/board/samsung/trats/
trats.c
329
writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->
div_fsys1
);
Completed in 3568 milliseconds