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      1 /* SPDX-License-Identifier: GPL-2.0+ */
      2 /*
      3  * (C) Copyright 2010 Samsung Electronics
      4  * Minkyu Kang <mk7.kang (at) samsung.com>
      5  */
      6 
      7 #ifndef __ASM_ARM_ARCH_CLOCK_H_
      8 #define __ASM_ARM_ARCH_CLOCK_H_
      9 
     10 #ifndef __ASSEMBLY__
     11 struct exynos4_clock {
     12 	unsigned char	res1[0x4200];
     13 	unsigned int	src_leftbus;
     14 	unsigned char	res2[0x1fc];
     15 	unsigned int	mux_stat_leftbus;
     16 	unsigned char	res4[0xfc];
     17 	unsigned int	div_leftbus;
     18 	unsigned char	res5[0xfc];
     19 	unsigned int	div_stat_leftbus;
     20 	unsigned char	res6[0x1fc];
     21 	unsigned int	gate_ip_leftbus;
     22 	unsigned char	res7[0x1fc];
     23 	unsigned int	clkout_leftbus;
     24 	unsigned int	clkout_leftbus_div_stat;
     25 	unsigned char	res8[0x37f8];
     26 	unsigned int	src_rightbus;
     27 	unsigned char	res9[0x1fc];
     28 	unsigned int	mux_stat_rightbus;
     29 	unsigned char	res10[0xfc];
     30 	unsigned int	div_rightbus;
     31 	unsigned char	res11[0xfc];
     32 	unsigned int	div_stat_rightbus;
     33 	unsigned char	res12[0x1fc];
     34 	unsigned int	gate_ip_rightbus;
     35 	unsigned char	res13[0x1fc];
     36 	unsigned int	clkout_rightbus;
     37 	unsigned int	clkout_rightbus_div_stat;
     38 	unsigned char	res14[0x3608];
     39 	unsigned int	epll_lock;
     40 	unsigned char	res15[0xc];
     41 	unsigned int	vpll_lock;
     42 	unsigned char	res16[0xec];
     43 	unsigned int	epll_con0;
     44 	unsigned int	epll_con1;
     45 	unsigned char	res17[0x8];
     46 	unsigned int	vpll_con0;
     47 	unsigned int	vpll_con1;
     48 	unsigned char	res18[0xe8];
     49 	unsigned int	src_top0;
     50 	unsigned int	src_top1;
     51 	unsigned char	res19[0x8];
     52 	unsigned int	src_cam;
     53 	unsigned int	src_tv;
     54 	unsigned int	src_mfc;
     55 	unsigned int	src_g3d;
     56 	unsigned int	src_image;
     57 	unsigned int	src_lcd0;
     58 	unsigned int	src_lcd1;
     59 	unsigned int	src_maudio;
     60 	unsigned int	src_fsys;
     61 	unsigned char	res20[0xc];
     62 	unsigned int	src_peril0;
     63 	unsigned int	src_peril1;
     64 	unsigned char	res21[0xb8];
     65 	unsigned int	src_mask_top;
     66 	unsigned char	res22[0xc];
     67 	unsigned int	src_mask_cam;
     68 	unsigned int	src_mask_tv;
     69 	unsigned char	res23[0xc];
     70 	unsigned int	src_mask_lcd0;
     71 	unsigned int	src_mask_lcd1;
     72 	unsigned int	src_mask_maudio;
     73 	unsigned int	src_mask_fsys;
     74 	unsigned char	res24[0xc];
     75 	unsigned int	src_mask_peril0;
     76 	unsigned int	src_mask_peril1;
     77 	unsigned char	res25[0xb8];
     78 	unsigned int	mux_stat_top;
     79 	unsigned char	res26[0x14];
     80 	unsigned int	mux_stat_mfc;
     81 	unsigned int	mux_stat_g3d;
     82 	unsigned int	mux_stat_image;
     83 	unsigned char	res27[0xdc];
     84 	unsigned int	div_top;
     85 	unsigned char	res28[0xc];
     86 	unsigned int	div_cam;
     87 	unsigned int	div_tv;
     88 	unsigned int	div_mfc;
     89 	unsigned int	div_g3d;
     90 	unsigned int	div_image;
     91 	unsigned int	div_lcd0;
     92 	unsigned int	div_lcd1;
     93 	unsigned int	div_maudio;
     94 	unsigned int	div_fsys0;
     95 	unsigned int	div_fsys1;
     96 	unsigned int	div_fsys2;
     97 	unsigned int	div_fsys3;
     98 	unsigned int	div_peril0;
     99 	unsigned int	div_peril1;
    100 	unsigned int	div_peril2;
    101 	unsigned int	div_peril3;
    102 	unsigned int	div_peril4;
    103 	unsigned int	div_peril5;
    104 	unsigned char	res29[0x18];
    105 	unsigned int	div2_ratio;
    106 	unsigned char	res30[0x8c];
    107 	unsigned int	div_stat_top;
    108 	unsigned char	res31[0xc];
    109 	unsigned int	div_stat_cam;
    110 	unsigned int	div_stat_tv;
    111 	unsigned int	div_stat_mfc;
    112 	unsigned int	div_stat_g3d;
    113 	unsigned int	div_stat_image;
    114 	unsigned int	div_stat_lcd0;
    115 	unsigned int	div_stat_lcd1;
    116 	unsigned int	div_stat_maudio;
    117 	unsigned int	div_stat_fsys0;
    118 	unsigned int	div_stat_fsys1;
    119 	unsigned int	div_stat_fsys2;
    120 	unsigned int	div_stat_fsys3;
    121 	unsigned int	div_stat_peril0;
    122 	unsigned int	div_stat_peril1;
    123 	unsigned int	div_stat_peril2;
    124 	unsigned int	div_stat_peril3;
    125 	unsigned int	div_stat_peril4;
    126 	unsigned int	div_stat_peril5;
    127 	unsigned char	res32[0x18];
    128 	unsigned int	div2_stat;
    129 	unsigned char	res33[0x29c];
    130 	unsigned int	gate_ip_cam;
    131 	unsigned int	gate_ip_tv;
    132 	unsigned int	gate_ip_mfc;
    133 	unsigned int	gate_ip_g3d;
    134 	unsigned int	gate_ip_image;
    135 	unsigned int	gate_ip_lcd0;
    136 	unsigned int	gate_ip_lcd1;
    137 	unsigned char	res34[0x4];
    138 	unsigned int	gate_ip_fsys;
    139 	unsigned char	res35[0x8];
    140 	unsigned int	gate_ip_gps;
    141 	unsigned int	gate_ip_peril;
    142 	unsigned char	res36[0xc];
    143 	unsigned int	gate_ip_perir;
    144 	unsigned char	res37[0xc];
    145 	unsigned int	gate_block;
    146 	unsigned char	res38[0x8c];
    147 	unsigned int	clkout_cmu_top;
    148 	unsigned int	clkout_cmu_top_div_stat;
    149 	unsigned char	res39[0x37f8];
    150 	unsigned int	src_dmc;
    151 	unsigned char	res40[0xfc];
    152 	unsigned int	src_mask_dmc;
    153 	unsigned char	res41[0xfc];
    154 	unsigned int	mux_stat_dmc;
    155 	unsigned char	res42[0xfc];
    156 	unsigned int	div_dmc0;
    157 	unsigned int	div_dmc1;
    158 	unsigned char	res43[0xf8];
    159 	unsigned int	div_stat_dmc0;
    160 	unsigned int	div_stat_dmc1;
    161 	unsigned char	res44[0x2f8];
    162 	unsigned int	gate_ip_dmc;
    163 	unsigned char	res45[0xfc];
    164 	unsigned int	clkout_cmu_dmc;
    165 	unsigned int	clkout_cmu_dmc_div_stat;
    166 	unsigned char	res46[0x5f8];
    167 	unsigned int	dcgidx_map0;
    168 	unsigned int	dcgidx_map1;
    169 	unsigned int	dcgidx_map2;
    170 	unsigned char	res47[0x14];
    171 	unsigned int	dcgperf_map0;
    172 	unsigned int	dcgperf_map1;
    173 	unsigned char	res48[0x18];
    174 	unsigned int	dvcidx_map;
    175 	unsigned char	res49[0x1c];
    176 	unsigned int	freq_cpu;
    177 	unsigned int	freq_dpm;
    178 	unsigned char	res50[0x18];
    179 	unsigned int	dvsemclk_en;
    180 	unsigned int	maxperf;
    181 	unsigned char	res51[0x2f78];
    182 	unsigned int	apll_lock;
    183 	unsigned char	res52[0x4];
    184 	unsigned int	mpll_lock;
    185 	unsigned char	res53[0xf4];
    186 	unsigned int	apll_con0;
    187 	unsigned int	apll_con1;
    188 	unsigned int	mpll_con0;
    189 	unsigned int	mpll_con1;
    190 	unsigned char	res54[0xf0];
    191 	unsigned int	src_cpu;
    192 	unsigned char	res55[0x1fc];
    193 	unsigned int	mux_stat_cpu;
    194 	unsigned char	res56[0xfc];
    195 	unsigned int	div_cpu0;
    196 	unsigned int	div_cpu1;
    197 	unsigned char	res57[0xf8];
    198 	unsigned int	div_stat_cpu0;
    199 	unsigned int	div_stat_cpu1;
    200 	unsigned char	res58[0x3f8];
    201 	unsigned int	clkout_cmu_cpu;
    202 	unsigned int	clkout_cmu_cpu_div_stat;
    203 	unsigned char	res59[0x5f8];
    204 	unsigned int	armclk_stopctrl;
    205 	unsigned int	atclk_stopctrl;
    206 	unsigned char	res60[0x8];
    207 	unsigned int	parityfail_status;
    208 	unsigned int	parityfail_clear;
    209 	unsigned char	res61[0xe8];
    210 	unsigned int	apll_con0_l8;
    211 	unsigned int	apll_con0_l7;
    212 	unsigned int	apll_con0_l6;
    213 	unsigned int	apll_con0_l5;
    214 	unsigned int	apll_con0_l4;
    215 	unsigned int	apll_con0_l3;
    216 	unsigned int	apll_con0_l2;
    217 	unsigned int	apll_con0_l1;
    218 	unsigned int	iem_control;
    219 	unsigned char	res62[0xdc];
    220 	unsigned int	apll_con1_l8;
    221 	unsigned int	apll_con1_l7;
    222 	unsigned int	apll_con1_l6;
    223 	unsigned int	apll_con1_l5;
    224 	unsigned int	apll_con1_l4;
    225 	unsigned int	apll_con1_l3;
    226 	unsigned int	apll_con1_l2;
    227 	unsigned int	apll_con1_l1;
    228 	unsigned char	res63[0xe0];
    229 	unsigned int	div_iem_l8;
    230 	unsigned int	div_iem_l7;
    231 	unsigned int	div_iem_l6;
    232 	unsigned int	div_iem_l5;
    233 	unsigned int	div_iem_l4;
    234 	unsigned int	div_iem_l3;
    235 	unsigned int	div_iem_l2;
    236 	unsigned int	div_iem_l1;
    237 };
    238 
    239 struct exynos4x12_clock {
    240 	unsigned char	res1[0x4200];
    241 	unsigned int	src_leftbus;
    242 	unsigned char	res2[0x1fc];
    243 	unsigned int	mux_stat_leftbus;
    244 	unsigned char	res3[0xfc];
    245 	unsigned int	div_leftbus;
    246 	unsigned char	res4[0xfc];
    247 	unsigned int	div_stat_leftbus;
    248 	unsigned char	res5[0x1fc];
    249 	unsigned int	gate_ip_leftbus;
    250 	unsigned char	res6[0x12c];
    251 	unsigned int	gate_ip_image;
    252 	unsigned char	res7[0xcc];
    253 	unsigned int	clkout_leftbus;
    254 	unsigned int	clkout_leftbus_div_stat;
    255 	unsigned char	res8[0x37f8];
    256 	unsigned int	src_rightbus;
    257 	unsigned char	res9[0x1fc];
    258 	unsigned int	mux_stat_rightbus;
    259 	unsigned char	res10[0xfc];
    260 	unsigned int	div_rightbus;
    261 	unsigned char	res11[0xfc];
    262 	unsigned int	div_stat_rightbus;
    263 	unsigned char	res12[0x1fc];
    264 	unsigned int	gate_ip_rightbus;
    265 	unsigned char	res13[0x15c];
    266 	unsigned int	gate_ip_perir;
    267 	unsigned char	res14[0x9c];
    268 	unsigned int	clkout_rightbus;
    269 	unsigned int	clkout_rightbus_div_stat;
    270 	unsigned char	res15[0x3608];
    271 	unsigned int	epll_lock;
    272 	unsigned char	res16[0xc];
    273 	unsigned int	vpll_lock;
    274 	unsigned char	res17[0xec];
    275 	unsigned int	epll_con0;
    276 	unsigned int	epll_con1;
    277 	unsigned int	epll_con2;
    278 	unsigned char	res18[0x4];
    279 	unsigned int	vpll_con0;
    280 	unsigned int	vpll_con1;
    281 	unsigned int	vpll_con2;
    282 	unsigned char	res19[0xe4];
    283 	unsigned int	src_top0;
    284 	unsigned int	src_top1;
    285 	unsigned char	res20[0x8];
    286 	unsigned int	src_cam;
    287 	unsigned int	src_tv;
    288 	unsigned int	src_mfc;
    289 	unsigned int	src_g3d;
    290 	unsigned char	res21[0x4];
    291 	unsigned int	src_lcd;
    292 	unsigned int	src_isp;
    293 	unsigned int	src_maudio;
    294 	unsigned int	src_fsys;
    295 	unsigned char	res22[0xc];
    296 	unsigned int	src_peril0;
    297 	unsigned int	src_peril1;
    298 	unsigned int	src_cam1;
    299 	unsigned char	res23[0xb4];
    300 	unsigned int	src_mask_top;
    301 	unsigned char	res24[0xc];
    302 	unsigned int	src_mask_cam;
    303 	unsigned int	src_mask_tv;
    304 	unsigned char	res25[0xc];
    305 	unsigned int	src_mask_lcd;
    306 	unsigned int	src_mask_isp;
    307 	unsigned int	src_mask_maudio;
    308 	unsigned int	src_mask_fsys;
    309 	unsigned char	res26[0xc];
    310 	unsigned int	src_mask_peril0;
    311 	unsigned int	src_mask_peril1;
    312 	unsigned char	res27[0xb8];
    313 	unsigned int	mux_stat_top0;
    314 	unsigned int	mux_stat_top1;
    315 	unsigned char	res28[0x10];
    316 	unsigned int	mux_stat_mfc;
    317 	unsigned int	mux_stat_g3d;
    318 	unsigned char	res29[0x28];
    319 	unsigned int	mux_stat_cam1;
    320 	unsigned char	res30[0xb4];
    321 	unsigned int	div_top;
    322 	unsigned char	res31[0xc];
    323 	unsigned int	div_cam;
    324 	unsigned int	div_tv;
    325 	unsigned int	div_mfc;
    326 	unsigned int	div_g3d;
    327 	unsigned char	res32[0x4];
    328 	unsigned int	div_lcd;
    329 	unsigned int	div_isp;
    330 	unsigned int	div_maudio;
    331 	unsigned int	div_fsys0;
    332 	unsigned int	div_fsys1;
    333 	unsigned int	div_fsys2;
    334 	unsigned int	div_fsys3;
    335 	unsigned int	div_peril0;
    336 	unsigned int	div_peril1;
    337 	unsigned int	div_peril2;
    338 	unsigned int	div_peril3;
    339 	unsigned int	div_peril4;
    340 	unsigned int	div_peril5;
    341 	unsigned int	div_cam1;
    342 	unsigned char	res33[0x14];
    343 	unsigned int	div2_ratio;
    344 	unsigned char	res34[0x8c];
    345 	unsigned int	div_stat_top;
    346 	unsigned char	res35[0xc];
    347 	unsigned int	div_stat_cam;
    348 	unsigned int	div_stat_tv;
    349 	unsigned int	div_stat_mfc;
    350 	unsigned int	div_stat_g3d;
    351 	unsigned char	res36[0x4];
    352 	unsigned int	div_stat_lcd;
    353 	unsigned int	div_stat_isp;
    354 	unsigned int	div_stat_maudio;
    355 	unsigned int	div_stat_fsys0;
    356 	unsigned int	div_stat_fsys1;
    357 	unsigned int	div_stat_fsys2;
    358 	unsigned int	div_stat_fsys3;
    359 	unsigned int	div_stat_peril0;
    360 	unsigned int	div_stat_peril1;
    361 	unsigned int	div_stat_peril2;
    362 	unsigned int	div_stat_peril3;
    363 	unsigned int	div_stat_peril4;
    364 	unsigned int	div_stat_peril5;
    365 	unsigned int	div_stat_cam1;
    366 	unsigned char	res37[0x14];
    367 	unsigned int	div2_stat;
    368 	unsigned char	res38[0x29c];
    369 	unsigned int	gate_ip_cam;
    370 	unsigned int	gate_ip_tv;
    371 	unsigned int	gate_ip_mfc;
    372 	unsigned int	gate_ip_g3d;
    373 	unsigned char	res39[0x4];
    374 	unsigned int	gate_ip_lcd;
    375 	unsigned int	gate_ip_isp;
    376 	unsigned char	res40[0x4];
    377 	unsigned int	gate_ip_fsys;
    378 	unsigned char	res41[0x8];
    379 	unsigned int	gate_ip_gps;
    380 	unsigned int	gate_ip_peril;
    381 	unsigned char	res42[0xc];
    382 	unsigned char	res43[0x4];
    383 	unsigned char	res44[0xc];
    384 	unsigned int	gate_block;
    385 	unsigned char	res45[0x8c];
    386 	unsigned int	clkout_cmu_top;
    387 	unsigned int	clkout_cmu_top_div_stat;
    388 	unsigned char	res46[0x3600];
    389 	unsigned int	mpll_lock;
    390 	unsigned char	res47[0xfc];
    391 	unsigned int	mpll_con0;
    392 	unsigned int	mpll_con1;
    393 	unsigned char	res48[0xf0];
    394 	unsigned int	src_dmc;
    395 	unsigned char	res49[0xfc];
    396 	unsigned int	src_mask_dmc;
    397 	unsigned char	res50[0xfc];
    398 	unsigned int	mux_stat_dmc;
    399 	unsigned char	res51[0xfc];
    400 	unsigned int	div_dmc0;
    401 	unsigned int	div_dmc1;
    402 	unsigned char	res52[0xf8];
    403 	unsigned int	div_stat_dmc0;
    404 	unsigned int	div_stat_dmc1;
    405 	unsigned char	res53[0xf8];
    406 	unsigned int	gate_bus_dmc0;
    407 	unsigned int	gate_bus_dmc1;
    408 	unsigned char	res54[0x1f8];
    409 	unsigned int	gate_ip_dmc0;
    410 	unsigned int	gate_ip_dmc1;
    411 	unsigned char	res55[0xf8];
    412 	unsigned int	clkout_cmu_dmc;
    413 	unsigned int	clkout_cmu_dmc_div_stat;
    414 	unsigned char	res56[0x5f8];
    415 	unsigned int	dcgidx_map0;
    416 	unsigned int	dcgidx_map1;
    417 	unsigned int	dcgidx_map2;
    418 	unsigned char	res57[0x14];
    419 	unsigned int	dcgperf_map0;
    420 	unsigned int	dcgperf_map1;
    421 	unsigned char	res58[0x18];
    422 	unsigned int	dvcidx_map;
    423 	unsigned char	res59[0x1c];
    424 	unsigned int	freq_cpu;
    425 	unsigned int	freq_dpm;
    426 	unsigned char	res60[0x18];
    427 	unsigned int	dvsemclk_en;
    428 	unsigned int	maxperf;
    429 	unsigned char	res61[0x8];
    430 	unsigned int	dmc_freq_ctrl;
    431 	unsigned int	dmc_pause_ctrl;
    432 	unsigned int	dddrphy_lock_ctrl;
    433 	unsigned int	c2c_state;
    434 	unsigned char	res62[0x2f60];
    435 	unsigned int	apll_lock;
    436 	unsigned char	res63[0x8];
    437 	unsigned char	res64[0xf4];
    438 	unsigned int	apll_con0;
    439 	unsigned int	apll_con1;
    440 	unsigned char	res65[0xf8];
    441 	unsigned int	src_cpu;
    442 	unsigned char	res66[0x1fc];
    443 	unsigned int	mux_stat_cpu;
    444 	unsigned char	res67[0xfc];
    445 	unsigned int	div_cpu0;
    446 	unsigned int	div_cpu1;
    447 	unsigned char	res68[0xf8];
    448 	unsigned int	div_stat_cpu0;
    449 	unsigned int	div_stat_cpu1;
    450 	unsigned char	res69[0x2f8];
    451 	unsigned int	clk_gate_ip_cpu;
    452 	unsigned char	res70[0xfc];
    453 	unsigned int	clkout_cmu_cpu;
    454 	unsigned int	clkout_cmu_cpu_div_stat;
    455 	unsigned char	res71[0x5f8];
    456 	unsigned int	armclk_stopctrl;
    457 	unsigned int	atclk_stopctrl;
    458 	unsigned char	res72[0x10];
    459 	unsigned char	res73[0x8];
    460 	unsigned int	pwr_ctrl;
    461 	unsigned int	pwr_ctrl2;
    462 	unsigned char	res74[0xd8];
    463 	unsigned int	apll_con0_l8;
    464 	unsigned int	apll_con0_l7;
    465 	unsigned int	apll_con0_l6;
    466 	unsigned int	apll_con0_l5;
    467 	unsigned int	apll_con0_l4;
    468 	unsigned int	apll_con0_l3;
    469 	unsigned int	apll_con0_l2;
    470 	unsigned int	apll_con0_l1;
    471 	unsigned int	iem_control;
    472 	unsigned char	res75[0xdc];
    473 	unsigned int	apll_con1_l8;
    474 	unsigned int	apll_con1_l7;
    475 	unsigned int	apll_con1_l6;
    476 	unsigned int	apll_con1_l5;
    477 	unsigned int	apll_con1_l4;
    478 	unsigned int	apll_con1_l3;
    479 	unsigned int	apll_con1_l2;
    480 	unsigned int	apll_con1_l1;
    481 	unsigned char	res76[0xe0];
    482 	unsigned int	div_iem_l8;
    483 	unsigned int	div_iem_l7;
    484 	unsigned int	div_iem_l6;
    485 	unsigned int	div_iem_l5;
    486 	unsigned int	div_iem_l4;
    487 	unsigned int	div_iem_l3;
    488 	unsigned int	div_iem_l2;
    489 	unsigned int	div_iem_l1;
    490 	unsigned char	res77[0xe0];
    491 	unsigned int	l2_status;
    492 	unsigned char	res78[0xc];
    493 	unsigned int	cpu_status;
    494 	unsigned char	res79[0xc];
    495 	unsigned int	ptm_status;
    496 	unsigned char	res80[0x2edc];
    497 	unsigned int	div_isp0;
    498 	unsigned int	div_isp1;
    499 	unsigned char	res81[0xf8];
    500 	unsigned int	div_stat_isp0;
    501 	unsigned int	div_stat_isp1;
    502 	unsigned char	res82[0x3f8];
    503 	unsigned int	gate_ip_isp0;
    504 	unsigned int	gate_ip_isp1;
    505 	unsigned char	res83[0x1f8];
    506 	unsigned int	clkout_cmu_isp;
    507 	unsigned int	clkout_cmu_ispd_div_stat;
    508 	unsigned char	res84[0xf8];
    509 	unsigned int	cmu_isp_spar0;
    510 	unsigned int	cmu_isp_spar1;
    511 	unsigned int	cmu_isp_spar2;
    512 	unsigned int	cmu_isp_spar3;
    513 };
    514 
    515 struct exynos5_clock {
    516 	unsigned int	apll_lock;
    517 	unsigned char	res1[0xfc];
    518 	unsigned int	apll_con0;
    519 	unsigned int	apll_con1;
    520 	unsigned char	res2[0xf8];
    521 	unsigned int	src_cpu;
    522 	unsigned char	res3[0x1fc];
    523 	unsigned int	mux_stat_cpu;
    524 	unsigned char	res4[0xfc];
    525 	unsigned int	div_cpu0;
    526 	unsigned int	div_cpu1;
    527 	unsigned char	res5[0xf8];
    528 	unsigned int	div_stat_cpu0;
    529 	unsigned int	div_stat_cpu1;
    530 	unsigned char	res6[0x1f8];
    531 	unsigned int	gate_sclk_cpu;
    532 	unsigned char	res7[0x1fc];
    533 	unsigned int	clkout_cmu_cpu;
    534 	unsigned int	clkout_cmu_cpu_div_stat;
    535 	unsigned char	res8[0x5f8];
    536 	unsigned int	armclk_stopctrl;
    537 	unsigned char	res9[0x0c];
    538 	unsigned int	parityfail_status;
    539 	unsigned int	parityfail_clear;
    540 	unsigned char	res10[0x8];
    541 	unsigned int	pwr_ctrl;
    542 	unsigned int	pwr_ctr2;
    543 	unsigned char	res11[0xd8];
    544 	unsigned int	apll_con0_l8;
    545 	unsigned int	apll_con0_l7;
    546 	unsigned int	apll_con0_l6;
    547 	unsigned int	apll_con0_l5;
    548 	unsigned int	apll_con0_l4;
    549 	unsigned int	apll_con0_l3;
    550 	unsigned int	apll_con0_l2;
    551 	unsigned int	apll_con0_l1;
    552 	unsigned int	iem_control;
    553 	unsigned char	res12[0xdc];
    554 	unsigned int	apll_con1_l8;
    555 	unsigned int	apll_con1_l7;
    556 	unsigned int	apll_con1_l6;
    557 	unsigned int	apll_con1_l5;
    558 	unsigned int	apll_con1_l4;
    559 	unsigned int	apll_con1_l3;
    560 	unsigned int	apll_con1_l2;
    561 	unsigned int	apll_con1_l1;
    562 	unsigned char	res13[0xe0];
    563 	unsigned int	div_iem_l8;
    564 	unsigned int	div_iem_l7;
    565 	unsigned int	div_iem_l6;
    566 	unsigned int	div_iem_l5;
    567 	unsigned int	div_iem_l4;
    568 	unsigned int	div_iem_l3;
    569 	unsigned int	div_iem_l2;
    570 	unsigned int	div_iem_l1;
    571 	unsigned char	res14[0x2ce0];
    572 	unsigned int	mpll_lock;
    573 	unsigned char	res15[0xfc];
    574 	unsigned int	mpll_con0;
    575 	unsigned int	mpll_con1;
    576 	unsigned char	res16[0xf8];
    577 	unsigned int	src_core0;
    578 	unsigned int	src_core1;
    579 	unsigned char	res17[0xf8];
    580 	unsigned int	src_mask_core;
    581 	unsigned char	res18[0x100];
    582 	unsigned int	mux_stat_core1;
    583 	unsigned char	res19[0xf8];
    584 	unsigned int	div_core0;
    585 	unsigned int	div_core1;
    586 	unsigned int	div_sysrgt;
    587 	unsigned char	res20[0xf4];
    588 	unsigned int	div_stat_core0;
    589 	unsigned int	div_stat_core1;
    590 	unsigned int	div_stat_sysrgt;
    591 	unsigned char	res21[0x2f4];
    592 	unsigned int	gate_ip_core;
    593 	unsigned int	gate_ip_sysrgt;
    594 	unsigned char	res22[0x8];
    595 	unsigned int	c2c_monitor;
    596 	unsigned char	res23[0xec];
    597 	unsigned int	clkout_cmu_core;
    598 	unsigned int	clkout_cmu_core_div_stat;
    599 	unsigned char	res24[0x5f8];
    600 	unsigned int	dcgidx_map0;
    601 	unsigned int	dcgidx_map1;
    602 	unsigned int	dcgidx_map2;
    603 	unsigned char	res25[0x14];
    604 	unsigned int	dcgperf_map0;
    605 	unsigned int	dcgperf_map1;
    606 	unsigned char	res26[0x18];
    607 	unsigned int	dvcidx_map;
    608 	unsigned char	res27[0x1c];
    609 	unsigned int	freq_cpu;
    610 	unsigned int	freq_dpm;
    611 	unsigned char	res28[0x18];
    612 	unsigned int	dvsemclk_en;
    613 	unsigned int	maxperf;
    614 	unsigned char	res29[0xf78];
    615 	unsigned int	c2c_config;
    616 	unsigned char	res30[0x24fc];
    617 	unsigned int	div_acp;
    618 	unsigned char	res31[0xfc];
    619 	unsigned int	div_stat_acp;
    620 	unsigned char	res32[0x1fc];
    621 	unsigned int	gate_ip_acp;
    622 	unsigned char	res33[0xfc];
    623 	unsigned int	div_syslft;
    624 	unsigned char	res34[0xc];
    625 	unsigned int	div_stat_syslft;
    626 	unsigned char	res35[0x1c];
    627 	unsigned int	gate_ip_syslft;
    628 	unsigned char	res36[0xcc];
    629 	unsigned int	clkout_cmu_acp;
    630 	unsigned int	clkout_cmu_acp_div_stat;
    631 	unsigned char	res37[0x8];
    632 	unsigned int	ufmc_config;
    633 	unsigned char	res38[0x38ec];
    634 	unsigned int	div_isp0;
    635 	unsigned int	div_isp1;
    636 	unsigned int	div_isp2;
    637 	unsigned char	res39[0xf4];
    638 	unsigned int	div_stat_isp0;
    639 	unsigned int	div_stat_isp1;
    640 	unsigned int	div_stat_isp2;
    641 	unsigned char	res40[0x3f4];
    642 	unsigned int	gate_ip_isp0;
    643 	unsigned int	gate_ip_isp1;
    644 	unsigned char	res41[0xf8];
    645 	unsigned int	gate_sclk_isp;
    646 	unsigned char	res42[0xc];
    647 	unsigned int	mcuisp_pwr_ctrl;
    648 	unsigned char	res43[0xec];
    649 	unsigned int	clkout_cmu_isp;
    650 	unsigned int	clkout_cmu_isp_div_stat;
    651 	unsigned char	res44[0x3618];
    652 	unsigned int	cpll_lock;
    653 	unsigned char	res45[0xc];
    654 	unsigned int	epll_lock;
    655 	unsigned char	res46[0xc];
    656 	unsigned int	vpll_lock;
    657 	unsigned char	res47[0xc];
    658 	unsigned int	gpll_lock;
    659 	unsigned char	res48[0xcc];
    660 	unsigned int	cpll_con0;
    661 	unsigned int	cpll_con1;
    662 	unsigned char	res49[0x8];
    663 	unsigned int	epll_con0;
    664 	unsigned int	epll_con1;
    665 	unsigned int	epll_con2;
    666 	unsigned char	res50[0x4];
    667 	unsigned int	vpll_con0;
    668 	unsigned int	vpll_con1;
    669 	unsigned int	vpll_con2;
    670 	unsigned char	res51[0x4];
    671 	unsigned int	gpll_con0;
    672 	unsigned int	gpll_con1;
    673 	unsigned char	res52[0xb8];
    674 	unsigned int	src_top0;
    675 	unsigned int	src_top1;
    676 	unsigned int	src_top2;
    677 	unsigned int	src_top3;
    678 	unsigned int	src_gscl;
    679 	unsigned char	res53[0x8];
    680 	unsigned int	src_disp1_0;
    681 	unsigned char	res54[0x10];
    682 	unsigned int	src_mau;
    683 	unsigned int	src_fsys;
    684 	unsigned int	src_gen;
    685 	unsigned char	res55[0x4];
    686 	unsigned int	src_peric0;
    687 	unsigned int	src_peric1;
    688 	unsigned char	res56[0x18];
    689 	unsigned int	sclk_src_isp;
    690 	unsigned char	res57[0x9c];
    691 	unsigned int	src_mask_top;
    692 	unsigned char	res58[0xc];
    693 	unsigned int	src_mask_gscl;
    694 	unsigned char	res59[0x8];
    695 	unsigned int	src_mask_disp1_0;
    696 	unsigned char	res60[0x4];
    697 	unsigned int	src_mask_mau;
    698 	unsigned char	res61[0x8];
    699 	unsigned int	src_mask_fsys;
    700 	unsigned int	src_mask_gen;
    701 	unsigned char	res62[0x8];
    702 	unsigned int	src_mask_peric0;
    703 	unsigned int	src_mask_peric1;
    704 	unsigned char	res63[0x18];
    705 	unsigned int	src_mask_isp;
    706 	unsigned char	res67[0x9c];
    707 	unsigned int	mux_stat_top0;
    708 	unsigned int	mux_stat_top1;
    709 	unsigned int	mux_stat_top2;
    710 	unsigned int	mux_stat_top3;
    711 	unsigned char	res68[0xf0];
    712 	unsigned int	div_top0;
    713 	unsigned int	div_top1;
    714 	unsigned char	res69[0x8];
    715 	unsigned int	div_gscl;
    716 	unsigned char	res70[0x8];
    717 	unsigned int	div_disp1_0;
    718 	unsigned char	res71[0xc];
    719 	unsigned int	div_gen;
    720 	unsigned char	res72[0x4];
    721 	unsigned int	div_mau;
    722 	unsigned int	div_fsys0;
    723 	unsigned int	div_fsys1;
    724 	unsigned int	div_fsys2;
    725 	unsigned char	res73[0x4];
    726 	unsigned int	div_peric0;
    727 	unsigned int	div_peric1;
    728 	unsigned int	div_peric2;
    729 	unsigned int	div_peric3;
    730 	unsigned int	div_peric4;
    731 	unsigned int	div_peric5;
    732 	unsigned char	res74[0x10];
    733 	unsigned int	sclk_div_isp;
    734 	unsigned char	res75[0xc];
    735 	unsigned int	div2_ratio0;
    736 	unsigned int	div2_ratio1;
    737 	unsigned char	res76[0x8];
    738 	unsigned int	div4_ratio;
    739 	unsigned char	res77[0x6c];
    740 	unsigned int	div_stat_top0;
    741 	unsigned int	div_stat_top1;
    742 	unsigned char	res78[0x8];
    743 	unsigned int	div_stat_gscl;
    744 	unsigned char	res79[0x8];
    745 	unsigned int	div_stat_disp1_0;
    746 	unsigned char	res80[0xc];
    747 	unsigned int	div_stat_gen;
    748 	unsigned char	res81[0x4];
    749 	unsigned int	div_stat_mau;
    750 	unsigned int	div_stat_fsys0;
    751 	unsigned int	div_stat_fsys1;
    752 	unsigned int	div_stat_fsys2;
    753 	unsigned char	res82[0x4];
    754 	unsigned int	div_stat_peric0;
    755 	unsigned int	div_stat_peric1;
    756 	unsigned int	div_stat_peric2;
    757 	unsigned int	div_stat_peric3;
    758 	unsigned int	div_stat_peric4;
    759 	unsigned int	div_stat_peric5;
    760 	unsigned char	res83[0x10];
    761 	unsigned int	sclk_div_stat_isp;
    762 	unsigned char	res84[0xc];
    763 	unsigned int	div2_stat0;
    764 	unsigned int	div2_stat1;
    765 	unsigned char	res85[0x8];
    766 	unsigned int	div4_stat;
    767 	unsigned char	res86[0x184];
    768 	unsigned int	gate_top_sclk_disp1;
    769 	unsigned int	gate_top_sclk_gen;
    770 	unsigned char	res87[0xc];
    771 	unsigned int	gate_top_sclk_mau;
    772 	unsigned int	gate_top_sclk_fsys;
    773 	unsigned char	res88[0xc];
    774 	unsigned int	gate_top_sclk_peric;
    775 	unsigned char	res89[0x1c];
    776 	unsigned int	gate_top_sclk_isp;
    777 	unsigned char	res90[0xac];
    778 	unsigned int	gate_ip_gscl;
    779 	unsigned char	res91[0x4];
    780 	unsigned int	gate_ip_disp1;
    781 	unsigned int	gate_ip_mfc;
    782 	unsigned int	gate_ip_g3d;
    783 	unsigned int	gate_ip_gen;
    784 	unsigned char	res92[0xc];
    785 	unsigned int	gate_ip_fsys;
    786 	unsigned char	res93[0x8];
    787 	unsigned int	gate_ip_peric;
    788 	unsigned char	res94[0xc];
    789 	unsigned int	gate_ip_peris;
    790 	unsigned char	res95[0x1c];
    791 	unsigned int	gate_block;
    792 	unsigned char	res96[0x1c];
    793 	unsigned int	mcuiop_pwr_ctrl;
    794 	unsigned char	res97[0x5c];
    795 	unsigned int	clkout_cmu_top;
    796 	unsigned int	clkout_cmu_top_div_stat;
    797 	unsigned char	res98[0x37f8];
    798 	unsigned int	src_lex;
    799 	unsigned char	res99[0x1fc];
    800 	unsigned int	mux_stat_lex;
    801 	unsigned char	res100[0xfc];
    802 	unsigned int	div_lex;
    803 	unsigned char	res101[0xfc];
    804 	unsigned int	div_stat_lex;
    805 	unsigned char	res102[0x1fc];
    806 	unsigned int	gate_ip_lex;
    807 	unsigned char	res103[0x1fc];
    808 	unsigned int	clkout_cmu_lex;
    809 	unsigned int	clkout_cmu_lex_div_stat;
    810 	unsigned char	res104[0x3af8];
    811 	unsigned int	div_r0x;
    812 	unsigned char	res105[0xfc];
    813 	unsigned int	div_stat_r0x;
    814 	unsigned char	res106[0x1fc];
    815 	unsigned int	gate_ip_r0x;
    816 	unsigned char	res107[0x1fc];
    817 	unsigned int	clkout_cmu_r0x;
    818 	unsigned int	clkout_cmu_r0x_div_stat;
    819 	unsigned char	res108[0x3af8];
    820 	unsigned int	div_r1x;
    821 	unsigned char	res109[0xfc];
    822 	unsigned int	div_stat_r1x;
    823 	unsigned char	res110[0x1fc];
    824 	unsigned int	gate_ip_r1x;
    825 	unsigned char	res111[0x1fc];
    826 	unsigned int	clkout_cmu_r1x;
    827 	unsigned int	clkout_cmu_r1x_div_stat;
    828 	unsigned char	res112[0x3608];
    829 	unsigned int	bpll_lock;
    830 	unsigned char	res113[0xfc];
    831 	unsigned int	bpll_con0;
    832 	unsigned int	bpll_con1;
    833 	unsigned char	res114[0xe8];
    834 	unsigned int	src_cdrex;
    835 	unsigned char	res115[0x1fc];
    836 	unsigned int	mux_stat_cdrex;
    837 	unsigned char	res116[0xfc];
    838 	unsigned int	div_cdrex;
    839 	unsigned char	res117[0xfc];
    840 	unsigned int	div_stat_cdrex;
    841 	unsigned char	res118[0x2fc];
    842 	unsigned int	gate_ip_cdrex;
    843 	unsigned char	res119[0x10];
    844 	unsigned int	dmc_freq_ctrl;
    845 	unsigned char	res120[0x4];
    846 	unsigned int	drex2_pause;
    847 	unsigned char	res121[0xe0];
    848 	unsigned int	clkout_cmu_cdrex;
    849 	unsigned int	clkout_cmu_cdrex_div_stat;
    850 	unsigned char	res122[0x8];
    851 	unsigned int	lpddr3phy_ctrl;
    852 	unsigned int	lpddr3phy_con0;
    853 	unsigned int	lpddr3phy_con1;
    854 	unsigned int	lpddr3phy_con2;
    855 	unsigned int	lpddr3phy_con3;
    856 	unsigned int	pll_div2_sel;
    857 	unsigned char	res123[0xf5d8];
    858 };
    859 
    860 struct exynos5420_clock {
    861 	unsigned int	apll_lock;			/* 0x10010000 */
    862 	unsigned char	res1[0xfc];
    863 	unsigned int	apll_con0;
    864 	unsigned int	apll_con1;
    865 	unsigned char	res2[0xf8];
    866 	unsigned int	src_cpu;
    867 	unsigned char	res3[0x1fc];
    868 	unsigned int	mux_stat_cpu;
    869 	unsigned char	res4[0xfc];
    870 	unsigned int	div_cpu0;		/* 0x10010500 */
    871 	unsigned int	div_cpu1;
    872 	unsigned char	res5[0xf8];
    873 	unsigned int	div_stat_cpu0;
    874 	unsigned int	div_stat_cpu1;
    875 	unsigned char	res6[0xf8];
    876 	unsigned int	gate_bus_cpu;
    877 	unsigned char	res7[0xfc];
    878 	unsigned int	gate_sclk_cpu;
    879 	unsigned char	res8[0x1fc];
    880 	unsigned int	clkout_cmu_cpu;		/* 0x10010a00 */
    881 	unsigned int	clkout_cmu_cpu_div_stat;
    882 	unsigned char	res9[0x5f8];
    883 	unsigned int	armclk_stopctrl;
    884 	unsigned char	res10[0x4];
    885 	unsigned int	arm_ema_ctrl;
    886 	unsigned int	arm_ema_status;
    887 	unsigned char	res11[0x10];
    888 	unsigned int	pwr_ctrl;
    889 	unsigned int	pwr_ctrl2;
    890 	unsigned char	res12[0xd8];
    891 	unsigned int	apll_con0_l8;		/* 0x1001100 */
    892 	unsigned int	apll_con0_l7;
    893 	unsigned int	apll_con0_l6;
    894 	unsigned int	apll_con0_l5;
    895 	unsigned int	apll_con0_l4;
    896 	unsigned int	apll_con0_l3;
    897 	unsigned int	apll_con0_l2;
    898 	unsigned int	apll_con0_l1;
    899 	unsigned int	iem_control;
    900 	unsigned char	res13[0xdc];
    901 	unsigned int	apll_con1_l8;		/* 0x10011200 */
    902 	unsigned int	apll_con1_l7;
    903 	unsigned int	apll_con1_l6;
    904 	unsigned int	apll_con1_l5;
    905 	unsigned int	apll_con1_l4;
    906 	unsigned int	apll_con1_l3;
    907 	unsigned int	apll_con1_l2;
    908 	unsigned int	apll_con1_l1;
    909 	unsigned char	res14[0xe0];
    910 	unsigned int	clkdiv_iem_l8;
    911 	unsigned int	clkdiv_iem_l7;		/* 0x10011304 */
    912 	unsigned int	clkdiv_iem_l6;
    913 	unsigned int	clkdiv_iem_l5;
    914 	unsigned int	clkdiv_iem_l4;
    915 	unsigned int	clkdiv_iem_l3;
    916 	unsigned int	clkdiv_iem_l2;
    917 	unsigned int	clkdiv_iem_l1;
    918 	unsigned char	res15[0xe0];
    919 	unsigned int	l2_status;
    920 	unsigned char	res16[0x0c];
    921 	unsigned int	cpu_status;		/* 0x10011410 */
    922 	unsigned char	res17[0x0c];
    923 	unsigned int	ptm_status;
    924 	unsigned char	res18[0xbdc];
    925 	unsigned int	cmu_cpu_spare0;
    926 	unsigned int	cmu_cpu_spare1;
    927 	unsigned int	cmu_cpu_spare2;
    928 	unsigned int	cmu_cpu_spare3;
    929 	unsigned int	cmu_cpu_spare4;
    930 	unsigned char	res19[0x1fdc];
    931 	unsigned int	cmu_cpu_version;
    932 	unsigned char	res20[0x20c];
    933 	unsigned int	src_cperi0;		/* 0x10014200 */
    934 	unsigned int	src_cperi1;
    935 	unsigned char	res21[0xf8];
    936 	unsigned int	src_mask_cperi;
    937 	unsigned char	res22[0x100];
    938 	unsigned int	mux_stat_cperi1;
    939 	unsigned char	res23[0xfc];
    940 	unsigned int	div_cperi1;
    941 	unsigned char	res24[0xfc];
    942 	unsigned int	div_stat_cperi1;
    943 	unsigned char	res25[0xf8];
    944 	unsigned int	gate_bus_cperi0;	/* 0x10014700 */
    945 	unsigned int	gate_bus_cperi1;
    946 	unsigned char	res26[0xf8];
    947 	unsigned int	gate_sclk_cperi;
    948 	unsigned char	res27[0xfc];
    949 	unsigned int	gate_ip_cperi;
    950 	unsigned char	res28[0xfc];
    951 	unsigned int	clkout_cmu_cperi;
    952 	unsigned int	clkout_cmu_cperi_div_stat;
    953 	unsigned char	res29[0x5f8];
    954 	unsigned int	dcgidx_map0;		/* 0x10015000 */
    955 	unsigned int	dcgidx_map1;
    956 	unsigned int	dcgidx_map2;
    957 	unsigned char	res30[0x14];
    958 	unsigned int	dcgperf_map0;
    959 	unsigned int	dcgperf_map1;
    960 	unsigned char	res31[0x18];
    961 	unsigned int	dvcidx_map;
    962 	unsigned char	res32[0x1c];
    963 	unsigned int	freq_cpu;
    964 	unsigned int	freq_dpm;
    965 	unsigned char	res33[0x18];
    966 	unsigned int	dvsemclk_en;		/* 0x10015080 */
    967 	unsigned int	maxperf;
    968 	unsigned char	res34[0x2e78];
    969 	unsigned int	cmu_cperi_spare0;
    970 	unsigned int	cmu_cperi_spare1;
    971 	unsigned int	cmu_cperi_spare2;
    972 	unsigned int	cmu_cperi_spare3;
    973 	unsigned int	cmu_cperi_spare4;
    974 	unsigned int	cmu_cperi_spare5;
    975 	unsigned int	cmu_cperi_spare6;
    976 	unsigned int	cmu_cperi_spare7;
    977 	unsigned int	cmu_cperi_spare8;
    978 	unsigned char	res35[0xcc];
    979 	unsigned int	cmu_cperi_version;		/* 0x10017ff0 */
    980 	unsigned char	res36[0x50c];
    981 	unsigned int	div_g2d;
    982 	unsigned char	res37[0xfc];
    983 	unsigned int	div_stat_g2d;
    984 	unsigned char	res38[0xfc];
    985 	unsigned int	gate_bus_g2d;
    986 	unsigned char	res39[0xfc];
    987 	unsigned int	gate_ip_g2d;
    988 	unsigned char	res40[0x1fc];
    989 	unsigned int	clkout_cmu_g2d;
    990 	unsigned int	clkout_cmu_g2d_div_stat;	/* 0x10018a04 */
    991 	unsigned char	res41[0xf8];
    992 	unsigned int	cmu_g2d_spare0;
    993 	unsigned int	cmu_g2d_spare1;
    994 	unsigned int	cmu_g2d_spare2;
    995 	unsigned int	cmu_g2d_spare3;
    996 	unsigned int	cmu_g2d_spare4;
    997 	unsigned char	res42[0x34dc];
    998 	unsigned int	cmu_g2d_version;
    999 	unsigned char	res43[0x30c];
   1000 	unsigned int	div_cmu_isp0;
   1001 	unsigned int	div_cmu_isp1;
   1002 	unsigned int	div_isp2;		/* 0x1001c308 */
   1003 	unsigned char	res44[0xf4];
   1004 	unsigned int	div_stat_cmu_isp0;
   1005 	unsigned int	div_stat_cmu_isp1;
   1006 	unsigned int	div_stat_isp2;
   1007 	unsigned char	res45[0x2f4];
   1008 	unsigned int	gate_bus_isp0;
   1009 	unsigned int	gate_bus_isp1;
   1010 	unsigned int	gate_bus_isp2;
   1011 	unsigned int	gate_bus_isp3;
   1012 	unsigned char	res46[0xf0];
   1013 	unsigned int	gate_ip_isp0;
   1014 	unsigned int	gate_ip_isp1;
   1015 	unsigned char	res47[0xf8];
   1016 	unsigned int	gate_sclk_isp;
   1017 	unsigned char	res48[0x0c];
   1018 	unsigned int	mcuisp_pwr_ctrl;		/* 0x1001c910 */
   1019 	unsigned char	res49[0x0ec];
   1020 	unsigned int	clkout_cmu_isp;
   1021 	unsigned int	clkout_cmu_isp_div_stat;
   1022 	unsigned char	res50[0xf8];
   1023 	unsigned int	cmu_isp_spare0;
   1024 	unsigned int	cmu_isp_spare1;
   1025 	unsigned int	cmu_isp_spare2;
   1026 	unsigned int	cmu_isp_spare3;
   1027 	unsigned char	res51[0x34e0];
   1028 	unsigned int	cmu_isp_version;
   1029 	unsigned char	res52[0x2c];
   1030 	unsigned int	cpll_lock;			/* 10020020 */
   1031 	unsigned char	res53[0xc];
   1032 	unsigned int	dpll_lock;
   1033 	unsigned char	res54[0xc];
   1034 	unsigned int	epll_lock;
   1035 	unsigned char	res55[0xc];
   1036 	unsigned int	rpll_lock;
   1037 	unsigned char	res56[0xc];
   1038 	unsigned int	ipll_lock;
   1039 	unsigned char	res57[0xc];
   1040 	unsigned int	spll_lock;
   1041 	unsigned char	res58[0xc];
   1042 	unsigned int	vpll_lock;
   1043 	unsigned char	res59[0xc];
   1044 	unsigned int	mpll_lock;
   1045 	unsigned char	res60[0x8c];
   1046 	unsigned int	cpll_con0;			/* 10020120 */
   1047 	unsigned int	cpll_con1;
   1048 	unsigned int	dpll_con0;
   1049 	unsigned int	dpll_con1;
   1050 	unsigned int	epll_con0;
   1051 	unsigned int	epll_con1;
   1052 	unsigned int	epll_con2;
   1053 	unsigned char	res601[0x4];
   1054 	unsigned int	rpll_con0;
   1055 	unsigned int	rpll_con1;
   1056 	unsigned int	rpll_con2;
   1057 	unsigned char	res602[0x4];
   1058 	unsigned int	ipll_con0;
   1059 	unsigned int	ipll_con1;
   1060 	unsigned char	res61[0x8];
   1061 	unsigned int	spll_con0;
   1062 	unsigned int	spll_con1;
   1063 	unsigned char	res62[0x8];
   1064 	unsigned int	vpll_con0;
   1065 	unsigned int	vpll_con1;
   1066 	unsigned char	res63[0x8];
   1067 	unsigned int	mpll_con0;
   1068 	unsigned int	mpll_con1;
   1069 	unsigned char	res64[0x78];
   1070 	unsigned int	src_top0;		/* 0x10020200 */
   1071 	unsigned int	src_top1;
   1072 	unsigned int	src_top2;
   1073 	unsigned int	src_top3;
   1074 	unsigned int	src_top4;
   1075 	unsigned int	src_top5;
   1076 	unsigned int	src_top6;
   1077 	unsigned int	src_top7;
   1078 	unsigned char	res65[0xc];
   1079 	unsigned int	src_disp10;		/* 0x1002022c */
   1080 	unsigned char	res66[0x10];
   1081 	unsigned int	src_mau;
   1082 	unsigned int	src_fsys;
   1083 	unsigned char	res67[0x8];
   1084 	unsigned int	src_peric0;
   1085 	unsigned int	src_peric1;
   1086 	unsigned char	res68[0x18];
   1087 	unsigned int	src_isp;
   1088 	unsigned char	res69[0x0c];
   1089 	unsigned int	src_top10;
   1090 	unsigned int	src_top11;
   1091 	unsigned int	src_top12;
   1092 	unsigned char	res70[0x74];
   1093 	unsigned int	src_mask_top0;
   1094 	unsigned int	src_mask_top1;
   1095 	unsigned int	src_mask_top2;
   1096 	unsigned char	res71[0x10];
   1097 	unsigned int	src_mask_top7;
   1098 	unsigned char	res72[0xc];
   1099 	unsigned int	src_mask_disp10;	/* 0x1002032c */
   1100 	unsigned char	res73[0x4];
   1101 	unsigned int	src_mask_mau;
   1102 	unsigned char	res74[0x8];
   1103 	unsigned int	src_mask_fsys;
   1104 	unsigned char	res75[0xc];
   1105 	unsigned int	src_mask_peric0;
   1106 	unsigned int	src_mask_peric1;
   1107 	unsigned char	res76[0x18];
   1108 	unsigned int	src_mask_isp;
   1109 	unsigned char	res77[0x8c];
   1110 	unsigned int	mux_stat_top0;		/* 0x10020400 */
   1111 	unsigned int	mux_stat_top1;
   1112 	unsigned int	mux_stat_top2;
   1113 	unsigned int	mux_stat_top3;
   1114 	unsigned int	mux_stat_top4;
   1115 	unsigned int	mux_stat_top5;
   1116 	unsigned int	mux_stat_top6;
   1117 	unsigned int	mux_stat_top7;
   1118 	unsigned char	res78[0x60];
   1119 	unsigned int	mux_stat_top10;
   1120 	unsigned int	mux_stat_top11;
   1121 	unsigned int	mux_stat_top12;
   1122 	unsigned char	res79[0x74];
   1123 	unsigned int	div_top0;		/* 0x10020500 */
   1124 	unsigned int	div_top1;
   1125 	unsigned int	div_top2;
   1126 	unsigned char	res80[0x20];
   1127 	unsigned int	div_disp10;
   1128 	unsigned char	res81[0x14];
   1129 	unsigned int	div_mau;
   1130 	unsigned int	div_fsys0;
   1131 	unsigned int	div_fsys1;
   1132 	unsigned int	div_fsys2;
   1133 	unsigned char	res82[0x4];
   1134 	unsigned int	div_peric0;
   1135 	unsigned int	div_peric1;
   1136 	unsigned int	div_peric2;
   1137 	unsigned int	div_peric3;
   1138 	unsigned int	div_peric4;		/* 0x10020568 */
   1139 	unsigned char	res83[0x14];
   1140 	unsigned int	div_isp0;
   1141 	unsigned int	div_isp1;
   1142 	unsigned char	res84[0x8];
   1143 	unsigned int	clkdiv2_ratio;
   1144 	unsigned char	res850[0xc];
   1145 	unsigned int	clkdiv4_ratio;
   1146 	unsigned char	res85[0x5c];
   1147 	unsigned int	div_stat_top0;
   1148 	unsigned int	div_stat_top1;
   1149 	unsigned int	div_stat_top2;
   1150 	unsigned char	res86[0x20];
   1151 	unsigned int	div_stat_disp10;
   1152 	unsigned char	res87[0x14];
   1153 	unsigned int	div_stat_mau;		/* 0x10020644 */
   1154 	unsigned int	div_stat_fsys0;
   1155 	unsigned int	div_stat_fsys1;
   1156 	unsigned int	div_stat_fsys2;
   1157 	unsigned char	res88[0x4];
   1158 	unsigned int	div_stat_peric0;
   1159 	unsigned int	div_stat_peric1;
   1160 	unsigned int	div_stat_peric2;
   1161 	unsigned int	div_stat_peric3;
   1162 	unsigned int	div_stat_peric4;
   1163 	unsigned char	res89[0x14];
   1164 	unsigned int	div_stat_isp0;
   1165 	unsigned int	div_stat_isp1;
   1166 	unsigned char	res90[0x8];
   1167 	unsigned int	clkdiv2_stat0;
   1168 	unsigned char	res91[0xc];
   1169 	unsigned int	clkdiv4_stat;
   1170 	unsigned char	res92[0x5c];
   1171 	unsigned int	gate_bus_top;		/* 0x10020700 */
   1172 	unsigned char	res93[0xc];
   1173 	unsigned int	gate_bus_gscl0;
   1174 	unsigned char	res94[0xc];
   1175 	unsigned int	gate_bus_gscl1;
   1176 	unsigned char	res95[0x4];
   1177 	unsigned int	gate_bus_disp1;
   1178 	unsigned char	res96[0x4];
   1179 	unsigned int	gate_bus_wcore;
   1180 	unsigned int	gate_bus_mfc;
   1181 	unsigned int	gate_bus_g3d;
   1182 	unsigned int	gate_bus_gen;
   1183 	unsigned int	gate_bus_fsys0;
   1184 	unsigned int	gate_bus_fsys1;
   1185 	unsigned int	gate_bus_fsys2;
   1186 	unsigned int	gate_bus_mscl;
   1187 	unsigned int	gate_bus_peric;
   1188 	unsigned int	gate_bus_peric1;
   1189 	unsigned char	res97[0x8];
   1190 	unsigned int	gate_bus_peris0;
   1191 	unsigned int	gate_bus_peris1;	/* 0x10020764 */
   1192 	unsigned char	res98[0x8];
   1193 	unsigned int	gate_bus_noc;
   1194 	unsigned char	res99[0xac];
   1195 	unsigned int	gate_top_sclk_gscl;
   1196 	unsigned char	res1000[0x4];
   1197 	unsigned int	gate_top_sclk_disp1;
   1198 	unsigned char	res100[0x10];
   1199 	unsigned int	gate_top_sclk_mau;
   1200 	unsigned int	gate_top_sclk_fsys;
   1201 	unsigned char	res101[0xc];
   1202 	unsigned int	gate_top_sclk_peric;
   1203 	unsigned char	res102[0xc];
   1204 	unsigned int	gate_top_sclk_cperi;
   1205 	unsigned char	res103[0xc];
   1206 	unsigned int	gate_top_sclk_isp;
   1207 	unsigned char	res104[0x9c];
   1208 	unsigned int	gate_ip_gscl0;
   1209 	unsigned char	res105[0xc];
   1210 	unsigned int	gate_ip_gscl1;
   1211 	unsigned char	res106[0x4];
   1212 	unsigned int	gate_ip_disp1;
   1213 	unsigned int	gate_ip_mfc;
   1214 	unsigned int	gate_ip_g3d;
   1215 	unsigned int	gate_ip_gen;		/* 0x10020934 */
   1216 	unsigned char	res107[0xc];
   1217 	unsigned int	gate_ip_fsys;
   1218 	unsigned char	res108[0x8];
   1219 	unsigned int	gate_ip_peric;
   1220 	unsigned char	res109[0xc];
   1221 	unsigned int	gate_ip_peris;
   1222 	unsigned char	res110[0xc];
   1223 	unsigned int	gate_ip_mscl;
   1224 	unsigned char	res111[0xc];
   1225 	unsigned int	gate_ip_block;
   1226 	unsigned char	res112[0xc];
   1227 	unsigned int	bypass;
   1228 	unsigned char	res113[0x6c];
   1229 	unsigned int	clkout_cmu_top;
   1230 	unsigned int	clkout_cmu_top_div_stat;
   1231 	unsigned char	res114[0xf8];
   1232 	unsigned int	clkout_top_spare0;
   1233 	unsigned int	clkout_top_spare1;
   1234 	unsigned int	clkout_top_spare2;
   1235 	unsigned int	clkout_top_spare3;
   1236 	unsigned char	res115[0x34e0];
   1237 	unsigned int	clkout_top_version;
   1238 	unsigned char	res116[0xc01c];
   1239 	unsigned int	bpll_lock;			/* 0x10030010 */
   1240 	unsigned char	res117[0xfc];
   1241 	unsigned int	bpll_con0;
   1242 	unsigned int	bpll_con1;
   1243 	unsigned char	res118[0xe8];
   1244 	unsigned int	src_cdrex;
   1245 	unsigned char	res119[0x1fc];
   1246 	unsigned int	mux_stat_cdrex;
   1247 	unsigned char	res120[0xfc];
   1248 	unsigned int	div_cdrex0;
   1249 	unsigned int	div_cdrex1;
   1250 	unsigned char	res121[0xf8];
   1251 	unsigned int	div_stat_cdrex;
   1252 	unsigned char	res1211[0xfc];
   1253 	unsigned int	gate_bus_cdrex;
   1254 	unsigned int	gate_bus_cdrex1;
   1255 	unsigned char	res122[0x1f8];
   1256 	unsigned int	gate_ip_cdrex;
   1257 	unsigned char	res123[0x10];
   1258 	unsigned int	dmc_freq_ctrl;		/* 0x10030914 */
   1259 	unsigned char	res124[0x4];
   1260 	unsigned int	pause;
   1261 	unsigned int	ddrphy_lock_ctrl;
   1262 	unsigned char	res125[0xdc];
   1263 	unsigned int	clkout_cmu_cdrex;
   1264 	unsigned int	clkout_cmu_cdrex_div_stat;
   1265 	unsigned char	res126[0x8];
   1266 	unsigned int	lpddr3phy_ctrl;
   1267 	unsigned int	lpddr3phy_con0;
   1268 	unsigned int	lpddr3phy_con1;
   1269 	unsigned int	lpddr3phy_con2;
   1270 	unsigned int	lpddr3phy_con3;
   1271 	unsigned int	lpddr3phy_con4;
   1272 	unsigned int	lpddr3phy_con5;		/* 0x10030a28 */
   1273 	unsigned int	pll_div2_sel;
   1274 	unsigned char	res127[0xd0];
   1275 	unsigned int	cmu_cdrex_spare0;
   1276 	unsigned int	cmu_cdrex_spare1;
   1277 	unsigned int	cmu_cdrex_spare2;
   1278 	unsigned int	cmu_cdrex_spare3;
   1279 	unsigned int	cmu_cdrex_spare4;
   1280 	unsigned char	res128[0x34dc];
   1281 	unsigned int	cmu_cdrex_version;		/* 0x10033ff0 */
   1282 	unsigned char	res129[0x400c];
   1283 	unsigned int	kpll_lock;
   1284 	unsigned char	res130[0xfc];
   1285 	unsigned int	kpll_con0;
   1286 	unsigned int	kpll_con1;
   1287 	unsigned char	res131[0xf8];
   1288 	unsigned int	src_kfc;
   1289 	unsigned char	res132[0x1fc];
   1290 	unsigned int	mux_stat_kfc;		/* 0x10038400 */
   1291 	unsigned char	res133[0xfc];
   1292 	unsigned int	div_kfc0;
   1293 	unsigned char	res134[0xfc];
   1294 	unsigned int	div_stat_kfc0;
   1295 	unsigned char	res135[0xfc];
   1296 	unsigned int	gate_bus_cpu_kfc;
   1297 	unsigned char	res136[0xfc];
   1298 	unsigned int	gate_sclk_cpu_kfc;
   1299 	unsigned char	res137[0x1fc];
   1300 	unsigned int	clkout_cmu_kfc;
   1301 	unsigned int	clkout_cmu_kfc_div_stat;	/* 0x10038a04 */
   1302 	unsigned char	res138[0x5f8];
   1303 	unsigned int	armclk_stopctrl_kfc;
   1304 	unsigned char	res139[0x4];
   1305 	unsigned int	armclk_ema_ctrl_kfc;
   1306 	unsigned int	armclk_ema_status_kfc;
   1307 	unsigned char	res140[0x10];
   1308 	unsigned int	pwr_ctrl_kfc;
   1309 	unsigned int	pwr_ctrl2_kfc;
   1310 	unsigned char	res141[0xd8];
   1311 	unsigned int	kpll_con0_l8;
   1312 	unsigned int	kpll_con0_l7;
   1313 	unsigned int	kpll_con0_l6;
   1314 	unsigned int	kpll_con0_l5;
   1315 	unsigned int	kpll_con0_l4;
   1316 	unsigned int	kpll_con0_l3;
   1317 	unsigned int	kpll_con0_l2;
   1318 	unsigned int	kpll_con0_l1;
   1319 	unsigned int	iem_control_kfc;		/* 0x10039120 */
   1320 	unsigned char	res142[0xdc];
   1321 	unsigned int	kpll_con1_l8;
   1322 	unsigned int	kpll_con1_l7;
   1323 	unsigned int	kpll_con1_l6;
   1324 	unsigned int	kpll_con1_l5;
   1325 	unsigned int	kpll_con1_l4;
   1326 	unsigned int	kpll_con1_l3;
   1327 	unsigned int	kpll_con1_l2;
   1328 	unsigned int	kpll_con1_l1;
   1329 	unsigned char	res143[0xe0];
   1330 	unsigned int	clkdiv_iem_l8_kfc;		/* 0x10039300 */
   1331 	unsigned int	clkdiv_iem_l7_kfc;
   1332 	unsigned int	clkdiv_iem_l6_kfc;
   1333 	unsigned int	clkdiv_iem_l5_kfc;
   1334 	unsigned int	clkdiv_iem_l4_kfc;
   1335 	unsigned int	clkdiv_iem_l3_kfc;
   1336 	unsigned int	clkdiv_iem_l2_kfc;
   1337 	unsigned int	clkdiv_iem_l1_kfc;
   1338 	unsigned char	res144[0xe0];
   1339 	unsigned int	l2_status_kfc;
   1340 	unsigned char	res145[0xc];
   1341 	unsigned int	cpu_status_kfc;		/* 0x10039410 */
   1342 	unsigned char	res146[0xc];
   1343 	unsigned int	ptm_status_kfc;
   1344 	unsigned char	res147[0xbdc];
   1345 	unsigned int	cmu_kfc_spare0;
   1346 	unsigned int	cmu_kfc_spare1;
   1347 	unsigned int	cmu_kfc_spare2;
   1348 	unsigned int	cmu_kfc_spare3;
   1349 	unsigned int	cmu_kfc_spare4;
   1350 	unsigned char	res148[0x1fdc];
   1351 	unsigned int	cmu_kfc_version;		/* 0x1003bff0 */
   1352 };
   1353 
   1354 /* structure for epll configuration used in audio clock configuration */
   1355 struct set_epll_con_val {
   1356 	unsigned int freq_out;		/* frequency out */
   1357 	unsigned int en_lock_det;	/* enable lock detect */
   1358 	unsigned int m_div;		/* m divider value */
   1359 	unsigned int p_div;		/* p divider value */
   1360 	unsigned int s_div;		/* s divider value */
   1361 	unsigned int k_dsm;		/* k value of delta signal modulator */
   1362 };
   1363 #endif
   1364 
   1365 #define MPLL_FOUT_SEL_SHIFT	4
   1366 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT	29  /* EPLL Locked bit position*/
   1367 #define TIMEOUT_EPLL_LOCK		1000
   1368 
   1369 #define AUDIO_0_RATIO_MASK		0x0f
   1370 #define AUDIO_1_RATIO_MASK		0x0f
   1371 
   1372 #define AUDIO0_SEL_MASK			0xf
   1373 #define AUDIO1_SEL_MASK			0xf
   1374 
   1375 #define CLK_SRC_SCLK_EPLL		0x7
   1376 #define CLK_SRC_MOUT_EPLL		(1<<12)
   1377 #define AUDIO_CLKMUX_ASS		(1<<0)
   1378 
   1379 /* CON0 bit-fields */
   1380 #define EPLL_CON0_MDIV_MASK		0x1ff
   1381 #define EPLL_CON0_PDIV_MASK		0x3f
   1382 #define EPLL_CON0_SDIV_MASK		0x7
   1383 #define EPLL_CON0_MDIV_SHIFT		16
   1384 #define EPLL_CON0_PDIV_SHIFT		8
   1385 #define EPLL_CON0_SDIV_SHIFT		0
   1386 #define EPLL_CON0_LOCK_DET_EN_SHIFT	28
   1387 #define EPLL_CON0_LOCK_DET_EN_MASK	1
   1388 
   1389 #define MPLL_FOUT_SEL_MASK	0x1
   1390 #define BPLL_FOUT_SEL_SHIFT	0
   1391 #define BPLL_FOUT_SEL_MASK	0x1
   1392 #endif
   1393