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    Searched refs:mpll_con0 (Results 1 - 6 of 6) sorted by null

  /external/u-boot/arch/arm/mach-exynos/
clock_init_exynos4.c 87 writel(MPLL_CON0_VAL, &clk->mpll_con0);
clock_init_exynos5.c 628 writel(val, &clk->mpll_con0);
629 while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
849 writel(val, &clk->mpll_con0);
850 while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
clock.c 196 r = readl(&clk->mpll_con0);
226 r = readl(&clk->mpll_con0);
257 r = readl(&clk->mpll_con0);
315 r = readl(&clk->mpll_con0);
    [all...]
  /external/u-boot/board/samsung/odroid/
odroid.c 205 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
208 while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
  /external/u-boot/arch/arm/mach-exynos/include/mach/
clock.h 188 unsigned int mpll_con0; member in struct:exynos4_clock
391 unsigned int mpll_con0; member in struct:exynos4x12_clock
574 unsigned int mpll_con0; member in struct:exynos5_clock
1067 unsigned int mpll_con0; member in struct:exynos5420_clock
    [all...]
  /external/u-boot/board/samsung/trats/
trats.c 342 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);

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