1 /** @file 2 * 3 * Copyright (c) 2016, Hisilicon Limited. All rights reserved. 4 * Copyright (c) 2016, Linaro Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #ifndef __PCIE_REG_OFFSET__ 17 #define __PCIE_REG_OFFSET__ 18 19 20 21 22 #define PCIE_EEP_PCI_CFG_HDR0_REG (0x0) 23 #define PCIE_EEP_PCI_CFG_HDR1_REG (0x4) 24 #define PCIE_EEP_PCI_CFG_HDR2_REG (0x8) 25 #define PCIE_EEP_PCI_CFG_HDR3_REG (0xC) 26 #define PCIE_EEP_PCI_CFG_HDR4_REG (0x10) 27 #define PCIE_EEP_PCI_CFG_HDR5_REG (0x14) 28 #define PCIE_EEP_PCI_CFG_HDR6_REG (0x18) 29 #define PCIE_EEP_PCI_CFG_HDR7_REG (0x1C) 30 #define PCIE_EEP_PCI_CFG_HDR8_REG (0x20) 31 #define PCIE_EEP_PCI_CFG_HDR9_REG (0x24) 32 #define PCIE_EEP_PCI_CFG_HDR10_REG (0x28) 33 #define PCIE_EEP_PCI_CFG_HDR11_REG (0x2C) 34 #define PCIE_EEP_PCI_CFG_HDR12_REG (0x30) 35 #define PCIE_EEP_PCI_CFG_HDR13_REG (0x34) 36 #define PCIE_EEP_PCI_CFG_HDR14_REG (0x38) 37 #define PCIE_EEP_PCI_CFG_HDR15_REG (0x3C) 38 #define PCIE_EEP_PCI_PM_CAP0_REG (0x40) 39 #define PCIE_EEP_PCI_PM_CAP1_REG (0x44) 40 #define PCIE_EEP_PCI_MSI_CAP0_REG (0x50) 41 #define PCIE_EEP_PCI_MSI_CAP1_REG (0x54) 42 #define PCIE_EEP_PCI_MSI_CAP2_REG (0x58) 43 #define PCIE_EEP_PCI_MSI_CAP3_REG (0x5C) 44 #define PCIE_EEP_PCIE_CAP0_REG (0x70) 45 #define PCIE_EEP_PCIE_CAP1_REG (0x74) 46 #define PCIE_EEP_PCIE_CAP2_REG (0x78) 47 #define PCIE_EEP_PCIE_CAP3_REG (0x7C) 48 #define PCIE_EEP_PCIE_CAP4_REG (0x80) 49 #define PCIE_EEP_PCIE_CAP5_REG (0x84) 50 #define PCIE_EEP_PCIE_CAP6_REG (0x88) 51 #define PCIE_EEP_PCIE_CAP7_REG (0x8C) 52 #define PCIE_EEP_PCIE_CAP8_REG (0x90) 53 #define PCIE_EEP_PCIE_CAP9_REG (0x94) 54 #define PCIE_EEP_PCIE_CAP10_REG (0x98) 55 #define PCIE_EEP_PCIE_CAP11_REG (0x9C) 56 #define PCIE_EEP_PCIE_CAP12_REG (0xA0) 57 #define PCIE_EEP_SLOT_CAP_REG (0xC0) 58 #define PCIE_EEP_AER_CAP0_REG (0x100) 59 #define PCIE_EEP_AER_CAP1_REG (0x104) 60 #define PCIE_EEP_AER_CAP2_REG (0x108) 61 #define PCIE_EEP_AER_CAP3_REG (0x10C) 62 #define PCIE_EEP_AER_CAP4_REG (0x110) 63 #define PCIE_EEP_AER_CAP5_REG (0x114) 64 #define PCIE_EEP_AER_CAP6_REG (0x118) 65 #define PCIE_EEP_AER_CAP7_REG (0x11C) 66 #define PCIE_EEP_AER_CAP8_REG (0x120) 67 #define PCIE_EEP_AER_CAP9_REG (0x124) 68 #define PCIE_EEP_AER_CAP10_REG (0x128) 69 #define PCIE_EEP_AER_CAP11_REG (0x12C) 70 #define PCIE_EEP_AER_CAP12_REG (0x130) 71 #define PCIE_EEP_AER_CAP13_REG (0x134) 72 #define PCIE_EEP_VC_CAP0_REG (0x140) 73 #define PCIE_EEP_VC_CAP1_REG (0x144) 74 #define PCIE_EEP_VC_CAP2_REG (0x148) 75 #define PCIE_EEP_VC_CAP3_REG (0x14C) 76 #define PCIE_EEP_VC_CAP4_REG (0x150) 77 #define PCIE_EEP_VC_CAP5_REG (0x154) 78 #define PCIE_EEP_VC_CAP6_REG (0x158) 79 #define PCIE_EEP_VC_CAP7_REG (0x15C) 80 #define PCIE_EEP_VC_CAP8_REG (0x160) 81 #define PCIE_EEP_VC_CAP9_REG (0x164) 82 #define PCIE_EEP_PORT_LOGIC0_REG (0x700) 83 #define PCIE_EEP_PORT_LOGIC1_REG (0x704) 84 #define PCIE_EEP_PORT_LOGIC2_REG (0x708) 85 #define PCIE_EEP_PORT_LOGIC3_REG (0x70C) 86 #define PCIE_EEP_PORT_LOGIC4_REG (0x710) 87 #define PCIE_EEP_PORT_LOGIC5_REG (0x714) 88 #define PCIE_EEP_PORT_LOGIC6_REG (0x718) 89 #define PCIE_EEP_PORT_LOGIC7_REG (0x71C) 90 #define PCIE_EEP_PORT_LOGIC8_REG (0x720) 91 #define PCIE_EEP_PORT_LOGIC9_REG (0x724) 92 #define PCIE_EEP_PORT_LOGIC10_REG (0x728) 93 #define PCIE_EEP_PORT_LOGIC11_REG (0x72C) 94 #define PCIE_EEP_PORT_LOGIC12_REG (0x730) 95 #define PCIE_EEP_PORT_LOGIC13_REG (0x734) 96 #define PCIE_EEP_PORT_LOGIC14_REG (0x738) 97 #define PCIE_EEP_PORT_LOGIC15_REG (0x73C) 98 #define PCIE_EEP_PORT_LOGIC16_REG (0x748) 99 #define PCIE_EEP_PORT_LOGIC17_REG (0x74C) 100 #define PCIE_EEP_PORT_LOGIC18_REG (0x750) 101 #define PCIE_EEP_PORT_LOGIC19_REG (0x7A8) 102 #define PCIE_EEP_PORT_LOGIC20_REG (0x7AC) 103 #define PCIE_EEP_PORT_LOGIC21_REG (0x7B0) 104 #define PCIE_EEP_PORT_LOGIC22_REG (0x80C) 105 #define PCIE_EEP_PORTLOGIC23_REG (0x810) 106 #define PCIE_EEP_PORTLOGIC24_REG (0x814) 107 #define PCIE_EEP_PORTLOGIC25_REG (0x818) 108 #define PCIE_EEP_PORTLOGIC26_REG (0x81C) 109 #define PCIE_EEP_PORTLOGIC27_REG (0x820) 110 #define PCIE_EEP_PORTLOGIC28_REG (0x824) 111 #define PCIE_EEP_PORTLOGIC29_REG (0x828) 112 #define PCIE_EEP_PORTLOGIC30_REG (0x82C) 113 #define PCIE_EEP_PORTLOGIC31_REG (0x830) 114 #define PCIE_EEP_PORTLOGIC32_REG (0x834) 115 #define PCIE_EEP_PORTLOGIC33_REG (0x838) 116 #define PCIE_EEP_PORTLOGIC34_REG (0x83C) 117 #define PCIE_EEP_PORTLOGIC35_REG (0x840) 118 #define PCIE_EEP_PORTLOGIC36_REG (0x844) 119 #define PCIE_EEP_PORTLOGIC37_REG (0x848) 120 #define PCIE_EEP_PORTLOGIC38_REG (0x84C) 121 #define PCIE_EEP_PORTLOGIC39_REG (0x850) 122 #define PCIE_EEP_PORTLOGIC40_REG (0x854) 123 #define PCIE_EEP_PORTLOGIC41_REG (0x858) 124 #define PCIE_EEP_PORTLOGIC42_REG (0x85C) 125 #define PCIE_EEP_PORTLOGIC43_REG (0x860) 126 #define PCIE_EEP_PORTLOGIC44_REG (0x864) 127 #define PCIE_EEP_PORTLOGIC45_REG (0x868) 128 #define PCIE_EEP_PORTLOGIC46_REG (0x86C) 129 #define PCIE_EEP_PORTLOGIC47_REG (0x870) 130 #define PCIE_EEP_PORTLOGIC48_REG (0x874) 131 #define PCIE_EEP_PORTLOGIC49_REG (0x878) 132 #define PCIE_EEP_PORTLOGIC50_REG (0x87C) 133 #define PCIE_EEP_PORTLOGIC51_REG (0x880) 134 #define PCIE_EEP_PORTLOGIC52_REG (0x884) 135 #define PCIE_EEP_PORTLOGIC53_REG (0x888) 136 #define PCIE_EEP_GEN3_CONTRL_REG (0x890) 137 #define PCIE_EEP_PIPE_LOOPBACK_REG (0x8B8) 138 #define PCIE_EEP_PORTLOGIC54_REG (0x900) 139 #define PCIE_EEP_PORTLOGIC55_REG (0x904) 140 #define PCIE_EEP_PORTLOGIC56_REG (0x908) 141 #define PCIE_EEP_PORTLOGIC57_REG (0x90C) 142 #define PCIE_EEP_PORTLOGIC58_REG (0x910) 143 #define PCIE_EEP_PORTLOGIC59_REG (0x914) 144 #define PCIE_EEP_PORTLOGIC60_REG (0x918) 145 #define PCIE_EEP_PORTLOGIC61_REG (0x91C) 146 #define PCIE_EEP_PORTLOGIC62_REG (0x97C) 147 #define PCIE_EEP_PORTLOGIC63_REG (0x980) 148 #define PCIE_EEP_PORTLOGIC64_REG (0x99C) 149 #define PCIE_EEP_PORTLOGIC65_REG (0x9A0) 150 #define PCIE_EEP_PORTLOGIC66_REG (0x9BC) 151 #define PCIE_EEP_PORTLOGIC67_REG (0x9C4) 152 #define PCIE_EEP_PORTLOGIC68_REG (0x9C8) 153 #define PCIE_EEP_PORTLOGIC69_REG (0x9CC) 154 #define PCIE_EEP_PORTLOGIC70_REG (0x9D0) 155 #define PCIE_EEP_PORTLOGIC71_REG (0x9D4) 156 #define PCIE_EEP_PORTLOGIC72_REG (0x9D8) 157 #define PCIE_EEP_PORTLOGIC73_REG (0x9DC) 158 #define PCIE_EEP_PORTLOGIC74_REG (0x9E0) 159 #define PCIE_EEP_PORTLOGIC75_REG (0xA00) 160 #define PCIE_EEP_PORTLOGIC76_REG (0xA10) 161 #define PCIE_EEP_PORTLOGIC77_REG (0xA18) 162 #define PCIE_EEP_PORTLOGIC78_REG (0xA1C) 163 #define PCIE_EEP_PORTLOGIC79_REG (0xA24) 164 #define PCIE_EEP_PORTLOGIC80_REG (0xA28) 165 #define PCIE_EEP_PORTLOGIC81_REG (0xA34) 166 #define PCIE_EEP_PORTLOGIC82_REG (0xA3C) 167 #define PCIE_EEP_PORTLOGIC83_REG (0xA40) 168 #define PCIE_EEP_PORTLOGIC84_REG (0xA44) 169 #define PCIE_EEP_PORTLOGIC85_REG (0xA48) 170 #define PCIE_EEP_PORTLOGIC86_REG (0xA6C) 171 #define PCIE_EEP_PORTLOGIC87_REG (0xA70) 172 #define PCIE_EEP_PORTLOGIC88_REG (0xA78) 173 #define PCIE_EEP_PORTLOGIC89_REG (0xA7C) 174 #define PCIE_EEP_PORTLOGIC90_REG (0xA80) 175 #define PCIE_EEP_PORTLOGIC91_REG (0xA84) 176 #define PCIE_EEP_PORTLOGIC92_REG (0xA88) 177 #define PCIE_EEP_PORTLOGIC93_REG (0xA8C) 178 #define PCIE_EEP_PORTLOGIC94_REG (0xA90) 179 180 //pcie iatu internal registers define 181 #define IATU_OFFSET 0x700 182 #define IATU_VIEW_POINT 0x200 183 #define IATU_REGION_CTRL1 0x204 184 #define IATU_REGION_CTRL2 0x208 185 #define IATU_REGION_BASE_LOW 0x20C 186 #define IATU_REGION_BASE_HIGH 0x210 187 #define IATU_REGION_BASE_LIMIT 0x214 188 #define IATU_REGION_TARGET_LOW 0x218 189 #define IATU_REGION_TARGET_HIGH 0x21C 190 #define IATU_SHIIF_MODE 0x90000000 191 #define IATU_NORMAL_MODE 0x80000000 192 #define IATU_CTRL1_TYPE_CONFIG0 0x4 193 #define IATU_CTRL1_TYPE_CONFIG1 0x5 194 #define IATU_CTRL1_TYPE_MEM 0 195 #define IATU_CTRL1_TYPE_IO 2 196 197 198 typedef union tagPipeLoopBack 199 { 200 struct 201 { 202 UINT32 reserved : 31 ; 203 UINT32 pipe_loopback_enable : 1 ; 204 }Bits; 205 UINT32 UInt32; 206 }PCIE_PIPE_LOOPBACK_U; 207 208 typedef union tagEepPciCfgHdr0 209 { 210 211 struct 212 { 213 UINT32 vendor_id : 16 ; 214 UINT32 device_id : 16 ; 215 } Bits; 216 217 218 UINT32 UInt32; 219 220 } PCIE_EEP_PCI_CFG_HDR0_U; 221 222 223 224 typedef union tagEepPciCfgHdr1 225 { 226 227 struct 228 { 229 UINT32 io_space_enable : 1 ; 230 UINT32 memory_space_enable : 1 ; 231 UINT32 bus_master_enable : 1 ; 232 UINT32 specialcycleenable : 1 ; 233 UINT32 memory_write_and_invalidate : 1 ; 234 UINT32 vga_palette_snoop_enable : 1 ; 235 UINT32 parity_error_response : 1 ; 236 UINT32 idsel_stepping_waitcycle_control : 1 ; 237 UINT32 serr_enable : 1 ; 238 UINT32 fastback_to_backenable : 1 ; 239 UINT32 interrupt_disable : 1 ; 240 UINT32 Reserved_2 : 5 ; 241 UINT32 Reserved_1 : 3 ; 242 UINT32 intx_status : 1 ; 243 UINT32 capabilitieslist : 1 ; 244 UINT32 pcibus66mhzcapable : 1 ; 245 UINT32 Reserved_0 : 1 ; 246 UINT32 fastback_to_back : 1 ; 247 UINT32 masterdataparityerror : 1 ; 248 UINT32 devsel_timing : 2 ; 249 UINT32 signaled_target_abort : 1 ; 250 UINT32 received_target_abort : 1 ; 251 UINT32 received_master_abort : 1 ; 252 UINT32 signaled_system_error : 1 ; 253 UINT32 detected_parity_error : 1 ; 254 } Bits; 255 256 257 UINT32 UInt32; 258 259 } PCIE_EEP_PCI_CFG_HDR1_U; 260 261 typedef union tagEepPciCfgHdr2 262 { 263 264 struct 265 { 266 UINT32 revision_identification : 8 ; 267 UINT32 Reserved_3 : 8 ; 268 UINT32 sub_class : 8 ; 269 UINT32 baseclass : 8 ; 270 } Bits; 271 272 273 UINT32 UInt32; 274 275 } PCIE_EEP_PCI_CFG_HDR2_U; 276 277 278 279 typedef union tagEepPciCfgHdr3 280 { 281 282 struct 283 { 284 UINT32 cache_line_size : 8 ; 285 UINT32 mstr_lat_tmr : 8 ; 286 UINT32 multi_function_device : 7 ; 287 UINT32 hdr_type : 1 ; 288 UINT32 bist : 8 ; 289 } Bits; 290 291 292 UINT32 UInt32; 293 294 } PCIE_EEP_PCI_CFG_HDR3_U; 295 296 297 298 typedef union tagEepPciCfgHdr4 299 { 300 301 struct 302 { 303 UINT32 sbar01_space_inicator : 1 ; 304 UINT32 sbar01_type : 2 ; 305 UINT32 sbar01_prefetchable : 1 ; 306 UINT32 sbar01_lower : 28 ; 307 } Bits; 308 309 310 UINT32 UInt32; 311 312 } PCIE_EEP_PCI_CFG_HDR4_U; 313 314 315 316 typedef union tagEepPciCfgHdr6 317 { 318 319 struct 320 { 321 UINT32 sbar23_space_inicator : 1 ; 322 UINT32 sbar23_type : 2 ; 323 UINT32 sbar23_prefetchable : 1 ; 324 UINT32 Reserved_4 : 8 ; 325 UINT32 sbar23_lower : 20 ; 326 } Bits; 327 328 329 UINT32 UInt32; 330 331 } PCIE_EEP_PCI_CFG_HDR6_U; 332 333 334 335 typedef union tagEepPciCfgHdr8 336 { 337 338 struct 339 { 340 UINT32 sbar45_space_inicator : 1 ; 341 UINT32 sbar45_type : 2 ; 342 UINT32 sbar45_prefetchable : 1 ; 343 UINT32 Reserved_5 : 8 ; 344 UINT32 sbar45_lower : 20 ; 345 } Bits; 346 347 348 UINT32 UInt32; 349 350 } PCIE_EEP_PCI_CFG_HDR8_U; 351 352 353 354 typedef union tagEepPciCfgHdr11 355 { 356 357 struct 358 { 359 UINT32 subsystem_vendor_id : 16 ; 360 UINT32 subsystemid : 16 ; 361 } Bits; 362 363 364 UINT32 UInt32; 365 366 } PCIE_EEP_PCI_CFG_HDR11_U; 367 368 369 370 typedef union tagEepPciCfgHdr13 371 { 372 373 struct 374 { 375 UINT32 capptr : 8 ; 376 UINT32 Reserved_6 : 24 ; 377 } Bits; 378 379 380 UINT32 UInt32; 381 382 } PCIE_EEP_PCI_CFG_HDR13_U; 383 384 385 386 typedef union tagEepPciCfgHdr15 387 { 388 389 struct 390 { 391 UINT32 int_line : 8 ; 392 UINT32 int_pin : 8 ; 393 UINT32 Min_Grant : 8 ; 394 UINT32 Max_Latency : 8 ; 395 } Bits; 396 397 398 UINT32 UInt32; 399 400 } PCIE_EEP_PCI_CFG_HDR15_U; 401 402 403 404 typedef union tagEepPciMsiCap0 405 { 406 407 struct 408 { 409 UINT32 msi_cap_id : 8 ; 410 UINT32 next_capability_pointer : 8 ; 411 UINT32 msi_enabled : 1 ; 412 UINT32 multiple_message_capable : 3 ; 413 UINT32 multiple_message_enabled : 3 ; 414 UINT32 msi_64_en : 1 ; 415 UINT32 pvm_en : 1 ; 416 UINT32 message_control_register : 7 ; 417 } Bits; 418 419 420 UINT32 UInt32; 421 422 } PCIE_EEP_PCI_MSI_CAP0_U; 423 424 425 426 typedef union tagEepPciMsiCap1 427 { 428 429 struct 430 { 431 UINT32 Reserved_11 : 2 ; 432 UINT32 msi_addr_low : 30 ; 433 } Bits; 434 435 436 UINT32 UInt32; 437 438 } PCIE_EEP_PCI_MSI_CAP1_U; 439 440 441 442 typedef union tagEepPciMsiCap3 443 { 444 445 struct 446 { 447 UINT32 msi_data : 16 ; 448 UINT32 Reserved_12 : 16 ; 449 } Bits; 450 451 452 UINT32 UInt32; 453 454 } PCIE_EEP_PCI_MSI_CAP3_U; 455 456 457 458 typedef union tagEepPcieCap0 459 { 460 461 struct 462 { 463 UINT32 pcie_cap_id : 8 ; 464 UINT32 pcie_next_ptr : 8 ; 465 UINT32 pcie_capability_version : 4 ; 466 UINT32 device_port_type : 4 ; 467 UINT32 slot_implemented : 1 ; 468 UINT32 interrupt_message_number : 5 ; 469 UINT32 Reserved_13 : 2 ; 470 } Bits; 471 472 473 UINT32 UInt32; 474 475 } PCIE_EEP_PCIE_CAP0_U; 476 477 478 479 typedef union tagEepPcieCap1 480 { 481 482 struct 483 { 484 UINT32 max_payload_size_supported : 3 ; 485 UINT32 phantom_function_supported : 2 ; 486 UINT32 extended_tagEepfield_supported : 1 ; 487 UINT32 endpoint_l0sacceptable_latency : 3 ; 488 UINT32 endpoint_l1acceptable_latency : 3 ; 489 UINT32 undefined : 3 ; 490 UINT32 Reserved_16 : 3 ; 491 UINT32 captured_slot_power_limit_value : 8 ; 492 UINT32 captured_slot_power_limit_scale : 2 ; 493 UINT32 function_level_reset : 1 ; 494 UINT32 Reserved_15 : 3 ; 495 } Bits; 496 497 498 UINT32 UInt32; 499 500 } PCIE_EEP_PCIE_CAP1_U; 501 502 503 504 typedef union tagEepPcieCap2 505 { 506 507 struct 508 { 509 UINT32 correctable_error_reporting_enable : 1 ; 510 UINT32 non_fatal_error_reporting_enable : 1 ; 511 UINT32 fatal_error_reporting_enable : 1 ; 512 UINT32 urenable : 1 ; 513 UINT32 enable_relaxed_ordering : 1 ; 514 UINT32 max_payload_size : 3 ; 515 UINT32 extended_tagEepfieldenable : 1 ; 516 UINT32 phantom_function_enable : 1 ; 517 UINT32 auxpowerpmenable : 1 ; 518 UINT32 enablenosnoop : 1 ; 519 UINT32 max_read_request_size : 3 ; 520 UINT32 Reserved_18 : 1 ; 521 UINT32 correctableerrordetected : 1 ; 522 UINT32 non_fatalerrordetected : 1 ; 523 UINT32 fatalerrordetected : 1 ; 524 UINT32 unsupportedrequestdetected : 1 ; 525 UINT32 auxpowerdetected : 1 ; 526 UINT32 transactionpending : 1 ; 527 UINT32 Reserved_17 : 10 ; 528 } Bits; 529 530 531 UINT32 UInt32; 532 533 } PCIE_EEP_PCIE_CAP2_U; 534 535 536 537 typedef union tagEepPcieCap3 538 { 539 540 struct 541 { 542 UINT32 max_link_speed : 4 ; 543 UINT32 max_link_width : 6 ; 544 UINT32 active_state_power_management : 2 ; 545 UINT32 l0s_exitlatency : 3 ; 546 UINT32 l1_exit_latency : 3 ; 547 UINT32 clock_power_management : 1 ; 548 UINT32 surprise_down_error_report_cap : 1 ; 549 UINT32 data_link_layer_active_report_cap : 1 ; 550 UINT32 link_bandwidth_noti_cap : 1 ; 551 UINT32 aspm_option_compliance : 1 ; 552 UINT32 Reserved_19 : 1 ; 553 UINT32 port_number : 8 ; 554 } Bits; 555 556 557 UINT32 UInt32; 558 559 } PCIE_EEP_PCIE_CAP3_U; 560 561 562 563 564 typedef union tagEepPcieCap4 565 { 566 567 struct 568 { 569 UINT32 active_state_power_management : 2 ; 570 UINT32 Reserved_22 : 1 ; 571 UINT32 rcb : 1 ; 572 UINT32 link_disable : 1 ; 573 UINT32 retrain_link : 1 ; 574 UINT32 common_clock_config : 1 ; 575 UINT32 extended_sync : 1 ; 576 UINT32 enable_clock_pwr_management : 1 ; 577 UINT32 hw_auto_width_disable : 1 ; 578 UINT32 link_bandwidth_management_int_en : 1 ; 579 UINT32 link_auto_bandwidth_int_en : 1 ; 580 UINT32 Reserved_21 : 4 ; 581 UINT32 current_link_speed : 4 ; 582 UINT32 negotiated_link_width : 6 ; 583 UINT32 Reserved_20 : 1 ; 584 UINT32 link_training : 1 ; 585 UINT32 slot_clock_configration : 1 ; 586 UINT32 data_link_layer_active : 1 ; 587 UINT32 link_bandwidth_management_status : 1 ; 588 UINT32 link_auto_bandwidth_status : 1 ; 589 } Bits; 590 591 592 UINT32 UInt32; 593 594 } PCIE_EEP_PCIE_CAP4_U; 595 596 597 598 599 typedef union tagEepPcieCap5 600 { 601 602 struct 603 { 604 UINT32 attentioonbuttonpresent : 1 ; 605 UINT32 powercontrollerpresent : 1 ; 606 UINT32 mrlsensorpresent : 1 ; 607 UINT32 attentionindicatorpresent : 1 ; 608 UINT32 powerindicatorpresent : 1 ; 609 UINT32 hot_plugsurprise : 1 ; 610 UINT32 hot_plugcapable : 1 ; 611 UINT32 slotpowerlimitvalue : 8 ; 612 UINT32 slotpowerlimitscale : 2 ; 613 UINT32 electromechanicalinterlockpresen : 1 ; 614 UINT32 no_cmd_complete_support : 1 ; 615 UINT32 phy_slot_number : 13 ; 616 } Bits; 617 618 619 UINT32 UInt32; 620 621 } PCIE_EEP_PCIE_CAP5_U; 622 623 624 625 626 typedef union tagEepPcieCap6 627 { 628 629 struct 630 { 631 UINT32 attentionbuttonpressedenable : 1 ; 632 UINT32 powerfaultdetectedenable : 1 ; 633 UINT32 mrlsensorchangedenable : 1 ; 634 UINT32 presencedetectchangedenable : 1 ; 635 UINT32 commandcompletedinterruptenable : 1 ; 636 UINT32 hot_pluginterruptenable : 1 ; 637 UINT32 attentionindicatorcontrol : 2 ; 638 UINT32 powerindicatorcontrol : 2 ; 639 UINT32 powercontrollercontrol : 1 ; 640 UINT32 electromechanicalinterlockcontrol : 1 ; 641 UINT32 datalinklayerstatechangedenable : 1 ; 642 UINT32 Reserved_23 : 3 ; 643 UINT32 attentionbuttonpressed : 1 ; 644 UINT32 powerfaultdetected : 1 ; 645 UINT32 mrlsensorchanged : 1 ; 646 UINT32 presencedetectchanged : 1 ; 647 UINT32 commandcompleted : 1 ; 648 UINT32 mrlsensorstate : 1 ; 649 UINT32 presencedetectstate : 1 ; 650 UINT32 electromechanicalinterlockstatus : 1 ; 651 UINT32 datalinklayerstatechanged : 1 ; 652 UINT32 slot_ctrl_status : 7 ; 653 } Bits; 654 655 656 UINT32 UInt32; 657 658 } PCIE_EEP_PCIE_CAP6_U; 659 660 661 662 663 typedef union tagEepPcieCap7 664 { 665 666 struct 667 { 668 UINT32 systemerroroncorrectableerrorenable : 1 ; 669 UINT32 systemerroronnon_fatalerrorenable : 1 ; 670 UINT32 systemerroronfatalerrorenable : 1 ; 671 UINT32 pmeinterruptenable : 1 ; 672 UINT32 crssoftwarevisibilityenable : 1 ; 673 UINT32 Reserved_24 : 11 ; 674 UINT32 crssoftwarevisibility : 1 ; 675 UINT32 root_cap : 15 ; 676 } Bits; 677 678 679 UINT32 UInt32; 680 681 } PCIE_EEP_PCIE_CAP7_U; 682 683 684 685 686 typedef union tagEepPcieCap8 687 { 688 689 struct 690 { 691 UINT32 pmerequesterid : 16 ; 692 UINT32 pmestatus : 1 ; 693 UINT32 pmepending : 1 ; 694 UINT32 root_status : 14 ; 695 } Bits; 696 697 698 UINT32 UInt32; 699 700 } PCIE_EEP_PCIE_CAP8_U; 701 702 703 704 705 typedef union tagEepPcieCap9 706 { 707 708 struct 709 { 710 UINT32 completiontimeoutrangessupported : 4 ; 711 UINT32 completiontimeoutdisablesupported : 1 ; 712 UINT32 ariforwardingsupported : 1 ; 713 UINT32 atomicoproutingsupported : 1 ; 714 UINT32 _2_bitatomicopcompletersupported : 1 ; 715 UINT32 _4_bitatomicopcompletersupported : 1 ; 716 UINT32 _28_bitcascompletersupported : 1 ; 717 UINT32 noro_enabledpr_prpassing : 1 ; 718 UINT32 Reserved_25 : 1 ; 719 UINT32 tphcompletersupported : 2 ; 720 UINT32 dev_cap2 : 18 ; 721 } Bits; 722 723 724 UINT32 UInt32; 725 726 } PCIE_EEP_PCIE_CAP9_U; 727 728 729 730 731 typedef union tagEepPcieCap10 732 { 733 734 struct 735 { 736 UINT32 completiontimeoutvalue : 4 ; 737 UINT32 completiontimeoutdisable : 1 ; 738 UINT32 ariforwardingsupported : 1 ; 739 UINT32 atomicoprequesterenable : 1 ; 740 UINT32 atomicopegressblocking : 1 ; 741 UINT32 idorequestenable : 1 ; 742 UINT32 idocompletionenable : 1 ; 743 UINT32 dev_ctrl2 : 22 ; 744 } Bits; 745 746 747 UINT32 UInt32; 748 749 } PCIE_EEP_PCIE_CAP10_U; 750 751 752 753 754 typedef union tagEepPcieCap11 755 { 756 757 struct 758 { 759 UINT32 Reserved_27 : 1 ; 760 UINT32 gen1_suport : 1 ; 761 UINT32 gen2_suport : 1 ; 762 UINT32 gen3_suport : 1 ; 763 UINT32 Reserved_26 : 4 ; 764 UINT32 crosslink_supported : 1 ; 765 UINT32 link_cap2 : 23 ; 766 } Bits; 767 768 769 UINT32 UInt32; 770 771 } PCIE_EEP_PCIE_CAP11_U; 772 773 774 775 776 typedef union tagEepPcieCap12 777 { 778 779 struct 780 { 781 UINT32 targetlinkspeed : 4 ; 782 UINT32 entercompliance : 1 ; 783 UINT32 hardwareautonomousspeeddisa : 1 ; 784 UINT32 selectablede_empha : 1 ; 785 UINT32 transmitmargin : 3 ; 786 UINT32 _entermodifiedcompliance : 1 ; 787 UINT32 compliancesos : 1 ; 788 UINT32 de_emphasislevel : 4 ; 789 UINT32 currentde_emphasislevel : 1 ; 790 UINT32 equalizationcomplete : 1 ; 791 UINT32 equalizationphase1successful : 1 ; 792 UINT32 equalizationphase2successful : 1 ; 793 UINT32 equalizationphase3successful : 1 ; 794 UINT32 linkequalizationrequest : 1 ; 795 UINT32 link_ctrl2_status2 : 10 ; 796 } Bits; 797 798 799 UINT32 UInt32; 800 801 } PCIE_EEP_PCIE_CAP12_U; 802 803 804 805 806 typedef union tagEepSlotCap 807 { 808 809 struct 810 { 811 UINT32 slotnumberingcapabilitiesid : 8 ; 812 UINT32 nextcapabilitypointer : 8 ; 813 UINT32 add_incardslotsprovided : 5 ; 814 UINT32 firstinchassis : 1 ; 815 UINT32 Reserved_28 : 2 ; 816 UINT32 slot_cap : 8 ; 817 } Bits; 818 819 820 UINT32 UInt32; 821 822 } PCIE_EEP_SLOT_CAP_U; 823 824 825 826 827 typedef union tagEepAerCap0 828 { 829 830 struct 831 { 832 UINT32 pciexpressextendedcapabilityid : 16 ; 833 UINT32 capabilityversion : 4 ; 834 UINT32 aer_cap_hdr : 12 ; 835 } Bits; 836 837 838 UINT32 UInt32; 839 840 } PCIE_EEP_AER_CAP0_U; 841 842 843 844 845 typedef union tagEepAerCap1 846 { 847 848 struct 849 { 850 UINT32 Reserved_34 : 1 ; 851 UINT32 Reserved_33 : 3 ; 852 UINT32 datalinkprotocolerrorsta : 1 ; 853 UINT32 surprisedownerrorstatus : 1 ; 854 UINT32 Reserved_32 : 6 ; 855 UINT32 poisonedtlpstatu : 1 ; 856 UINT32 flowcontrolprotocolerrorst : 1 ; 857 UINT32 completiontimeouts : 1 ; 858 UINT32 completerabortstatus : 1 ; 859 UINT32 receiveroverflowstatus : 1 ; 860 UINT32 malformedtlpstatus : 1 ; 861 UINT32 ecrcerrorstatus : 1 ; 862 UINT32 ecrcerrorstat : 1 ; 863 UINT32 unsupportedrequesterrorstatus : 1 ; 864 UINT32 Reserved_31 : 3 ; 865 UINT32 atomicopegressblockedstatus : 1 ; 866 UINT32 uncorr_err_status : 7 ; 867 } Bits; 868 869 870 UINT32 UInt32; 871 872 } PCIE_EEP_AER_CAP1_U; 873 874 875 876 877 typedef union tagEepAerCap2 878 { 879 880 struct 881 { 882 UINT32 Reserved_38 : 1 ; 883 UINT32 Reserved_37 : 3 ; 884 UINT32 datalinkprotocolerrormask : 1 ; 885 UINT32 surprisedownerrormask : 1 ; 886 UINT32 Reserved_36 : 6 ; 887 UINT32 poisonedtlpmask : 1 ; 888 UINT32 flowcontrolprotocolerrormask : 1 ; 889 UINT32 completiontimeoutmask : 1 ; 890 UINT32 completerabortmask : 1 ; 891 UINT32 unexpectedcompletionmask : 1 ; 892 UINT32 receiveroverflowmask : 1 ; 893 UINT32 malformedtlpmask : 1 ; 894 UINT32 ecrcerrormask : 1 ; 895 UINT32 unsupportedrequesterrormask : 1 ; 896 UINT32 Reserved_35 : 3 ; 897 UINT32 atomicopegressblockedmask : 1 ; 898 UINT32 uncorr_err_mask : 7 ; 899 } Bits; 900 901 902 UINT32 UInt32; 903 904 } PCIE_EEP_AER_CAP2_U; 905 906 907 908 909 typedef union tagEepAerCap3 910 { 911 912 struct 913 { 914 UINT32 Reserved_42 : 1 ; 915 UINT32 Reserved_41 : 3 ; 916 UINT32 datalinkprotocolerrorsever : 1 ; 917 UINT32 surprisedownerrorseverity : 1 ; 918 UINT32 Reserved_40 : 6 ; 919 UINT32 poisonedtlpseverity : 1 ; 920 UINT32 flowcontrolprotocolerrorseveri : 1 ; 921 UINT32 completiontimeoutseverity : 1 ; 922 UINT32 completerabortseverity : 1 ; 923 UINT32 unexpectedcompletionseverity : 1 ; 924 UINT32 receiveroverflowseverity : 1 ; 925 UINT32 malformedtlpseverity : 1 ; 926 UINT32 ecrcerrorseverity : 1 ; 927 UINT32 unsupportedrequesterrorseverity : 1 ; 928 UINT32 Reserved_39 : 3 ; 929 UINT32 atomicopegressblockedseverity : 1 ; 930 UINT32 uncorr_err_ser : 7 ; 931 } Bits; 932 933 934 UINT32 UInt32; 935 936 } PCIE_EEP_AER_CAP3_U; 937 938 939 940 941 typedef union tagEepAerCap4 942 { 943 944 struct 945 { 946 UINT32 receivererrorstatus : 1 ; 947 UINT32 Reserved_44 : 5 ; 948 UINT32 badtlpstatus : 1 ; 949 UINT32 baddllpstatus : 1 ; 950 UINT32 replay_numrolloverstatus : 1 ; 951 UINT32 Reserved_43 : 3 ; 952 UINT32 replytimertimeoutstatus : 1 ; 953 UINT32 advisorynon_fatalerrorstatus : 1 ; 954 UINT32 corr_err_status : 18 ; 955 } Bits; 956 957 958 UINT32 UInt32; 959 960 } PCIE_EEP_AER_CAP4_U; 961 962 963 964 965 typedef union tagEepAerCap5 966 { 967 968 struct 969 { 970 UINT32 receivererrormask : 1 ; 971 UINT32 Reserved_46 : 5 ; 972 UINT32 badtlpmask : 1 ; 973 UINT32 baddllpmask : 1 ; 974 UINT32 replay_numrollovermask : 1 ; 975 UINT32 Reserved_45 : 3 ; 976 UINT32 replytimertimeoutmask : 1 ; 977 UINT32 advisorynon_fatalerrormask : 1 ; 978 UINT32 corr_err_mask : 18 ; 979 } Bits; 980 981 982 UINT32 UInt32; 983 984 } PCIE_EEP_AER_CAP5_U; 985 986 987 988 989 typedef union tagEepAerCap6 990 { 991 992 struct 993 { 994 UINT32 firsterrorpointer : 5 ; 995 UINT32 ecrcgenerationcapability : 1 ; 996 UINT32 ecrcgenerationenable : 1 ; 997 UINT32 ecrccheckcapable : 1 ; 998 UINT32 ecrccheckenable : 1 ; 999 UINT32 adv_cap_ctrl : 23 ; 1000 } Bits; 1001 1002 1003 UINT32 UInt32; 1004 1005 } PCIE_EEP_AER_CAP6_U; 1006 1007 typedef union tagGen3Ctrol 1008 { 1009 struct 1010 { 1011 UINT32 reserved : 16 ; 1012 UINT32 equalization_disable : 1 ; 1013 UINT32 reserved2 : 15 ; 1014 }Bits; 1015 UINT32 UInt32; 1016 }PCIE_GRN3_CONTRL; 1017 1018 1019 1020 1021 typedef union tagEepAerCap11 1022 { 1023 1024 struct 1025 { 1026 UINT32 correctableerrorreportingenable : 1 ; 1027 UINT32 non_fatalerrorreportingenable : 1 ; 1028 UINT32 fatalerrorreportingenable : 1 ; 1029 UINT32 root_err_cmd : 29 ; 1030 } Bits; 1031 1032 1033 UINT32 UInt32; 1034 1035 } PCIE_EEP_AER_CAP11_U; 1036 1037 1038 1039 1040 typedef union tagEepAerCap12 1041 { 1042 1043 struct 1044 { 1045 UINT32 err_correceived : 1 ; 1046 UINT32 multipleerr_correceived : 1 ; 1047 UINT32 err_fatal_nonfatalreceived : 1 ; 1048 UINT32 multipleerr_fatal_nonfatalreceived : 1 ; 1049 UINT32 firstuncorrectablefatal : 1 ; 1050 UINT32 non_fatalerrormessagesreceived : 1 ; 1051 UINT32 fatalerrormessagesreceived : 1 ; 1052 UINT32 Reserved_47 : 20 ; 1053 UINT32 root_err_status : 5 ; 1054 } Bits; 1055 1056 1057 UINT32 UInt32; 1058 1059 } PCIE_EEP_AER_CAP12_U; 1060 1061 1062 1063 1064 typedef union tagEepAerCap13 1065 { 1066 1067 struct 1068 { 1069 UINT32 err_corsourceidentification : 16 ; 1070 UINT32 err_src_id : 16 ; 1071 } Bits; 1072 1073 1074 UINT32 UInt32; 1075 1076 } PCIE_EEP_AER_CAP13_U; 1077 1078 1079 1080 1081 typedef union tagEepVcCap0 1082 { 1083 1084 struct 1085 { 1086 UINT32 pciexpressextendedcapabilityid : 16 ; 1087 UINT32 capabilityversion : 4 ; 1088 UINT32 vc_cap_hdr : 12 ; 1089 } Bits; 1090 1091 1092 UINT32 UInt32; 1093 1094 } PCIE_EEP_VC_CAP0_U; 1095 1096 1097 1098 1099 typedef union tagEepVcCap1 1100 { 1101 1102 struct 1103 { 1104 UINT32 extendedvccount : 3 ; 1105 UINT32 Reserved_50 : 1 ; 1106 UINT32 lowpriorityextendedvccount : 3 ; 1107 UINT32 Reserved_49 : 1 ; 1108 UINT32 referenceclock : 2 ; 1109 UINT32 portarbitrationtableentrysize : 2 ; 1110 UINT32 vc_cap1 : 20 ; 1111 } Bits; 1112 1113 1114 UINT32 UInt32; 1115 1116 } PCIE_EEP_VC_CAP1_U; 1117 1118 1119 1120 1121 typedef union tagEepVcCap2 1122 { 1123 1124 struct 1125 { 1126 UINT32 vcarbitrationcapability : 8 ; 1127 UINT32 Reserved_51 : 16 ; 1128 UINT32 vc_cap2 : 8 ; 1129 } Bits; 1130 1131 1132 UINT32 UInt32; 1133 1134 } PCIE_EEP_VC_CAP2_U; 1135 1136 1137 1138 1139 typedef union tagEepVcCap3 1140 { 1141 1142 struct 1143 { 1144 UINT32 loadvcarbitrationtable : 1 ; 1145 UINT32 vcarbitrationselect : 3 ; 1146 UINT32 Reserved_53 : 12 ; 1147 UINT32 arbitrationtablestatus : 1 ; 1148 UINT32 Reserved_52 : 15 ; 1149 } Bits; 1150 1151 1152 UINT32 UInt32; 1153 1154 } PCIE_EEP_VC_CAP3_U; 1155 1156 1157 1158 1159 typedef union tagEepVcCap4 1160 { 1161 1162 struct 1163 { 1164 UINT32 portarbitrationcapability : 8 ; 1165 UINT32 Reserved_56 : 6 ; 1166 UINT32 Reserved_55 : 1 ; 1167 UINT32 rejectsnooptransactions : 1 ; 1168 UINT32 maximumtimeslots : 7 ; 1169 UINT32 Reserved_54 : 1 ; 1170 UINT32 vc_res_cap : 8 ; 1171 } Bits; 1172 1173 1174 UINT32 UInt32; 1175 1176 } PCIE_EEP_VC_CAP4_U; 1177 1178 1179 1180 1181 typedef union tagEepVcCap5 1182 { 1183 1184 struct 1185 { 1186 UINT32 tc_vcmap : 8 ; 1187 UINT32 Reserved_59 : 8 ; 1188 UINT32 loadportarbitrationtable : 1 ; 1189 UINT32 portarbitrationselec : 3 ; 1190 UINT32 Reserved_58 : 4 ; 1191 UINT32 vcid : 3 ; 1192 UINT32 Reserved_57 : 4 ; 1193 UINT32 vc_res_ctrl : 1 ; 1194 } Bits; 1195 1196 1197 UINT32 UInt32; 1198 1199 } PCIE_EEP_VC_CAP5_U; 1200 1201 1202 1203 1204 typedef union tagEepVcCap6 1205 { 1206 1207 struct 1208 { 1209 UINT32 Reserved_60 : 16 ; 1210 UINT32 portarbitrationtablestatus : 1 ; 1211 UINT32 vcnegotiationpending : 1 ; 1212 UINT32 vc_res_status : 14 ; 1213 } Bits; 1214 1215 1216 UINT32 UInt32; 1217 1218 } PCIE_EEP_VC_CAP6_U; 1219 1220 1221 1222 1223 typedef union tagEepVcCap7 1224 { 1225 1226 struct 1227 { 1228 UINT32 portarbitrationcapability : 8 ; 1229 UINT32 Reserved_63 : 6 ; 1230 UINT32 Reserved_62 : 1 ; 1231 UINT32 rejectsnooptransactions : 1 ; 1232 UINT32 maximumtimeslots : 7 ; 1233 UINT32 Reserved_61 : 1 ; 1234 UINT32 vc_res_cap0 : 8 ; 1235 } Bits; 1236 1237 1238 UINT32 UInt32; 1239 1240 } PCIE_EEP_VC_CAP7_U; 1241 1242 1243 1244 1245 typedef union tagEepVcCap8 1246 { 1247 1248 struct 1249 { 1250 UINT32 tc_vcmap : 8 ; 1251 UINT32 Reserved_66 : 8 ; 1252 UINT32 loadportarbitrationtable : 1 ; 1253 UINT32 portarbitrationselect : 3 ; 1254 UINT32 Reserved_65 : 4 ; 1255 UINT32 vcid : 3 ; 1256 UINT32 Reserved_64 : 4 ; 1257 UINT32 vc_res_ctrl0 : 1 ; 1258 } Bits; 1259 1260 1261 UINT32 UInt32; 1262 1263 } PCIE_EEP_VC_CAP8_U; 1264 1265 1266 1267 1268 typedef union tagEepVcCap9 1269 { 1270 1271 struct 1272 { 1273 UINT32 Reserved_67 : 16 ; 1274 UINT32 arbitrationtablestatus : 1 ; 1275 UINT32 vcnegotiationpending : 1 ; 1276 UINT32 vc_res_status0 : 14 ; 1277 } Bits; 1278 1279 1280 UINT32 UInt32; 1281 1282 } PCIE_EEP_VC_CAP9_U; 1283 1284 1285 1286 1287 typedef union tagEepPortLogic0 1288 { 1289 1290 struct 1291 { 1292 UINT32 ack_lat_timer : 16 ; 1293 UINT32 replay_timer : 16 ; 1294 } Bits; 1295 1296 1297 UINT32 UInt32; 1298 1299 } PCIE_EEP_PORT_LOGIC0_U; 1300 1301 1302 1303 1304 typedef union tagEepPortLogic2 1305 { 1306 1307 struct 1308 { 1309 UINT32 linknumber : 8 ; 1310 UINT32 Reserved_70 : 7 ; 1311 UINT32 forcelink : 1 ; 1312 UINT32 linkstate : 6 ; 1313 UINT32 Reserved_69 : 2 ; 1314 UINT32 port_force_link : 8 ; 1315 } Bits; 1316 1317 1318 UINT32 UInt32; 1319 1320 } PCIE_EEP_PORT_LOGIC2_U; 1321 1322 1323 1324 1325 typedef union tagEepPortLogic3 1326 { 1327 1328 struct 1329 { 1330 UINT32 ackfrequency : 8 ; 1331 UINT32 n_fts : 8 ; 1332 UINT32 commonclockn_fts : 8 ; 1333 UINT32 l0sentrancelatency : 3 ; 1334 UINT32 l1entrancelatency : 3 ; 1335 UINT32 enteraspml1withoutreceiveinl0s : 1 ; 1336 UINT32 ack_aspm : 1 ; 1337 } Bits; 1338 1339 1340 UINT32 UInt32; 1341 1342 } PCIE_EEP_PORT_LOGIC3_U; 1343 1344 1345 1346 1347 typedef union tagEepPortLogic4 1348 { 1349 1350 struct 1351 { 1352 UINT32 vendorspecificdllprequest : 1 ; 1353 UINT32 scrambledisable : 1 ; 1354 UINT32 loopbackenable : 1 ; 1355 UINT32 resetassert : 1 ; 1356 UINT32 Reserved_73 : 1 ; 1357 UINT32 dlllinkenable : 1 ; 1358 UINT32 Reserved_72 : 1 ; 1359 UINT32 fastlinkmode : 1 ; 1360 UINT32 Reserved_71 : 8 ; 1361 UINT32 linkmodeenable : 6 ; 1362 UINT32 crosslinkenable : 1 ; 1363 UINT32 crosslinkactive : 1 ; 1364 UINT32 port_link_ctrl : 8 ; 1365 } Bits; 1366 1367 1368 UINT32 UInt32; 1369 1370 } PCIE_EEP_PORT_LOGIC4_U; 1371 1372 1373 1374 1375 typedef union tagEepPortLogic5 1376 { 1377 1378 struct 1379 { 1380 UINT32 insertlaneskewfortransmit : 24 ; 1381 UINT32 flowcontroldisable : 1 ; 1382 UINT32 ack_nakdisable : 1 ; 1383 UINT32 Reserved_74 : 5 ; 1384 UINT32 lane_skew : 1 ; 1385 } Bits; 1386 1387 1388 UINT32 UInt32; 1389 1390 } PCIE_EEP_PORT_LOGIC5_U; 1391 1392 1393 1394 1395 typedef union tagEepPortLogic6 1396 { 1397 1398 struct 1399 { 1400 UINT32 numberoftssymbols : 4 ; 1401 UINT32 Reserved_76 : 4 ; 1402 UINT32 numberofskpsymbols : 3 ; 1403 UINT32 Reserved_75 : 3 ; 1404 UINT32 timermodifierforreplaytimer : 5 ; 1405 UINT32 timermodifierforack_naklatencytimer : 5 ; 1406 UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ; 1407 UINT32 sym_num : 3 ; 1408 } Bits; 1409 1410 1411 UINT32 UInt32; 1412 1413 } PCIE_EEP_PORT_LOGIC6_U; 1414 1415 1416 1417 1418 typedef union tagEepPortLogic7 1419 { 1420 1421 struct 1422 { 1423 UINT32 vc0posteddataqueuedepth : 11 ; 1424 UINT32 Reserved_77 : 4 ; 1425 UINT32 sym_timer : 1 ; 1426 UINT32 maskfunctionmismatchfilteringfo : 1 ; 1427 UINT32 maskpoisonedtlpfiltering : 1 ; 1428 UINT32 maskbarmatchfiltering : 1 ; 1429 UINT32 masktype1configurationrequestfiltering : 1 ; 1430 UINT32 masklockedrequestfiltering : 1 ; 1431 UINT32 masktagerrorrulesforreceivedcompletions : 1 ; 1432 UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ; 1433 UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ; 1434 UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ; 1435 UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ; 1436 UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ; 1437 UINT32 maske_crcerror_filtering : 1 ; 1438 UINT32 maske_crcerror_filtering_forcompletions : 1 ; 1439 UINT32 message_control : 1 ; 1440 UINT32 maskfilteringofreceived : 1 ; 1441 UINT32 flt_mask1 : 1 ; 1442 } Bits; 1443 1444 1445 UINT32 UInt32; 1446 1447 } PCIE_EEP_PORT_LOGIC7_U; 1448 1449 1450 1451 1452 typedef union tagEepPortLogic8 1453 { 1454 1455 struct 1456 { 1457 UINT32 cx_flt_mask_venmsg0_drop : 1 ; 1458 UINT32 cx_flt_mask_venmsg1_drop : 1 ; 1459 UINT32 cx_flt_mask_dabort_4ucpl : 1 ; 1460 UINT32 cx_flt_mask_handle_flush : 1 ; 1461 UINT32 flt_mask2 : 28 ; 1462 } Bits; 1463 1464 1465 UINT32 UInt32; 1466 1467 } PCIE_EEP_PORT_LOGIC8_U; 1468 1469 1470 1471 1472 typedef union tagEepPortLogic9 1473 { 1474 1475 struct 1476 { 1477 UINT32 amba_multi_outbound_decomp_np : 1 ; 1478 UINT32 amba_obnp_ctrl : 31 ; 1479 } Bits; 1480 1481 1482 UINT32 UInt32; 1483 1484 } PCIE_EEP_PORT_LOGIC9_U; 1485 1486 1487 1488 1489 typedef union tagEepPortLogic12 1490 { 1491 1492 struct 1493 { 1494 UINT32 transmitposteddatafccredits : 12 ; 1495 UINT32 transmitpostedheaderfccredits : 8 ; 1496 UINT32 tx_pfc_status : 12 ; 1497 } Bits; 1498 1499 1500 UINT32 UInt32; 1501 1502 } PCIE_EEP_PORT_LOGIC12_U; 1503 1504 1505 1506 1507 typedef union tagEepPortLogic13 1508 { 1509 1510 struct 1511 { 1512 UINT32 transmitnon_posteddatafccredits : 12 ; 1513 UINT32 transmitnon_postedheaderfccredits : 8 ; 1514 UINT32 tx_npfc_status : 12 ; 1515 } Bits; 1516 1517 1518 UINT32 UInt32; 1519 1520 } PCIE_EEP_PORT_LOGIC13_U; 1521 1522 1523 1524 1525 typedef union tagEepPortLogic14 1526 { 1527 1528 struct 1529 { 1530 UINT32 transmitcompletiondatafccredits : 12 ; 1531 UINT32 transmitcompletionheaderfccredits : 8 ; 1532 UINT32 tx_cplfc_status : 12 ; 1533 } Bits; 1534 1535 1536 UINT32 UInt32; 1537 1538 } PCIE_EEP_PORT_LOGIC14_U; 1539 1540 1541 1542 1543 typedef union tagEepPortLogic15 1544 { 1545 1546 struct 1547 { 1548 UINT32 rx_tlp_fc_credit_not_retured : 1 ; 1549 UINT32 tx_retry_buf_not_empty : 1 ; 1550 UINT32 rx_queue_not_empty : 1 ; 1551 UINT32 Reserved_79 : 13 ; 1552 UINT32 fc_latency_timer_override_value : 13 ; 1553 UINT32 Reserved_78 : 2 ; 1554 UINT32 fc_latency_timer_override_en : 1 ; 1555 } Bits; 1556 1557 1558 UINT32 UInt32; 1559 1560 } PCIE_EEP_PORT_LOGIC15_U; 1561 1562 1563 1564 1565 typedef union tagEepPortLogic16 1566 { 1567 1568 struct 1569 { 1570 UINT32 vc0posteddatacredits : 12 ; 1571 UINT32 vc0postedheadercredits : 8 ; 1572 UINT32 Reserved_81 : 1 ; 1573 UINT32 vc0_postedtlpqueuemode : 1 ; 1574 UINT32 vc0postedtlpqueuemode : 1 ; 1575 UINT32 vc0postedtlpqueuemo : 1 ; 1576 UINT32 Reserved_80 : 6 ; 1577 UINT32 tlptypeorderingforvc0 : 1 ; 1578 UINT32 rx_pque_ctrl : 1 ; 1579 } Bits; 1580 1581 1582 UINT32 UInt32; 1583 1584 } PCIE_EEP_PORT_LOGIC16_U; 1585 1586 1587 1588 1589 typedef union tagEepPortLogic17 1590 { 1591 1592 struct 1593 { 1594 UINT32 vc0non_posteddatacredits : 12 ; 1595 UINT32 vc0non_postedheadercredits : 8 ; 1596 UINT32 rx_npque_ctrl : 12 ; 1597 } Bits; 1598 1599 1600 UINT32 UInt32; 1601 1602 } PCIE_EEP_PORT_LOGIC17_U; 1603 1604 1605 1606 1607 typedef union tagEepPortLogic18 1608 { 1609 1610 struct 1611 { 1612 UINT32 vco_comp_data_credits : 12 ; 1613 UINT32 vc0_cpl_header_credt : 8 ; 1614 UINT32 Reserved_83 : 12 ; 1615 } Bits; 1616 1617 1618 UINT32 UInt32; 1619 1620 } PCIE_EEP_PORT_LOGIC18_U; 1621 1622 1623 1624 1625 typedef union tagEepPortLogic19 1626 { 1627 1628 struct 1629 { 1630 UINT32 vco_posted_data_que_path : 14 ; 1631 UINT32 Reserved_84 : 2 ; 1632 UINT32 vco_posted_head_queue_depth : 10 ; 1633 UINT32 vc_pbuf_ctrl : 6 ; 1634 } Bits; 1635 1636 1637 UINT32 UInt32; 1638 1639 } PCIE_EEP_PORT_LOGIC19_U; 1640 1641 1642 1643 1644 typedef union tagEepPortLogic20 1645 { 1646 1647 struct 1648 { 1649 UINT32 vco_np_data_que_depth : 14 ; 1650 UINT32 Reserved_86 : 2 ; 1651 UINT32 vco_np_header_que_depth : 10 ; 1652 UINT32 vc_npbuf_ctrl : 6 ; 1653 } Bits; 1654 1655 1656 UINT32 UInt32; 1657 1658 } PCIE_EEP_PORT_LOGIC20_U; 1659 1660 1661 1662 1663 typedef union tagEepPortLogic21 1664 { 1665 1666 struct 1667 { 1668 UINT32 vco_comp_data_queue_depth : 14 ; 1669 UINT32 Reserved_88 : 2 ; 1670 UINT32 vco_posted_head_queue_depth : 10 ; 1671 UINT32 Reserved_87 : 6 ; 1672 } Bits; 1673 1674 1675 UINT32 UInt32; 1676 1677 } PCIE_EEP_PORT_LOGIC21_U; 1678 1679 1680 1681 1682 typedef union tagEepPortLogic22 1683 { 1684 1685 struct 1686 { 1687 UINT32 n_fts : 8 ; 1688 UINT32 pre_determ_num_of_lane : 9 ; 1689 UINT32 det_sp_change : 1 ; 1690 UINT32 config_phy_tx_sw : 1 ; 1691 UINT32 config_tx_comp_rcv_bit : 1 ; 1692 UINT32 set_emp_level : 1 ; 1693 UINT32 Reserved_89 : 11 ; 1694 } Bits; 1695 1696 1697 UINT32 UInt32; 1698 1699 } PCIE_EEP_PORT_LOGIC22_U; 1700 1701 1702 1703 1704 typedef union tagEepPortlogic25 1705 { 1706 1707 struct 1708 { 1709 UINT32 remote_rd_req_size : 3 ; 1710 UINT32 Reserved_92 : 5 ; 1711 UINT32 remote_max_brd_tag : 8 ; 1712 UINT32 Reserved_91 : 16 ; 1713 } Bits; 1714 1715 1716 UINT32 UInt32; 1717 1718 } PCIE_EEP_PORTLOGIC25_U; 1719 1720 1721 1722 1723 typedef union tagEepPortlogic26 1724 { 1725 1726 struct 1727 { 1728 UINT32 resize_master_resp_compser : 1 ; 1729 UINT32 axi_ctrl1 : 31 ; 1730 } Bits; 1731 1732 1733 UINT32 UInt32; 1734 1735 } PCIE_EEP_PORTLOGIC26_U; 1736 1737 1738 1739 1740 typedef union tagEepPortlogic54 1741 { 1742 1743 struct 1744 { 1745 UINT32 region_index : 4 ; 1746 UINT32 Reserved_93 : 27 ; 1747 UINT32 iatu_view : 1 ; 1748 } Bits; 1749 1750 1751 UINT32 UInt32; 1752 1753 } PCIE_EEP_PORTLOGIC54_U; 1754 1755 1756 1757 1758 typedef union tagEepPortlogic55 1759 { 1760 1761 struct 1762 { 1763 UINT32 iatu1_type : 5 ; 1764 UINT32 iatu1_tc : 3 ; 1765 UINT32 iatu1_td : 1 ; 1766 UINT32 iatu1_attr : 2 ; 1767 UINT32 Reserved_97 : 5 ; 1768 UINT32 iatu1_at : 2 ; 1769 UINT32 Reserved_96 : 2 ; 1770 UINT32 iatu1_id : 3 ; 1771 UINT32 Reserved_95 : 9 ; 1772 } Bits; 1773 1774 1775 UINT32 UInt32; 1776 1777 } PCIE_EEP_PORTLOGIC55_U; 1778 1779 1780 1781 1782 typedef union tagEepPortlogic56 1783 { 1784 1785 struct 1786 { 1787 UINT32 iatu2_type : 8 ; 1788 UINT32 iatu2_bar_num : 3 ; 1789 UINT32 Reserved_101 : 3 ; 1790 UINT32 iatu2_tc_match_en : 1 ; 1791 UINT32 iatu2_td_match_en : 1 ; 1792 UINT32 iatu2_attr_match_en : 1 ; 1793 UINT32 Reserved_100 : 1 ; 1794 UINT32 iatu2_at_match_en : 1 ; 1795 UINT32 iatu2_func_num_match_en : 1 ; 1796 UINT32 iatu2_virtual_func_num_match_en : 1 ; 1797 UINT32 message_code_match_en : 1 ; 1798 UINT32 Reserved_99 : 2 ; 1799 UINT32 iatu2_response_code : 2 ; 1800 UINT32 Reserved_98 : 1 ; 1801 UINT32 iatu2_fuzzy_type_match_mode : 1 ; 1802 UINT32 iatu2_cfg_shift_mode : 1 ; 1803 UINT32 iatu2_ivert_mode : 1 ; 1804 UINT32 iatu2_match_mode : 1 ; 1805 UINT32 iatu2_region_en : 1 ; 1806 } Bits; 1807 1808 1809 UINT32 UInt32; 1810 1811 } PCIE_EEP_PORTLOGIC56_U; 1812 1813 1814 1815 1816 typedef union tagEepPortlogic57 1817 { 1818 1819 struct 1820 { 1821 UINT32 iatu_start_low : 12 ; 1822 UINT32 iatu_start_high : 20 ; 1823 } Bits; 1824 1825 1826 UINT32 UInt32; 1827 1828 } PCIE_EEP_PORTLOGIC57_U; 1829 1830 1831 1832 1833 typedef union tagEepPortlogic59 1834 { 1835 1836 struct 1837 { 1838 UINT32 iatu_limit_low : 12 ; 1839 UINT32 iatu_limit_high : 20 ; 1840 } Bits; 1841 1842 1843 UINT32 UInt32; 1844 1845 } PCIE_EEP_PORTLOGIC59_U; 1846 1847 1848 1849 1850 typedef union tagEepPortlogic60 1851 { 1852 1853 struct 1854 { 1855 UINT32 xlated_addr_high : 12 ; 1856 UINT32 xlated_addr_low : 20 ; 1857 } Bits; 1858 1859 1860 UINT32 UInt32; 1861 1862 } PCIE_EEP_PORTLOGIC60_U; 1863 1864 1865 1866 1867 typedef union tagEepPortlogic62 1868 { 1869 1870 struct 1871 { 1872 UINT32 dma_wr_eng_en : 1 ; 1873 UINT32 dma_wr_ena : 31 ; 1874 } Bits; 1875 1876 1877 UINT32 UInt32; 1878 1879 } PCIE_EEP_PORTLOGIC62_U; 1880 1881 1882 1883 1884 typedef union tagEepPortlogic63 1885 { 1886 1887 struct 1888 { 1889 UINT32 wr_doorbell_num : 3 ; 1890 UINT32 Reserved_103 : 28 ; 1891 UINT32 dma_wr_dbell_stop : 1 ; 1892 } Bits; 1893 1894 1895 UINT32 UInt32; 1896 1897 } PCIE_EEP_PORTLOGIC63_U; 1898 1899 1900 1901 1902 typedef union tagEepPortlogic64 1903 { 1904 1905 struct 1906 { 1907 UINT32 dma_read_eng_en : 1 ; 1908 UINT32 Reserved_104 : 31 ; 1909 } Bits; 1910 1911 1912 UINT32 UInt32; 1913 1914 } PCIE_EEP_PORTLOGIC64_U; 1915 1916 1917 1918 1919 typedef union tagEepPortlogic65 1920 { 1921 1922 struct 1923 { 1924 UINT32 rd_doorbell_num : 3 ; 1925 UINT32 Reserved_106 : 28 ; 1926 UINT32 dma_rd_dbell_stop : 1 ; 1927 } Bits; 1928 1929 1930 UINT32 UInt32; 1931 1932 } PCIE_EEP_PORTLOGIC65_U; 1933 1934 1935 1936 1937 typedef union tagEepPortlogic66 1938 { 1939 1940 struct 1941 { 1942 UINT32 done_int_status : 8 ; 1943 UINT32 Reserved_108 : 8 ; 1944 UINT32 abort_int_status : 8 ; 1945 UINT32 Reserved_107 : 8 ; 1946 } Bits; 1947 1948 1949 UINT32 UInt32; 1950 1951 } PCIE_EEP_PORTLOGIC66_U; 1952 1953 1954 1955 1956 typedef union tagEepPortlogic67 1957 { 1958 1959 struct 1960 { 1961 UINT32 done_int_mask : 8 ; 1962 UINT32 Reserved_111 : 8 ; 1963 UINT32 abort_int_mask : 8 ; 1964 UINT32 Reserved_110 : 8 ; 1965 } Bits; 1966 1967 1968 UINT32 UInt32; 1969 1970 } PCIE_EEP_PORTLOGIC67_U; 1971 1972 1973 1974 1975 typedef union tagEepPortlogic68 1976 { 1977 1978 struct 1979 { 1980 UINT32 done_int_clr : 8 ; 1981 UINT32 Reserved_114 : 8 ; 1982 UINT32 abort_int_clr : 8 ; 1983 UINT32 Reserved_113 : 8 ; 1984 } Bits; 1985 1986 1987 UINT32 UInt32; 1988 1989 } PCIE_EEP_PORTLOGIC68_U; 1990 1991 1992 1993 1994 typedef union tagEepPortlogic69 1995 { 1996 1997 struct 1998 { 1999 UINT32 app_rd_err_det : 8 ; 2000 UINT32 Reserved_116 : 8 ; 2001 UINT32 ll_element_fetch_err_det : 8 ; 2002 UINT32 Reserved_115 : 8 ; 2003 } Bits; 2004 2005 2006 UINT32 UInt32; 2007 2008 } PCIE_EEP_PORTLOGIC69_U; 2009 2010 2011 2012 2013 typedef union tagEepPortlogic74 2014 { 2015 2016 struct 2017 { 2018 UINT32 dma_wr_c0_imwr_data : 16 ; 2019 UINT32 dma_wr_c1_imwr_data : 16 ; 2020 } Bits; 2021 2022 2023 UINT32 UInt32; 2024 2025 } PCIE_EEP_PORTLOGIC74_U; 2026 2027 2028 2029 2030 typedef union tagEepPortlogic75 2031 { 2032 2033 struct 2034 { 2035 UINT32 wr_ch_ll_remote_abort_int_en : 8 ; 2036 UINT32 Reserved_118 : 8 ; 2037 UINT32 wr_ch_ll_local_abort_int_en : 8 ; 2038 UINT32 Reserved_117 : 8 ; 2039 } Bits; 2040 2041 2042 UINT32 UInt32; 2043 2044 } PCIE_EEP_PORTLOGIC75_U; 2045 2046 2047 2048 2049 typedef union tagEepPortlogic76 2050 { 2051 2052 struct 2053 { 2054 UINT32 done_int_status : 8 ; 2055 UINT32 Reserved_121 : 8 ; 2056 UINT32 abort_int_status : 8 ; 2057 UINT32 Reserved_120 : 8 ; 2058 } Bits; 2059 2060 2061 UINT32 UInt32; 2062 2063 } PCIE_EEP_PORTLOGIC76_U; 2064 2065 2066 2067 2068 typedef union tagEepPortlogic77 2069 { 2070 2071 struct 2072 { 2073 UINT32 done_int_mask : 8 ; 2074 UINT32 Reserved_123 : 8 ; 2075 UINT32 abort_int_mask : 8 ; 2076 UINT32 dma_rd_int_mask : 8 ; 2077 } Bits; 2078 2079 2080 UINT32 UInt32; 2081 2082 } PCIE_EEP_PORTLOGIC77_U; 2083 2084 2085 2086 2087 typedef union tagEepPortlogic78 2088 { 2089 2090 struct 2091 { 2092 UINT32 done_int_clr : 8 ; 2093 UINT32 Reserved_125 : 8 ; 2094 UINT32 abort_int_clr : 8 ; 2095 UINT32 dma_rd_int_clr : 8 ; 2096 } Bits; 2097 2098 2099 UINT32 UInt32; 2100 2101 } PCIE_EEP_PORTLOGIC78_U; 2102 2103 2104 2105 2106 typedef union tagEepPortlogic79 2107 { 2108 2109 struct 2110 { 2111 UINT32 app_wr_err_det : 8 ; 2112 UINT32 Reserved_126 : 8 ; 2113 UINT32 link_list_fetch_err_det : 8 ; 2114 UINT32 dma_rd_err_low : 8 ; 2115 } Bits; 2116 2117 2118 UINT32 UInt32; 2119 2120 } PCIE_EEP_PORTLOGIC79_U; 2121 2122 2123 2124 2125 typedef union tagEepPortlogic80 2126 { 2127 2128 struct 2129 { 2130 UINT32 unspt_request : 8 ; 2131 UINT32 completer_abort : 8 ; 2132 UINT32 cpl_time_out : 8 ; 2133 UINT32 data_poison : 8 ; 2134 } Bits; 2135 2136 2137 UINT32 UInt32; 2138 2139 } PCIE_EEP_PORTLOGIC80_U; 2140 2141 2142 2143 2144 typedef union tagEepPortlogic81 2145 { 2146 2147 struct 2148 { 2149 UINT32 remote_abort_int_en : 8 ; 2150 UINT32 Reserved_128 : 8 ; 2151 UINT32 local_abort_int_en : 8 ; 2152 UINT32 dma_rd_ll_err_ena : 8 ; 2153 } Bits; 2154 2155 2156 UINT32 UInt32; 2157 2158 } PCIE_EEP_PORTLOGIC81_U; 2159 2160 2161 2162 2163 typedef union tagEepPortlogic86 2164 { 2165 2166 struct 2167 { 2168 UINT32 channel_dir : 3 ; 2169 UINT32 Reserved_131 : 28 ; 2170 UINT32 dma_ch_con_idx : 1 ; 2171 } Bits; 2172 2173 2174 UINT32 UInt32; 2175 2176 } PCIE_EEP_PORTLOGIC86_U; 2177 2178 2179 2180 2181 typedef union tagEepPortlogic87 2182 { 2183 2184 struct 2185 { 2186 UINT32 cycle_bit : 1 ; 2187 UINT32 toggle_cycle_bit : 1 ; 2188 UINT32 load_link_pointer : 1 ; 2189 UINT32 local_int_en : 1 ; 2190 UINT32 remote_int_en : 1 ; 2191 UINT32 channel_status : 2 ; 2192 UINT32 Reserved_135 : 1 ; 2193 UINT32 consumer_cycle_state : 1 ; 2194 UINT32 linked_list_en : 1 ; 2195 UINT32 Reserved_134 : 2 ; 2196 UINT32 func_num_dma : 5 ; 2197 UINT32 Reserved_133 : 7 ; 2198 UINT32 no_snoop : 1 ; 2199 UINT32 ro : 1 ; 2200 UINT32 td : 1 ; 2201 UINT32 tc : 3 ; 2202 UINT32 dma_ch_ctrl : 2 ; 2203 } Bits; 2204 2205 2206 UINT32 UInt32; 2207 2208 } PCIE_EEP_PORTLOGIC87_U; 2209 2210 2211 2212 2213 typedef union tagEepPortlogic93 2214 { 2215 2216 struct 2217 { 2218 UINT32 Reserved_137 : 2 ; 2219 UINT32 dma_ll_ptr_low : 30 ; 2220 } Bits; 2221 2222 2223 UINT32 UInt32; 2224 2225 } PCIE_EEP_PORTLOGIC93_U; 2226 2227 2228 2229 #define PCIE_MEEP_SBAR23XLAT_LOWER_REG (0x0) 2230 #define PCIE_MEEP_SBAR23XLAT_UPPER_REG (0x4) 2231 #define PCIE_MEEP_SBAR45XLAT_LOWER_REG (0x8) 2232 #define PCIE_MEEP_SBAR45XLAT_UPPER_REG (0xC) 2233 #define PCIE_MEEP_SBAR23LMT_LOWER_REG (0x10) 2234 #define PCIE_MEEP_SBAR23LMT_UPPER_REG (0x14) 2235 #define PCIE_MEEP_SBAR45LMT_LOWER_REG (0x18) 2236 #define PCIE_MEEP_SBAR45LMT_UPPER_REG (0x1C) 2237 #define PCIE_MEEP_SDOORBELL_REG (0x20) 2238 #define PCIE_MEEP_SDOORBELL_MASK_REG (0x24) 2239 #define PCIE_MEEP_CBDF_SBDF_REG (0x28) 2240 #define PCIE_MEEP_NTB_CNTL_REG (0x2C) 2241 #define PCIE_MEEP_PCI_CFG_HDR0_REG (0x1000) 2242 #define PCIE_MEEP_PCI_CFG_HDR1_REG (0x1004) 2243 #define PCIE_MEEP_PCI_CFG_HDR2_REG (0x1008) 2244 #define PCIE_MEEP_PCI_CFG_HDR3_REG (0x100C) 2245 #define PCIE_MEEP_PCI_CFG_HDR4_REG (0x1010) 2246 #define PCIE_MEEP_PCI_CFG_HDR5_REG (0x1014) 2247 #define PCIE_MEEP_PCI_CFG_HDR6_REG (0x1018) 2248 #define PCIE_MEEP_PCI_CFG_HDR7_REG (0x101C) 2249 #define PCIE_MEEP_PCI_CFG_HDR8_REG (0x1020) 2250 #define PCIE_MEEP_PCI_CFG_HDR9_REG (0x1024) 2251 #define PCIE_MEEP_PCI_CFG_HDR10_REG (0x1028) 2252 #define PCIE_MEEP_PCI_CFG_HDR11_REG (0x102C) 2253 #define PCIE_MEEP_PCI_CFG_HDR12_REG (0x1030) 2254 #define PCIE_MEEP_PCI_CFG_HDR13_REG (0x1034) 2255 #define PCIE_MEEP_PCI_CFG_HDR14_REG (0x1038) 2256 #define PCIE_MEEP_PCI_CFG_HDR15_REG (0x103C) 2257 #define PCIE_MEEP_PCI_PM_CAP0_REG (0x1040) 2258 #define PCIE_MEEP_PCI_PM_CAP1_REG (0x1044) 2259 #define PCIE_MEEP_PCI_MSI_CAP0_REG (0x1050) 2260 #define PCIE_MEEP_PCI_MSI_CAP1_REG (0x1054) 2261 #define PCIE_MEEP_PCI_MSI_CAP2_REG (0x1058) 2262 #define PCIE_MEEP_PCI_MSI_CAP3_REG (0x105C) 2263 #define PCIE_MEEP_PCIE_CAP0_REG (0x1070) 2264 #define PCIE_MEEP_PCIE_CAP1_REG (0x1074) 2265 #define PCIE_MEEP_PCIE_CAP2_REG (0x1078) 2266 #define PCIE_MEEP_PCIE_CAP3_REG (0x107C) 2267 #define PCIE_MEEP_PCIE_CAP4_REG (0x1080) 2268 #define PCIE_MEEP_PCIE_CAP5_REG (0x1084) 2269 #define PCIE_MEEP_PCIE_CAP6_REG (0x1088) 2270 #define PCIE_MEEP_PCIE_CAP7_REG (0x108C) 2271 #define PCIE_MEEP_PCIE_CAP8_REG (0x1090) 2272 #define PCIE_MEEP_PCIE_CAP9_REG (0x1094) 2273 #define PCIE_MEEP_PCIE_CAP10_REG (0x1098) 2274 #define PCIE_MEEP_PCIE_CAP11_REG (0x109C) 2275 #define PCIE_MEEP_PCIE_CAP12_REG (0x10A0) 2276 #define PCIE_MEEP_SLOT_CAP_REG (0x10C0) 2277 #define PCIE_MEEP_AER_CAP0_REG (0x1100) 2278 #define PCIE_MEEP_AER_CAP1_REG (0x1104) 2279 #define PCIE_MEEP_AER_CAP2_REG (0x1108) 2280 #define PCIE_MEEP_AER_CAP3_REG (0x110C) 2281 #define PCIE_MEEP_AER_CAP4_REG (0x1110) 2282 #define PCIE_MEEP_AER_CAP5_REG (0x1114) 2283 #define PCIE_MEEP_AER_CAP6_REG (0x1118) 2284 #define PCIE_MEEP_AER_CAP7_REG (0x11C) 2285 #define PCIE_MEEP_AER_CAP8_REG (0x120) 2286 #define PCIE_MEEP_AER_CAP9_REG (0x124) 2287 #define PCIE_MEEP_AER_CAP10_REG (0x128) 2288 #define PCIE_MEEP_AER_CAP11_REG (0x112C) 2289 #define PCIE_MEEP_AER_CAP12_REG (0x1130) 2290 #define PCIE_MEEP_AER_CAP13_REG (0x1134) 2291 #define PCIE_MEEP_VC_CAP0_REG (0x1140) 2292 #define PCIE_MEEP_VC_CAP1_REG (0x1144) 2293 #define PCIE_MEEP_VC_CAP2_REG (0x1148) 2294 #define PCIE_MEEP_VC_CAP3_REG (0x114C) 2295 #define PCIE_MEEP_VC_CAP4_REG (0x1150) 2296 #define PCIE_MEEP_VC_CAP5_REG (0x1154) 2297 #define PCIE_MEEP_VC_CAP6_REG (0x1158) 2298 #define PCIE_MEEP_VC_CAP7_REG (0x115C) 2299 #define PCIE_MEEP_VC_CAP8_REG (0x1160) 2300 #define PCIE_MEEP_VC_CAP9_REG (0x1164) 2301 #define PCIE_MEEP_PORT_LOGIC0_REG (0x1700) 2302 #define PCIE_MEEP_PORT_LOGIC1_REG (0x1704) 2303 #define PCIE_MEEP_PORT_LOGIC2_REG (0x1708) 2304 #define PCIE_MEEP_PORT_LOGIC3_REG (0x170C) 2305 #define PCIE_MEEP_PORT_LOGIC4_REG (0x1710) 2306 #define PCIE_MEEP_PORT_LOGIC5_REG (0x1714) 2307 #define PCIE_MEEP_PORT_LOGIC6_REG (0x1718) 2308 #define PCIE_MEEP_PORT_LOGIC7_REG (0x171C) 2309 #define PCIE_MEEP_PORT_LOGIC8_REG (0x1720) 2310 #define PCIE_MEEP_PORT_LOGIC9_REG (0x1724) 2311 #define PCIE_MEEP_PORT_LOGIC10_REG (0x1728) 2312 #define PCIE_MEEP_PORT_LOGIC11_REG (0x172C) 2313 #define PCIE_MEEP_PORT_LOGIC12_REG (0x1730) 2314 #define PCIE_MEEP_PORT_LOGIC13_REG (0x1734) 2315 #define PCIE_MEEP_PORT_LOGIC14_REG (0x1738) 2316 #define PCIE_MEEP_PORT_LOGIC15_REG (0x173C) 2317 #define PCIE_MEEP_PORT_LOGIC16_REG (0x1748) 2318 #define PCIE_MEEP_PORT_LOGIC17_REG (0x174C) 2319 #define PCIE_MEEP_PORT_LOGIC18_REG (0x1750) 2320 #define PCIE_MEEP_PORT_LOGIC19_REG (0x17A8) 2321 #define PCIE_MEEP_PORT_LOGIC20_REG (0x17AC) 2322 #define PCIE_MEEP_PORT_LOGIC21_REG (0x17B0) 2323 #define PCIE_MEEP_PORT_LOGIC22_REG (0x180C) 2324 #define PCIE_MEEP_PORTLOGIC23_REG (0x1810) 2325 #define PCIE_MEEP_PORTLOGIC24_REG (0x1814) 2326 #define PCIE_MEEP_PORTLOGIC25_REG (0x1818) 2327 #define PCIE_MEEP_PORTLOGIC26_REG (0x181C) 2328 #define PCIE_MEEP_PORTLOGIC27_REG (0x1820) 2329 #define PCIE_MEEP_PORTLOGIC28_REG (0x1824) 2330 #define PCIE_MEEP_PORTLOGIC29_REG (0x1828) 2331 #define PCIE_MEEP_PORTLOGIC30_REG (0x182C) 2332 #define PCIE_MEEP_PORTLOGIC31_REG (0x1830) 2333 #define PCIE_MEEP_PORTLOGIC32_REG (0x1834) 2334 #define PCIE_MEEP_PORTLOGIC33_REG (0x1838) 2335 #define PCIE_MEEP_PORTLOGIC34_REG (0x183C) 2336 #define PCIE_MEEP_PORTLOGIC35_REG (0x1840) 2337 #define PCIE_MEEP_PORTLOGIC36_REG (0x1844) 2338 #define PCIE_MEEP_PORTLOGIC37_REG (0x1848) 2339 #define PCIE_MEEP_PORTLOGIC38_REG (0x184C) 2340 #define PCIE_MEEP_PORTLOGIC39_REG (0x1850) 2341 #define PCIE_MEEP_PORTLOGIC40_REG (0x1854) 2342 #define PCIE_MEEP_PORTLOGIC41_REG (0x1858) 2343 #define PCIE_MEEP_PORTLOGIC42_REG (0x185C) 2344 #define PCIE_MEEP_PORTLOGIC43_REG (0x1860) 2345 #define PCIE_MEEP_PORTLOGIC44_REG (0x1864) 2346 #define PCIE_MEEP_PORTLOGIC45_REG (0x1868) 2347 #define PCIE_MEEP_PORTLOGIC46_REG (0x186C) 2348 #define PCIE_MEEP_PORTLOGIC47_REG (0x1870) 2349 #define PCIE_MEEP_PORTLOGIC48_REG (0x1874) 2350 #define PCIE_MEEP_PORTLOGIC49_REG (0x1878) 2351 #define PCIE_MEEP_PORTLOGIC50_REG (0x187C) 2352 #define PCIE_MEEP_PORTLOGIC51_REG (0x1880) 2353 #define PCIE_MEEP_PORTLOGIC52_REG (0x1884) 2354 #define PCIE_MEEP_PORTLOGIC53_REG (0x1888) 2355 #define PCIE_MEEP_PORTLOGIC54_REG (0x1900) 2356 #define PCIE_MEEP_PORTLOGIC55_REG (0x1904) 2357 #define PCIE_MEEP_PORTLOGIC56_REG (0x908) 2358 #define PCIE_MEEP_PORTLOGIC57_REG (0x190C) 2359 #define PCIE_MEEP_PORTLOGIC58_REG (0x1910) 2360 #define PCIE_MEEP_PORTLOGIC59_REG (0x1914) 2361 #define PCIE_MEEP_PORTLOGIC60_REG (0x1918) 2362 #define PCIE_MEEP_PORTLOGIC61_REG (0x191C) 2363 #define PCIE_MEEP_PORTLOGIC62_REG (0x197C) 2364 #define PCIE_MEEP_PORTLOGIC63_REG (0x1980) 2365 #define PCIE_MEEP_PORTLOGIC64_REG (0x199C) 2366 #define PCIE_MEEP_PORTLOGIC65_REG (0x19A0) 2367 #define PCIE_MEEP_PORTLOGIC66_REG (0x19BC) 2368 #define PCIE_MEEP_PORTLOGIC67_REG (0x19C4) 2369 #define PCIE_MEEP_PORTLOGIC68_REG (0x19C8) 2370 #define PCIE_MEEP_PORTLOGIC69_REG (0x19CC) 2371 #define PCIE_MEEP_PORTLOGIC70_REG (0x19D0) 2372 #define PCIE_MEEP_PORTLOGIC71_REG (0x19D4) 2373 #define PCIE_MEEP_PORTLOGIC72_REG (0x19D8) 2374 #define PCIE_MEEP_PORTLOGIC73_REG (0x19DC) 2375 #define PCIE_MEEP_PORTLOGIC74_REG (0x19E0) 2376 #define PCIE_MEEP_PORTLOGIC75_REG (0x1A00) 2377 #define PCIE_MEEP_PORTLOGIC76_REG (0x1A10) 2378 #define PCIE_MEEP_PORTLOGIC77_REG (0x1A18) 2379 #define PCIE_MEEP_PORTLOGIC78_REG (0x1A1C) 2380 #define PCIE_MEEP_PORTLOGIC79_REG (0x1A24) 2381 #define PCIE_MEEP_PORTLOGIC80_REG (0x1A28) 2382 #define PCIE_MEEP_PORTLOGIC81_REG (0x1A34) 2383 #define PCIE_MEEP_PORTLOGIC82_REG (0x1A3C) 2384 #define PCIE_MEEP_PORTLOGIC83_REG (0x1A40) 2385 #define PCIE_MEEP_PORTLOGIC84_REG (0x1A44) 2386 #define PCIE_MEEP_PORTLOGIC85_REG (0xA48) 2387 #define PCIE_MEEP_PORTLOGIC86_REG (0xA6C) 2388 #define PCIE_MEEP_PORTLOGIC87_REG (0x1A70) 2389 #define PCIE_MEEP_PORTLOGIC88_REG (0x1A78) 2390 #define PCIE_MEEP_PORTLOGIC89_REG (0x1A7C) 2391 #define PCIE_MEEP_PORTLOGIC90_REG (0x1A80) 2392 #define PCIE_MEEP_PORTLOGIC91_REG (0x1A84) 2393 #define PCIE_MEEP_PORTLOGIC92_REG (0x1A88) 2394 #define PCIE_MEEP_PORTLOGIC93_REG (0x1A8C) 2395 #define PCIE_MEEP_PORTLOGIC94_REG (0x1A90) 2396 #define PCIE_MEEP_PBAR23XLAT_LOWER_REG (0x8000) 2397 #define PCIE_MEEP_PBAR23XLAT_UPPER_REG (0x8004) 2398 #define PCIE_MEEP_PBAR45XLAT_LOWER_REG (0x8008) 2399 #define PCIE_MEEP_PBAR45XLAT_UPPER_REG (0x800C) 2400 #define PCIE_MEEP_PBAR23LMT_LOWER_REG (0x8010) 2401 #define PCIE_MEEP_PBAR23LMT_UPPER_REG (0x8014) 2402 #define PCIE_MEEP_PBAR45LMT_LOWER_REG (0x8018) 2403 #define PCIE_MEEP_PBAR45LMT_UPPER_REG (0x801C) 2404 #define PCIE_MEEP_PDOORBELL_REG (0x8020) 2405 #define PCIE_MEEP_PDOORBELL_MASK_REG (0x8024) 2406 #define PCIE_MEEP_B2B_BAR01XLAT_LOWER_REG (0x8028) 2407 #define PCIE_MEEP_B2B_BAR01XLAT_UPPER_REG (0x802C) 2408 #define PCIE_MEEP_B2B_DOORBELL_REG (0x8030) 2409 #define PCIE_MEEP_SPAD0_REG (0x8038) 2410 #define PCIE_MEEP_SPAD1_REG (0x803C) 2411 #define PCIE_MEEP_SPAD2_REG (0x8040) 2412 #define PCIE_MEEP_SPAD3_REG (0x8044) 2413 #define PCIE_MEEP_SPAD4_REG (0x8048) 2414 #define PCIE_MEEP_SPAD5_REG (0x804C) 2415 #define PCIE_MEEP_SPAD6_REG (0x8050) 2416 #define PCIE_MEEP_SPAD7_REG (0x8054) 2417 #define PCIE_MEEP_SPAD8_REG (0x8058) 2418 #define PCIE_MEEP_SPAD9_REG (0x805C) 2419 #define PCIE_MEEP_SPAD10_REG (0x8060) 2420 #define PCIE_MEEP_SPAD11_REG (0x8064) 2421 #define PCIE_MEEP_SPAD12_REG (0x8068) 2422 #define PCIE_MEEP_SPAD13_REG (0x806C) 2423 #define PCIE_MEEP_SPAD14_REG (0x8070) 2424 #define PCIE_MEEP_SPAD15_REG (0x8074) 2425 #define PCIE_MEEP_SPAD16_REG (0x8078) 2426 #define PCIE_MEEP_SPAD17_REG (0x807C) 2427 #define PCIE_MEEP_SPAD18_REG (0x8080) 2428 #define PCIE_MEEP_SPAD19_REG (0x8084) 2429 #define PCIE_MEEP_SPAD20_REG (0x8088) 2430 #define PCIE_MEEP_SPAD21_REG (0x808C) 2431 #define PCIE_MEEP_SPAD22_REG (0x8090) 2432 #define PCIE_MEEP_SPAD23_REG (0x8094) 2433 #define PCIE_MEEP_SPAD24_REG (0x8098) 2434 #define PCIE_MEEP_SPAD25_REG (0x809C) 2435 #define PCIE_MEEP_SPAD26_REG (0x80A0) 2436 #define PCIE_MEEP_SPAD27_REG (0x80A4) 2437 #define PCIE_MEEP_SPAD28_REG (0x80A8) 2438 #define PCIE_MEEP_SPAD29_REG (0x80AC) 2439 #define PCIE_MEEP_SPAD30_REG (0x80B0) 2440 #define PCIE_MEEP_SPAD31_REG (0x80B4) 2441 #define PCIE_MEEP_PPD_REG (0x8138) 2442 #define PCIE_MEEP_DEVICE_VENDOR_ID_REG (0x9000) 2443 #define PCIE_MEEP_PCISTS_PCICMD_REG (0x9004) 2444 #define PCIE_MEEP_CCR_RID_REG (0x9008) 2445 #define PCIE_MEEP_PBAR01_BASE_LOWER_REG (0x9010) 2446 #define PCIE_MEEP_PBAR01_BASE_UPPER_REG (0x9014) 2447 #define PCIE_MEEP_PBAR23_BASE_LOWER_REG (0x9018) 2448 #define PCIE_MEEP_PBAR23_BASE_UPPER_REG (0x901C) 2449 #define PCIE_MEEP_PBAR45_BASE_LOWER_REG (0x9020) 2450 #define PCIE_MEEP_PBAR45_BASE_UPPER_REG (0x9024) 2451 #define PCIE_MEEP_CARDBUSCISPTR_REG (0x9028) 2452 #define PCIE_MEEP_SUBSYSTEMID_REG (0x902C) 2453 #define PCIE_MEEP_EXPANSIONROM_BASE_ADDR_REG (0x9030) 2454 #define PCIE_MEEP_CAPPTR_REG (0x9034) 2455 #define PCIE_MEEP_INTERRUPT_REG (0x903C) 2456 #define PCIE_MEEP_MSI_CAPABILITY_REGISTER_REG (0x9050) 2457 #define PCIE_MEEP_MSI_LOWER32_BITADDRESS_REG (0x9054) 2458 #define PCIE_MEEP_MSI_UPPER32_BIT_ADDRESS_REG (0x9058) 2459 #define PCIE_MEEP_MSI_DATA_REG (0x905C) 2460 #define PCIE_MEEP_MSI_MASK_REG (0x9060) 2461 #define PCIE_MEEP_MSI_PENDING_REG (0x9064) 2462 #define PCIE_MEEP_PCIE_CAPABILITY_REGISTER_REG (0x9070) 2463 #define PCIE_MEEP_DEVICE_CAPABILITIES_REGISTER_REG (0x9074) 2464 #define PCIE_MEEP_DEVICE_STATUS_REGISTER_REG (0x9078) 2465 #define PCIE_MEEP_LINK_CAPABILITY_REG (0x907C) 2466 #define PCIE_MEEP_LINK_CONTROL_STATUS_REG (0x9080) 2467 #define PCIE_MEEP_AER_CAP_HEADER_REG (0x9100) 2468 #define PCIE_MEEP_UC_ERROR_STATUS_REG (0x9104) 2469 #define PCIE_MEEP_UC_ERROR_MASK_REG (0x9108) 2470 #define PCIE_MEEP_UC_ERROR_SEVERITY_REG (0x910C) 2471 #define PCIE_MEEP_C_ERROR_STATUS_REG (0x9110) 2472 #define PCIE_MEEP_C_ERROR_MASK_REG (0x9114) 2473 #define PCIE_MEEP_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_REG (0x9118) 2474 #define PCIE_MEEP_HEADER_LOG_REGISTERS_1_REG (0x911C) 2475 #define PCIE_MEEP_HEADER_LOG_REGISTERS_2_REG (0x9120) 2476 #define PCIE_MEEP_HEADER_LOG_REGISTERS_3_REG (0x9124) 2477 #define PCIE_MEEP_HEADER_LOG_REGISTERS_4_REG (0x9128) 2478 #define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_1_REG (0x9130) 2479 #define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_2_REG (0x9134) 2480 #define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_3_REG (0x9138) 2481 #define PCIE_MEEP_TLP_PREFIX_LOGREGISTERS_4_REG (0x913C) 2482 #define PCIE_MEEP_NTB_IEP_CONFIG_SPACE_LOWER_REG (0x9700) 2483 #define PCIE_MEEP_NTB_IEP_CONFIG_SPACE_UPPER_REG (0x9704) 2484 #define PCIE_MEEP_NTB_IEP_BAR01_CTRL_REG (0x9708) 2485 #define PCIE_MEEP_NTB_IEP_BAR23_CTRL_REG (0x970C) 2486 #define PCIE_MEEP_NTB_IEP_BAR45_CTRL_REG (0x9710) 2487 #define PCIE_MEEP_MSI_CTRL_ADDRESS_LOWER_REG (0x9714) 2488 #define PCIE_MEEP_MSI_CTRL_ADDRESS_UPPER_REG (0x9718) 2489 #define PCIE_MEEP_MSI_CTRL_INT_EN_REG (0x971C) 2490 #define PCIE_MEEP_MSI_CTRL_INT0_MASK_REG (0x9720) 2491 #define PCIE_MEEP_MSI_CTRL_INT_STATUS_REG (0x9724) 2492 #define PCIE_MEEP_DBI_RO_WR_EN_REG (0x9728) 2493 #define PCIE_MEEP_AXI_ERR_RESPONSE_REG (0x972C) 2494 2495 2496 2497 typedef union tagMeepSbar23xlatLower 2498 { 2499 2500 struct 2501 { 2502 UINT32 Reserved_0 : 12 ; 2503 UINT32 sbar23xlat_lower : 20 ; 2504 } Bits; 2505 2506 2507 UINT32 UInt32; 2508 2509 } PCIE_MEEP_SBAR23XLAT_LOWER_U; 2510 2511 2512 2513 2514 typedef union tagMeepSbar45xlatLower 2515 { 2516 2517 struct 2518 { 2519 UINT32 Reserved_1 : 12 ; 2520 UINT32 sbar45xlat_lower : 20 ; 2521 } Bits; 2522 2523 2524 UINT32 UInt32; 2525 2526 } PCIE_MEEP_SBAR45XLAT_LOWER_U; 2527 2528 2529 2530 2531 typedef union tagMeepSbar23lmtLower 2532 { 2533 2534 struct 2535 { 2536 UINT32 Reserved_2 : 12 ; 2537 UINT32 sbar45limit_lower : 20 ; 2538 } Bits; 2539 2540 2541 UINT32 UInt32; 2542 2543 } PCIE_MEEP_SBAR23LMT_LOWER_U; 2544 2545 2546 2547 2548 typedef union tagMeepSbar45lmtLower 2549 { 2550 2551 struct 2552 { 2553 UINT32 Reserved_3 : 12 ; 2554 UINT32 sbar45limit_lower : 20 ; 2555 } Bits; 2556 2557 2558 UINT32 UInt32; 2559 2560 } PCIE_MEEP_SBAR45LMT_LOWER_U; 2561 2562 2563 2564 2565 typedef union tagMeepSbar45lmtUpper 2566 { 2567 2568 struct 2569 { 2570 UINT32 Reserved_4 : 12 ; 2571 UINT32 sbar45limit_upper : 20 ; 2572 } Bits; 2573 2574 2575 UINT32 UInt32; 2576 2577 } PCIE_MEEP_SBAR45LMT_UPPER_U; 2578 2579 2580 2581 2582 typedef union tagMeepCbdfSbdf 2583 { 2584 2585 struct 2586 { 2587 UINT32 sfunc : 3 ; 2588 UINT32 sdev : 5 ; 2589 UINT32 sbus : 8 ; 2590 UINT32 cap_sfunc : 3 ; 2591 UINT32 cap_sdev : 5 ; 2592 UINT32 cap_sbus : 8 ; 2593 } Bits; 2594 2595 2596 UINT32 UInt32; 2597 2598 } PCIE_MEEP_CBDF_SBDF_U; 2599 2600 2601 2602 2603 typedef union tagMeepNtbCntl 2604 { 2605 2606 struct 2607 { 2608 UINT32 s_link_disable : 1 ; 2609 UINT32 Reserved_6 : 1 ; 2610 UINT32 eep_shadow_en : 1 ; 2611 UINT32 Reserved_5 : 29 ; 2612 } Bits; 2613 2614 2615 UINT32 UInt32; 2616 2617 } PCIE_MEEP_NTB_CNTL_U; 2618 2619 2620 2621 2622 typedef union tagMeepPciCfgHdr0 2623 { 2624 2625 struct 2626 { 2627 UINT32 vendor_id : 16 ; 2628 UINT32 device_id : 16 ; 2629 } Bits; 2630 2631 2632 UINT32 UInt32; 2633 2634 } PCIE_MEEP_PCI_CFG_HDR0_U; 2635 2636 2637 2638 2639 typedef union tagMeepPciCfgHdr1 2640 { 2641 2642 struct 2643 { 2644 UINT32 io_space_enable : 1 ; 2645 UINT32 memory_space_enable : 1 ; 2646 UINT32 bus_master_enable : 1 ; 2647 UINT32 specialcycleenable : 1 ; 2648 UINT32 memory_write_and_invalidate : 1 ; 2649 UINT32 vga_palette_snoop_enable : 1 ; 2650 UINT32 parity_error_response : 1 ; 2651 UINT32 idsel_stepping_waitcycle_control : 1 ; 2652 UINT32 serr_enable : 1 ; 2653 UINT32 fastback_to_backenable : 1 ; 2654 UINT32 interrupt_disable : 1 ; 2655 UINT32 Reserved_10 : 5 ; 2656 UINT32 Reserved_9 : 3 ; 2657 UINT32 intx_status : 1 ; 2658 UINT32 capabilitieslist : 1 ; 2659 UINT32 pcibus66mhzcapable : 1 ; 2660 UINT32 Reserved_8 : 1 ; 2661 UINT32 fastback_to_back : 1 ; 2662 UINT32 masterdataparityerror : 1 ; 2663 UINT32 devsel_timing : 2 ; 2664 UINT32 signaled_target_abort : 1 ; 2665 UINT32 received_target_abort : 1 ; 2666 UINT32 received_master_abort : 1 ; 2667 UINT32 signaled_system_error : 1 ; 2668 UINT32 detected_parity_error : 1 ; 2669 } Bits; 2670 2671 2672 UINT32 UInt32; 2673 2674 } PCIE_MEEP_PCI_CFG_HDR1_U; 2675 2676 2677 2678 2679 typedef union tagMeepPciCfgHdr2 2680 { 2681 2682 struct 2683 { 2684 UINT32 revision_identification : 8 ; 2685 UINT32 Reserved_11 : 8 ; 2686 UINT32 sub_class : 8 ; 2687 UINT32 baseclass : 8 ; 2688 } Bits; 2689 2690 2691 UINT32 UInt32; 2692 2693 } PCIE_MEEP_PCI_CFG_HDR2_U; 2694 2695 2696 2697 2698 typedef union tagMeepPciCfgHdr3 2699 { 2700 2701 struct 2702 { 2703 UINT32 cache_line_size : 8 ; 2704 UINT32 mstr_lat_tmr : 8 ; 2705 UINT32 multi_function_device : 7 ; 2706 UINT32 hdr_type : 1 ; 2707 UINT32 bist : 8 ; 2708 } Bits; 2709 2710 2711 UINT32 UInt32; 2712 2713 } PCIE_MEEP_PCI_CFG_HDR3_U; 2714 2715 2716 2717 2718 typedef union tagMeepPciCfgHdr4 2719 { 2720 2721 struct 2722 { 2723 UINT32 sbar01_space_inicator : 1 ; 2724 UINT32 sbar01_type : 2 ; 2725 UINT32 sbar01_prefetchable : 1 ; 2726 UINT32 sbar01_lower : 28 ; 2727 } Bits; 2728 2729 2730 UINT32 UInt32; 2731 2732 } PCIE_MEEP_PCI_CFG_HDR4_U; 2733 2734 2735 2736 2737 typedef union tagMeepPciCfgHdr6 2738 { 2739 2740 struct 2741 { 2742 UINT32 sbar23_space_inicator : 1 ; 2743 UINT32 sbar23_type : 2 ; 2744 UINT32 sbar23_prefetchable : 1 ; 2745 UINT32 Reserved_12 : 8 ; 2746 UINT32 sbar23_lower : 20 ; 2747 } Bits; 2748 2749 2750 UINT32 UInt32; 2751 2752 } PCIE_MEEP_PCI_CFG_HDR6_U; 2753 2754 2755 2756 2757 typedef union tagMeepPciCfgHdr8 2758 { 2759 2760 struct 2761 { 2762 UINT32 sbar45_space_inicator : 1 ; 2763 UINT32 sbar45_type : 2 ; 2764 UINT32 sbar45_prefetchable : 1 ; 2765 UINT32 Reserved_13 : 8 ; 2766 UINT32 sbar45_lower : 20 ; 2767 } Bits; 2768 2769 2770 UINT32 UInt32; 2771 2772 } PCIE_MEEP_PCI_CFG_HDR8_U; 2773 2774 2775 2776 2777 typedef union tagMeepPciCfgHdr11 2778 { 2779 2780 struct 2781 { 2782 UINT32 subsystem_vendor_id : 16 ; 2783 UINT32 subsystemid : 16 ; 2784 } Bits; 2785 2786 2787 UINT32 UInt32; 2788 2789 } PCIE_MEEP_PCI_CFG_HDR11_U; 2790 2791 2792 2793 2794 typedef union tagMeepPciCfgHdr13 2795 { 2796 2797 struct 2798 { 2799 UINT32 cap_ptr : 8 ; 2800 UINT32 Reserved_14 : 24 ; 2801 } Bits; 2802 2803 2804 UINT32 UInt32; 2805 2806 } PCIE_MEEP_PCI_CFG_HDR13_U; 2807 2808 2809 2810 2811 typedef union tagMeepPciCfgHdr15 2812 { 2813 2814 struct 2815 { 2816 UINT32 int_line : 8 ; 2817 UINT32 int_pin : 8 ; 2818 UINT32 Min_Grant : 8 ; 2819 UINT32 Max_Latency : 8 ; 2820 } Bits; 2821 2822 2823 UINT32 UInt32; 2824 2825 } PCIE_MEEP_PCI_CFG_HDR15_U; 2826 2827 2828 2829 2830 typedef union tagMeepPciMsiCap0 2831 { 2832 2833 struct 2834 { 2835 UINT32 msi_cap_id : 8 ; 2836 UINT32 next_capability_pointer : 8 ; 2837 UINT32 msi_enabled : 1 ; 2838 UINT32 multiple_message_capable : 3 ; 2839 UINT32 multiple_message_enabled : 3 ; 2840 UINT32 msi_64_en : 1 ; 2841 UINT32 pvm : 1 ; 2842 UINT32 Reserved_18 : 7 ; 2843 } Bits; 2844 2845 2846 UINT32 UInt32; 2847 2848 } PCIE_MEEP_PCI_MSI_CAP0_U; 2849 2850 2851 2852 2853 typedef union tagMeepPciMsiCap1 2854 { 2855 2856 struct 2857 { 2858 UINT32 Reserved_20 : 2 ; 2859 UINT32 msi_addr_low : 30 ; 2860 } Bits; 2861 2862 2863 UINT32 UInt32; 2864 2865 } PCIE_MEEP_PCI_MSI_CAP1_U; 2866 2867 2868 2869 2870 typedef union tagMeepPciMsiCap3 2871 { 2872 2873 struct 2874 { 2875 UINT32 msi_data : 16 ; 2876 UINT32 Reserved_21 : 16 ; 2877 } Bits; 2878 2879 2880 UINT32 UInt32; 2881 2882 } PCIE_MEEP_PCI_MSI_CAP3_U; 2883 2884 2885 2886 2887 typedef union tagMeepPcieCap0 2888 { 2889 2890 struct 2891 { 2892 UINT32 pcie_cap_id : 8 ; 2893 UINT32 pcie_next_ptr : 8 ; 2894 UINT32 pcie_capability_version : 4 ; 2895 UINT32 device_port_type : 4 ; 2896 UINT32 slot_implemented : 1 ; 2897 UINT32 interrupt_message_number : 5 ; 2898 UINT32 Reserved_22 : 2 ; 2899 } Bits; 2900 2901 2902 UINT32 UInt32; 2903 2904 } PCIE_MEEP_PCIE_CAP0_U; 2905 2906 2907 2908 2909 typedef union tagMeepPcieCap1 2910 { 2911 2912 struct 2913 { 2914 UINT32 max_payload_size_supported : 3 ; 2915 UINT32 phantom_function_supported : 2 ; 2916 UINT32 extended_tagfield_supported : 1 ; 2917 UINT32 endpoint_l0sacceptable_latency : 3 ; 2918 UINT32 endpoint_l1acceptable_latency : 3 ; 2919 UINT32 undefined : 3 ; 2920 UINT32 Reserved_24 : 3 ; 2921 UINT32 captured_slot_power_limit_value : 8 ; 2922 UINT32 captured_slot_power_limit_scale : 2 ; 2923 UINT32 function_level_reset : 1 ; 2924 UINT32 dev_cap : 3 ; 2925 } Bits; 2926 2927 2928 UINT32 UInt32; 2929 2930 } PCIE_MEEP_PCIE_CAP1_U; 2931 2932 2933 2934 2935 typedef union tagMeepPcieCap2 2936 { 2937 2938 struct 2939 { 2940 UINT32 correctable_error_reporting_enable : 1 ; 2941 UINT32 non_fatal_error_reporting_enable : 1 ; 2942 UINT32 fatal_error_reporting_enable : 1 ; 2943 UINT32 urenable : 1 ; 2944 UINT32 enable_relaxed_ordering : 1 ; 2945 UINT32 max_payload_size : 3 ; 2946 UINT32 extended_tagfieldenable : 1 ; 2947 UINT32 phantom_function_enable : 1 ; 2948 UINT32 auxpowerpmenable : 1 ; 2949 UINT32 enablenosnoop : 1 ; 2950 UINT32 max_read_request_size : 3 ; 2951 UINT32 Reserved_26 : 1 ; 2952 UINT32 correctableerrordetected : 1 ; 2953 UINT32 non_fatalerrordetected : 1 ; 2954 UINT32 fatalerrordetected : 1 ; 2955 UINT32 unsupportedrequestdetected : 1 ; 2956 UINT32 auxpowerdetected : 1 ; 2957 UINT32 transactionpending : 1 ; 2958 UINT32 Reserved_25 : 10 ; 2959 } Bits; 2960 2961 2962 UINT32 UInt32; 2963 2964 } PCIE_MEEP_PCIE_CAP2_U; 2965 2966 2967 2968 2969 typedef union tagMeepPcieCap3 2970 { 2971 2972 struct 2973 { 2974 UINT32 max_link_speed : 4 ; 2975 UINT32 max_link_width : 6 ; 2976 UINT32 active_state_power_management : 2 ; 2977 UINT32 l0s_exitlatency : 3 ; 2978 UINT32 l1_exit_latency : 3 ; 2979 UINT32 clock_power_management : 1 ; 2980 UINT32 surprise_down_error_report_cap : 1 ; 2981 UINT32 data_link_layer_active_report_cap : 1 ; 2982 UINT32 link_bandwidth_noti_cap : 1 ; 2983 UINT32 aspm_option_compliance : 1 ; 2984 UINT32 Reserved_27 : 1 ; 2985 UINT32 port_number : 8 ; 2986 } Bits; 2987 2988 2989 UINT32 UInt32; 2990 2991 } PCIE_MEEP_PCIE_CAP3_U; 2992 2993 2994 2995 2996 typedef union tagMeepPcieCap4 2997 { 2998 2999 struct 3000 { 3001 UINT32 active_state_power_management : 2 ; 3002 UINT32 Reserved_30 : 1 ; 3003 UINT32 rcb : 1 ; 3004 UINT32 link_disable : 1 ; 3005 UINT32 retrain_link : 1 ; 3006 UINT32 common_clock_config : 1 ; 3007 UINT32 extended_sync : 1 ; 3008 UINT32 enable_clock_pwr_management : 1 ; 3009 UINT32 hw_auto_width_disable : 1 ; 3010 UINT32 link_bandwidth_management_int_en : 1 ; 3011 UINT32 link_auto_bandwidth_int_en : 1 ; 3012 UINT32 Reserved_29 : 4 ; 3013 UINT32 current_link_speed : 4 ; 3014 UINT32 negotiated_link_width : 6 ; 3015 UINT32 Reserved_28 : 1 ; 3016 UINT32 link_training : 1 ; 3017 UINT32 slot_clock_configration : 1 ; 3018 UINT32 data_link_layer_active : 1 ; 3019 UINT32 link_bandwidth_management_status : 1 ; 3020 UINT32 link_auto_bandwidth_status : 1 ; 3021 } Bits; 3022 3023 3024 UINT32 UInt32; 3025 3026 } PCIE_MEEP_PCIE_CAP4_U; 3027 3028 3029 3030 3031 typedef union tagMeepPcieCap5 3032 { 3033 3034 struct 3035 { 3036 UINT32 attentionbuttonpresent : 1 ; 3037 UINT32 powercontrollerpresent : 1 ; 3038 UINT32 mrlsensorpresent : 1 ; 3039 UINT32 attentionindicatorpresent : 1 ; 3040 UINT32 powerindicatorpresent : 1 ; 3041 UINT32 hot_plugsurprise : 1 ; 3042 UINT32 hot_plugcapable : 1 ; 3043 UINT32 slotpowerlimitvalue : 8 ; 3044 UINT32 slotpowerlimitscale : 2 ; 3045 UINT32 electromechanicalinterlockpresen : 1 ; 3046 UINT32 no_cmd_complete_support : 1 ; 3047 UINT32 phy_slot_number : 13 ; 3048 } Bits; 3049 3050 3051 UINT32 UInt32; 3052 3053 } PCIE_MEEP_PCIE_CAP5_U; 3054 3055 3056 3057 3058 typedef union tagMeepPcieCap6 3059 { 3060 3061 struct 3062 { 3063 UINT32 attentionbuttonpressedenable : 1 ; 3064 UINT32 powerfaultdetectedenable : 1 ; 3065 UINT32 mrlsensorchangedenable : 1 ; 3066 UINT32 presencedetectchangedenable : 1 ; 3067 UINT32 commandcompletedinterruptenable : 1 ; 3068 UINT32 hot_pluginterruptenable : 1 ; 3069 UINT32 attentionindicatorcontrol : 2 ; 3070 UINT32 powerindicatorcontrol : 2 ; 3071 UINT32 powercontrollercontrol : 1 ; 3072 UINT32 electromechanicalinterlockcontrol : 1 ; 3073 UINT32 datalinklayerstatechangedenable : 1 ; 3074 UINT32 Reserved_31 : 3 ; 3075 UINT32 attentionbuttonpressed : 1 ; 3076 UINT32 powerfaultdetected : 1 ; 3077 UINT32 mrlsensorchanged : 1 ; 3078 UINT32 presencedetectchanged : 1 ; 3079 UINT32 commandcompleted : 1 ; 3080 UINT32 mrlsensorstate : 1 ; 3081 UINT32 presencedetectstate : 1 ; 3082 UINT32 electromechanicalinterlockstatus : 1 ; 3083 UINT32 datalinklayerstatechanged : 1 ; 3084 UINT32 slot_ctrl_status : 7 ; 3085 } Bits; 3086 3087 3088 UINT32 UInt32; 3089 3090 } PCIE_MEEP_PCIE_CAP6_U; 3091 3092 3093 3094 3095 typedef union tagMeepPcieCap7 3096 { 3097 3098 struct 3099 { 3100 UINT32 systemerroroncorrectableerrorenable : 1 ; 3101 UINT32 systemerroronnon_fatalerrorenable : 1 ; 3102 UINT32 systemerroronfatalerrorenable : 1 ; 3103 UINT32 pmeinterruptenable : 1 ; 3104 UINT32 crssoftwarevisibilityenable : 1 ; 3105 UINT32 Reserved_32 : 11 ; 3106 UINT32 crssoftwarevisibility : 1 ; 3107 UINT32 root_cap : 15 ; 3108 } Bits; 3109 3110 3111 UINT32 UInt32; 3112 3113 } PCIE_MEEP_PCIE_CAP7_U; 3114 3115 3116 3117 3118 typedef union tagMeepPcieCap8 3119 { 3120 3121 struct 3122 { 3123 UINT32 pmerequesterid : 16 ; 3124 UINT32 pmestatus : 1 ; 3125 UINT32 pmepending : 1 ; 3126 UINT32 root_status : 14 ; 3127 } Bits; 3128 3129 3130 UINT32 UInt32; 3131 3132 } PCIE_MEEP_PCIE_CAP8_U; 3133 3134 3135 3136 3137 typedef union tagMeepPcieCap9 3138 { 3139 3140 struct 3141 { 3142 UINT32 completiontimeoutrangessupported : 4 ; 3143 UINT32 completiontimeoutdisablesupported : 1 ; 3144 UINT32 ariforwardingsupported : 1 ; 3145 UINT32 atomicoproutingsupported : 1 ; 3146 UINT32 _2_bitatomicopcompletersupported : 1 ; 3147 UINT32 _4_bitatomicopcompletersupported : 1 ; 3148 UINT32 _28_bitcascompletersupported : 1 ; 3149 UINT32 noro_enabledpr_prpassing : 1 ; 3150 UINT32 Reserved_33 : 1 ; 3151 UINT32 tphcompletersupported : 2 ; 3152 UINT32 dev_cap2 : 18 ; 3153 } Bits; 3154 3155 3156 UINT32 UInt32; 3157 3158 } PCIE_MEEP_PCIE_CAP9_U; 3159 3160 3161 3162 3163 typedef union tagMeepPcieCap10 3164 { 3165 3166 struct 3167 { 3168 UINT32 completiontimeoutvalue : 4 ; 3169 UINT32 completiontimeoutdisable : 1 ; 3170 UINT32 ariforwardingsupported : 1 ; 3171 UINT32 atomicoprequesterenable : 1 ; 3172 UINT32 atomicopegressblocking : 1 ; 3173 UINT32 idorequestenable : 1 ; 3174 UINT32 idocompletionenable : 1 ; 3175 UINT32 dev_ctrl2 : 22 ; 3176 } Bits; 3177 3178 3179 UINT32 UInt32; 3180 3181 } PCIE_MEEP_PCIE_CAP10_U; 3182 3183 3184 3185 3186 typedef union tagMeepPcieCap11 3187 { 3188 3189 struct 3190 { 3191 UINT32 Reserved_35 : 1 ; 3192 UINT32 gen1_suport : 1 ; 3193 UINT32 gen2_suport : 1 ; 3194 UINT32 gen3_suport : 1 ; 3195 UINT32 Reserved_34 : 4 ; 3196 UINT32 crosslink_supported : 1 ; 3197 UINT32 link_cap2 : 23 ; 3198 } Bits; 3199 3200 3201 UINT32 UInt32; 3202 3203 } PCIE_MEEP_PCIE_CAP11_U; 3204 3205 3206 3207 3208 typedef union tagMeepPcieCap12 3209 { 3210 3211 struct 3212 { 3213 UINT32 targetlinkspeed : 4 ; 3214 UINT32 entercompliance : 1 ; 3215 UINT32 hardwareautonomousspeeddisa : 1 ; 3216 UINT32 selectablede_empha : 1 ; 3217 UINT32 transmitmargin : 3 ; 3218 UINT32 _entermodifiedcompliance : 1 ; 3219 UINT32 compliancesos : 1 ; 3220 UINT32 de_emphasislevel : 4 ; 3221 UINT32 currentde_emphasislevel : 1 ; 3222 UINT32 equalizationcomplete : 1 ; 3223 UINT32 equalizationphase1successful : 1 ; 3224 UINT32 equalizationphase2successful : 1 ; 3225 UINT32 equalizationphase3successful : 1 ; 3226 UINT32 linkequalizationrequest : 1 ; 3227 UINT32 link_ctrl2_status2 : 10 ; 3228 } Bits; 3229 3230 3231 UINT32 UInt32; 3232 3233 } PCIE_MEEP_PCIE_CAP12_U; 3234 3235 3236 3237 3238 typedef union tagMeepSlotCap 3239 { 3240 3241 struct 3242 { 3243 UINT32 slotnumberingcapabilitiesid : 8 ; 3244 UINT32 nextcapabilitypointer : 8 ; 3245 UINT32 add_incardslotsprovided : 5 ; 3246 UINT32 firstinchassis : 1 ; 3247 UINT32 Reserved_36 : 2 ; 3248 UINT32 slot_cap : 8 ; 3249 } Bits; 3250 3251 3252 UINT32 UInt32; 3253 3254 } PCIE_MEEP_SLOT_CAP_U; 3255 3256 3257 3258 3259 typedef union tagMeepAerCap0 3260 { 3261 3262 struct 3263 { 3264 UINT32 pciexpressextendedcapabilityid : 16 ; 3265 UINT32 capabilityversion : 4 ; 3266 UINT32 aer_cap_hdr : 12 ; 3267 } Bits; 3268 3269 3270 UINT32 UInt32; 3271 3272 } PCIE_MEEP_AER_CAP0_U; 3273 3274 3275 3276 3277 typedef union tagMeepAerCap1 3278 { 3279 3280 struct 3281 { 3282 UINT32 Reserved_42 : 1 ; 3283 UINT32 Reserved_41 : 3 ; 3284 UINT32 datalinkprotocolerrorsta : 1 ; 3285 UINT32 surprisedownerrorstatus : 1 ; 3286 UINT32 Reserved_40 : 6 ; 3287 UINT32 poisonedtlpstatu : 1 ; 3288 UINT32 flowcontrolprotocolerrorst : 1 ; 3289 UINT32 completiontimeouts : 1 ; 3290 UINT32 completerabortstatus : 1 ; 3291 UINT32 receiveroverflowstatus : 1 ; 3292 UINT32 malformedtlpstatus : 1 ; 3293 UINT32 ecrcerrorstatus : 1 ; 3294 UINT32 ecrcerrorstat : 1 ; 3295 UINT32 unsupportedrequesterrorstatus : 1 ; 3296 UINT32 Reserved_39 : 3 ; 3297 UINT32 atomicopegressblockedstatus : 1 ; 3298 UINT32 uncorr_err_status : 7 ; 3299 } Bits; 3300 3301 3302 UINT32 UInt32; 3303 3304 } PCIE_MEEP_AER_CAP1_U; 3305 3306 3307 3308 3309 typedef union tagMeepAerCap2 3310 { 3311 3312 struct 3313 { 3314 UINT32 Reserved_46 : 1 ; 3315 UINT32 Reserved_45 : 3 ; 3316 UINT32 datalinkprotocolerrormask : 1 ; 3317 UINT32 surprisedownerrormask : 1 ; 3318 UINT32 Reserved_44 : 6 ; 3319 UINT32 poisonedtlpmask : 1 ; 3320 UINT32 flowcontrolprotocolerrormask : 1 ; 3321 UINT32 completiontimeoutmask : 1 ; 3322 UINT32 completerabortmask : 1 ; 3323 UINT32 unexpectedcompletionmask : 1 ; 3324 UINT32 receiveroverflowmask : 1 ; 3325 UINT32 malformedtlpmask : 1 ; 3326 UINT32 ecrcerrormask : 1 ; 3327 UINT32 unsupportedrequesterrormask : 1 ; 3328 UINT32 Reserved_43 : 3 ; 3329 UINT32 atomicopegressblockedmask : 1 ; 3330 UINT32 uncorr_err_mask : 7 ; 3331 } Bits; 3332 3333 3334 UINT32 UInt32; 3335 3336 } PCIE_MEEP_AER_CAP2_U; 3337 3338 3339 3340 3341 typedef union tagMeepAerCap3 3342 { 3343 3344 struct 3345 { 3346 UINT32 Reserved_50 : 1 ; 3347 UINT32 Reserved_49 : 3 ; 3348 UINT32 datalinkprotocolerrorsever : 1 ; 3349 UINT32 surprisedownerrorseverity : 1 ; 3350 UINT32 Reserved_48 : 6 ; 3351 UINT32 poisonedtlpseverity : 1 ; 3352 UINT32 flowcontrolprotocolerrorseveri : 1 ; 3353 UINT32 completiontimeoutseverity : 1 ; 3354 UINT32 completerabortseverity : 1 ; 3355 UINT32 unexpectedcompletionseverity : 1 ; 3356 UINT32 receiveroverflowseverity : 1 ; 3357 UINT32 malformedtlpseverity : 1 ; 3358 UINT32 ecrcerrorseverity : 1 ; 3359 UINT32 unsupportedrequesterrorseverity : 1 ; 3360 UINT32 Reserved_47 : 3 ; 3361 UINT32 atomicopegressblockedseverity : 1 ; 3362 UINT32 uncorr_err_ser : 7 ; 3363 } Bits; 3364 3365 3366 UINT32 UInt32; 3367 3368 } PCIE_MEEP_AER_CAP3_U; 3369 3370 3371 3372 3373 typedef union tagMeepAerCap4 3374 { 3375 3376 struct 3377 { 3378 UINT32 receivererrorstatus : 1 ; 3379 UINT32 Reserved_52 : 5 ; 3380 UINT32 badtlpstatus : 1 ; 3381 UINT32 baddllpstatus : 1 ; 3382 UINT32 replay_numrolloverstatus : 1 ; 3383 UINT32 Reserved_51 : 3 ; 3384 UINT32 replytimertimeoutstatus : 1 ; 3385 UINT32 advisorynon_fatalerrorstatus : 1 ; 3386 UINT32 corr_err_status : 18 ; 3387 } Bits; 3388 3389 3390 UINT32 UInt32; 3391 3392 } PCIE_MEEP_AER_CAP4_U; 3393 3394 3395 3396 3397 typedef union tagMeepAerCap5 3398 { 3399 3400 struct 3401 { 3402 UINT32 receivererrormask : 1 ; 3403 UINT32 Reserved_54 : 5 ; 3404 UINT32 badtlpmask : 1 ; 3405 UINT32 baddllpmask : 1 ; 3406 UINT32 replay_numrollovermask : 1 ; 3407 UINT32 Reserved_53 : 3 ; 3408 UINT32 replytimertimeoutmask : 1 ; 3409 UINT32 advisorynon_fatalerrormask : 1 ; 3410 UINT32 corr_err_mask : 18 ; 3411 } Bits; 3412 3413 3414 UINT32 UInt32; 3415 3416 } PCIE_MEEP_AER_CAP5_U; 3417 3418 3419 3420 3421 typedef union tagMeepAerCap6 3422 { 3423 3424 struct 3425 { 3426 UINT32 firsterrorpointer : 5 ; 3427 UINT32 ecrcgenerationcapability : 1 ; 3428 UINT32 ecrcgenerationenable : 1 ; 3429 UINT32 ecrccheckcapable : 1 ; 3430 UINT32 ecrccheckenable : 1 ; 3431 UINT32 adv_cap_ctrl : 23 ; 3432 } Bits; 3433 3434 3435 UINT32 UInt32; 3436 3437 } PCIE_MEEP_AER_CAP6_U; 3438 3439 3440 3441 3442 typedef union tagMeepAerCap11 3443 { 3444 3445 struct 3446 { 3447 UINT32 correctableerrorreportingenable : 1 ; 3448 UINT32 non_fatalerrorreportingenable : 1 ; 3449 UINT32 fatalerrorreportingenable : 1 ; 3450 UINT32 root_err_cmd : 29 ; 3451 } Bits; 3452 3453 3454 UINT32 UInt32; 3455 3456 } PCIE_MEEP_AER_CAP11_U; 3457 3458 3459 3460 3461 typedef union tagMeepAerCap12 3462 { 3463 3464 struct 3465 { 3466 UINT32 err_correceived : 1 ; 3467 UINT32 multipleerr_correceived : 1 ; 3468 UINT32 err_fatal_nonfatalreceived : 1 ; 3469 UINT32 multipleerr_fatal_nonfatalreceived : 1 ; 3470 UINT32 firstuncorrectablefatal : 1 ; 3471 UINT32 non_fatalerrormessagesreceived : 1 ; 3472 UINT32 fatalerrormessagesreceived : 1 ; 3473 UINT32 Reserved_57 : 20 ; 3474 UINT32 root_err_status : 5 ; 3475 } Bits; 3476 3477 3478 UINT32 UInt32; 3479 3480 } PCIE_MEEP_AER_CAP12_U; 3481 3482 3483 3484 3485 typedef union tagMeepAerCap13 3486 { 3487 3488 struct 3489 { 3490 UINT32 err_corsourceidentification : 16 ; 3491 UINT32 err_src_id : 16 ; 3492 } Bits; 3493 3494 3495 UINT32 UInt32; 3496 3497 } PCIE_MEEP_AER_CAP13_U; 3498 3499 3500 3501 3502 typedef union tagMeepVcCap0 3503 { 3504 3505 struct 3506 { 3507 UINT32 pciexpressextendedcapabilityid : 16 ; 3508 UINT32 capabilityversion : 4 ; 3509 UINT32 vc_cap_hdr : 12 ; 3510 } Bits; 3511 3512 3513 UINT32 UInt32; 3514 3515 } PCIE_MEEP_VC_CAP0_U; 3516 3517 3518 3519 3520 typedef union tagMeepVcCap1 3521 { 3522 3523 struct 3524 { 3525 UINT32 extendedvccount : 3 ; 3526 UINT32 Reserved_60 : 1 ; 3527 UINT32 lowpriorityextendedvccount : 3 ; 3528 UINT32 Reserved_59 : 1 ; 3529 UINT32 referenceclock : 2 ; 3530 UINT32 portarbitrationtableentrysize : 2 ; 3531 UINT32 vc_cap1 : 20 ; 3532 } Bits; 3533 3534 3535 UINT32 UInt32; 3536 3537 } PCIE_MEEP_VC_CAP1_U; 3538 3539 3540 3541 3542 typedef union tagMeepVcCap2 3543 { 3544 3545 struct 3546 { 3547 UINT32 vcarbitrationcapability : 8 ; 3548 UINT32 Reserved_61 : 16 ; 3549 UINT32 vc_cap2 : 8 ; 3550 } Bits; 3551 3552 3553 UINT32 UInt32; 3554 3555 } PCIE_MEEP_VC_CAP2_U; 3556 3557 3558 3559 3560 typedef union tagMeepVcCap3 3561 { 3562 3563 struct 3564 { 3565 UINT32 loadvcarbitrationtable : 1 ; 3566 UINT32 vcarbitrationselect : 3 ; 3567 UINT32 Reserved_63 : 12 ; 3568 UINT32 arbitrationtablestatus : 1 ; 3569 UINT32 Reserved_62 : 15 ; 3570 } Bits; 3571 3572 3573 UINT32 UInt32; 3574 3575 } PCIE_MEEP_VC_CAP3_U; 3576 3577 3578 3579 3580 typedef union tagMeepVcCap4 3581 { 3582 3583 struct 3584 { 3585 UINT32 portarbitrationcapability : 8 ; 3586 UINT32 Reserved_66 : 6 ; 3587 UINT32 Reserved_65 : 1 ; 3588 UINT32 rejectsnooptransactions : 1 ; 3589 UINT32 maximumtimeslots : 7 ; 3590 UINT32 Reserved_64 : 1 ; 3591 UINT32 vc_res_cap : 8 ; 3592 } Bits; 3593 3594 3595 UINT32 UInt32; 3596 3597 } PCIE_MEEP_VC_CAP4_U; 3598 3599 3600 3601 3602 typedef union tagMeepVcCap5 3603 { 3604 3605 struct 3606 { 3607 UINT32 tc_vcmap : 8 ; 3608 UINT32 Reserved_69 : 8 ; 3609 UINT32 loadportarbitrationtable : 1 ; 3610 UINT32 portarbitrationselec : 3 ; 3611 UINT32 Reserved_68 : 4 ; 3612 UINT32 vcid : 3 ; 3613 UINT32 Reserved_67 : 4 ; 3614 UINT32 vc_res_ctrl : 1 ; 3615 } Bits; 3616 3617 3618 UINT32 UInt32; 3619 3620 } PCIE_MEEP_VC_CAP5_U; 3621 3622 3623 3624 3625 typedef union tagMeepVcCap6 3626 { 3627 3628 struct 3629 { 3630 UINT32 Reserved_70 : 16 ; 3631 UINT32 portarbitrationtablestatus : 1 ; 3632 UINT32 vcnegotiationpending : 1 ; 3633 UINT32 vc_res_status : 14 ; 3634 } Bits; 3635 3636 3637 UINT32 UInt32; 3638 3639 } PCIE_MEEP_VC_CAP6_U; 3640 3641 3642 3643 3644 typedef union tagMeepVcCap7 3645 { 3646 3647 struct 3648 { 3649 UINT32 portarbitrationcapability : 8 ; 3650 UINT32 Reserved_73 : 6 ; 3651 UINT32 Reserved_72 : 1 ; 3652 UINT32 rejectsnooptransactions : 1 ; 3653 UINT32 maximumtimeslots : 7 ; 3654 UINT32 Reserved_71 : 1 ; 3655 UINT32 vc_res_cap0 : 8 ; 3656 } Bits; 3657 3658 3659 UINT32 UInt32; 3660 3661 } PCIE_MEEP_VC_CAP7_U; 3662 3663 3664 3665 3666 typedef union tagMeepVcCap8 3667 { 3668 3669 struct 3670 { 3671 UINT32 tc_vcmap : 8 ; 3672 UINT32 Reserved_76 : 8 ; 3673 UINT32 loadportarbitrationtable : 1 ; 3674 UINT32 portarbitrationselect : 3 ; 3675 UINT32 Reserved_75 : 4 ; 3676 UINT32 vcid : 3 ; 3677 UINT32 Reserved_74 : 4 ; 3678 UINT32 vc_res_ctrl0 : 1 ; 3679 } Bits; 3680 3681 3682 UINT32 UInt32; 3683 3684 } PCIE_MEEP_VC_CAP8_U; 3685 3686 3687 3688 3689 typedef union tagMeepVcCap9 3690 { 3691 3692 struct 3693 { 3694 UINT32 Reserved_77 : 16 ; 3695 UINT32 arbitrationtablestatus : 1 ; 3696 UINT32 vcnegotiationpending : 1 ; 3697 UINT32 vc_res_status0 : 14 ; 3698 } Bits; 3699 3700 3701 UINT32 UInt32; 3702 3703 } PCIE_MEEP_VC_CAP9_U; 3704 3705 3706 3707 3708 typedef union tagMeepPortLogic0 3709 { 3710 3711 struct 3712 { 3713 UINT32 ack_lat_timer : 16 ; 3714 UINT32 replay_timer : 16 ; 3715 } Bits; 3716 3717 3718 UINT32 UInt32; 3719 3720 } PCIE_MEEP_PORT_LOGIC0_U; 3721 3722 3723 3724 3725 typedef union tagMeepPortLogic2 3726 { 3727 3728 struct 3729 { 3730 UINT32 linknumber : 8 ; 3731 UINT32 Reserved_80 : 7 ; 3732 UINT32 forcelink : 1 ; 3733 UINT32 linkstate : 6 ; 3734 UINT32 Reserved_79 : 2 ; 3735 UINT32 port_force_link : 8 ; 3736 } Bits; 3737 3738 3739 UINT32 UInt32; 3740 3741 } PCIE_MEEP_PORT_LOGIC2_U; 3742 3743 3744 3745 3746 typedef union tagMeepPortLogic3 3747 { 3748 3749 struct 3750 { 3751 UINT32 ackfrequency : 8 ; 3752 UINT32 n_fts : 8 ; 3753 UINT32 commonclockn_fts : 8 ; 3754 UINT32 l0sentrancelatency : 3 ; 3755 UINT32 l1entrancelatency : 3 ; 3756 UINT32 enteraspml1withoutreceiveinl0s : 1 ; 3757 UINT32 ack_aspm : 1 ; 3758 } Bits; 3759 3760 3761 UINT32 UInt32; 3762 3763 } PCIE_MEEP_PORT_LOGIC3_U; 3764 3765 3766 3767 3768 typedef union tagMeepPortLogic4 3769 { 3770 3771 struct 3772 { 3773 UINT32 vendorspecificdllprequest : 1 ; 3774 UINT32 scrambledisable : 1 ; 3775 UINT32 loopbackenable : 1 ; 3776 UINT32 resetassert : 1 ; 3777 UINT32 Reserved_83 : 1 ; 3778 UINT32 dlllinkenable : 1 ; 3779 UINT32 Reserved_82 : 1 ; 3780 UINT32 fastlinkmode : 1 ; 3781 UINT32 Reserved_81 : 8 ; 3782 UINT32 linkmodeenable : 6 ; 3783 UINT32 crosslinkenable : 1 ; 3784 UINT32 crosslinkactive : 1 ; 3785 UINT32 port_link_ctrl : 8 ; 3786 } Bits; 3787 3788 3789 UINT32 UInt32; 3790 3791 } PCIE_MEEP_PORT_LOGIC4_U; 3792 3793 3794 3795 3796 typedef union tagMeepPortLogic5 3797 { 3798 3799 struct 3800 { 3801 UINT32 insertlaneskewfortransmit : 24 ; 3802 UINT32 flowcontroldisable : 1 ; 3803 UINT32 ack_nakdisable : 1 ; 3804 UINT32 Reserved_84 : 5 ; 3805 UINT32 lane_skew : 1 ; 3806 } Bits; 3807 3808 3809 UINT32 UInt32; 3810 3811 } PCIE_MEEP_PORT_LOGIC5_U; 3812 3813 3814 3815 3816 typedef union tagMeepPortLogic6 3817 { 3818 3819 struct 3820 { 3821 UINT32 numberoftssymbols : 4 ; 3822 UINT32 Reserved_86 : 4 ; 3823 UINT32 numberofskpsymbols : 3 ; 3824 UINT32 Reserved_85 : 3 ; 3825 UINT32 timermodifierforreplaytimer : 5 ; 3826 UINT32 timermodifierforack_naklatencytimer : 5 ; 3827 UINT32 timermodifierforflowcontrolwatchdogtimer : 5 ; 3828 UINT32 sym_num : 3 ; 3829 } Bits; 3830 3831 3832 UINT32 UInt32; 3833 3834 } PCIE_MEEP_PORT_LOGIC6_U; 3835 3836 3837 3838 3839 typedef union tagMeepPortLogic7 3840 { 3841 3842 struct 3843 { 3844 UINT32 vc0posteddataqueuedepth : 11 ; 3845 UINT32 Reserved_87 : 4 ; 3846 UINT32 sym_timer : 1 ; 3847 UINT32 maskfunctionmismatchfilteringfo : 1 ; 3848 UINT32 maskpoisonedtlpfiltering : 1 ; 3849 UINT32 maskbarmatchfiltering : 1 ; 3850 UINT32 masktype1configurationrequestfiltering : 1 ; 3851 UINT32 masklockedrequestfiltering : 1 ; 3852 UINT32 masktagerrorrulesforreceivedcompletions : 1 ; 3853 UINT32 maskrequesteridmismatcherrorforreceivedcompletions : 1 ; 3854 UINT32 maskfunctionmismatcherrorforreceivedcompletions : 1 ; 3855 UINT32 mask_traffic_classmis_match_error_forreceived_completions : 1 ; 3856 UINT32 mask_attributesmismatcherrorforreceivedcompletions : 1 ; 3857 UINT32 mask_length_mismatch_error_forreceive_dcompletions : 1 ; 3858 UINT32 maske_crcerror_filtering : 1 ; 3859 UINT32 maske_crcerror_filtering_forcompletions : 1 ; 3860 UINT32 message_control : 1 ; 3861 UINT32 maskfilteringofreceived : 1 ; 3862 UINT32 flt_mask1 : 1 ; 3863 } Bits; 3864 3865 3866 UINT32 UInt32; 3867 3868 } PCIE_MEEP_PORT_LOGIC7_U; 3869 3870 3871 3872 3873 typedef union tagMeepPortLogic8 3874 { 3875 3876 struct 3877 { 3878 UINT32 cx_flt_mask_venmsg0_drop : 1 ; 3879 UINT32 cx_flt_mask_venmsg1_drop : 1 ; 3880 UINT32 cx_flt_mask_dabort_4ucpl : 1 ; 3881 UINT32 cx_flt_mask_handle_flush : 1 ; 3882 UINT32 flt_mask2 : 28 ; 3883 } Bits; 3884 3885 3886 UINT32 UInt32; 3887 3888 } PCIE_MEEP_PORT_LOGIC8_U; 3889 3890 3891 3892 3893 typedef union tagMeepPortLogic9 3894 { 3895 3896 struct 3897 { 3898 UINT32 amba_multi_outbound_decomp_np : 1 ; 3899 UINT32 amba_obnp_ctrl : 31 ; 3900 } Bits; 3901 3902 3903 UINT32 UInt32; 3904 3905 } PCIE_MEEP_PORT_LOGIC9_U; 3906 3907 3908 3909 3910 typedef union tagMeepPortLogic12 3911 { 3912 3913 struct 3914 { 3915 UINT32 transmitposteddatafccredits : 12 ; 3916 UINT32 transmitpostedheaderfccredits : 8 ; 3917 UINT32 tx_pfc_status : 12 ; 3918 } Bits; 3919 3920 3921 UINT32