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    Searched refs:drmCommandWriteRead (Results 1 - 25 of 42) sorted by null

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  /external/libdrm/amdgpu/
amdgpu_vm.c 36 return drmCommandWriteRead(dev->fd, DRM_AMDGPU_VM,
47 return drmCommandWriteRead(dev->fd, DRM_AMDGPU_VM,
amdgpu_bo.c 82 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
115 return drmCommandWriteRead(bo->dev->fd,
136 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_METADATA,
150 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_OP,
453 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_MMAP, &args,
521 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_WAIT_IDLE,
546 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_USERPTR,
607 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
629 r = drmCommandWriteRead(list->dev->fd, DRM_AMDGPU_BO_LIST,
673 r = drmCommandWriteRead(handle->dev->fd, DRM_AMDGPU_BO_LIST
    [all...]
amdgpu_cs.c 77 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
125 r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
156 r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
312 r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS,
722 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
765 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_FENCE_TO_HANDLE,
  /external/mesa3d/src/loader/
pci_id_driver_map.c 38 ret = drmCommandWriteRead(fd, DRM_NOUVEAU_GETPARAM, &gp, sizeof(gp));
  /external/libdrm/freedreno/msm/
msm_bo.c 44 ret = drmCommandWriteRead(bo->dev->fd, DRM_MSM_GEM_INFO,
100 ret = drmCommandWriteRead(bo->dev->fd, DRM_MSM_GEM_MADVISE, &req, sizeof(req));
114 drmCommandWriteRead(bo->dev->fd, DRM_MSM_GEM_INFO, &req, sizeof(req));
145 ret = drmCommandWriteRead(dev->fd, DRM_MSM_GEM_NEW,
msm_pipe.c 41 ret = drmCommandWriteRead(pipe->dev->fd, DRM_MSM_GET_PARAM,
117 ret = drmCommandWriteRead(pipe->dev->fd, DRM_MSM_SUBMITQUEUE_NEW,
  /external/libdrm/libkms/
intel.c 108 ret = drmCommandWriteRead(kms->fd, DRM_I915_GEM_CREATE, &arg, sizeof(arg));
126 ret = drmCommandWriteRead(kms->fd, DRM_I915_GEM_SET_TILING, &tile, sizeof(tile));
168 ret = drmCommandWriteRead(bo->base.kms->fd, DRM_I915_GEM_MMAP_GTT, &arg, sizeof(arg));
radeon.c 117 ret = drmCommandWriteRead(kms->fd, DRM_RADEON_GEM_CREATE,
166 ret = drmCommandWriteRead(bo->base.kms->fd, DRM_RADEON_GEM_MMAP,
exynos.c 108 ret = drmCommandWriteRead(kms->fd, DRM_EXYNOS_GEM_CREATE, &arg, sizeof(arg));
nouveau.c 114 ret = drmCommandWriteRead(kms->fd, DRM_NOUVEAU_GEM_NEW, &arg, sizeof(arg));
vmwgfx.c 101 ret = drmCommandWriteRead(bo->base.kms->fd,
  /external/libdrm/tests/radeon/
rbo.c 72 r = drmCommandWriteRead(fd, DRM_RADEON_GEM_CREATE,
108 r = drmCommandWriteRead(bo->fd, DRM_RADEON_GEM_MMAP,
167 ret = drmCommandWriteRead(bo->fd, DRM_RADEON_GEM_WAIT_IDLE,
  /external/libdrm/radeon/
radeon_bo_gem.c 105 r = drmCommandWriteRead(bom->fd, DRM_RADEON_GEM_CREATE,
169 r = drmCommandWriteRead(boi->bom->fd,
225 ret = drmCommandWriteRead(boi->bom->fd, DRM_RADEON_GEM_BUSY,
242 r = drmCommandWriteRead(boi->bom->fd,
257 r = drmCommandWriteRead(boi->bom->fd,
354 r = drmCommandWriteRead(boi->bom->fd,
  /external/libdrm/tegra/
tegra.c 127 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_CREATE, &args,
255 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_MMAP, &args,
304 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_GET_FLAGS, &args,
328 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_SET_FLAGS, &args,
349 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_GET_TILING, &args,
377 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_SET_TILING, &args,
  /external/libdrm/freedreno/kgsl/
kgsl_bo.c 57 ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_ALLOC,
144 ret = drmCommandWriteRead(dev->fd, DRM_KGSL_GEM_CREATE,
237 ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_GET_BUFINFO,
301 ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_GET_BUFINFO,
  /external/mesa3d/src/gallium/winsys/svga/drm/
vmw_screen_ioctl.c 106 ret = drmCommandWriteRead(vws->ioctl.drm_fd,
182 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_SURFACE,
249 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_CREATE,
371 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_REF,
532 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_ALLOC_DMABUF, &arg,
723 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_FENCE_SIGNALED,
752 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_FENCE_WAIT,
788 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_SHADER,
900 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
909 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM
    [all...]
  /external/libdrm/nouveau/
abi16.c 45 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
66 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
92 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
158 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_NOTIFIEROBJ_ALLOC,
354 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_GEM_NEW,
  /external/libdrm/etnaviv/
etnaviv_perfmon.c 42 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_PM_QUERY_SIG, &req, sizeof(req));
74 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_PM_QUERY_DOM, &req, sizeof(req));
etnaviv_gpu.c 38 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_GET_PARAM, &req, sizeof(req));
etnaviv_bo.c 121 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_GEM_NEW,
149 ret = drmCommandWriteRead(bo->dev->fd, DRM_ETNAVIV_GEM_INFO,
  /external/minigbm/
vc4.c 69 ret = drmCommandWriteRead(bo->drv->fd, DRM_VC4_MMAP_BO, &bo_map, sizeof(bo_map));
tegra.c 248 ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_SET_TILING, &gem_tile,
307 ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_MMAP, &gem_map, sizeof(gem_map));
  /external/libdrm/omap/
omap_drm.c 139 ret = drmCommandWriteRead(dev->fd, DRM_OMAP_GET_PARAM, &req, sizeof(req));
206 if (drmCommandWriteRead(dev->fd, DRM_OMAP_GEM_NEW, &req, sizeof(req))) {
270 int ret = drmCommandWriteRead(bo->dev->fd, DRM_OMAP_GEM_INFO,
  /external/mesa3d/src/gallium/winsys/radeon/drm/
radeon_drm_bo.c 68 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
189 if (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_OP,
362 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_VA, &va,
436 if (drmCommandWriteRead(bo->rws->fd,
624 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
668 r = drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va));
848 drmCommandWriteRead(bo->rws->fd,
909 drmCommandWriteRead(bo->rws->fd,
    [all...]
radeon_drm_winsys.c 81 if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
113 retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
338 drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
343 retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,

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