1 /* 2 * Copyright 2009 Corbin Simpson 3 * Copyright 2011 Marek Olk <maraeo (at) gmail.com> 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining 7 * a copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 */ 27 28 #include "radeon_drm_bo.h" 29 #include "radeon_drm_cs.h" 30 #include "radeon_drm_public.h" 31 32 #include "util/u_memory.h" 33 #include "util/u_hash_table.h" 34 35 #include <xf86drm.h> 36 #include <stdio.h> 37 #include <sys/types.h> 38 #include <sys/stat.h> 39 #include <unistd.h> 40 #include <fcntl.h> 41 #include <radeon_surface.h> 42 43 static struct util_hash_table *fd_tab = NULL; 44 static mtx_t fd_tab_mutex = _MTX_INITIALIZER_NP; 45 46 /* Enable/disable feature access for one command stream. 47 * If enable == true, return true on success. 48 * Otherwise, return false. 49 * 50 * We basically do the same thing kernel does, because we have to deal 51 * with multiple contexts (here command streams) backed by one winsys. */ 52 static bool radeon_set_fd_access(struct radeon_drm_cs *applier, 53 struct radeon_drm_cs **owner, 54 mtx_t *mutex, 55 unsigned request, const char *request_name, 56 bool enable) 57 { 58 struct drm_radeon_info info; 59 unsigned value = enable ? 1 : 0; 60 61 memset(&info, 0, sizeof(info)); 62 63 mtx_lock(&*mutex); 64 65 /* Early exit if we are sure the request will fail. */ 66 if (enable) { 67 if (*owner) { 68 mtx_unlock(&*mutex); 69 return false; 70 } 71 } else { 72 if (*owner != applier) { 73 mtx_unlock(&*mutex); 74 return false; 75 } 76 } 77 78 /* Pass through the request to the kernel. */ 79 info.value = (unsigned long)&value; 80 info.request = request; 81 if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO, 82 &info, sizeof(info)) != 0) { 83 mtx_unlock(&*mutex); 84 return false; 85 } 86 87 /* Update the rights in the winsys. */ 88 if (enable) { 89 if (value) { 90 *owner = applier; 91 mtx_unlock(&*mutex); 92 return true; 93 } 94 } else { 95 *owner = NULL; 96 } 97 98 mtx_unlock(&*mutex); 99 return false; 100 } 101 102 static bool radeon_get_drm_value(int fd, unsigned request, 103 const char *errname, uint32_t *out) 104 { 105 struct drm_radeon_info info; 106 int retval; 107 108 memset(&info, 0, sizeof(info)); 109 110 info.value = (unsigned long)out; 111 info.request = request; 112 113 retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info)); 114 if (retval) { 115 if (errname) { 116 fprintf(stderr, "radeon: Failed to get %s, error number %d\n", 117 errname, retval); 118 } 119 return false; 120 } 121 return true; 122 } 123 124 /* Helper function to do the ioctls needed for setup and init. */ 125 static bool do_winsys_init(struct radeon_drm_winsys *ws) 126 { 127 struct drm_radeon_gem_info gem_info; 128 int retval; 129 drmVersionPtr version; 130 131 memset(&gem_info, 0, sizeof(gem_info)); 132 133 /* We do things in a specific order here. 134 * 135 * DRM version first. We need to be sure we're running on a KMS chipset. 136 * This is also for some features. 137 * 138 * Then, the PCI ID. This is essential and should return usable numbers 139 * for all Radeons. If this fails, we probably got handed an FD for some 140 * non-Radeon card. 141 * 142 * The GEM info is actually bogus on the kernel side, as well as our side 143 * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because 144 * we don't actually use the info for anything yet. 145 * 146 * The GB and Z pipe requests should always succeed, but they might not 147 * return sensical values for all chipsets, but that's alright because 148 * the pipe drivers already know that. 149 */ 150 151 /* Get DRM version. */ 152 version = drmGetVersion(ws->fd); 153 if (version->version_major != 2 || 154 version->version_minor < 12) { 155 fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is " 156 "only compatible with 2.12.0 (kernel 3.2) or later.\n", 157 __FUNCTION__, 158 version->version_major, 159 version->version_minor, 160 version->version_patchlevel); 161 drmFreeVersion(version); 162 return false; 163 } 164 165 ws->info.drm_major = version->version_major; 166 ws->info.drm_minor = version->version_minor; 167 ws->info.drm_patchlevel = version->version_patchlevel; 168 drmFreeVersion(version); 169 170 /* Get PCI ID. */ 171 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID", 172 &ws->info.pci_id)) 173 return false; 174 175 /* Check PCI ID. */ 176 switch (ws->info.pci_id) { 177 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break; 178 #include "pci_ids/r300_pci_ids.h" 179 #undef CHIPSET 180 181 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break; 182 #include "pci_ids/r600_pci_ids.h" 183 #undef CHIPSET 184 185 #define CHIPSET(pci_id, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break; 186 #include "pci_ids/radeonsi_pci_ids.h" 187 #undef CHIPSET 188 189 default: 190 fprintf(stderr, "radeon: Invalid PCI ID.\n"); 191 return false; 192 } 193 194 switch (ws->info.family) { 195 default: 196 case CHIP_UNKNOWN: 197 fprintf(stderr, "radeon: Unknown family.\n"); 198 return false; 199 case CHIP_R300: 200 case CHIP_R350: 201 case CHIP_RV350: 202 case CHIP_RV370: 203 case CHIP_RV380: 204 case CHIP_RS400: 205 case CHIP_RC410: 206 case CHIP_RS480: 207 ws->info.chip_class = R300; 208 break; 209 case CHIP_R420: /* R4xx-based cores. */ 210 case CHIP_R423: 211 case CHIP_R430: 212 case CHIP_R480: 213 case CHIP_R481: 214 case CHIP_RV410: 215 case CHIP_RS600: 216 case CHIP_RS690: 217 case CHIP_RS740: 218 ws->info.chip_class = R400; 219 break; 220 case CHIP_RV515: /* R5xx-based cores. */ 221 case CHIP_R520: 222 case CHIP_RV530: 223 case CHIP_R580: 224 case CHIP_RV560: 225 case CHIP_RV570: 226 ws->info.chip_class = R500; 227 break; 228 case CHIP_R600: 229 case CHIP_RV610: 230 case CHIP_RV630: 231 case CHIP_RV670: 232 case CHIP_RV620: 233 case CHIP_RV635: 234 case CHIP_RS780: 235 case CHIP_RS880: 236 ws->info.chip_class = R600; 237 break; 238 case CHIP_RV770: 239 case CHIP_RV730: 240 case CHIP_RV710: 241 case CHIP_RV740: 242 ws->info.chip_class = R700; 243 break; 244 case CHIP_CEDAR: 245 case CHIP_REDWOOD: 246 case CHIP_JUNIPER: 247 case CHIP_CYPRESS: 248 case CHIP_HEMLOCK: 249 case CHIP_PALM: 250 case CHIP_SUMO: 251 case CHIP_SUMO2: 252 case CHIP_BARTS: 253 case CHIP_TURKS: 254 case CHIP_CAICOS: 255 ws->info.chip_class = EVERGREEN; 256 break; 257 case CHIP_CAYMAN: 258 case CHIP_ARUBA: 259 ws->info.chip_class = CAYMAN; 260 break; 261 case CHIP_TAHITI: 262 case CHIP_PITCAIRN: 263 case CHIP_VERDE: 264 case CHIP_OLAND: 265 case CHIP_HAINAN: 266 ws->info.chip_class = SI; 267 break; 268 case CHIP_BONAIRE: 269 case CHIP_KAVERI: 270 case CHIP_KABINI: 271 case CHIP_HAWAII: 272 case CHIP_MULLINS: 273 ws->info.chip_class = CIK; 274 break; 275 } 276 277 /* Set which chips don't have dedicated VRAM. */ 278 switch (ws->info.family) { 279 case CHIP_RS400: 280 case CHIP_RC410: 281 case CHIP_RS480: 282 case CHIP_RS600: 283 case CHIP_RS690: 284 case CHIP_RS740: 285 case CHIP_RS780: 286 case CHIP_RS880: 287 case CHIP_PALM: 288 case CHIP_SUMO: 289 case CHIP_SUMO2: 290 case CHIP_ARUBA: 291 case CHIP_KAVERI: 292 case CHIP_KABINI: 293 case CHIP_MULLINS: 294 ws->info.has_dedicated_vram = false; 295 break; 296 297 default: 298 ws->info.has_dedicated_vram = true; 299 } 300 301 /* Check for dma */ 302 ws->info.num_sdma_rings = 0; 303 /* DMA is disabled on R700. There is IB corruption and hangs. */ 304 if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) { 305 ws->info.num_sdma_rings = 1; 306 } 307 308 /* Check for UVD and VCE */ 309 ws->info.has_hw_decode = false; 310 ws->info.vce_fw_version = 0x00000000; 311 if (ws->info.drm_minor >= 32) { 312 uint32_t value = RADEON_CS_RING_UVD; 313 if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING, 314 "UVD Ring working", &value)) 315 ws->info.has_hw_decode = value; 316 317 value = RADEON_CS_RING_VCE; 318 if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING, 319 NULL, &value) && value) { 320 321 if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION, 322 "VCE FW version", &value)) 323 ws->info.vce_fw_version = value; 324 } 325 } 326 327 /* Check for userptr support. */ 328 { 329 struct drm_radeon_gem_userptr args = {0}; 330 331 /* If the ioctl doesn't exist, -EINVAL is returned. 332 * 333 * If the ioctl exists, it should return -EACCES 334 * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER 335 * aren't set. 336 */ 337 ws->info.has_userptr = 338 drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR, 339 &args, sizeof(args)) == -EACCES; 340 } 341 342 /* Get GEM info. */ 343 retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO, 344 &gem_info, sizeof(gem_info)); 345 if (retval) { 346 fprintf(stderr, "radeon: Failed to get MM info, error number %d\n", 347 retval); 348 return false; 349 } 350 ws->info.gart_size = gem_info.gart_size; 351 ws->info.vram_size = gem_info.vram_size; 352 ws->info.vram_vis_size = gem_info.vram_visible; 353 /* Older versions of the kernel driver reported incorrect values, and 354 * didn't support more than 256MB of visible VRAM anyway 355 */ 356 if (ws->info.drm_minor < 49) 357 ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size, 256*1024*1024); 358 359 /* Radeon allocates all buffers as contigous, which makes large allocations 360 * unlikely to succeed. */ 361 ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.7; 362 if (ws->info.has_dedicated_vram) 363 ws->info.max_alloc_size = MIN2(ws->info.vram_size * 0.7, ws->info.max_alloc_size); 364 if (ws->info.drm_minor < 40) 365 ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024); 366 367 /* Get max clock frequency info and convert it to MHz */ 368 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL, 369 &ws->info.max_shader_clock); 370 ws->info.max_shader_clock /= 1000; 371 372 ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN); 373 374 /* Generation-specific queries. */ 375 if (ws->gen == DRV_R300) { 376 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES, 377 "GB pipe count", 378 &ws->info.r300_num_gb_pipes)) 379 return false; 380 381 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES, 382 "Z pipe count", 383 &ws->info.r300_num_z_pipes)) 384 return false; 385 } 386 else if (ws->gen >= DRV_R600) { 387 uint32_t tiling_config = 0; 388 389 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS, 390 "num backends", 391 &ws->info.num_render_backends)) 392 return false; 393 394 /* get the GPU counter frequency, failure is not fatal */ 395 radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL, 396 &ws->info.clock_crystal_freq); 397 398 radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL, 399 &tiling_config); 400 401 ws->info.r600_num_banks = 402 ws->info.chip_class >= EVERGREEN ? 403 4 << ((tiling_config & 0xf0) >> 4) : 404 4 << ((tiling_config & 0x30) >> 4); 405 406 ws->info.pipe_interleave_bytes = 407 ws->info.chip_class >= EVERGREEN ? 408 256 << ((tiling_config & 0xf00) >> 8) : 409 256 << ((tiling_config & 0xc0) >> 6); 410 411 if (!ws->info.pipe_interleave_bytes) 412 ws->info.pipe_interleave_bytes = 413 ws->info.chip_class >= EVERGREEN ? 512 : 256; 414 415 radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL, 416 &ws->info.num_tile_pipes); 417 418 /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the 419 * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti) 420 * reports a different value (12). Fix it by setting what's in the 421 * GB_TILE_MODE array (8). 422 */ 423 if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12) 424 ws->info.num_tile_pipes = 8; 425 426 if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL, 427 &ws->info.r600_gb_backend_map)) 428 ws->info.r600_gb_backend_map_valid = true; 429 430 /* Default value. */ 431 ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.num_render_backends); 432 /* 433 * This fails (silently) on non-GCN or older kernels, overwriting the 434 * default enabled_rb_mask with the result of the last query. 435 */ 436 if (ws->gen >= DRV_SI) 437 radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL, 438 &ws->info.enabled_rb_mask); 439 440 ws->info.has_virtual_memory = false; 441 if (ws->info.drm_minor >= 13) { 442 uint32_t ib_vm_max_size; 443 444 ws->info.has_virtual_memory = true; 445 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL, 446 &ws->va_start)) 447 ws->info.has_virtual_memory = false; 448 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL, 449 &ib_vm_max_size)) 450 ws->info.has_virtual_memory = false; 451 radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL, 452 &ws->va_unmap_working); 453 } 454 if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false)) 455 ws->info.has_virtual_memory = false; 456 } 457 458 /* Get max pipes, this is only needed for compute shaders. All evergreen+ 459 * chips have at least 2 pipes, so we use 2 as a default. */ 460 ws->info.r600_max_quad_pipes = 2; 461 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL, 462 &ws->info.r600_max_quad_pipes); 463 464 /* All GPUs have at least one compute unit */ 465 ws->info.num_good_compute_units = 1; 466 radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL, 467 &ws->info.num_good_compute_units); 468 469 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL, 470 &ws->info.max_se); 471 472 if (!ws->info.max_se) { 473 switch (ws->info.family) { 474 default: 475 ws->info.max_se = 1; 476 break; 477 case CHIP_CYPRESS: 478 case CHIP_HEMLOCK: 479 case CHIP_BARTS: 480 case CHIP_CAYMAN: 481 case CHIP_TAHITI: 482 case CHIP_PITCAIRN: 483 case CHIP_BONAIRE: 484 ws->info.max_se = 2; 485 break; 486 case CHIP_HAWAII: 487 ws->info.max_se = 4; 488 break; 489 } 490 } 491 492 radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL, 493 &ws->info.max_sh_per_se); 494 495 radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL, 496 &ws->accel_working2); 497 if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) { 498 fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, " 499 "returned accel_working2 value %u is smaller than 2. " 500 "Please install a newer kernel.\n", 501 ws->accel_working2); 502 return false; 503 } 504 505 if (ws->info.chip_class == CIK) { 506 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL, 507 ws->info.cik_macrotile_mode_array)) { 508 fprintf(stderr, "radeon: Kernel 3.13 is required for CIK support.\n"); 509 return false; 510 } 511 } 512 513 if (ws->info.chip_class >= SI) { 514 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL, 515 ws->info.si_tile_mode_array)) { 516 fprintf(stderr, "radeon: Kernel 3.10 is required for SI support.\n"); 517 return false; 518 } 519 } 520 521 /* Hawaii with old firmware needs type2 nop packet. 522 * accel_working2 with value 3 indicates the new firmware. 523 */ 524 ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI || 525 (ws->info.family == CHIP_HAWAII && 526 ws->accel_working2 < 3); 527 ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */ 528 ws->info.ib_start_alignment = 4096; 529 530 ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; 531 532 return true; 533 } 534 535 static void radeon_winsys_destroy(struct radeon_winsys *rws) 536 { 537 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws; 538 539 if (util_queue_is_initialized(&ws->cs_queue)) 540 util_queue_destroy(&ws->cs_queue); 541 542 mtx_destroy(&ws->hyperz_owner_mutex); 543 mtx_destroy(&ws->cmask_owner_mutex); 544 545 if (ws->info.has_virtual_memory) 546 pb_slabs_deinit(&ws->bo_slabs); 547 pb_cache_deinit(&ws->bo_cache); 548 549 if (ws->gen >= DRV_R600) { 550 radeon_surface_manager_free(ws->surf_man); 551 } 552 553 util_hash_table_destroy(ws->bo_names); 554 util_hash_table_destroy(ws->bo_handles); 555 util_hash_table_destroy(ws->bo_vas); 556 mtx_destroy(&ws->bo_handles_mutex); 557 mtx_destroy(&ws->bo_va_mutex); 558 mtx_destroy(&ws->bo_fence_lock); 559 560 if (ws->fd >= 0) 561 close(ws->fd); 562 563 FREE(rws); 564 } 565 566 static void radeon_query_info(struct radeon_winsys *rws, 567 struct radeon_info *info) 568 { 569 *info = ((struct radeon_drm_winsys *)rws)->info; 570 } 571 572 static bool radeon_cs_request_feature(struct radeon_winsys_cs *rcs, 573 enum radeon_feature_id fid, 574 bool enable) 575 { 576 struct radeon_drm_cs *cs = radeon_drm_cs(rcs); 577 578 switch (fid) { 579 case RADEON_FID_R300_HYPERZ_ACCESS: 580 return radeon_set_fd_access(cs, &cs->ws->hyperz_owner, 581 &cs->ws->hyperz_owner_mutex, 582 RADEON_INFO_WANT_HYPERZ, "Hyper-Z", 583 enable); 584 585 case RADEON_FID_R300_CMASK_ACCESS: 586 return radeon_set_fd_access(cs, &cs->ws->cmask_owner, 587 &cs->ws->cmask_owner_mutex, 588 RADEON_INFO_WANT_CMASK, "AA optimizations", 589 enable); 590 } 591 return false; 592 } 593 594 static uint64_t radeon_query_value(struct radeon_winsys *rws, 595 enum radeon_value_id value) 596 { 597 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws; 598 uint64_t retval = 0; 599 600 switch (value) { 601 case RADEON_REQUESTED_VRAM_MEMORY: 602 return ws->allocated_vram; 603 case RADEON_REQUESTED_GTT_MEMORY: 604 return ws->allocated_gtt; 605 case RADEON_MAPPED_VRAM: 606 return ws->mapped_vram; 607 case RADEON_MAPPED_GTT: 608 return ws->mapped_gtt; 609 case RADEON_BUFFER_WAIT_TIME_NS: 610 return ws->buffer_wait_time; 611 case RADEON_NUM_MAPPED_BUFFERS: 612 return ws->num_mapped_buffers; 613 case RADEON_TIMESTAMP: 614 if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) { 615 assert(0); 616 return 0; 617 } 618 619 radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp", 620 (uint32_t*)&retval); 621 return retval; 622 case RADEON_NUM_GFX_IBS: 623 return ws->num_gfx_IBs; 624 case RADEON_NUM_SDMA_IBS: 625 return ws->num_sdma_IBs; 626 case RADEON_NUM_BYTES_MOVED: 627 radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED, 628 "num-bytes-moved", (uint32_t*)&retval); 629 return retval; 630 case RADEON_NUM_EVICTIONS: 631 case RADEON_NUM_VRAM_CPU_PAGE_FAULTS: 632 case RADEON_VRAM_VIS_USAGE: 633 case RADEON_GFX_BO_LIST_COUNTER: 634 case RADEON_GFX_IB_SIZE_COUNTER: 635 return 0; /* unimplemented */ 636 case RADEON_VRAM_USAGE: 637 radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE, 638 "vram-usage", (uint32_t*)&retval); 639 return retval; 640 case RADEON_GTT_USAGE: 641 radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE, 642 "gtt-usage", (uint32_t*)&retval); 643 return retval; 644 case RADEON_GPU_TEMPERATURE: 645 radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP, 646 "gpu-temp", (uint32_t*)&retval); 647 return retval; 648 case RADEON_CURRENT_SCLK: 649 radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK, 650 "current-gpu-sclk", (uint32_t*)&retval); 651 return retval; 652 case RADEON_CURRENT_MCLK: 653 radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK, 654 "current-gpu-mclk", (uint32_t*)&retval); 655 return retval; 656 case RADEON_GPU_RESET_COUNTER: 657 radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER, 658 "gpu-reset-counter", (uint32_t*)&retval); 659 return retval; 660 case RADEON_CS_THREAD_TIME: 661 return util_queue_get_thread_time_nano(&ws->cs_queue, 0); 662 } 663 return 0; 664 } 665 666 static bool radeon_read_registers(struct radeon_winsys *rws, 667 unsigned reg_offset, 668 unsigned num_registers, uint32_t *out) 669 { 670 struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws; 671 unsigned i; 672 673 for (i = 0; i < num_registers; i++) { 674 uint32_t reg = reg_offset + i*4; 675 676 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, ®)) 677 return false; 678 out[i] = reg; 679 } 680 return true; 681 } 682 683 static unsigned hash_fd(void *key) 684 { 685 int fd = pointer_to_intptr(key); 686 struct stat stat; 687 fstat(fd, &stat); 688 689 return stat.st_dev ^ stat.st_ino ^ stat.st_rdev; 690 } 691 692 static int compare_fd(void *key1, void *key2) 693 { 694 int fd1 = pointer_to_intptr(key1); 695 int fd2 = pointer_to_intptr(key2); 696 struct stat stat1, stat2; 697 fstat(fd1, &stat1); 698 fstat(fd2, &stat2); 699 700 return stat1.st_dev != stat2.st_dev || 701 stat1.st_ino != stat2.st_ino || 702 stat1.st_rdev != stat2.st_rdev; 703 } 704 705 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", true) 706 707 static bool radeon_winsys_unref(struct radeon_winsys *ws) 708 { 709 struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws; 710 bool destroy; 711 712 /* When the reference counter drops to zero, remove the fd from the table. 713 * This must happen while the mutex is locked, so that 714 * radeon_drm_winsys_create in another thread doesn't get the winsys 715 * from the table when the counter drops to 0. */ 716 mtx_lock(&fd_tab_mutex); 717 718 destroy = pipe_reference(&rws->reference, NULL); 719 if (destroy && fd_tab) 720 util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd)); 721 722 mtx_unlock(&fd_tab_mutex); 723 return destroy; 724 } 725 726 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x))) 727 728 static unsigned handle_hash(void *key) 729 { 730 return PTR_TO_UINT(key); 731 } 732 733 static int handle_compare(void *key1, void *key2) 734 { 735 return PTR_TO_UINT(key1) != PTR_TO_UINT(key2); 736 } 737 738 PUBLIC struct radeon_winsys * 739 radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config, 740 radeon_screen_create_t screen_create) 741 { 742 struct radeon_drm_winsys *ws; 743 744 mtx_lock(&fd_tab_mutex); 745 if (!fd_tab) { 746 fd_tab = util_hash_table_create(hash_fd, compare_fd); 747 } 748 749 ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd)); 750 if (ws) { 751 pipe_reference(NULL, &ws->reference); 752 mtx_unlock(&fd_tab_mutex); 753 return &ws->base; 754 } 755 756 ws = CALLOC_STRUCT(radeon_drm_winsys); 757 if (!ws) { 758 mtx_unlock(&fd_tab_mutex); 759 return NULL; 760 } 761 762 ws->fd = fcntl(fd, F_DUPFD_CLOEXEC, 3); 763 764 if (!do_winsys_init(ws)) 765 goto fail1; 766 767 pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0, 768 MIN2(ws->info.vram_size, ws->info.gart_size), 769 radeon_bo_destroy, 770 radeon_bo_can_reclaim); 771 772 if (ws->info.has_virtual_memory) { 773 /* There is no fundamental obstacle to using slab buffer allocation 774 * without GPUVM, but enabling it requires making sure that the drivers 775 * honor the address offset. 776 */ 777 if (!pb_slabs_init(&ws->bo_slabs, 778 RADEON_SLAB_MIN_SIZE_LOG2, RADEON_SLAB_MAX_SIZE_LOG2, 779 RADEON_MAX_SLAB_HEAPS, 780 ws, 781 radeon_bo_can_reclaim_slab, 782 radeon_bo_slab_alloc, 783 radeon_bo_slab_free)) 784 goto fail_cache; 785 786 ws->info.min_alloc_size = 1 << RADEON_SLAB_MIN_SIZE_LOG2; 787 } else { 788 ws->info.min_alloc_size = ws->info.gart_page_size; 789 } 790 791 if (ws->gen >= DRV_R600) { 792 ws->surf_man = radeon_surface_manager_new(ws->fd); 793 if (!ws->surf_man) 794 goto fail_slab; 795 } 796 797 /* init reference */ 798 pipe_reference_init(&ws->reference, 1); 799 800 /* Set functions. */ 801 ws->base.unref = radeon_winsys_unref; 802 ws->base.destroy = radeon_winsys_destroy; 803 ws->base.query_info = radeon_query_info; 804 ws->base.cs_request_feature = radeon_cs_request_feature; 805 ws->base.query_value = radeon_query_value; 806 ws->base.read_registers = radeon_read_registers; 807 808 radeon_drm_bo_init_functions(ws); 809 radeon_drm_cs_init_functions(ws); 810 radeon_surface_init_functions(ws); 811 812 (void) mtx_init(&ws->hyperz_owner_mutex, mtx_plain); 813 (void) mtx_init(&ws->cmask_owner_mutex, mtx_plain); 814 815 ws->bo_names = util_hash_table_create(handle_hash, handle_compare); 816 ws->bo_handles = util_hash_table_create(handle_hash, handle_compare); 817 ws->bo_vas = util_hash_table_create(handle_hash, handle_compare); 818 (void) mtx_init(&ws->bo_handles_mutex, mtx_plain); 819 (void) mtx_init(&ws->bo_va_mutex, mtx_plain); 820 (void) mtx_init(&ws->bo_fence_lock, mtx_plain); 821 ws->va_offset = ws->va_start; 822 list_inithead(&ws->va_holes); 823 824 /* TTM aligns the BO size to the CPU page size */ 825 ws->info.gart_page_size = sysconf(_SC_PAGESIZE); 826 827 if (ws->num_cpus > 1 && debug_get_option_thread()) 828 util_queue_init(&ws->cs_queue, "radeon_cs", 8, 1, 0); 829 830 /* Create the screen at the end. The winsys must be initialized 831 * completely. 832 * 833 * Alternatively, we could create the screen based on "ws->gen" 834 * and link all drivers into one binary blob. */ 835 ws->base.screen = screen_create(&ws->base, config); 836 if (!ws->base.screen) { 837 radeon_winsys_destroy(&ws->base); 838 mtx_unlock(&fd_tab_mutex); 839 return NULL; 840 } 841 842 util_hash_table_set(fd_tab, intptr_to_pointer(ws->fd), ws); 843 844 /* We must unlock the mutex once the winsys is fully initialized, so that 845 * other threads attempting to create the winsys from the same fd will 846 * get a fully initialized winsys and not just half-way initialized. */ 847 mtx_unlock(&fd_tab_mutex); 848 849 return &ws->base; 850 851 fail_slab: 852 if (ws->info.has_virtual_memory) 853 pb_slabs_deinit(&ws->bo_slabs); 854 fail_cache: 855 pb_cache_deinit(&ws->bo_cache); 856 fail1: 857 mtx_unlock(&fd_tab_mutex); 858 if (ws->surf_man) 859 radeon_surface_manager_free(ws->surf_man); 860 if (ws->fd >= 0) 861 close(ws->fd); 862 863 FREE(ws); 864 return NULL; 865 } 866
