| /external/llvm/test/MC/Mips/ |
| elf-gprel-32-64.s | 49 dsrl $3, $3, 32
|
| rotations64.s | 110 # CHECK-64: dsrl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3a]
129 # CHECK-64: dsrl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfa]
134 # CHECK-64: dsrl $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7a]
138 # CHECK-64: dsrl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3a]
157 # CHECK-64: dsrl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfa]
162 # CHECK-64: dsrl $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7a]
179 # CHECK-64: dsrl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x7a]
184 # CHECK-64: dsrl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3a]
187 # CHECK-64: dsrl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x7a]
192 # CHECK-64: dsrl $1, $5, 31 # encoding: [0x00,0x05,0x0f,0xfa
[all...] |
| do_switch3.s | 41 dsrl $2, $3, 32
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| elf-gprel-32-64.s | 49 dsrl $3, $3, 32
|
| rotations64.s | 110 # CHECK-64: dsrl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3a]
129 # CHECK-64: dsrl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfa]
134 # CHECK-64: dsrl $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7a]
138 # CHECK-64: dsrl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3a]
157 # CHECK-64: dsrl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfa]
162 # CHECK-64: dsrl $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7a]
179 # CHECK-64: dsrl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x7a]
184 # CHECK-64: dsrl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3a]
187 # CHECK-64: dsrl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x7a]
192 # CHECK-64: dsrl $1, $5, 31 # encoding: [0x00,0x05,0x0f,0xfa
[all...] |
| do_switch3.s | 41 dsrl $2, $3, 32
|
| /external/u-boot/arch/mips/include/asm/ |
| asm.h | 294 #define INT_SRL dsrl
338 #define LONG_SRL dsrl
390 #define PTR_SRL dsrl
|
| /bionic/libc/private/ |
| bionic_asm_mips.h | 157 #define PTR_SRL dsrl
|
| /external/libffi/src/mips/ |
| ffitarget.h | 159 # define SRL dsrl
|
| /external/python/cpython2/Modules/_ctypes/libffi/src/mips/ |
| ffitarget.h | 159 # define SRL dsrl
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 44 dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
45 dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
46 dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 40 dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
41 dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
42 dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 39 dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
40 dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
41 dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 40 dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
41 dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
42 dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 38 dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
39 dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
40 dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 37 dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
38 dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
39 dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 44 dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
45 dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
46 dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 40 dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
41 dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
42 dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 39 dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
40 dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
41 dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 40 dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
41 dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
42 dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 38 dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
39 dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
40 dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips3/ |
| valid.s | 109 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
110 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
111 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
112 dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
113 dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 95 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
96 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
97 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 99 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
100 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
101 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 99 dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
100 dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
101 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
