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    Searched refs:dv_ddr2_regs_ctrl (Results 1 - 3 of 3) sorted by null

  /external/u-boot/arch/arm/mach-davinci/include/mach/
ddr2_defs.h 13 struct dv_ddr2_regs_ctrl { struct
80 #define dv_ddr2_regs_ctrl \ macro
81 ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)
  /external/u-boot/arch/arm/mach-davinci/
da850_lowlevel.c 187 writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
206 setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
216 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
222 &dv_ddr2_regs_ctrl->sdbcr2);
224 writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
225 writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
229 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
238 &dv_ddr2_regs_ctrl->sdrcr);
246 clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
248 writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr)
    [all...]
dm365_lowlevel.c 216 writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
220 &dv_ddr2_regs_ctrl->sdbcr);
222 &dv_ddr2_regs_ctrl->sdbcr);
225 writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
227 writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
229 writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
231 writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
234 writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);

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