1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SoC-specific lowlevel code for DA850 4 * 5 * Copyright (C) 2011 6 * Heiko Schocher, DENX Software Engineering, hs (at) denx.de. 7 */ 8 #include <common.h> 9 #include <nand.h> 10 #include <ns16550.h> 11 #include <post.h> 12 #include <asm/arch/da850_lowlevel.h> 13 #include <asm/arch/hardware.h> 14 #include <asm/arch/davinci_misc.h> 15 #include <asm/arch/ddr2_defs.h> 16 #include <asm/ti-common/davinci_nand.h> 17 #include <asm/arch/pll_defs.h> 18 19 void davinci_enable_uart0(void) 20 { 21 lpsc_on(DAVINCI_LPSC_UART0); 22 23 /* Bringup UART0 out of reset */ 24 REG(UART0_PWREMU_MGMT) = 0x00006001; 25 } 26 27 #if defined(CONFIG_SYS_DA850_PLL_INIT) 28 static void da850_waitloop(unsigned long loopcnt) 29 { 30 unsigned long i; 31 32 for (i = 0; i < loopcnt; i++) 33 asm(" NOP"); 34 } 35 36 static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) 37 { 38 if (reg == davinci_pllc0_regs) 39 /* Unlock PLL registers. */ 40 clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK); 41 42 /* 43 * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled 44 * through MMR 45 */ 46 clrbits_le32(®->pllctl, PLLCTL_PLLENSRC); 47 /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */ 48 clrbits_le32(®->pllctl, PLLCTL_EXTCLKSRC); 49 50 /* Set PLLEN=0 => PLL BYPASS MODE */ 51 clrbits_le32(®->pllctl, PLLCTL_PLLEN); 52 53 da850_waitloop(150); 54 55 if (reg == davinci_pllc0_regs) { 56 /* 57 * Select the Clock Mode bit 8 as External Clock or On Chip 58 * Oscilator 59 */ 60 dv_maskbits(®->pllctl, ~PLLCTL_RES_9); 61 setbits_le32(®->pllctl, 62 (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT)); 63 } 64 65 /* Clear PLLRST bit to reset the PLL */ 66 clrbits_le32(®->pllctl, PLLCTL_PLLRST); 67 68 /* Disable the PLL output */ 69 setbits_le32(®->pllctl, PLLCTL_PLLDIS); 70 71 /* PLL initialization sequence */ 72 /* 73 * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of 74 * power down bit 75 */ 76 clrbits_le32(®->pllctl, PLLCTL_PLLPWRDN); 77 78 /* Enable the PLL from Disable Mode PLLDIS bit to 0 */ 79 clrbits_le32(®->pllctl, PLLCTL_PLLDIS); 80 81 #if defined(CONFIG_SYS_DA850_PLL0_PREDIV) 82 /* program the prediv */ 83 if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV) 84 writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV), 85 ®->prediv); 86 #endif 87 88 /* Program the required multiplier value in PLLM */ 89 writel(pllmult, ®->pllm); 90 91 /* program the postdiv */ 92 if (reg == davinci_pllc0_regs) 93 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV), 94 ®->postdiv); 95 else 96 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV), 97 ®->postdiv); 98 99 /* 100 * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that 101 * no GO operation is currently in progress 102 */ 103 while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT) 104 ; 105 106 if (reg == davinci_pllc0_regs) { 107 writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, ®->plldiv1); 108 writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, ®->plldiv2); 109 writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, ®->plldiv3); 110 writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, ®->plldiv4); 111 writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, ®->plldiv5); 112 writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, ®->plldiv6); 113 writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, ®->plldiv7); 114 } else { 115 writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, ®->plldiv1); 116 writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, ®->plldiv2); 117 writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, ®->plldiv3); 118 } 119 120 /* 121 * Set the GOSET bit in PLLCMD to 1 to initiate a new divider 122 * transition. 123 */ 124 setbits_le32(®->pllcmd, PLLCMD_GOSTAT); 125 126 /* 127 * Wait for the GOSTAT bit in PLLSTAT to clear to 0 128 * (completion of phase alignment). 129 */ 130 while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT) 131 ; 132 133 /* Wait for PLL to reset properly. See PLL spec for PLL reset time */ 134 da850_waitloop(200); 135 136 /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */ 137 setbits_le32(®->pllctl, PLLCTL_PLLRST); 138 139 /* Wait for PLL to lock. See PLL spec for PLL lock time */ 140 da850_waitloop(2400); 141 142 /* 143 * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass 144 * mode 145 */ 146 setbits_le32(®->pllctl, PLLCTL_PLLEN); 147 148 149 /* 150 * clear EMIFA and EMIFB clock source settings, let them 151 * run off SYSCLK 152 */ 153 if (reg == davinci_pllc0_regs) 154 dv_maskbits(&davinci_syscfg_regs->cfgchip3, 155 ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC)); 156 157 return 0; 158 } 159 #endif /* CONFIG_SYS_DA850_PLL_INIT */ 160 161 #if defined(CONFIG_SYS_DA850_DDR_INIT) 162 static int da850_ddr_setup(void) 163 { 164 unsigned long tmp; 165 166 /* Enable the Clock to DDR2/mDDR */ 167 lpsc_on(DAVINCI_LPSC_DDR_EMIF); 168 169 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl); 170 if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) { 171 /* Begin VTP Calibration */ 172 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); 173 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); 174 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); 175 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); 176 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); 177 178 /* Polling READY bit to see when VTP calibration is done */ 179 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl); 180 while ((tmp & VTP_READY) != VTP_READY) 181 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl); 182 183 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); 184 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); 185 } 186 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); 187 writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); 188 189 if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) { 190 /* DDR2 */ 191 clrbits_le32(&davinci_syscfg1_regs->ddr_slew, 192 (1 << DDR_SLEW_DDR_PDENA_BIT) | 193 (1 << DDR_SLEW_CMOSEN_BIT)); 194 } else { 195 /* MOBILE DDR */ 196 setbits_le32(&davinci_syscfg1_regs->ddr_slew, 197 (1 << DDR_SLEW_DDR_PDENA_BIT) | 198 (1 << DDR_SLEW_CMOSEN_BIT)); 199 } 200 201 /* 202 * SDRAM Configuration Register (SDCR): 203 * First set the BOOTUNLOCK bit to make configuration bits 204 * writeable. 205 */ 206 setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK); 207 208 /* 209 * Write the new value of these bits and clear BOOTUNLOCK. 210 * At the same time, set the TIMUNLOCK bit to allow changing 211 * the timing registers 212 */ 213 tmp = CONFIG_SYS_DA850_DDR2_SDBCR; 214 tmp &= ~DV_DDR_BOOTUNLOCK; 215 tmp |= DV_DDR_TIMUNLOCK; 216 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); 217 218 /* write memory configuration and timing */ 219 if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) { 220 /* MOBILE DDR only*/ 221 writel(CONFIG_SYS_DA850_DDR2_SDBCR2, 222 &dv_ddr2_regs_ctrl->sdbcr2); 223 } 224 writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); 225 writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); 226 227 /* clear the TIMUNLOCK bit and write the value of the CL field */ 228 tmp &= ~DV_DDR_TIMUNLOCK; 229 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); 230 231 /* 232 * LPMODEN and MCLKSTOPEN must be set! 233 * Without this bits set, PSC don;t switch states !! 234 */ 235 writel(CONFIG_SYS_DA850_DDR2_SDRCR | 236 (1 << DV_DDR_SRCR_LPMODEN_SHIFT) | 237 (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT), 238 &dv_ddr2_regs_ctrl->sdrcr); 239 240 /* SyncReset the Clock to EMIF3A SDRAM */ 241 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF); 242 /* Enable the Clock to EMIF3A SDRAM */ 243 lpsc_on(DAVINCI_LPSC_DDR_EMIF); 244 245 /* disable self refresh */ 246 clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 247 DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN); 248 writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); 249 250 return 0; 251 } 252 #endif /* CONFIG_SYS_DA850_DDR_INIT */ 253 254 __attribute__((weak)) 255 void board_gpio_init(void) 256 { 257 return; 258 } 259 260 int arch_cpu_init(void) 261 { 262 /* Unlock kick registers */ 263 writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); 264 writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); 265 266 dv_maskbits(&davinci_syscfg_regs->suspsrc, 267 CONFIG_SYS_DA850_SYSCFG_SUSPSRC); 268 269 /* configure pinmux settings */ 270 if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size)) 271 return 1; 272 273 #if defined(CONFIG_SYS_DA850_PLL_INIT) 274 /* PLL setup */ 275 da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM); 276 da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM); 277 #endif 278 /* setup CSn config */ 279 #if defined(CONFIG_SYS_DA850_CS2CFG) 280 writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr); 281 #endif 282 #if defined(CONFIG_SYS_DA850_CS3CFG) 283 writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr); 284 #endif 285 286 da8xx_configure_lpsc_items(lpsc, lpsc_size); 287 288 /* GPIO setup */ 289 board_gpio_init(); 290 291 292 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), 293 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); 294 295 /* 296 * Fix Power and Emulation Management Register 297 * see sprufw3a.pdf page 37 Table 24 298 */ 299 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 300 DAVINCI_UART_PWREMU_MGMT_UTRST), 301 #if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) 302 &davinci_uart0_ctrl_regs->pwremu_mgmt); 303 #else 304 &davinci_uart2_ctrl_regs->pwremu_mgmt); 305 #endif 306 307 #if defined(CONFIG_SYS_DA850_DDR_INIT) 308 da850_ddr_setup(); 309 #endif 310 311 return 0; 312 } 313
