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  /external/swiftshader/third_party/LLVM/utils/TableGen/
CodeGenInstruction.cpp 36 if (Init->getDef()->getName() != "outs")
45 if (Init->getDef()->getName() != "ins")
67 Record *Rec = Arg->getDef();
85 ->getDef()->getName() != "ops")
416 if (ADI && ADI->getDef() == InstOpRec) {
422 ResOp = ResultOperand(Result->getArgName(AliasOpNo), ADI->getDef());
427 if (ADI && ADI->getDef()->isSubClassOf("Register")) {
432 InstOpRec = dynamic_cast<DefInit*>(DI->getArg(0))->getDef();
442 .contains(T.getRegBank().getReg(ADI->getDef())))
443 throw TGError(Loc, "fixed register " + ADI->getDef()->getName()
    [all...]
PseudoLoweringEmitter.cpp 34 if (DI->getDef()->isSubClassOf("Register") ||
35 DI->getDef()->getName() == "zero_reg") {
37 OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
46 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
48 "Pseudo operand type '" + DI->getDef()->getName() +
88 Record *Operator = OpDef->getDef();
SetTheory.cpp 170 dynamic_cast<DefInit&>(*Expr->getOperator()).getDef()->getRecords();
177 Record *Rec = Records.getDef(OS.str());
228 if (const RecVec *Result = expand(Def->getDef()))
230 Elts.insert(Def->getDef());
245 Operator *Op = Operators.lookup(OpInit->getDef()->getName());
CodeGenRegisters.cpp 103 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
112 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
116 SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef());
124 SubRegs[BaseIdxInit->getDef()] = R2;
309 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
317 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
352 assert(!getDef() && "Only synthesized classes can inherit properties");
503 if (!RegClasses[rci]->getDef())
576 if (Record *Def = RC->getDef())
CodeGenDAGPatterns.cpp 746 Record *Def = Pred->getDef();
870 !static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef()
874 getValueType(static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef());
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
CodeGenInstruction.cpp 36 if (Init->getDef()->getName() != "outs")
45 if (Init->getDef()->getName() != "ins")
69 Record *Rec = Arg->getDef();
91 cast<DefInit>(MIOpInfo->getOperator())->getDef()->getName() != "ops")
444 return Constraint->getDef()->isSubClassOf("TypedOperand") &&
445 Constraint->getDef()->getValueAsBit("IsPointer");
466 Record *ResultRecord = ADI ? ADI->getDef() : nullptr;
468 if (ADI && ADI->getDef() == InstOpRec) {
483 if (ADI && ADI->getDef()->isSubClassOf("RegisterOperand"))
484 ADI = ADI->getDef()->getValueAsDef("RegClass")->getDefInit()
    [all...]
OptParserEmitter.cpp 183 OS << getOptionName(*DI->getDef());
231 GroupFlags = DI->getDef()->getValueAsListInit("Flags");
232 OS << getOptionName(*DI->getDef());
239 OS << getOptionName(*DI->getDef());
264 << cast<DefInit>(I)->getDef()->getName();
268 << cast<DefInit>(I)->getDef()->getName();
PseudoLoweringEmitter.cpp 81 if (DI->getDef()->isSubClassOf("Register") ||
82 DI->getDef()->getName() == "zero_reg") {
84 OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
95 "Pseudo operand type '" + DI->getDef()->getName() +
135 Record *Operator = OpDef->getDef();
RegisterBankEmitter.cpp 60 const Record &getDef() const { return TheDef; }
67 for (const auto &RCDef : getDef().getValueAsListOfDefs("RegisterClasses"))
308 PrintWarning(Bank.getDef().getLoc(), "Register bank names should be "
311 PrintNote(Bank.getDef().getLoc(), "RegisterBank was declared here");
CodeGenDAGPatterns.cpp     [all...]
RISCVCompressInstEmitter.cpp 201 if (DI->getDef()->isSubClassOf("Register")) {
203 if (!validateRegister(DI->getDef(), Inst.Operands[i].Rec))
206 "'Register: '" + DI->getDef()->getName() +
210 OperandMap[i].Data.Reg = DI->getDef();
217 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst))
221 DI->getDef()->getName() +
281 return Type1->getDef() == Type2->getDef();
416 Record *Operator = OpDef->getDef();
433 Record *DestOperator = DestOpDef->getDef();
    [all...]
  /external/llvm/utils/TableGen/
CodeGenInstruction.cpp 36 if (Init->getDef()->getName() != "outs")
45 if (Init->getDef()->getName() != "ins")
69 Record *Rec = Arg->getDef();
90 cast<DefInit>(MIOpInfo->getOperator())->getDef()->getName() != "ops")
446 Record *ResultRecord = ADI ? ADI->getDef() : nullptr;
448 if (ADI && ADI->getDef() == InstOpRec) {
463 if (ADI && ADI->getDef()->isSubClassOf("RegisterOperand"))
464 ADI = ADI->getDef()->getValueAsDef("RegClass")->getDefInit();
466 if (ADI && ADI->getDef()->isSubClassOf("RegisterClass")) {
470 .hasSubClass(&T.getRegisterClass(ADI->getDef())))
    [all...]
OptParserEmitter.cpp 181 OS << getOptionName(*DI->getDef());
226 GroupFlags = DI->getDef()->getValueAsListInit("Flags");
227 OS << getOptionName(*DI->getDef());
234 OS << getOptionName(*DI->getDef());
259 << cast<DefInit>(I)->getDef()->getName();
263 << cast<DefInit>(I)->getDef()->getName();
PseudoLoweringEmitter.cpp 81 if (DI->getDef()->isSubClassOf("Register") ||
82 DI->getDef()->getName() == "zero_reg") {
84 OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
95 "Pseudo operand type '" + DI->getDef()->getName() +
135 Record *Operator = OpDef->getDef();
CodeGenDAGPatterns.cpp 875 Record *Def = Pred->getDef();
    [all...]
  /external/mesa3d/src/gallium/drivers/nouveau/codegen/
nv50_ir_lowering_nvc0.cpp 76 bld.mkMovFromReg(i->getDef(0), i->op == OP_DIV ? 0 : 1);
96 Value *src[2], *dst[2], *def = i->getDef(0);
170 Value *dst64 = lo->getDef(0);
538 prev->setSrc(prev->srcCount(), useVec[i].tex->getDef(0));
544 bar->setSrc(bar->srcCount(), useVec[i].tex->getDef(0));
731 if (!i->getDef(0)->refCount())
    [all...]
nv50_ir_lowering_nv50.cpp 180 bld->mkOp2(OP_UNION, mul->sType, mul->getDef(0), rr[5], rr[6]);
182 bld->mkMov(mul->getDef(0), r[4]);
185 bld->mkMov(mul->getDef(0), t[3]);
415 i->getDef(0)->reg.size = 2; // $aX are only 16 bit
448 arl = bld.mkOp2(OP_SHL, TYPE_U32, i->getDef(0), bld.getSSA(), bld.mkImm(0));
457 Value *def = mul->getDef(0);
466 Value *res = cloneShallow(func, mul->getDef(0));
469 add->setSrc(0, mul->getDef(0));
586 if (insn->defExists(0) && insn->getDef(0)->reg.file == FILE_ADDRESS)
676 tid = bld.mkMov(bld.getScratch(), arg, TYPE_U32)->getDef(0)
    [all...]
nv50_ir_lowering_gm107.cpp 181 bld.mkOp3(OP_SHFL, TYPE_F32, tex->getDef(c), tex->getDef(c), bld.mkImm(0), quad);
188 mov = bld.mkMov(def[c][l], tex->getDef(c));
195 Instruction *u = bld.mkOp(OP_UNION, TYPE_U32, i->getDef(c));
231 insn->setSrc(0, shfl->getDef(0));
nv50_ir_peephole.cpp 53 if (!getDef(0)->equals(getSrc(0)))
74 if (getDef(d)->refCount() || getDef(d)->reg.data.id >= 0)
110 if (mov->getDef(0)->reg.data.id < 0 && si && si->op != OP_PHI) {
273 if (ld->getDef(0)->refCount() == 0)
715 i->setSrc(1, bld.mkMov(bld.getSSA(type), i->getSrc(0), type)->getDef(0));
866 mul2->def(0).replace(mul1->getDef(0), false);
873 mul2->def(0).replace(mul1->getDef(0), false);
881 if (mul2->getDef(0)->refCount() == 1 && !mul2->saturate) {
885 insn = (*mul2->getDef(0)->uses.begin())->getInsn()
    [all...]
nv50_ir_ra.cpp 469 LValue *tmp = new_LValue(func, phi->getDef(0)->asLValue());
515 LValue *tmp = new_LValue(func, cal->getDef(d)->asLValue());
521 mov->setDef(0, cal->getDef(d));
599 bb->liveSet.clr(i->getDef(d)->id);
605 bb->liveSet.clr(i->getDef(0)->id);
654 bb->liveSet.clr(i->getDef(0)->id);
675 bb->liveSet.clr(i->getDef(d)->id);
676 if (i->getDef(d)->reg.data.id >= 0) // add hazard for fixed regs
677 i->getDef(d)->livei.extend(i->serial, i->serial);
1021 LValue *rep = (split ? insn->getSrc(0) : insn->getDef(0))->asLValue()
    [all...]
  /external/clang/utils/TableGen/
ClangSACheckersEmitter.cpp 33 return isHidden(*DI->getDef());
47 name = getPackageFullName(DI->getDef());
135 package = DI->getDef();
156 Record *parentPackage = DI->getDef();
162 recordGroupMap[DI->getDef()]->Checkers.insert(R);
169 addPackageToCheckerGroup(packages[i], DI->getDef(), recordGroupMap);
210 OS << groupToSortIndex[DI->getDef()] << ", ";
238 OS << groupToSortIndex[DI->getDef()] << ", ";
ClangDiagnosticsEmitter.cpp 86 std::string CatName = getCategoryFromDiagGroup(Group->getDef(),
176 std::string GroupName = DI->getDef()->getValueAsString("GroupName");
232 const Record *NextDiagGroup = GroupInit->getDef();
263 const Record *NextDiagGroup = GroupInit->getDef();
276 SrcMgr.PrintMessage(GroupInit->getDef()->getLoc().front(),
404 const Record *GroupRec = Group->getDef();
423 if (groupInPedantic(Group->getDef()))
520 const Record *GroupRec = Group->getDef();
552 DiagsInGroup.find(DI->getDef()->getValueAsString("GroupName"));
    [all...]
  /external/python/pyasn1/pyasn1/type/
tagmap.py 95 def getDef(self):
  /external/llvm/lib/TableGen/
SetTheory.cpp 204 cast<DefInit>(Expr->getOperator())->getDef()->getRecords();
215 Record *Rec = Records.getDef(OS.str());
275 if (const RecVec *Result = expand(Def->getDef()))
277 Elts.insert(Def->getDef());
292 auto I = Operators.find(OpInit->getDef()->getName());
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/TableGen/
SetTheory.cpp 215 cast<DefInit>(Expr->getOperator())->getDef()->getRecords();
226 Record *Rec = Records.getDef(OS.str());
286 if (const RecVec *Result = expand(Def->getDef()))
288 Elts.insert(Def->getDef());
303 auto I = Operators.find(OpInit->getDef()->getName());

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