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  /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/
RegisterAliasing.cpp 16 llvm::BitVector AliasedBits(RegInfo.getNumRegs());
29 : SourceBits(RegInfo.getNumRegs()), AliasedBits(RegInfo.getNumRegs()),
30 Origins(RegInfo.getNumRegs()) {}
64 EmptyRegisters(RegInfo.getNumRegs()) {}
  /external/llvm/include/llvm/CodeGen/
LivePhysRegs.h 56 LiveRegs.setUniverse(TRI->getNumRegs());
64 LiveRegs.setUniverse(TRI->getNumRegs());
76 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
86 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
  /external/swiftshader/third_party/LLVM/lib/Target/PTX/
PTXRegisterInfo.h 42 BitVector Reserved(getNumRegs());
  /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
LivePhysRegs.h 59 LiveRegs.setUniverse(TRI.getNumRegs());
69 LiveRegs.setUniverse(TRI.getNumRegs());
81 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
91 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
  /external/llvm/lib/CodeGen/
RegUsageInfoCollector.cpp 106 unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
117 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
133 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
RegisterClassInfo.cpp 56 CSRNum.resize(TRI->getNumRegs(), 0);
84 unsigned NumRegs = RC->getNumRegs();
178 unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
TargetFrameLoweringImpl.cpp 66 // SavedRegs.size() == TRI.getNumRegs() after this call even if there are no
68 SavedRegs.resize(TRI.getNumRegs());
CriticalAntiDepBreaker.cpp 35 Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0),
36 DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {}
43 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
103 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
249 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
452 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
506 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
RegisterUsageInfo.cpp 86 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
  /external/swiftshader/third_party/llvm-7.0/llvm/unittests/tools/llvm-exegesis/X86/
RegisterAliasingTest.cpp 63 const llvm::BitVector NoReservedReg(RegInfo.getNumRegs());
69 llvm::BitVector sum(RegInfo.getNumRegs());
81 const llvm::BitVector NoReservedReg(RegInfo.getNumRegs());
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
RegUsageInfoCollector.cpp 95 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
114 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
139 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
169 for (unsigned PReg = 1, PRegE = TRI.getNumRegs(); PReg < PRegE; ++PReg) {
RegisterClassInfo.cpp 63 CalleeSavedAliases.resize(TRI->getNumRegs(), 0);
96 unsigned NumRegs = RC->getNumRegs();
189 unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
CriticalAntiDepBreaker.cpp 50 Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0),
51 DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {}
57 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
120 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
266 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
467 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
521 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
RegisterUsageInfo.cpp 96 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
TargetFrameLoweringImpl.cpp 75 // SavedRegs.size() == TRI.getNumRegs() after this call even if there are no
77 SavedRegs.resize(TRI.getNumRegs());
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/
Nios2RegisterInfo.cpp 41 BitVector Reserved(getNumRegs());
  /external/swiftshader/third_party/LLVM/include/llvm/MC/
MCRegisterInfo.h 63 /// getNumRegs - Return the number of registers in this class.
65 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
70 assert(i < getNumRegs() && "Register number out of range!");
253 /// getNumRegs - Return the number of registers this target has (useful for
255 unsigned getNumRegs() const {
  /external/swiftshader/third_party/LLVM/lib/CodeGen/
RegisterClassInfo.cpp 47 CSRNum.resize(TRI->getNumRegs(), 0);
74 unsigned NumRegs = RC->getNumRegs();
MachineRegisterInfo.cpp 24 UsedPhysRegs.resize(TRI.getNumRegs());
27 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
28 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
60 if (NewRC->getNumRegs() < MinNumRegs)
  /external/swiftshader/third_party/LLVM/lib/Target/
TargetRegisterInfo.cpp 39 else if (TRI && Reg < TRI->getNumRegs())
83 BitVector Allocatable(getNumRegs());
  /external/llvm/lib/Target/NVPTX/
NVPTXRegisterInfo.cpp 87 BitVector Reserved(getNumRegs());
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
RDFRegisters.cpp 31 RegInfos.resize(TRI.getNumRegs());
33 BitVector BadRC(TRI.getNumRegs());
88 for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
109 for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
200 unsigned NumRegs = TRI.getNumRegs();
335 BitVector Regs(PRI.getTRI().getNumRegs());
342 BitVector AR(PRI.getTRI().getNumRegs());
  /external/llvm/lib/Target/AMDGPU/
R600RegisterInfo.cpp 29 BitVector Reserved(getNumRegs());
  /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/AsmParser/
MBlazeAsmLexer.cpp 45 unsigned numRegs = info->getNumRegs();
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
NVPTXRegisterInfo.cpp 109 BitVector Reserved(getNumRegs());

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