/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
TargetRegisterInfo.cpp | 307 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) { 315 unsigned MinSize = getRegSizeInBits(*RCA); 323 if (!RC || getRegSizeInBits(*RC) < MinSize) 332 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC)) 341 if (getRegSizeInBits(*BestRC) == MinSize) 461 unsigned TargetRegisterInfo::getRegSizeInBits(unsigned Reg, 480 return getRegSizeInBits(*RC);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
X86RegisterInfo.cpp | 136 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) 143 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) 150 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) 157 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) 170 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC) [all...] |
X86CallLowering.cpp | 138 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); 260 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
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X86FlagsCopyLowering.cpp | [all...] |
X86SpeculativeLoadHardening.cpp | 741 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
NVPTXInstrInfo.cpp | 41 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
RegisterBank.cpp | 52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) &&
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InstructionSelect.cpp | 203 if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
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RegisterBankInfo.cpp | 469 return TRI.getRegSizeInBits(*RC); 471 return TRI.getRegSizeInBits(Reg, MRI);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
SystemZRegisterInfo.cpp | 258 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) 265 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
AVRAsmPrinter.cpp | 116 unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8;
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AVRFrameLowering.cpp | 254 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && 292 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
HexagonVExtract.cpp | 139 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8;
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BitTracker.cpp | 341 return TRI.getRegSizeInBits(VC); 717 return TRI.getRegSizeInBits(PC); [all...] |
HexagonBitTracker.cpp | 119 return TRI.getRegSizeInBits(RC); 122 return TRI.getRegSizeInBits(*RC); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
SIRegisterInfo.cpp | 692 getSpillEltSize(getRegSizeInBits(*RC) / 8, true); 863 getSpillEltSize(getRegSizeInBits(*RC) / 8, false); [all...] |
GCNRegPressure.cpp | 91 (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) : 92 (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
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SIInstrInfo.h | 716 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8; 722 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; [all...] |
SIInstrInfo.cpp | 302 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; 306 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; 453 return (NumLoads * (RI.getRegSizeInBits(*DstRC) / 8)) <= LoadClusterThreshold; 563 if (RI.getRegSizeInBits(*RC) > 32) { 655 if (RI.getRegSizeInBits(*RegClass) > 32) { 811 if (RI.getRegSizeInBits(*DstRC) == 32) { 813 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) { 815 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) { [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
TargetRegisterInfo.h | 314 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { 763 unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const; [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
RISCVInstrInfo.cpp | 121 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? 148 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/AsmPrinter/ |
DwarfExpression.cpp | 124 unsigned RegSize = TRI.getRegSizeInBits(*RC);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
ARMBaseRegisterInfo.cpp | 817 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && 818 getRegSizeInBits(*SrcRC) < 256) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
MipsAsmPrinter.cpp | 292 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8; 293 unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8; 294 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8; [all...] |
MipsSEInstrInfo.cpp | 700 unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF)); 701 unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF)); [all...] |